JP2002182984A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor with a configuration by which written matters information of a regular sentence data which is preserved in a memory and secrecy information are nearly perfectly prevented from being leaked or illegally rewritten. SOLUTION: The data processor is shared by more than one circuits or devices, which comprise a programmable circuit, and is provided with the memory where a preservation area where access by the programmable circuit is limited is arranged in a part of a storage area as the preservation area of information to be non-ciphered sentence data. When the programmable circuit performs access to the non-opened area of the memory, access is regarded as the illegal one so that an illegal access preventing operation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly, to a data processing apparatus comprising: a decryptor (descrambler) for decrypting ciphertext data into plaintext data; and a programmable circuit operable by an externally written program. The present invention relates to a data processing device provided.

[0002]

2. Description of the Related Art In a data transmission process of compressed audio (Audio) data and image (Video, Visual) data, and an AV data reproducing device which is a data processing device thereof,
It is indispensable to take measures to prevent information leakage to prevent illegal duplication of confidential information such as copyrighted work information or billing information representing copyrighted work requiring copyright protection.

[0003] As one of the information leakage prevention measures, data inputted to a data processing apparatus is subjected to encryption processing in advance. For this reason, a descrambler, which is a decryptor that decrypts ciphertext data into plaintext data (non-ciphertext data), is provided inside the data processing device.

FIG. 7 is a block diagram showing a configuration of a conventional data processing device provided with a descrambler.

The conventional data processing device 17 comprises a programmable circuit 1, a descrambler 2, and an AV decoder 3.
, A DA converter (DAC) 4, a memory controller 5, and one memory 6.

[0006] The programmable circuit 1 is operable by a program written from outside. Further, the programmable circuit 1 has an external data port EDP for inputting / outputting data with the outside. Programmable circuit 1
Is a typical example of an arithmetic processing unit (CPU, MP
U).

The programmable circuit 1 has a configuration in which an external program writing circuit 20 can be connected to a programming port PP. And the programmable circuit 1
Can execute an arbitrary program written by the program writing circuit 20.

Therefore, the operation of the entire data processing device 17 can be controlled by the programmable circuit 1. It is also possible to externally write data to the memory 6 via the programmable circuit 1 and read data stored in the memory 6 to the outside via the programmable circuit 1.

The descrambler 2 is a decoder for decrypting ciphertext data input from the outside into plaintext data. Therefore, ciphertext data is input to the descrambler 2 from outside. Then, the descrambler 2 decrypts the ciphertext data into plaintext data. Then, the descrambler 2 writes the decrypted plaintext data to the specified address of the memory 6 via the memory controller 5.

The AV decoder 3 is a decoder that decodes plaintext data into audio or video or audio and video AV digital signals. The flat data decoded into the AV digital signal is the flat data read from the memory 6.

The DA converter 4 converts an AV digital signal from a digital signal to a digital signal and outputs it as an analog AV signal.

One memory 6 is shared by the programmable circuit 1, the descrambler 2, and the AV decoder 3. Then, the memory 6 stores and stores the plaintext data at the designated address.

The memory controller 5 is interposed between the programmable circuit 1, the descrambler 2, the AV decoder 3 and the memory 6. The memory controller 5 has a built-in data selector Sel1 inserted and connected to the data transmission path and an address selector Sel2 inserted and connected to the addressing path. Then, the memory controller 5 performs data writing and reading of the address of the memory 6 specified via the data selector Sel1 and the address selector Sel2. Data writing and reading of the memory 6 are performed in response to a request from the programmable circuit 1, the descrambler 2, or the AV decoder 3. Any of the programmable circuit 1, the descrambler 2, and the AV decoder 3
Any area inside the memory 6 can be accessed.

As described above, the data processing device 17
Has a UMA (Unified Memory Architecture) structure. The UMA structure refers to a structure in which a plurality of circuits or devices such as a built-in programmable circuit 1, a descrambler 2, and an AV decoder 3 share one memory 6 via a memory controller 5.

[0015]

As described above, in the conventional data processing device, the programmable circuit 1
An arbitrary program can be written and executed from the outside. Further, the programmable circuit 1 can access any storage area of the memory 6. Therefore,
The decrypted plaintext data stored in the memory 6 can be read out.

The plaintext data stored in the memory 6 may include confidential information such as copyrighted information indicating a copyrighted work requiring copyright protection and billing information. Therefore,
In a conventional data processing apparatus, there is a risk that such confidential information may be leaked due to unauthorized access via the programmable circuit 1.

In the configuration of the conventional data processing apparatus, there is no other means to prevent the leakage of the plaintext data except to keep the information on the usage of the data processing apparatus private. That is, the conventional data processing device has insufficient tamper resistance. The tamper resistance is a property of trying to prevent the operation analysis of a device or a program by reverse engineering or the extraction of internal data.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a data processing apparatus having a UMA structure, such as copyrighted information, billing information, and the like of plaintext data stored in a memory. An object of the present invention is to provide a data processing device having a configuration capable of almost completely preventing leakage or unauthorized rewriting of confidential information.

[0019]

According to the basic structure of the data processing apparatus according to the present invention, the data processing apparatus is shared by a programmable circuit operable by a program written from the outside and a plurality of circuits or apparatuses including the programmable circuit. In addition, a memory provided as a part of the storage area is provided with a storage area in which access by the programmable circuit is limited as a storage area for information that has become non-ciphertext data.

When the programmable circuit attempts to access the storage area of the memory, the access is regarded as an unauthorized access and an unauthorized access preventing operation is performed.

With this configuration, it is possible to almost completely prevent leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory.

When the memory is mounted on the same semiconductor substrate as the plurality of circuits or devices sharing the memory, plaintext data appearing on a bus connected to the memory is read from the outside. Can not be.

According to a specific configuration of the data processing apparatus according to the present invention, a programmable circuit operable by a program written from the outside and having an external data port for inputting and outputting data to and from the outside, And a non-public area shared by a plurality of circuits or devices including a decoder for decrypting ciphertext data into plaintext data, and in which access by the programmable circuit is restricted, and the plurality of circuits or devices The storage area is divided into a public area that can be accessed by any of the above, a memory for storing and storing plaintext data at a specified address, and a built-in address interposed between the plurality of circuits or devices and the memory The address of the memory specified by the programmable circuit via the detection circuit is the secret area. When an address, said address detection circuit detects the access by the address specified as the unauthorized access, characterized in that it comprises a memory controller that performs trusted operations.

More specifically, a dummy memory selection command for selecting the dummy memory is sent to a dummy data selector which is inserted and connected to a data transmission path between the programmable circuit and the memory and has a dummy memory. It is preferable that the unauthorized access prevention operation output from the address detection circuit is performed.

A dummy data address selection command for selecting a dummy data address provided in a part of the open area is sent to a dummy data selector inserted and connected to a data transmission path between the programmable circuit and the memory. The above unauthorized access prevention operation output from the address detection circuit may be performed.

The address detection circuit may perform the unauthorized access prevention operation of outputting an access rejection notice to the programmable circuit. In this case, the data transmission path between the programmable circuit and the memory further passes through a switch built in the address detection circuit, and the address detection circuit outputs the access rejection notice when , The switch may be turned off.

The address detecting circuit may perform the unauthorized access preventing operation of outputting an error notification to the programmable circuit. In this case, further, the data transmission path between the programmable circuit and the memory shall pass through a switch built in the address detection circuit, and the address detection circuit, when outputting the error notification, The switch may be turned off.

The address detection circuit may output the system reset command signal for resetting and initializing the operation of the entire system to the programmable circuit to perform the unauthorized access prevention operation.

The address detection circuit may output the programmable circuit operation stop command signal for stopping the operation of the programmable circuit to the unauthorized access prevention operation.

[0030] The address detection circuit may output a memory power shutoff command for shutting off the power of the memory to the memory to perform the unauthorized access prevention operation.

The address detection circuit may output the external data port shutoff command to shut off the external data port to the programmable circuit to perform the unauthorized access prevention operation.

In a specific configuration of the data processing apparatus according to the present invention, each of the data processing devices is inserted and connected between the plurality of circuits or devices and the memory, and each data between the plurality of circuits or devices and the memory. It is preferable to include a data selector and an address selector for respectively selecting one of the transmission path and each of the address designation paths.

Alternatively, a shared data bus shared as a data transmission path between the plurality of circuits or devices and the memory and a shared address bus shared as an address designation path may be transmitted from the plurality of circuits or devices. It is preferable to provide a bus arbiter for notifying permission / denial of a bus use request to be made.

When the memory is mounted on the same semiconductor substrate as the plurality of circuits or devices sharing the memory and the memory controller, the memory is mounted on a bus connecting the memory and the memory controller. The appearing plaintext data can be prevented from being read from the outside.

The above-mentioned programmable circuit is preferably an arithmetic processing unit.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing apparatus according to the present invention
As a storage area exclusively for confidential information such as copyrighted work information and billing information that has been decrypted into plaintext data, a secret area that restricts access by the programmable circuit is provided in a part of the storage area of the memory. A UMA structure data processing device.

The data processing apparatus according to the present invention regards an access to an undisclosed area of a memory from outside via a programmable circuit as an unauthorized access. Then, various unauthorized access preventing operations such as dummy data output, access rejection notification, and system reset are performed. Thereby, the data processing device according to the present invention prevents leakage or unauthorized rewriting of confidential information.

In the data processing device according to each embodiment of the present invention, the UMA structure includes a programmable circuit operable by a program written from the outside, and a decoder for decrypting ciphertext data into plaintext data. A structure in which a plurality of built-in circuits or built-in devices share one memory.

Hereinafter, embodiments of the data processing apparatus according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the data processing device according to the first embodiment of the present invention.

The data processing device 11 according to the first embodiment of the present invention comprises a programmable circuit 1, a descrambler 2, an AV decoder 3, and a DA converter (DAC).
4, a memory controller 5 and one memory 6.

The programmable circuit 1 can operate by a program written from outside. Further, the programmable circuit 1 has an external data port EDP for inputting / outputting data with the outside.

A typical example of the programmable circuit 1 is an arithmetic processing unit (CPU, MPU) as described above.
It is. Further, the programmable circuit 1 is configured so that an external program writing circuit 20 can be connected to the programming port PP. And the programmable circuit 1
Can execute an arbitrary program written by the program writing circuit 20. Therefore, the operation of the entire data processing device 17 can be controlled by the programmable circuit 1. It is also possible to externally write data to the public area 6a of the memory 6 via the programmable circuit 1 or read data stored in the public area 6a of the memory 6 to the outside via the programmable circuit 1. is there.

The descrambler 2 is a decryptor that decrypts ciphertext data input from the outside into plaintext data. The descrambler 2 receives ciphertext data. This ciphertext data is, for example, DES (Data Encry
ption Standard) etc.
PEG2 stream and the like. The descrambler 2 decrypts the ciphertext data into plaintext data. Then, the descrambler 2 writes the decrypted plaintext data to the specified address of the memory 6 via the memory controller 5.

The AV decoder 3 is a decoder that decodes the plaintext data and converts it into an audio or image or an audio and image AV digital signal. The plaintext data decoded as the AV digital signal is the plain data read from the private area 6b or the public area 6a of the memory 6.

The DA converter 4 converts the AV digital signal into a digital signal and outputs it as an AV analog signal to the outside.

One memory 6 is shared by the programmable circuit 1, the descrambler 2, and the AV decoder 3. The storage area of the memory 6 is divided into a private area 6b to which access by the programmable circuit 1 is restricted and a public area 6a to which any of the programmable circuit 1, the descrambler 2 and the AV decoder 3 can access.

The memory 6 is mounted on the same semiconductor substrate as the programmable circuit 1, the descrambler 2, the AV decoder 3, the DA converter 4, the memory controller 5, and the like. This prevents plaintext data appearing on the bus connecting the memory 6 and the memory controller 5 from being read from the outside.

When the decrypted plaintext data is confidential information such as copyrighted work information and billing information, the address of the private area 6b of the memory 6 is always designated. Therefore, the plaintext data of the confidential information is written in the private area 6b of the memory 6. The memory 6 sequentially accumulates and stores the plaintext data written in accordance with the specified address in the closed area 6b and the open area 6a.

The memory controller 5 has a data selector
Sel1, address selector Sel2, and address detection circuit 5
1 and a dummy data selector Sel3.

The data selector Sel 1 comprises a programmable circuit 1, a descrambler 2, an AV decoder 3 and a memory 6.
And is inserted and connected to the data transmission path between the two. Then, the data selector Sel 1 selects one of the programmable circuit 1, the descrambler 2, and each data transmission path between the AV decoder 3 and the memory 6.

The address selector Sel 2 is inserted and connected to the programmable circuit 1, the descrambler 2, and an address designation path between the AV decoder 3 and the memory 6. Then, the address selector Sel2 selects any one of the programmable circuits 1, the descrambler 2, and each addressing path between the AV decoder 3 and the memory 6.

The address detection circuit 51 is inserted and connected to an address designation path between the programmable circuit 1 and the memory 6. Here, in order to simplify the configuration of the address signal and address detection circuit 51, the address detection circuit 51 is inserted and connected to an address designation path between the programmable circuit 1 and the address selector Sel2. The address detection circuit 51 may be inserted and connected to an address designation path between the address selector Sel2 and the memory 6. In this case, however, the address detection circuit 51 must be able to identify whether the address signal is transmitted from the programmable circuit 1, the descrambler 2, or the AV decoder 3.

The dummy data selector Sel 3 is inserted and connected to a data transmission path between the programmable circuit 1 and the memory 6. Also, the dummy data selector Sel3 has:
A dummy memory 50 is provided.

When the address of the memory 6 specified by the programmable circuit 1 via the address detection circuit 51 is an address of the secret area 6b, the address detection circuit 51 detects an access by the address specification as an unauthorized access. . At that time, the address detection circuit 51
Outputs a dummy memory selection command for selecting the dummy memory 50 to the dummy data selector Sel3.

The descrambler 2 and the AV decoder 3
It only operates in accordance with a pre-designed specification, and it is impossible to perform an operation different from the original by accessing from the outside. On the other hand, the programmable circuit 1 usually has
The operation is performed by an operation program in which access to the private area 6b of the memory 6 is prohibited. However, the operation program itself of the programmable circuit 1 may be rewritten by an external access. Therefore,
Only a path via the programmable circuit 1 can be considered as a path for unauthorized access to the memory 6 from the outside. Therefore, when the programmable circuit 1 attempts to access the closed area 6b of the memory 6, the access is detected as an unauthorized access as described above.

The data processing device 11 according to the first embodiment of the present invention is a data processing device having a UMA structure. Therefore, a plurality of circuits or devices such as the built-in programmable circuit 1, the descrambler 2, and the AV decoder 3 share one memory 6 via the memory controller 5.

When a data write or read address is specified by the descrambler 2 or the AV decoder 3, the memory controller 5 writes or reads data at the address. This address designation is performed via the address selector Sel2. Data writing or reading of the address is performed regardless of whether the designated address is the address of the private area 6b or the public area 6a of the memory 6. Further, data writing or reading of the address is performed via the data selector Sel1.

On the other hand, in the data processing device 11 according to the first embodiment of the present invention, data writing from the outside to the secret area 6b of the memory 6 via the programmable circuit 1 is performed as follows. Limited by the memory controller 5. Also, data reading from the private area 6b of the memory 6 to the outside via the programmable circuit 1 is restricted by the memory controller 5 as described below.

The dummy data selector Sel3 can select either the dummy memory 50 or the data selector Sel1 connected to the memory 6. However, the dummy data selector Sel3 is normally the data selector Sel1.
Is selected.

When a data write or read address is designated by the programmable circuit 1, the memory controller 5 operates as follows.

When the specified address is the address of the public area 6a of the memory 6, the memory controller 5
Performs data writing or reading at the address. This address designation is performed via the address detection circuit 51 and the address selector Sel2. Further, data writing or reading of the address is performed via the dummy data selector Sel3 and the data selector Sel1.

On the other hand, if the specified address is an address in the private area 6b of the memory 6, the address detection circuit 51 detects an access by the specified address as an unauthorized access. At that time, the address detection circuit 51
Outputs a dummy memory selection command for selecting the dummy memory 50 to the dummy data selector Sel3.

The dummy data selector Sel3 selects the dummy memory 50 according to the dummy memory selection command.
As a result, if the unauthorized access is an access for reading data, the dummy data written in the dummy memory 50 in advance is read. If the unauthorized access is an access for data writing, data writing may be performed in a predetermined area of the dummy memory 50, or data writing may be rejected. Is also good.

The contents of the dummy data read from the dummy memory 50 are arbitrary. For example, it may be another data that appears to be the original data that the person who attempted unauthorized access attempted to read. Alternatively, the data may be data indicating that the access has been detected as an unauthorized access.

In the data processing device 11 according to the first embodiment of the present invention, in response to detection of unauthorized access,
The dummy data selector Sel3 selects the dummy memory 50. However, without providing the dummy memory 50,
The dummy data selector Sel3 is connected to the public area 6a of the memory 6.
May be accessed from a completely different address.
In this case, for example, a dummy data address for unauthorized access may be provided in a part of the public area 6a of the memory 6. It is preferable that dummy data is previously written in the dummy data address, as in the case of the dummy memory 50.

As described above, the UMA structure data processing apparatus according to the first embodiment of the present invention is a storage area dedicated to confidential information such as copyrighted work information and billing information that has been decrypted into plaintext data. An undisclosed area in which access by the programmable circuit is restricted is provided in a part of the storage area of the memory. When an attempt is made to access a secret area of the memory from the programmable circuit, the access is detected as an unauthorized access and a dummy memory is selected. As a result, it is possible to almost completely prevent leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory.

FIG. 2 is a block diagram showing a configuration of a data processing device according to the second embodiment of the present invention.

The data processing device 12 according to the second embodiment of the present invention comprises a programmable circuit 1, a descrambler 2, an AV decoder 3, and a DA converter (DAC).
4, a memory controller 5 and one memory 6.

The configuration and operation of the programmable circuit 1, the descrambler 2, the AV decoder 3, and the DA converter 4 and the configuration of the memory 6 are the same as those of the first embodiment, and therefore, detailed description is omitted.

The memory controller 5 has a data selector
Sel1, address selector Sel2, and address detection circuit 5
2 and built-in.

The data selector Sel 1 comprises a programmable circuit 1, a descrambler 2, an AV decoder 3 and a memory 6.
And is inserted and connected to the data transmission path between the two. Then, the data selector Sel 1 selects one of the programmable circuit 1, the descrambler 2, and each data transmission path between the AV decoder 3 and the memory 6.

The address selector Sel 2 is inserted and connected to the programmable circuit 1, the descrambler 2, and an address designation path between the AV decoder 3 and the memory 6. Then, the address selector Sel2 selects any one of the programmable circuits 1, the descrambler 2, and each addressing path between the AV decoder 3 and the memory 6.

The address detection circuit 52 is inserted and connected to the address designation path between the programmable circuit 1 and the memory 6. Here, in order to simplify the configuration of the address signal and address detection circuit 52, the address detection circuit 52 is inserted and connected to an address designation path between the programmable circuit 1 and the address selector Sel2. The address detection circuit 52 may be inserted and connected to the address designation path between the address selector Sel2 and the memory 6. However, in that case, the address detection circuit 52 must be able to identify which of the programmable circuit 1, the descrambler 2, and the AV decoder 3 the address signal is transmitted from.

When the address of the memory 6 specified by the programmable circuit 1 via the address detection circuit 52 is the address of the secret area 6b, the address detection circuit 52 detects an access by the address specification as an unauthorized access. . At that time, the address detection circuit 52
Outputs an access rejection notification to the programmable circuit 1.

The descrambler 2 and the AV decoder 3
It only operates in accordance with a pre-designed specification, and it is impossible to perform an operation different from the original by accessing from the outside. On the other hand, the programmable circuit 1 usually has
The operation is performed by an operation program in which access to the private area 6b of the memory 6 is prohibited. However, the operation program itself of the programmable circuit 1 may be rewritten by an external access. Therefore,
Only a path via the programmable circuit 1 can be considered as a path for unauthorized access to the memory 6 from the outside. Therefore, when the programmable circuit 1 attempts to access the closed area 6b of the memory 6, the access is detected as an unauthorized access as described above.

The data processing device 12 according to the second embodiment of the present invention is also a data processing device having a UMA structure. Therefore, a plurality of circuits or devices such as the built-in programmable circuit 1, the descrambler 2, and the AV decoder 3 share one memory 6 via the memory controller 5.

When a data write or read address is specified by the descrambler 2 or the AV decoder 3, the memory controller 5 writes or reads data at the address. This address designation is performed via the address selector Sel2. Data writing or reading of the address is performed regardless of whether the designated address is the address of the private area 6b or the public area 6a of the memory 6. Further, data writing or reading of the address is performed via the data selector Sel1.

On the other hand, in the data processing device 12 according to the second embodiment of the present invention, data writing to the private area 6b of the memory 6 from outside via the programmable circuit 1 is performed as follows. Limited by the memory controller 5. Also, data reading from the private area 6b of the memory 6 to the outside via the programmable circuit 1 is restricted by the memory controller 5 as described below.

When data write or read address is designated by programmable circuit 1, memory controller 5 operates as follows.

When the specified address is the address of the public area 6a of the memory 6, the memory controller 5
Performs data writing or reading at the address. This address designation is performed via the address detection circuit 52 and the address selector Sel2. Further, data writing or reading of the address is performed via the data selector Sel1.

On the other hand, when the specified address is an address in the private area 6b of the memory 6, the address detection circuit 52 detects an access by the specified address as an unauthorized access. At that time, the address detection circuit 52
Outputs an access rejection notification to the programmable circuit 1.

When the address detection circuit 52 outputs an access denial notice to the programmable circuit 1, the address detection circuit 52 is built in the address detection circuit 52 so that the data transmission path between the programmable circuit 1 and the memory 6 can be immediately cut off. Preferably, the switch passes through the data transmission path.

In the data processing device 12 according to the second embodiment of the present invention, in response to detection of unauthorized access,
The address detection circuit 52 outputs an access rejection notice to the programmable circuit 1. However, an error notification may be output instead of the access rejection notification.
Or, to prevent unauthorized data writing or reading,
An external data port shutoff command to shut off the external data port EDP may be output to the programmable circuit 1.
Alternatively, a memory power shutoff command for shutting off the power of the memory 6 may be output to the memory 6.

As described above, the UMA structured data processing apparatus according to the second embodiment of the present invention is a storage area dedicated to confidential information such as copyrighted work information and billing information that has been decrypted into plaintext data. An undisclosed area in which access by the programmable circuit is restricted is provided in a part of the storage area of the memory. When an attempt is made to access a secret area of the memory from the programmable circuit, the access is detected as an unauthorized access, and an access rejection notice is output. As a result, it is possible to almost completely prevent leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory.

FIG. 3 is a block diagram showing a configuration of a data processing device according to the third embodiment of the present invention.

The data processing device 13 according to the third embodiment of the present invention comprises a programmable circuit 1, a descrambler 2, an AV decoder 3, and a DA converter (DAC).
4, a memory controller 5 and one memory 6.

The configuration and operation of the programmable circuit 1, the descrambler 2, the AV decoder 3, and the DA converter 4 and the configuration of the memory 6 are the same as those of the first embodiment, and therefore, detailed description is omitted. However, the third of the present invention
The programmable circuit 1 in the data processing device 13 according to the embodiment includes a system reset port SRP for receiving a system reset command signal from the address detection circuit 53.

The memory controller 5 has a data selector
Sel1, address selector Sel2, and address detection circuit 5
3 and built-in.

The data selector Sel 1 comprises a programmable circuit 1, a descrambler 2, an AV decoder 3 and a memory 6.
And is inserted and connected to the data transmission path between the two. Then, the data selector Sel 1 selects one of the programmable circuit 1, the descrambler 2, and each data transmission path between the AV decoder 3 and the memory 6.

The address selector Sel 2 is inserted and connected to the programmable circuit 1, the descrambler 2, and an address designation path between the AV decoder 3 and the memory 6. Then, the address selector Sel2 selects any one of the programmable circuits 1, the descrambler 2, and each addressing path between the AV decoder 3 and the memory 6.

The address detection circuit 53 is inserted and connected to an address designation path between the programmable circuit 1 and the memory 6. Here, in order to simplify the configuration of the address signal and address detection circuit 53, the address detection circuit 53 is inserted and connected to an address designation path between the programmable circuit 1 and the address selector Sel2. The address detection circuit 53 may be inserted and connected to an address designation path between the address selector Sel2 and the memory 6. However, in this case, the address detection circuit 53 must be able to identify which of the programmable circuit 1, the descrambler 2, and the AV decoder 3 the address signal is transmitted from.

When the address of the memory 6 specified by the programmable circuit 1 via the address detection circuit 53 is the address of the secret area 6b, the address detection circuit 53 detects an access by the address specification as an unauthorized access. . At that time, the address detection circuit 53
Outputs to the programmable circuit 1 a system reset command signal for resetting and initializing the operation of the entire system.

The descrambler 2 and the AV decoder 3
It only operates in accordance with a pre-designed specification, and it is impossible to perform an operation different from the original by accessing from the outside. On the other hand, the programmable circuit 1 usually has
The operation is performed by an operation program in which access to the private area 6b of the memory 6 is prohibited. However, the operation program itself of the programmable circuit 1 may be rewritten by an external access. Therefore,
Only a path via the programmable circuit 1 can be considered as a path for unauthorized access to the memory 6 from the outside. Therefore, when the programmable circuit 1 attempts to access the closed area 6b of the memory 6, the access is detected as an unauthorized access as described above.

The data processing device 13 according to the third embodiment of the present invention is also a data processing device having a UMA structure. Therefore, a plurality of circuits or devices such as the built-in programmable circuit 1, the descrambler 2, and the AV decoder 3 share one memory 6 via the memory controller 5.

When a data write or read address is specified by the descrambler 2 or the AV decoder 3, the memory controller 5 writes or reads data at the address. This address designation is performed via the address selector Sel2. Data writing or reading of the address is performed regardless of whether the designated address is the address of the private area 6b or the public area 6a of the memory 6. Further, data writing or reading of the address is performed via the data selector Sel1.

On the other hand, in the data processing device 13 according to the third embodiment of the present invention, data writing to the private area 6b of the memory 6 from outside through the programmable circuit 1 is performed as follows. Limited by the memory controller 5. Also, data reading from the private area 6b of the memory 6 to the outside via the programmable circuit 1 is restricted by the memory controller 5 as described below.

When data write or read address is designated by programmable circuit 1, memory controller 5 operates as follows.

If the specified address is an address in the public area 6a of the memory 6, the memory controller 5
Performs data writing or reading at the address. This address designation is performed via the address detection circuit 53 and the address selector Sel2. Further, data writing or reading of the address is performed via the data selector Sel1.

On the other hand, if the specified address is an address in the private area 6b of the memory 6, the address detection circuit 53 detects an access by the specified address as an unauthorized access. At that time, the address detection circuit 53
Sends the system reset command signal to the programmable circuit 1
Output to As a result, the operation of the entire system of the data processing device 16 is reset and initialized. As a result, external unauthorized access via the programmable circuit 1 becomes impossible.

In the data processing device 13 according to the third embodiment of the present invention, in response to detection of unauthorized access,
The address detection circuit 53 outputs a system reset command signal to the programmable circuit 1. However, not limited to the system reset command signal, a programmable circuit operation stop command for stopping the operation of the programmable circuit 1 may be output. Alternatively, an external data port shutoff command for shutting off external data port EDP may be output to programmable circuit 1 in order to prevent unauthorized data writing or reading. Alternatively, a memory power shutoff command for shutting off the power of the memory 6 may be output to the memory 6.

As described above, the UMA structure data processing apparatus according to the third embodiment of the present invention is a storage area dedicated to confidential information such as copyrighted work information and billing information that has been decrypted into plaintext data. An undisclosed area in which access by the programmable circuit is restricted is provided in a part of the storage area of the memory. Then, when an attempt is made to access a secret area of the memory from the programmable circuit, the access is detected as an unauthorized access and a system reset command is output. As a result, it is possible to almost completely prevent leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory.

FIG. 4 is a block diagram showing a configuration of a data processing device according to the fourth embodiment of the present invention.

The data processing device 14 according to the fourth embodiment of the present invention comprises a programmable circuit 1, a descrambler 2, an AV decoder 3, and a DA converter (DAC).
4, a memory controller 5 and one memory 6.

The configuration and operation of the programmable circuit 1, the descrambler 2, the AV decoder 3, and the DA converter 4 and the configuration of the memory 6 are the same as those of the first embodiment.

The memory controller 5 has a built-in shared data bus and shared address bus, a bus arbiter 54, an address detection circuit 51, and a dummy data selector Sel.

The shared data bus is shared as a data transmission path between the programmable circuit 1, the descrambler 2, and the AV decoder 3 and the memory 6. The shared address bus is shared as an addressing path between the programmable circuit 1, the descrambler 2, and the AV decoder 3 and the memory 6.

Programmable circuit 1, descrambler 2
The AV decoder 3 issues a use request to the bus arbiter 54 for the shared data bus and the shared address bus.

The bus arbiter 54 notifies the use request of whether or not to permit use of the shared data bus and the shared address bus.

The address detection circuit 51 is inserted and connected to the address designation path between the programmable circuit 1 and the memory 6. Here, in order to simplify the configuration of the address signal and address detection circuit 51, the address detection circuit 51 is inserted and connected to an address designation path between the programmable circuit 1 and the shared address bus.
The address detection circuit 51 includes a shared address bus and a memory 6.
May be inserted and connected to the addressing path between the two. In this case, however, the address detection circuit 51 must be able to identify whether the address signal is transmitted from the programmable circuit 1, the descrambler 2, or the AV decoder 3.

The dummy data selector Sel is inserted and connected to a data transmission path between the programmable circuit 1 and the memory 6. Also, the dummy data selector Sel has
A dummy memory 50 is provided.

When the address of the memory 6 specified by the programmable circuit 1 via the address detection circuit 51 is the address of the secret area 6b, the address detection circuit 51 detects an access by the address specification as an unauthorized access. . At that time, the address detection circuit 51
Outputs a dummy memory selection command for selecting the dummy memory 50 to the dummy data selector Sel.

The descrambler 2 and the AV decoder 3
It only operates in accordance with a pre-designed specification, and it is impossible to perform an operation different from the original by accessing from the outside. On the other hand, the programmable circuit 1 usually has
The operation is performed by an operation program in which access to the private area 6b of the memory 6 is prohibited. However, the operation program itself of the programmable circuit 1 may be rewritten by an external access. Therefore,
Only a path via the programmable circuit 1 can be considered as a path for unauthorized access to the memory 6 from the outside. Therefore, when the programmable circuit 1 attempts to access the closed area 6b of the memory 6, the access is detected as an unauthorized access as described above.

The data processing device 14 according to the fourth embodiment of the present invention is a data processing device having a UMA structure. Therefore, a plurality of circuits or devices such as the built-in programmable circuit 1, the descrambler 2, and the AV decoder 3 share one memory 6 via the memory controller 5.

The data processing device 14 according to the fourth embodiment of the present invention has a configuration similar to that of the data processing device 11 according to the first embodiment of the present invention. However, the configuration of the memory controller 5 including the shared data bus, shared address bus, and bus arbiter 54 is the first.
This is different from the configuration of the memory controller 5 in the embodiment.

That is, in the data processing device 14 according to the fourth embodiment of the present invention, the programmable circuit 1, the descrambler 2, the AV decoder 3, and the memory 6 are connected via the shared address bus and the shared data bus. Always connected. Then, the programmable circuit 1, the descrambler 2, and the AV decoder 3 send a use request for the shared data bus and the shared address bus to the bus arbiter 54.
Do for The bus arbiter 54 notifies the use request of whether or not to permit use of the shared data bus and the shared address bus. When the use is permitted, the programmable circuit 1, the descrambler 2, or the AV decoder 3 can use the shared address bus and the shared data bus. Thereby, access to the memory 6 becomes possible. In this respect, the data processing device 1 according to the fourth embodiment of the present invention
4 is different from the first embodiment.

When the data write or read address is specified by the descrambler 2 or the AV decoder 3, the memory controller 5 writes or reads the data at the address. This addressing is performed via a shared address bus. When writing or reading data at the address, the designated address is stored in the private area 6 of the memory 6.
This is performed regardless of the address of the public area b or the public area 6a. Further, data writing or reading of the address is performed via a shared data bus.

On the other hand, in the data processing device 14 according to the fourth embodiment of the present invention, data writing to the secret area 6b of the memory 6 from outside via the programmable circuit 1 is performed as follows. Limited by the memory controller 5. Also, data reading from the private area 6b of the memory 6 to the outside via the programmable circuit 1 is restricted by the memory controller 5 as described below.

The dummy data selector Sel can select either the dummy memory 50 or the memory 6. However, the dummy data selector Sel is normally in a state where the memory 6 is selected.

When data write or read address is designated by programmable circuit 1, memory controller 5 operates as follows.

When the specified address is the address of the public area 6a of the memory 6, the memory controller 5
Performs data writing or reading at the address. This address designation is performed via the address detection circuit 51 and the shared address bus. Further, data writing or reading of the address is performed via the dummy data selector Sel and the shared data bus.

On the other hand, if the specified address is an address in the private area 6b of the memory 6, the address detection circuit 51 detects an access by the address specification as an unauthorized access. At that time, the address detection circuit 51
Outputs a dummy memory selection command for selecting the dummy memory 50 to the dummy data selector Sel.

The data selector Sel selects the dummy memory 50 in response to the dummy memory selection command. As a result, if the unauthorized access is an access for reading data, the dummy data written in the dummy memory 50 in advance is read. If the unauthorized access is an access for data writing, data writing may be performed in a predetermined area of the dummy memory 50, or data writing may be rejected. Is also good.

The contents of the dummy data read from the dummy memory 50 are arbitrary as in the first embodiment.

In the data processing device 14 according to the fourth embodiment of the present invention, in response to detection of unauthorized access,
The dummy data selector Sel3 selects the dummy memory 50. However, without providing the dummy memory 50,
The dummy data selector Sel3 is connected to the public area 6a of the memory 6.
May be accessed from a completely different address.
In this case, for example, a dummy data address for unauthorized access may be provided in a part of the public area 6a of the memory 6. It is preferable that dummy data is previously written in the dummy data address, as in the case of the dummy memory 50.

As described above, the UMA structured data processing apparatus according to the fourth embodiment of the present invention is a storage area dedicated to confidential information such as copyrighted work information and billing information that has been decrypted into plaintext data. An undisclosed area in which access by the programmable circuit is restricted is provided in a part of the storage area of the memory. When an attempt is made to access a secret area of the memory from the programmable circuit, the access is detected as an illegal access and a dummy memory is selected. As a result, leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory can be almost completely prevented. Further, since the configuration includes the shared address bus, the shared data bus, and the bus arbiter, the data selector and the address selector can be eliminated.

FIG. 5 is a block diagram showing a configuration of a data processing device according to the fifth embodiment of the present invention.

The data processing device 15 according to the fifth embodiment of the present invention comprises a programmable circuit 1, a descrambler 2, an AV decoder 3, and a DA converter (DAC).
4, a memory controller 5 and one memory 6.

The configuration and operation of the programmable circuit 1, the descrambler 2, the AV decoder 3, and the DA converter 4 and the configuration of the memory 6 are the same as those of the first embodiment, and therefore, detailed description is omitted.

The memory controller 5 has a built-in shared data bus and shared address bus, a bus arbiter 54, and an address detection circuit 52.

Since the configuration and operation of the shared data bus, shared address bus, and bus arbiter 54 are the same as those of the fourth embodiment, detailed description will be omitted.

The address detection circuit 52 is inserted and connected to the address designation path between the programmable circuit 1 and the memory 6. Here, in order to simplify the configuration of the address signal and address detection circuit 52, the address detection circuit 52 is inserted and connected to an address designation path between the programmable circuit 1 and the shared address bus.
The address detection circuit 52 includes a shared address bus and the memory 6.
May be inserted and connected to the addressing path between the two. However, in that case, the address detection circuit 52 must be able to identify which of the programmable circuit 1, the descrambler 2, and the AV decoder 3 the address signal is transmitted from.

When the address of the memory 6 specified by the programmable circuit 1 via the address detection circuit 52 is the address of the secret area 6b, the address detection circuit 52 detects an access by the address specification as an unauthorized access. . At that time, the address detection circuit 52
Outputs an access rejection notification to the programmable circuit 1.

The descrambler 2 and the AV decoder 3
It only operates in accordance with a pre-designed specification, and it is impossible to perform an operation different from the original by accessing from the outside. On the other hand, the programmable circuit 1 usually has
The operation is performed by an operation program in which access to the private area 6b of the memory 6 is prohibited. However, the operation program itself of the programmable circuit 1 may be rewritten by an external access. Therefore,
Only a path via the programmable circuit 1 can be considered as a path for unauthorized access to the memory 6 from the outside. Therefore, when the programmable circuit 1 attempts to access the closed area 6b of the memory 6, the access is detected as an unauthorized access as described above.

The data processing device 15 according to the fifth embodiment of the present invention is a data processing device having a UMA structure. Therefore, a plurality of circuits or devices such as the built-in programmable circuit 1, the descrambler 2, and the AV decoder 3 share one memory 6 via the memory controller 5.

The data processing device 14 according to the fifth embodiment of the present invention has a configuration similar to the data processing device 12 according to the second embodiment of the present invention. However, the configuration of the memory controller 5 including the shared data bus, shared address bus, and bus arbiter 54 is the same as that of the second embodiment.
This is different from the configuration of the memory controller 5 in the embodiment.

When a data write or read address is specified by the descrambler 2 or the AV decoder 3, the memory controller 5 writes or reads data at the address. This addressing is performed via a shared address bus. When writing or reading data at the address, the designated address is stored in the private area 6 of the memory 6.
This is performed regardless of the address of the public area b or the public area 6a. Further, data writing or reading of the address is performed via a shared data bus.

On the other hand, in the data processing device 15 according to the fifth embodiment of the present invention, data writing from the outside to the secret area 6b of the memory 6 via the programmable circuit 1 is performed as follows. Limited by the memory controller 5. Also, data reading from the private area 6b of the memory 6 to the outside via the programmable circuit 1 is restricted by the memory controller 5 as described below.

When data write or read address is designated by programmable circuit 1, memory controller 5 operates as follows.

When the specified address is an address in the public area 6a of the memory 6, the memory controller 5
Performs data writing or reading at the address. This address designation is performed via the address detection circuit 52 and the shared address bus. Further, data writing or reading of the address is performed via a shared data bus.

On the other hand, if the specified address is an address in the private area 6b of the memory 6, the address detection circuit 52 detects an access by the specified address as an unauthorized access. At that time, the address detection circuit 52
Outputs an access rejection notification to the programmable circuit 1.

When the address detection circuit 52 outputs an access rejection notice to the programmable circuit 1, the data transmission path is connected to the address detection circuit so that the data transmission path between the programmable circuit 1 and the memory 6 can be immediately cut off. It is good to go through the switch built in 52.

In the data processing device 15 according to the fifth embodiment of the present invention, in response to detection of unauthorized access,
The address detection circuit 52 outputs an access rejection notice to the programmable circuit 1. However, an error notification may be output instead of the access rejection notification.
Or, to prevent unauthorized data writing or reading,
An external data port shutoff command to shut off the external data port EDP may be output to the programmable circuit 1.
Alternatively, a memory power shutoff command for shutting off the power of the memory 6 may be output to the memory 6.

As described above, the UMA structure data processing device according to the fifth embodiment of the present invention is provided as a storage area dedicated to confidential information such as copyrighted work information and billing information that has been decrypted into plaintext data. An undisclosed area in which access by the programmable circuit is restricted is provided in a part of the storage area of the memory. When an attempt is made to access a secret area of the memory from the programmable circuit, the access is detected as an unauthorized access, and an access rejection notice is output. As a result, it is possible to almost completely prevent leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory. Further, since the configuration includes the shared address bus, the shared data bus, and the bus arbiter, the data selector and the address selector can be eliminated.

FIG. 6 is a block diagram showing a configuration of a data processing device according to the sixth embodiment of the present invention.

The data processing device 16 according to the sixth embodiment of the present invention comprises a programmable circuit 1, a descrambler 2, an AV decoder 3, and a DA converter (DAC).
4, a memory controller 5 and one memory 6.

The configurations and operations of the programmable circuit 1, the descrambler 2, the AV decoder 3, and the DA converter 4 and the configuration of the memory 6 are the same as those of the first embodiment, and therefore, detailed description is omitted. However, the sixth aspect of the present invention
The programmable circuit 1 in the data processing device 16 according to the embodiment includes a system reset port SRP for receiving a system reset command signal from the address detection circuit 53.

The memory controller 5 has a built-in shared data bus and shared address bus, a bus arbiter 54, and an address detection circuit 53.

The configuration and operation of the shared data bus, shared address bus, and bus arbiter 54 are the same as those of the fourth embodiment, and thus detailed description will be omitted.

The address detection circuit 53 is inserted and connected to the address designation path between the programmable circuit 1 and the memory 6. Here, in order to simplify the configuration of the address signal and address detection circuit 53, the address detection circuit 53 is inserted and connected to an address designation path between the programmable circuit 1 and the shared address bus.
The address detection circuit 53 includes a shared address bus and the memory 6.
May be inserted and connected to the addressing path between the two. However, in this case, the address detection circuit 53 must be able to identify which of the programmable circuit 1, the descrambler 2, and the AV decoder 3 the address signal is transmitted from.

When the address of the memory 6 specified by the programmable circuit 1 via the address detection circuit 53 is the address of the secret area 6b, the address detection circuit 53 detects an access by the address specification as an unauthorized access. . At that time, the address detection circuit 53
Outputs to the programmable circuit 1 a system reset command signal for resetting and initializing the operation of the entire system.

The descrambler 2 and the AV decoder 3
It only operates in accordance with a pre-designed specification, and it is impossible to perform an operation different from the original by accessing from the outside. On the other hand, the programmable circuit 1 usually has
The operation is performed by an operation program in which access to the private area 6b of the memory 6 is prohibited. However, the operation program itself of the programmable circuit 1 may be rewritten by an external access. Therefore,
Only a path via the programmable circuit 1 can be considered as a path for unauthorized access to the memory 6 from the outside. Therefore, when the programmable circuit 1 attempts to access the closed area 6b of the memory 6, the access is detected as an unauthorized access as described above.

The data processing device 16 according to the sixth embodiment of the present invention is a data processing device having a UMA structure. Therefore, a plurality of circuits or devices such as the built-in programmable circuit 1, the descrambler 2, and the AV decoder 3 share one memory 6 via the memory controller 5.

The data processing device 16 according to the sixth embodiment of the present invention has a configuration similar to that of the data processing device 13 according to the third embodiment of the present invention. However, the configuration of the memory controller 5 incorporating the shared data bus, shared address bus, and bus arbiter 54 is the third.
This is different from the configuration of the memory controller 5 in the embodiment.

When a data write or read address is specified by the descrambler 2 or the AV decoder 3, the memory controller 5 writes or reads data at the address. This addressing is performed via a shared address bus. When writing or reading data at the address, the designated address is stored in the private area 6 of the memory 6.
This is performed regardless of the address of the public area b or the public area 6a. Further, data writing or reading of the address is performed via a shared data bus.

On the other hand, in the data processing device 16 according to the sixth embodiment of the present invention, data writing from the outside to the private area 6b of the memory 6 via the programmable circuit 1 is performed as follows. Limited by the memory controller 5. Also, data reading from the private area 6b of the memory 6 to the outside via the programmable circuit 1 is restricted by the memory controller 5 as described below.

When data write or read address is designated by programmable circuit 1, memory controller 5 operates as follows.

When the specified address is an address in the public area 6a of the memory 6, the memory controller 5
Performs data writing or reading at the address. This address designation is performed via the address detection circuit 53 and the shared address bus. Further, data writing or reading of the address is performed via a shared data bus.

On the other hand, if the specified address is an address in the private area 6b of the memory 6, the address detection circuit 53 detects an access by the specified address as an unauthorized access. At that time, the address detection circuit 53
Sends the system reset command signal to the programmable circuit 1
Output to As a result, the operation of the entire system of the data processing device 16 is reset and initialized. As a result, external unauthorized access via the programmable circuit 1 becomes impossible.

In the data processing device 16 according to the sixth embodiment of the present invention, in response to detection of unauthorized access,
The address detection circuit 53 outputs a system reset command signal to the programmable circuit 1. However, not limited to the system reset command signal, a programmable circuit operation stop command for stopping the operation of the programmable circuit 1 may be output. Alternatively, an external data port shutoff command for shutting off external data port EDP may be output to programmable circuit 1 in order to prevent unauthorized data writing or reading. Alternatively, a memory power shutoff command for shutting off the power of the memory 6 may be output to the memory 6.

As described above, the UMA structure data processing device according to the sixth embodiment of the present invention is provided as a storage area dedicated to confidential information such as copyrighted work information and billing information that has been decrypted into plaintext data. An undisclosed area in which access by the programmable circuit is restricted is provided in a part of the storage area of the memory. Then, when an attempt is made to access a secret area of the memory from the programmable circuit, the access is detected as an unauthorized access and a system reset command is output. As a result, it is possible to almost completely prevent leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory. Further, since the configuration includes the shared address bus, the shared data bus, and the bus arbiter, the data selector and the address selector can be eliminated.

[0162]

According to the basic configuration of the data processing device according to the present invention, a programmable circuit operable by a program written from the outside and a plurality of circuits or devices including the programmable circuit are shared and non-programmable. A memory provided as a storage area for a part of the storage area as a storage area for the information that has become the ciphertext data, in which a storage area in which access by the programmable circuit is restricted is provided. And
When the programmable circuit attempts to access the secret area of the memory, the access is regarded as an unauthorized access and an unauthorized access preventing operation is performed. As a result, it is possible to almost completely prevent leakage or unauthorized rewriting of confidential information such as copyrighted work information and billing information of plaintext data stored in the shared memory.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a data processing device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a data processing device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a data processing device according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a data processing device according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional data processing device provided with a descrambler.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Programmable circuit 2 Descrambler 3 AV decoder 4 DA converter 5 Memory controller 6 Memory 6a Private area 6b Public area 20 Program writing circuit 50 Dummy memory 51, 52, 53 Address detection circuit Sel selector

Claims (18)

[Claims] A programmable circuit operable by a program written from the outside; and a programmable area shared by a plurality of circuits or devices including the programmable circuit and serving as non-ciphertext data storage area. A data processing device, comprising: a memory in which a storage area for which access is restricted is provided in a part of the storage area. 2. The data processing according to claim 1, wherein when the programmable circuit attempts to access the storage area of the memory, the access is regarded as an unauthorized access and an unauthorized access preventing operation is performed. apparatus. 3. The data processing device according to claim 1, wherein the memory is mounted on the same semiconductor substrate as the plurality of circuits or devices sharing the memory. 4. A programmable circuit operable by a program written from the outside and having an external data port for inputting and outputting data to and from the outside, the programmable circuit, and decrypting the ciphertext data into plaintext data. A storage area is shared by a plurality of circuits or devices including a decoder, and a storage area is in a non-public area where access by the programmable circuit is restricted, and a public area that can be accessed by any of the plurality of circuits or apparatuses. A memory for storing and storing plaintext data at a specified address, interposed between the plurality of circuits or devices and the memory;
When the address of the memory specified by the programmable circuit via the built-in address detection circuit is an address of the secret area, the address detection circuit detects an access by the address specification as an unauthorized access, and A data processing device comprising: a memory controller that performs a prevention operation. 5. An address detection circuit, comprising: 5. The data processing device according to claim 4, wherein the unauthorized access preventing operation is output. 6. A dummy data address selection command for selecting a dummy data address provided in a part of the open area to a dummy data selector inserted and connected to a data transmission path between the programmable circuit and the memory. 5. The data processing device according to claim 4, wherein the unauthorized access prevention operation in which the address detection circuit outputs the following is performed. 7. The data processing apparatus according to claim 4, wherein said address detection circuit performs said unauthorized access prevention operation of outputting an access denial notice to said programmable circuit. 8. A data transmission path between the programmable circuit and the memory passes through a switch built in the address detection circuit, and the address detection circuit outputs the access rejection notification. The data processing device according to claim 7, wherein the switch shuts off the switch. 9. The data processing apparatus according to claim 4, wherein said address detection circuit performs said unauthorized access prevention operation of outputting an error notification to said programmable circuit. 10. A data transmission path between the programmable circuit and the memory passes through a switch built in the address detection circuit, and the address detection circuit outputs the error notification when outputting the error notification. 10. The data processing apparatus according to claim 9, wherein the switch is turned off. 11. The illegal access prevention operation in which the address detection circuit outputs a system reset command signal for resetting and initializing the operation of the entire system to the programmable circuit. The data processing device according to claim 1. 12. The unauthorized access prevention operation in which the address detection circuit outputs a programmable circuit operation stop command signal for stopping the operation of the programmable circuit to the programmable circuit. Data processing equipment. 13. The data processing apparatus according to claim 4, wherein said address detection circuit outputs said memory power shutoff command for shutting off the power of said memory to said memory to perform said unauthorized access prevention operation. . 14. The data according to claim 4, wherein said address detection circuit outputs an external data port shutoff command for shutting off said external data port to said programmable circuit to perform said unauthorized access prevention operation. Processing equipment. 15. A data transmission path and an addressing path between the plurality of circuits or devices and the memory, respectively, which are inserted and connected between the plurality of circuits or devices and the memory, respectively. 15. The data processing device according to claim 4, further comprising a data selector and an address selector for selecting. 16. A shared data bus shared as a data transmission path between the plurality of circuits or devices and the memory, and a shared address bus shared as an address designation path, from the plurality of circuits or devices. 15. The data processing device according to claim 4, further comprising a bus arbiter for notifying permission / denial of a bus use request to be made. 17. The memory according to claim 1, wherein the memory is mounted on the same semiconductor substrate as the plurality of circuits or devices sharing the memory and the memory controller. Data processing equipment. 18. The data processing device according to claim 1, wherein the programmable circuit is an arithmetic processing device.