JPH0575597A - Secret key protecting system and cipher processing lsic by this system - Google Patents

Abstract

PURPOSE:To provide the secret key protecting system and the cipher processing of this system where read/write of a memory part where secret key data is stored can be checked but secret key data cannot be observed from the external. CONSTITUTION:Data in a memory part 1 where secret key information is stored can be read/written from the external in the test mode. A control part 2 which controls permission/inhibition of external output of read data from the memory part 1, a storage part 3 where all stored information are reset by input of a test mode signal TM and information related to addresses where data is written in the memory part 1 is stored thereafter, and a comparing part 4 which compares stored information of the storage part 3 and information related to the address for data read of the memory part 1 with each other are provided. When the test mode is set and the comparison in the comparing part 4 results in coincidence, the control part 2 permits data output. The memory part 1 and a cipher processing part which generates secret key information are unified and integrated into a cipher processing LSIC to improve the secrecy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a secret key protection system and a cryptographic processing LSIC according to the system, and more specifically, it is possible to externally read / write data in a memory section for storing information related to a secret key in a test mode. And a cryptographic processing LSIC according to the method.

In recent years, with the advancement of information technology in society, there is a strong demand for protection of data security, and the importance of cryptographic processing is increasing. Therefore, in a device that stores secret key information that plays a central role in such cryptographic processing or a cryptographic processing LSIC in which a cryptographic processing unit is integrated and integrated with this, secret management of key data is extremely important.
Even if the device equipped with C or the like is stolen and the operation is analyzed, it is important that the secret key data cannot be taken out.

[0003]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional cryptographic processing LSIC. In the figure, 10 is a cryptographic processing LSIC incorporated in a mobile communication terminal, 11 is a key processing unit according to NTT's FEAL-8 cryptographic algorithm, and 12 is a key processing unit. Selector part, 13
Is a memory unit, 14 is a data randomizing unit according to the same FEAL-8 encryption algorithm, and 15 is a tristate buffer circuit.

In the normal operation mode, the test mode signal TM is at the LOW level, which allows the selector section 1 to operate.
2 selects the A side of the input terminal, and the output TP of the buffer circuit 15 is high impedance. In this state, the 64-bit key data KD is secretly sent from the base station in advance. The key processing unit 11 sends this key data KD to the FEA.
The 256-bit length expanded key data EKD with increased encryption strength is generated by mixing according to the L-8 encryption algorithm, and this is stored in the memory unit 13.

Next, 64-bit plaintext data MD is sent from a CPU (not shown) in the base station or mobile communication terminal. The data randomizing unit 14 mixes the plaintext data MD and the expanded key data EKD of the memory unit 13 according to the FEAL-8 encryption algorithm to generate the encrypted data CD with further increased encryption strength, and outputs this to the outside. To do. Then, although not shown, the audio data that has been sampled and quantized externally is processed by the data randomizing unit 1.
It is encrypted by the encrypted data CD of No. 4 and is wirelessly transmitted.

By the way, such a FEAL-8 encryption algorithm is open to the public. Moreover, since the same cryptographic processing LSICs are on the market in large numbers, anyone can obtain them. Therefore, if a device equipped with such an LSIC is stolen, the encryption operation may be analyzed. However, if plaintext data MD
Even if is known, the audio data cannot be decrypted unless the expanded key data EKD is known. Moreover, the original key data KD is secretly sent, and the expanded key data EKD cannot be generated unless the key data KD is known. Therefore, a cryptographic processing system using such a cryptographic processing LSIC is seemingly safe.

However, this type of cryptographic processing LS is generally used.
In the IC, it is necessary to check whether or not the memory operation of the memory unit 13 is normally performed, and for this purpose, a test mode for testing the reading and writing of data of the memory unit 13 is provided. In this test mode, the test mode signal TM is H
IGH level, whereby the selector section 12 selects the B side of the input terminal, and the output of the buffer circuit 15 changes according to the input. That is, in test mode,
It is possible to write the test data TD to an arbitrary address TA from the outside or read the data of the arbitrary address TA to the test terminal TP. Therefore, in the conventional cryptographic processing LSIC, the test mode signal TM is set to HIGH.
By setting the level, the secret expanded key data EKD could be easily known.

[0008]

As described above, in the conventional cryptographic processing LSIC, it is possible to easily observe the secret expanded key data from the outside by setting the LSIC in the test mode. there were. An object of the present invention is to provide a secret key protection system that enables read / write inspection of a memory unit that stores secret key data from the outside, and secret key data cannot be observed from the outside, and a cryptographic processing LSIC according to the system. Especially.

[0009]

The above problems can be solved by the structure shown in FIG. That is, the secret key protection system of the present invention is
In the secret key protection system of the apparatus configured to be able to read / write the data of the memory unit 1 storing the information related to the secret key from the outside by the test mode, it is possible to control whether the read data of the memory unit 1 can be output to the outside. Of the control unit 2, the storage unit 3 that stores all the stored information by turning on the test mode signal TM, and stores the information related to the address at which the data is subsequently written to the memory unit 1; The control unit 2 is provided with the comparison unit 4 for comparing the stored information and the information related to the address for reading the data of the memory unit 1 and in the test mode and when the comparison match of the comparison unit 4 is obtained. To do.

Further, the cryptographic processing LSIC of the present invention is a cryptographic processing LSIC provided with a storage device configured to be able to externally read / write data in the memory unit 1 for storing information related to a secret key in a test mode. The control unit 2 that controls whether or not the read data of the memory unit 1 can be output to the external terminal TP, and all the stored information is reset by turning on the test mode signal TM, and the data is subsequently written to the memory unit 1. Storage unit 3 that stores information related to addresses
And a comparison unit 4 that compares the stored information in the storage unit 3 with the information related to the address in the memory unit 1 from which the data is read, and control is performed in the test mode and when the comparison match of the comparison unit 4 is obtained. It is configured to enable the output of the section 2.

[0011]

In the secret key protection system of the present invention, when the test mode signal TM is input, the edge signal ETM resets all the contents stored in the storage unit 3. Then, when some test data DATA is written in the memory unit 1 thereafter, the information related to the write address ADD at that time is stored in the storage unit 3 by the write enable signal WE at that time.
Memorized in. Thus, the arbitrary address A of the memory unit 1
Arbitrary data DATA can be written in DD, and information on the write address ADD is stored in the storage unit 3 for each writing.

When the data DATA is read from the memory section 1 in this test mode, the gate section 5 outputs the information related to the read address ADD at that time by the read enable signal RE at that time. Then, the comparison unit 4 compares the information related to the write address of the storage unit 3 and the information related to the read address of the gate unit 5, and when the comparison is successful, the control unit 2 is enabled to output, and other than that. Disables output.

Therefore, after entering the test mode, if some data is written in the memory unit 1, the data at that address can be read to the external TP, but the data at the address where no data was written, that is, the secret key, is used. Such data cannot be read by the external TP. Thus, according to the present invention, the read / write inspection of the memory unit 1 can be performed by setting the encryption processing LSIC in the test mode, but the secret key data cannot be read out to the outside.

Further, in the cryptographic processing LSIC of the present invention, in the test mode, a storage device configured to be able to externally read / write data in the memory unit 1 for storing information related to the secret key, and the secret key. The confidentiality of the cryptographic processing device is further enhanced by integrating and integrating the cryptographic processing unit that generates information and the like.

[0015]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 2 is a block diagram of a cryptographic processing LSIC of the embodiment. In the figure, 20 is the cryptographic processing LSIC of the embodiment incorporated in a mobile communication terminal, and 11 is an FE of NTT.
A key processing unit according to the AL-8 encryption algorithm, 12 is a selector unit, 13 is a memory unit (corresponding to 1 in FIG. 1), 14 is a data randomizing unit according to the FEAL-8 encryption algorithm, and 15 is a tristate buffer circuit ( 2 is equivalent to 2) and 8 is a secret key protection unit (corresponding to 3 to 5).

In the normal operation mode, the test mode signal TM is at the LOW level, which allows the selector section 1 to operate.
2 selects the A side of the input terminal, and the output TP of the buffer circuit 15 is high impedance. In this state, the 64-bit key data KD is secretly sent from the base station in advance. The key processing unit 11 sends this key data KD to the FEA.
The 256-bit length expanded key data EKD with increased encryption strength is generated by mixing according to the L-8 encryption algorithm, and this is stored in the memory unit 13.

Next, 64-bit plaintext data MD is sent from a CPU (not shown) in the base station or mobile communication terminal. The data randomizing unit 14 mixes the plaintext data MD and the expanded key data EKD of the memory unit 13 according to the FEAL-8 encryption algorithm to generate the encrypted data CD with further increased encryption strength, and outputs this to the outside. To do. Then, although not shown, the audio data that has been sampled and quantized externally is processed by the data randomizing unit 1.
It is encrypted by the encrypted data CD of No. 4 and is wirelessly transmitted.

In the test mode, the test mode signal TM is at the HIGH level, which allows the selector section 1 to operate.
2 selects the B side of the input terminal, and the buffer circuit 15 is controlled by the control signal S of the secret key protection unit 8 described later. FIG. 3 is a block diagram of a secret key protection unit of the embodiment. In the figure, 81 and 82 are decoders, 83 is a latch circuit, 84 is a comparison unit composed of an AND-OR gate circuit, and 8
Reference numeral 5 is a delay inverter element, and 86 and 87 are AND gate circuits. The decoder 81 and the latch circuit 83 correspond to the storage unit 3 in FIG. 1, the decoder 82 corresponds to the gate unit 5, and the comparison unit 84 corresponds to the comparison unit 4.

When the test mode signal TM is input, the rising portion thereof is delayed by the delay inverter element 85 and the AND circuit.
The edge signal ETM extracted by the gate circuit 86 is generated,
As a result, all outputs Q _{0 to} Q _n of the latch circuit 83 are reset. Then, when some test data is written to the memory section 1 thereafter, the write enable signal WE at that time causes the write address AD at that time to be written.
Any one of the signals A _{0 to} A _n generated by decoding D is generated, and this sets the corresponding bit of the latch circuit 83. In this way, it is possible to write the arbitrary data DATA to the arbitrary address ADD of the memory unit 1, and the signals A _{0 to} A obtained by decoding the write address ADD for each writing.
Any one of the _n occurs, which sets the corresponding bit in the latch circuit 83.

When data is read from the memory unit 1, the decoder 82 decodes the read address ADD at that time by the read enable signal RE at that time and outputs one of the signals A _{0 to} A _n. Occur. In this state, the comparison unit 84 outputs the output signals Q _{0 to} Q _n of the latch circuit 83.
AND-O of the output signals A _{0 to} A _n of the decoder 82
R logic is used.

For example, now the output signal A _{0 of the} decoder 82.
Is high level, the output signal Q of the latch circuit 83
_{When 0} is HIGH level, test data has already been written to this address, and the comparison unit 84
Outputs a HIGH level. When the output signal A _n of the decoder 82 is at the HIGH level and the output signal Q _n of the latch circuit 83 is at the LOW level, no test data has been written to this address,
The comparison unit 84 outputs a LOW level.

Since the test mode signal TM is input to the AND gate circuit 87, the secret key protection unit 8 is finally controlled to the HIGH level only when the comparison mode of the comparison unit 84 is obtained in the test mode. The signal S is output, and the buffer circuit 15 outputs the read data of the memory unit 1 to the external terminal TP only when the control signal S is at the HIGH level. In the above embodiment, the case where the cryptographic processing LSIC is incorporated in the mobile communication terminal is shown, but the present invention can be applied to any other cryptographic processing device.

In the above embodiment, NTT FEAL-
Although the cryptographic processing according to the 8 cryptographic algorithms is shown, the cryptographic processing according to other cryptographic algorithms is also applicable.

[0024]

As described above, according to the present invention, all the stored information is reset by the control unit 2 for controlling whether or not the read data of the memory unit 1 can be output to the outside, and the input of the test mode signal TM. The storage unit 3 that stores information related to the address at which the data is subsequently written to the memory unit 1.
And a comparison unit 4 that compares the stored information in the storage unit 3 with the information related to the address in the memory unit 1 from which the data is read, and control is performed in the test mode and when the comparison match of the comparison unit 4 is obtained. Since the section 2 can be output, the read / write inspection of the memory section 1 can be performed from the outside, and the secret key data cannot be observed from the outside. Therefore, misuse of the private key due to theft can be prevented.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a block diagram of a cryptographic processing LSIC according to the embodiment.

FIG. 3 is a block diagram of a secret key protection unit according to the embodiment.

FIG. 4 is a block diagram of a conventional encryption processing LSIC.

[Explanation of symbols]

 1 memory unit 2 control unit 3 storage unit 4 comparison unit 5 gate unit

Claims (2)

[Claims] 1. In a secret key protection system of an apparatus configured to be able to externally read / write data in a memory unit (1) which stores information related to a secret key in a test mode, reading of the memory unit (1) The control unit (2) that controls whether data can be output to the outside, and the address where all the stored information is reset by turning on the test mode signal (TM) and the data is subsequently written to the memory unit (1). A storage unit (3) for storing information related to the above, and a comparison unit (4) for comparing the stored information in the storage unit (3) with information related to an address for reading data from the memory unit (1), A secret key protection system characterized in that the control unit (2) is enabled for output in the test mode and when the comparison unit (4) obtains a comparison match. 2. A cryptographic processing LSIC including a storage device configured to externally read / write data in a memory unit (1) storing information related to a secret key in a test mode.
In the control section (2) for controlling whether or not the read data of the memory section (1) can be output to the external terminal (TP), all the stored information is reset by turning on the test mode signal (TM), and the subsequent memory A storage unit (3) that stores information related to an address at which data is written to the unit (1), and storage information of the storage unit (3) and information related to an address at which data of the memory unit (1) is read. And a comparison unit (4) for comparing the control unit (2) and the control unit (2) in the test mode. Cryptographic processing LSIC.