JP2016006836A - Light emitting diode substrate manufacturing method and lighting device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time for forming wiring on a substrate.SOLUTION: A light emitting diode substrate manufacturing method comprises the processes of: forming a plurality of catalyst layers on a principal surface of a resin substrate at specified intervals by continuously coating a principal surface of the resin substrate at specified intervals with an ink containing a catalyst; forming conductive layers on the plurality of catalyst layers, respectively, by using an electroless plating method after the process of forming the plurality of catalyst layers; forming additional conductive layers on the conductive layer serving as a cathode after the process of forming the conductive layers by using the conductive layer lying at an end of the plurality of conductive layers as a first electrode and applying voltage so as to deposit metal on the conductive layer used as the first electrode; and connecting a light emitting diode to the additional conductive layer and the conductive layer adjacent to each other at specified intervals by using a connection member after the process of forming the additional conductive layers.

Description

  The present invention relates to a method for manufacturing a light emitting diode substrate and a method for manufacturing a lighting device.

Conventionally, it is known to produce a light-emitting diode substrate on which a light-emitting diode is mounted by photo-etching copper on a substrate to which a copper foil is attached to form a wiring pattern on the substrate (see, for example, Patent Document 1).
On the other hand, it is also known to form a wiring pattern directly on a substrate using a paste containing a metal.

JP 2013-77727 A

However, the method of forming a wiring pattern by photoetching consumes resources wastefully and cannot reduce the cost. On the other hand, in the method of directly forming a wiring pattern on a substrate using a paste containing a metal, the loss of energy due to heat generation is large because the resistivity is high.
On the other hand, as a method of forming a low resistance wiring, there is a method of forming a wiring pattern by plating. However, the electroless plating method has a problem that it takes a long time to deposit a metal and a long time to form the wiring. is there.
Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a light emitting diode substrate and a method for manufacturing a lighting device that can reduce the time for forming wiring on the substrate. And

A method for manufacturing a light-emitting diode substrate according to an aspect of the present invention includes:
Forming a plurality of catalyst layers at a predetermined interval on the main surface of the resin substrate; and
After the step of forming the catalyst layer, using an electroless plating method, forming a conductive layer on each of the plurality of catalyst layers;
After the step of forming the conductive layer, a voltage is applied so that a metal is deposited on the conductive layer serving as the first electrode, with the conductive layer located at the end of the plurality of conductive layers serving as the first electrode. A step of forming an additional conductive layer on the conductive layer serving as the cathode;
After the step of forming the additional conductive layer, a step of connecting a light emitting diode using a connecting member to the additional conductive layer and the conductive layer adjacent to the predetermined interval;
Have

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of forming the plurality of catalyst layers, the catalyst layer is formed in order to form the conductive layer serving as a wiring for connecting a plurality of light emitting diode units in which a plurality of light emitting diodes are connected in series. And
Compared to the first width of the conductive layer connected between the first terminal connected to the positive electrode of the power source and the first connection point arranged on the anode side of the light emitting diode at one end of the light emitting diode unit. , Between the second terminal connected to the negative electrode of the power source and the third connection point electrically connected to the second connection point disposed on the cathode side of the light emitting diode at the other end of the light emitting diode unit. The second width of the conductive layer connected to may be wide.

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of connecting the light emitting diodes, a plurality of third conductive layers are formed between the first conductive layer located at one end and the second conductive layer located at the other end by the step of forming the conductive layer. In this case, a light emitting diode may be connected to the adjacent third conductive layer using a connecting member.

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of forming the plurality of catalyst layers, the plurality of catalyst layers include a first catalyst layer located at one end, a second catalyst layer located at the other end, the first catalyst layer, and the first catalyst layer. One or more third catalyst layers sandwiched between two catalyst layers, and formed on the main surface of the substrate,
In the step of forming the conductive layer, a first conductive layer is formed on the first catalyst layer, a second conductive layer is formed on the second catalyst layer, and a third conductive layer is formed on the third catalyst layer. The conductive layer may be formed.

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of forming the additional conductive layer, the first conductive layer and the second conductive layer are formed on the first conductive layer and the second conductive layer by using an electroplating method as a first electrode. A first additional conductive layer may be formed on the first conductive layer and a second additional conductive layer may be formed on the second conductive layer by applying a voltage so as to deposit metal. .

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of forming the additional conductive layer, the first conductive layer and the second conductive layer are electrically connected to a negative electrode of a power source and are connected to the first conductive layer and the second conductive layer. By maintaining a state where an electrode arranged so that a plating solution containing copper ions is interposed is electrically connected to the positive electrode of the power source for a specified time, copper is deposited on the first conductive layer. The first additional conductive layer and the second additional conductive layer may be formed.

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of connecting the light emitting diodes, a plurality of the light emitting diodes are connected by a connecting member so that a current flows from the first additional conductive layer to the second additional conductive layer through the third conductive layer. May be.

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of forming the plurality of catalyst layers, the plurality of catalyst layers are formed such that the number of the specified intervals is the same as the number of light emitting diodes arranged at the specified intervals,
In the step of connecting the light emitting diodes, soldering may be performed so that the light emitting diodes are arranged at each of the predetermined intervals.

In the method of manufacturing a light emitting diode substrate according to an aspect of the present invention,
In the step of connecting the light emitting diode, a connection member is applied on the conductive layer and the additional conductive layer, and the light emitting diode is connected to the conductive layer and the additional conductive layer using the applied connection member. May be.

  One embodiment of the present invention may be a method for manufacturing a lighting device including the method for manufacturing a light-emitting diode substrate according to any one of the above.

  Therefore, the method for manufacturing a light-emitting diode substrate according to one embodiment of the present invention can reduce the time for forming wirings on the substrate.

FIG. 1 is a diagram illustrating an example of a configuration of a lighting device 1 according to an embodiment which is an aspect of the present invention according to an embodiment which is an aspect of the present invention. FIG. 2 is an equivalent circuit of the illumination device 1 according to the present embodiment shown in FIG. FIG. 3 is an enlarged plan view of the input region RG1 of FIG. FIG. 4 is an enlarged plan view of the return region RG2 of FIG. FIG. 5 is an enlarged plan view of the central region RG3 of FIG. FIG. 6 is an enlarged plan view of the region RG4 of FIG. FIG. 7 is a cross-sectional view taken along the line F-F ′ of FIG. 6. FIG. 8 is a cross-sectional view taken along the line G-G ′ of FIG. 6. FIG. 9 is a flowchart showing an example of a manufacturing method of the light-emitting diode substrate LS shown in FIG. FIG. 10 is a schematic cross-sectional view showing the process of forming the catalyst layer of the light emitting diode substrate LS. FIG. 11 is a plan view showing the distribution of the catalyst layer formed on the main surface of the substrate A after the step of forming the catalyst layer. 12 is a cross-sectional view taken along the line H-H ′ of FIG. 11. FIG. 13 is a schematic cross-sectional view showing a process of forming a conductive layer of the light emitting diode substrate LS. FIG. 14 is a schematic cross-sectional view showing a step of forming an additional conductive layer of the light emitting diode substrate LS. FIG. 15 is a schematic cross-sectional view showing a process of applying solder to the light emitting diode substrate LS. FIG. 16 is a schematic cross-sectional view showing a process of connecting the light emitting diodes. FIG. 17 is a plan view showing a circuit formed on the main surface of the substrate A after the step of connecting the light emitting diodes. FIG. 18 is a diagram showing each wiring resistance constituting the basic circuit. FIG. 19 is a table showing the power consumption in each wiring resistance when manufactured by the manufacturing method of Comparative Example 1. FIG. 20 is a table showing power consumption in each wiring resistance when manufactured by the manufacturing method of Comparative Example 2. FIG. 21 is a table showing power consumption in each wiring resistance when manufactured by the manufacturing method of the present embodiment.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a lighting device 1 according to an embodiment which is an aspect of the present invention. As shown in FIG. 1, the lighting device 1 according to the present embodiment has a power source BT and light emission in which the first terminal T1 is connected to the positive electrode of the power source BT and the second terminal T2 is connected to the negative electrode of the power source BT. A diode substrate LS is provided. The light emitting diode substrate LS includes light emitting diode units (hereinafter referred to as LED units) X1 to X18.

  As shown in FIG. 1, the wiring connected between the first terminal T1 connected to the positive electrode of the power source BT and the first connection point P1 arranged on the anode side of the light emitting diode at one end of the light emitting diode unit. Compared to the first width, the second terminal T2 connected to the negative electrode of the power source BT and the second connection point P2 disposed on the cathode side of the light emitting diode at the other end of the light emitting diode unit were electrically connected. The second width of the wiring connected to the third connection point P3 is wide.

  FIG. 2 is an equivalent circuit of the illumination device 1 according to the present embodiment shown in FIG. As shown in FIG. 2, the LED units X1 to X18 are circuits in which eight light emitting diodes are connected in series. LED units X1 to X6 are connected in parallel, LED units X7 to X12 are connected in parallel, and LED units X13 to X18 are connected in parallel.

Among the eight light emitting diodes included in each of the LED units X1 to X6, the anode of one of the diodes is connected to the positive electrode of the power source BT.
Moreover, the cathode of the other end of the eight light emitting diodes included in each of the LED units X1 to X6 is connected to the anode of the one end of the eight light emitting diodes included in each of the LED units X7 to X12.
The cathode of the other end of the eight light emitting diodes included in each of the LED units X7 to X12 is connected to the anode of the one end of the eight light emitting diodes included in each of the LED units X13 to X18.
Moreover, the cathode of the diode of the other end is connected to the negative electrode of power supply BT among eight light emitting diodes which each LED unit X13-X18 has.

FIG. 3 is an enlarged plan view of the input region RG1 of FIG. As shown in FIG. 3, the anode of the light emitting diode L1-1 is connected to the first bus line, and the cathode of the light emitting diode L1-1 is connected to the anode of the light emitting diode L1-2.
The anode of the light emitting diode L1-i (i is an integer from 2 to 7) is connected to the cathode of the light emitting diode L1- (i-1), and the cathode of the light emitting diode L1-i is the light emitting diode L1- (i + 1). Connected to the anode.
The anode of the light emitting diode L1-8 is connected to the cathode of the light emitting diode L1-7, and the cathode of the light emitting diode L1-8 is connected to the second bus line BL2.
The third bus line BL3 will be described later.

FIG. 4 is an enlarged plan view of the return region RG2 of FIG. As shown in FIG. 4, the cathode of the light emitting diode L17-8 is connected to the second bus line BL2.
The anode of the light emitting diode L18-1 is connected to the first bus line BL1, and the cathode of the light emitting diode L18-1 is connected to the anode of the light emitting diode L18-2.
The anode of the light emitting diode L18-i (i is an integer from 2 to 7) is connected to the cathode of the light emitting diode L18- (i-1), and the cathode of the light emitting diode L18-i is the light emitting diode L18- (i + 1). Connected to the anode.
The anode of the light emitting diode L18-8 is connected to the cathode of the light emitting diode L18-7, and the cathode of the light emitting diode L18-8 is connected to the second bus line BL2 at the third connection point P3.
The third bus line BL3 is a bus line that connects the third connection point P3 and the second terminal T2 connected to the negative electrode of the power source BT.

FIG. 5 is an enlarged plan view of the central region RG3 of FIG. As shown in FIG. 5, the anode of the light emitting diode L9-1 is connected to the first bus line BL1, and the cathode of the light emitting diode L9-1 is connected to the fourth bus line BL4-1.
The anode of the light emitting diode L9-i (i is an integer from 2 to 7) is connected to the fourth bus line BL4- (i-1), and the cathode of the light emitting diode L9-i is the fourth bus line BL4-. Connected to (i + 1).
The anode of the light emitting diode L9-8 is connected to the fourth bus line BL4-7, and the cathode of the light emitting diode L9-8 is connected to the second bus line BL2.

  FIG. 6 is an enlarged plan view of the region RG4 of FIG. As shown in FIG. 6, the width WP of the first bus line and the width WN of the second bus line are, for example, 2.5 mm. The width WR of the third bus line is 5.0 mm, for example. The width WL of the fourth bus line is, for example, 3.0 mm. Thus, the width WR of the third bus line is wider than the width WP of the first bus line and the width WN of the second bus line.

  FIG. 7 is a cross-sectional view taken along the line F-F ′ of FIG. 6. As shown in FIG. 7, the light emitting diode substrate LS includes a resin substrate A, a plurality of catalyst layers B formed on the main surface of the substrate A at a predetermined interval, and a plurality of catalyst layers B. And a plurality of conductive layers C formed on the light emitting diodes L9-2 or L9-3 connected to the adjacent conductive layers C using cream solder S. Here, the cream solder S is obtained by adding a flux to solder powder to have an appropriate viscosity.

  FIG. 8 is a cross-sectional view taken along the line G-G ′ of FIG. 6. Here, the range along the line GG ′ of the first bus line BL1 in the section GG ′ is the range P, and the range along the line GG ′ of the second bus line BL2 in the section GG ′. The range along the range N and the third bus line BL3 in the section of GG ′ is the range along the line GG ′ of the third bus line BL3. The range of the fourth bus line BL4-3 in the section of the range R and GG ′ A range along 'is called a range L.

In the range P, the catalyst layer Bp is formed on the main surface of the substrate A, the conductive layer Cp is formed on the catalyst layer Bp, and the additional conductive layer Dp is formed on the conductive layer Cp.
Similarly, in the range N, the catalyst layer Bn is formed on the main surface of the substrate A, the conductive layer Cn is formed on the catalyst layer Bn, and the additional conductive layer Dn is formed on the conductive layer Cn. .
Similarly, in the range R, the catalyst layer Br is formed on the main surface of the substrate A, the conductive layer Cr is formed on the catalyst layer Br, and the additional conductive layer Dr is formed on the conductive layer Cr. .

  On the other hand, in the range L, the catalyst layer Bl is formed on the main surface of the substrate A, and the conductive layer Cl is formed on the catalyst layer Bl. However, the additional conductive layer is formed on the conductive layer Cl. Absent.

  Next, a method for manufacturing the light-emitting diode substrate LS shown in FIG. 1 will be described with reference to FIGS. FIG. 9 is a flowchart showing an example of a manufacturing method of the light-emitting diode substrate LS shown in FIG.

  (Step S1) FIG. 10 is a schematic cross-sectional view showing a step of forming a catalyst layer of the light emitting diode substrate LS. In this step S1, as shown in FIG. 10, by using the ink jet apparatus IJ, the ink IK containing the catalyst is continuously applied to the main surface of the resin substrate A with a specified interval, thereby the substrate A. A plurality of catalyst layers B are formed on the main surface. Here, the catalyst includes palladium as an example. The specified interval is an interval according to the distance between the anode terminal and the cathode terminal of the light emitting diode. In the step of forming the catalyst layer, ink is applied so that the number of specified intervals is the same as the number of light emitting diodes arranged at the specified intervals.

  Further, in the step of forming the plurality of catalyst layers, the catalyst layer B is formed in order to form a conductive layer serving as a wiring for connecting a plurality of light emitting diode units each having a plurality of light emitting diodes connected in series. As a result, the voltage at both ends of the light-emitting diode unit can be made lower than the voltage at both ends of the circuit in which all the light-emitting diodes are connected in series, and therefore, between the first terminal T1 and the second terminal T2. The required voltage can be lowered. As a result, the voltage of the power supply BT can be kept low. For example, an inexpensive power supply can be used for the power supply BT.

  FIG. 11 is a plan view showing the distribution of the catalyst layer formed on the main surface of the substrate A after the step of forming the catalyst layer. By executing the process of step S1, for example, as shown by a broken line in FIG. 11, a catalyst layer B having a predetermined interval on the main surface of the substrate A is formed. Further, a relay wiring catalyst layer a for forming a relay wiring used for electroplating is also formed.

  12 is a cross-sectional view taken along the line H-H ′ of FIG. 11. As shown in the sectional view of FIG. 12, as the plurality of catalyst layers, the first catalyst layer B1 located at one end, the second catalyst layer B2 located at the other end, the first catalyst layer B1 and the second catalyst layer The third catalyst layers B3a to B3f sandwiched between the catalyst layers B2 are formed on the main surface of the substrate A.

  In addition, although the six third catalyst layers are formed at regular intervals as an example, the number may be five or less, or may be seven or more. Alternatively, the first catalyst layer B1 and the second catalyst layer B2 may be formed at a predetermined interval without forming the third catalyst layer.

  (Step S2) Next, after the step of forming the catalyst layer B in Step S1 described above, the catalyst layer B is heated after the catalyst layer B is dried. For example, heating is performed at 150 ° C. for 30 minutes.

(Step S3) FIG. 13 is a schematic cross-sectional view showing a process of forming a conductive layer of the light emitting diode substrate LS. In step S3, as shown in FIG. 13, a conductive layer C is formed on each of the plurality of catalyst layers B by using an electroless plating method. Specifically, the first conductive layer C1 is formed on the first catalyst layer B1, the second conductive layer C2 is formed on the second catalyst layer B2, and the third conductive layer is formed on the third catalyst layers B3a to B3f. Conductive layers C3a to C3f are formed.
At that time, the conductive layer is formed by electroless plating, for example, for 3 minutes. The electroless plating method is, for example, an electroless copper plating method, and forms a conductive layer by depositing copper.

  FIG. 14 is a schematic cross-sectional view showing a step of forming an additional conductive layer of the light emitting diode substrate LS. The casing HS in FIG. 14 is filled with the plating solution PS.

  (Step S4) Next, in step S4, as shown in FIG. 14, the substrate A after the step of forming the conductive layer in step S3 is plated so that the plating solution PS is interposed between the electrodes ET. Place in the liquid PS. As shown in FIG. 14, the electrode ET is connected to the positive electrode of the power source BT2 via the terminal T3 and the resistor R1, and the first conductive layer C1 and the second conductive layer C2 are connected via a relay wiring (not shown) and the terminal T4. To the negative electrode of the power supply BT. Here, the relay wiring is wiring formed on the relay wiring catalyst layer a in FIG. 11 by an electroless plating method.

  Then, the conductive layer located at the end of the plurality of conductive layers is used as the first electrode, and a voltage is applied so that metal is deposited on the conductive layer used as the first electrode, whereby the conductive layer used as the first electrode is formed. An additional conductive layer is formed on the layer. In the present embodiment, as an example, the first electrode will be described below as a cathode. Specifically, as shown in FIG. 14, a metal is formed on the first conductive layer C1 and the second conductive layer C2 using the first conductive layer C1 and the second conductive layer C2 as cathodes by using an electrolytic plating method. As a result, a first additional conductive layer D1 is formed on the first conductive layer C1, and a second additional conductive layer D2 is formed on the second conductive layer C2.

  More specifically, as shown in FIG. 14, the first conductive layer C1 and the second conductive layer C2 are electrically connected to the negative electrode of the power source BT2, and the first conductive layer C1 and the second conductive layer C2 are connected. 1st additional conductive layer D1 by maintaining the state where electrode ET arranged so that the plating solution intervenes to is electrically connected to the positive electrode of power supply BT2 for a prescribed time (for example, 5 minutes) And a second additional conductive layer D2.

  As an example, the plating solution PS in this embodiment is a solution containing copper sulfate. That is, the plating solution PS contains copper ions. For this reason, in this embodiment, the first additional conductive layer D1 is formed by depositing copper on the first conductive layer C1, and the copper is deposited on the second conductive layer C2. Two additional conductive layers C2 are formed.

  Since the third conductive layers C3a to C3f are not connected to the first conductive layer C1 or the second conductive layer C2, no voltage is applied to the third conductive layers C3a to C3f. No additional conductive layer is formed on the conductive layers C3a to C3f.

Subsequently, in step S5 and step S6, solder is applied on the conductive layer and the additional conductive layer, and the light emitting diode is connected to the conductive layer and the additional conductive layer using the applied solder. FIG. 15 is a schematic cross-sectional view showing a process of applying solder to the light emitting diode substrate LS.
(Step S5) First, in step S5, as shown in FIG. 15, the cream solder S is applied on the first additional conductive layer D1 and the second additional conductive layer D2. Also, cream solder S is applied at two locations on each of the third conductive layers C3a to C3f.

  (Step S6) FIG. 16 is a schematic cross-sectional view showing a step of connecting a light emitting diode. In this step S6, a light emitting diode is connected to the conductive layer adjacent to the additional conductive layer with a specified interval using solder. Specifically, as shown in FIG. 16, the light emitting diode L1 is connected to the first additional conductive layer C1 and the third conductive layer B3a adjacent to each other with a specified interval using solder. Similarly, the light emitting diode L2 is connected to the second additional conductive layer D2 and the third conductive layer B3f adjacent to the second additional conductive layer D2 using a solder.

  Further, as shown in FIG. 16, a plurality of third conductive layers C3a are formed between the first conductive layer C1 located at one end and the second conductive layer C2 located at the other end by the step of forming the conductive layer. When .about.C3f are arranged, a light emitting diode is connected to the third conductive layers C3a to C3f adjacent to each other using solder.

  In the step of connecting the light emitting diodes, the plurality of light emitting diodes are soldered so that a current flows from the first additional conductive layer D1 to the second additional conductive layer D2 via the third conductive layers C3a to C3f. Attach. Thereby, an LED unit (for example, LED unit X1 in FIG. 2) in which light emitting diodes are connected in series as shown in FIG. 2 is formed.

  Further, in the step of connecting the light emitting diodes, soldering is performed so that the light emitting diodes are arranged at predetermined intervals. Thereby, the substrate shown in FIG. 17 is formed.

  FIG. 17 is a plan view showing a circuit formed on the main surface of the substrate A after the step of connecting the light emitting diodes. After the step of connecting the light emitting diodes in step S6, a circuit as shown in FIG. 17 is formed. Here, the cross section taken along the z-z ′ cross section of FIG. 17 is the schematic cross section of FIG. 16. Moreover, in FIG. 17, the cut line CL is shown. Further, the relay wiring a 'in FIG. 17 is a wiring formed on the relay wiring catalyst layer a in FIG. 11 by the electroless plating method and the electrolytic plating method.

  (Step S7) Next, in step S7, the light emitting diode substrate LS is obtained by cutting the substrate A along the cut line CL shown in FIG. As described above, after the step of connecting the light emitting diodes, the substrate A includes a circuit in which a plurality of LED units (for example, the LED units X1 in FIG. 2) in which a plurality of light emitting diodes are connected in series are connected in parallel. Disconnect.

  Subsequently, the manufacturing method of Comparative Examples 1 and 2 is compared with the manufacturing method of the present embodiment. The manufacturing methods of Comparative Examples 1 and 2 are also methods for manufacturing a light-emitting diode substrate showing the equivalent circuit shown in FIG. 2 under plating conditions different from the present embodiment. As shown in FIG. 2, the equivalent circuit is a circuit in which three basic circuits in which six LED units each having eight light emitting diodes connected in series are connected in parallel are connected in series. Hereinafter, the power consumption of the wiring resistance included in this basic circuit will be compared.

  Here, as an example, the current per light emitting diode is 0.1 A and 3 V is applied, and the basic circuit is composed of 48 light emitting diodes, so the total power consumption of the basic circuit is 14.4 (= 0.1 × 3 × 48) W.

  First, each wiring conflict of the basic circuit will be described with reference to FIG. FIG. 18 is a diagram showing each wiring resistance included in region RG5 of FIG. As illustrated in FIG. 18, RP1 to RP5 are positive wiring line resistances included in the first bus line BL1, and RN2 to RN6 are negative wiring line resistances included in the second bus line BL2. RL represents the entire wiring resistance included in the fourth bus line BL4 in the LED units U1 to U6. RR is the resistance of the wiring included in the region RG5 in the third bus line.

(Comparative Example 1)
The manufacturing method of Comparative Example 1 is an example in which wiring is formed by electroless plating for 15 minutes. When the wiring is formed in Comparative Example 1, the thickness of the wiring is 1.0 μm. FIG. 19 is a table showing the power consumption in each wiring resistance when manufactured by the manufacturing method of Comparative Example 1. As shown in FIG. 19, the total power consumption of the wiring portion is 1.06 W, and the power consumption of the wiring portion is 7.33 (= 1.06 / 14.4 × 100)% of the power consumption of the light emitting diode. It is.

(Comparative Example 2)
The manufacturing method of Comparative Example 2 is an example in which wiring is formed by an electroless plating method for 150 minutes. When the wiring is formed in Comparative Example 2, the thickness of the wiring is 3.5 μm. FIG. 20 is a table showing power consumption in each wiring resistance when manufactured by the manufacturing method of Comparative Example 2. As shown in FIG. 20, the total power consumption of the wiring portion is 0.3017 W, and the power consumption of the wiring portion is 2.10 (= 0.3017 / 14.4 × 100)% of the power consumption of the light emitting diode. It is.

(This embodiment)
As an example of the manufacturing method of this embodiment, after forming a wiring by an electroless plating method for 3 minutes, an electric field plating method is further performed for 10 minutes. That is, it is a case where a total of 13 minutes is required for plating by the electroless plating method and the electroplating method.

  When wiring is formed by this manufacturing method, the thickness of the wiring after plating using the electroless plating method is 0.3 μm, and the thickness of the wiring after plating using the electroplating method is 4.0 μm. As a result, in the entire wiring resistance RR included in the fourth bus line BL4, only the plating using the electroless plating method is performed, so that the final wiring thickness is 0.3 μm. On the other hand, since the other wiring resistance is subjected to both plating using the electroless plating method and plating using the electrolytic plating method, the final wiring thickness is 4.3 μm.

  FIG. 21 is a table showing power consumption in each wiring resistance when manufactured by the manufacturing method of the present embodiment. As shown in FIG. 21, the total power consumption of the wiring portion is 0.2753 W, and the power consumption of the wiring portion is 1.91 (= 0.2753 / 14.4 × 100)% of the power consumption of the light emitting diode. It is.

  Thus, the manufacturing method of this embodiment can suppress the power consumption in wiring compared with the manufacturing method of the comparative example 1 in the plating time equivalent to the manufacturing method of the comparative example 1. FIG. Moreover, the manufacturing method of this embodiment can form wiring with low power consumption equivalent to the manufacturing method of Comparative Example 2 in a shorter time than the manufacturing method of Comparative Example 2.

  As described above, in the method for manufacturing a light-emitting diode substrate according to one embodiment of the present invention, the substrate A is obtained by continuously applying the ink containing the catalyst to the main surface of the resin substrate A with a predetermined interval. Forming a plurality of catalyst layers B on the main surface. Furthermore, the method for manufacturing the light-emitting diode substrate includes a step of forming a conductive layer on each of the plurality of catalyst layers B using an electroless plating method after the step of forming the catalyst layer B. Furthermore, in the method of manufacturing the light emitting diode substrate, after the step of forming the conductive layer, the conductive layer located at the end of the plurality of conductive layers is used as a cathode, and a voltage is applied so that metal is deposited on the conductive layer using the cathode. By doing so, the method has a step of forming an additional conductive layer on the conductive layer as the cathode. Furthermore, the method for manufacturing the light emitting diode substrate includes a step of connecting the light emitting diode to the conductive layer adjacent to the additional conductive layer at a predetermined interval after the step of forming the additional conductive layer using solder.

  Therefore, in the method for manufacturing a light-emitting diode substrate according to one embodiment of the present invention, a conductive layer to be a cathode electrode used in electrolytic plating is formed using an electroless plating method, and the conductive layer is formed on the conductive layer by electrolytic plating. An additional conductive layer is formed. Since the electroplating method can increase the thickness of the plating in a short time as compared with the electroless plating method, the time for forming the wiring on the substrate A can be shortened.

Further, in the step of forming a plurality of catalyst layers, the catalyst layer B is formed so as to form a circuit in which a plurality of LED units each having a plurality of light emitting diodes connected in series are connected in parallel, and connected to the positive electrode of the power source BT. From the connection region P1 where currents output from a plurality of series circuits are joined, the negative electrode of the power supply BT is connected based on the width of the conductive layer and the additional conductive layer from the terminal T1 to the anode of the light emitting diode at one end of each LED unit. The catalyst layer B is formed so that the width of the conductive layer up to the second terminal T2 and the additional conductive layer is wide.
As a result, the voltage of the power supply BT can be suppressed, and the width of the third bus line having a large current value can be made wider than the width of the width BL1 of the first bus line. And power consumption of the entire light emitting diode substrate LS can be suppressed.

In the present embodiment, the catalyst layer is formed by applying the ink containing the catalyst with the ink jet apparatus IJ. However, the present invention is not limited to this. The catalyst layer may be formed using a printing method such as flexographic printing or screen printing.
In the present embodiment, the light emitting diode is connected to the conductive layer using solder. However, the present invention is not limited to this, and the light emitting diode may be connected to the conductive layer using another connection member.

  In this embodiment, as a method for forming the catalyst in a pattern, ink containing the catalyst is printed in a pattern on the main surface of the resin substrate. However, the present invention is not limited to this. A copper or complex is printed in a pattern on the main surface of the resin substrate to form a base layer for adsorbing the catalyst, and then the base layer is immersed in a liquid containing the catalyst to A catalyst layer may be formed. Alternatively, the complex surface is coated on the main surface of the resin substrate, and this coated complex is etched by UV exposure to form a complex layer pattern on the main surface of the resin substrate. The catalyst layer may be formed in a pattern by adsorbing the catalyst. Alternatively, by reducing the water repellency (wetability) of the main surface of the resin substrate by ultraviolet exposure or the like, and adsorbing the catalyst on a surface other than the surface exposed to ultraviolet light, that is, the surface where water repellency (wetability) is maintained. The catalyst layer may be formed in a pattern.

  In addition, embodiment is an illustration and the range of invention is not limited to them.

DESCRIPTION OF SYMBOLS 1 Lighting apparatus BT, BT2, Power supply LS Light emitting diode board | substrate X1-X18 LED unit L1-1 to L1-8, L2-1, L9-1 to L9-8, L17-8, L18-1 to L18-8 Light emitting diode BL1 first bus line BL2 second bus line BL3 third bus lines BL4-1 to BL4-7 fourth bus line A substrate B catalyst layer C1 first conductive layer C2 second conductive layers C3a to C3f 1st conductive layer D1 1st additional conductive layer D2 2nd additional conductive layer S Solder IJ Inkjet apparatus IK Ink R1 Resistance HS Case CL Cut line

Claims (10)

Forming a plurality of catalyst layers at a predetermined interval on the main surface of the resin substrate; and
After the step of forming the catalyst layer, using an electroless plating method, forming a conductive layer on each of the plurality of catalyst layers;
After the step of forming the conductive layer, a voltage is applied so that a metal is deposited on the conductive layer serving as the first electrode, with the conductive layer located at the end of the plurality of conductive layers serving as the first electrode. A step of forming an additional conductive layer on the conductive layer serving as the first electrode;
After the step of forming the additional conductive layer, a step of connecting a light emitting diode using a connecting member to the additional conductive layer and the conductive layer adjacent to the predetermined interval;
The manufacturing method of the light emitting diode board | substrate which has this. In the step of forming the plurality of catalyst layers, the catalyst layer is formed in order to form the conductive layer serving as a wiring for connecting a plurality of light emitting diode units in which a plurality of light emitting diodes are connected in series. And
Compared to the first width of the wiring connected between the first terminal connected to the positive electrode of the power source and the first connection point arranged on the anode side of the light emitting diode at one end of the light emitting diode unit, Between the second terminal connected to the negative electrode of the power source and the third connection point electrically connected to the second connection point arranged on the cathode side of the light emitting diode at the other end of the light emitting diode unit. The method for manufacturing a light-emitting diode substrate according to claim 1, wherein the second width of the connected wiring is wide. In the step of connecting the light emitting diodes, a plurality of third conductive layers are formed between the first conductive layer located at one end and the second conductive layer located at the other end by the step of forming the conductive layer. 3. The method for manufacturing a light emitting diode substrate according to claim 1, wherein a light emitting diode is further connected to the adjacent third conductive layer using a connecting member. In the step of forming the plurality of catalyst layers, the plurality of catalyst layers include a first catalyst layer located at one end, a second catalyst layer located at the other end, the first catalyst layer, and the first catalyst layer. One or more third catalyst layers sandwiched between two catalyst layers, and formed on the main surface of the substrate,
In the step of forming the conductive layer, a first conductive layer is formed on the first catalyst layer, a second conductive layer is formed on the second catalyst layer, and a third conductive layer is formed on the third catalyst layer. The manufacturing method of the light emitting diode substrate as described in any one of Claim 1 to 3. In the step of forming the additional conductive layer, the first conductive layer and the second conductive layer are formed on the first conductive layer and the second conductive layer by using an electroplating method as a first electrode. 5. A first additional conductive layer is formed on the first conductive layer and a second additional conductive layer is formed on the second conductive layer by applying a voltage so as to deposit metal. The manufacturing method of the light emitting diode substrate as described in 2 .. In the step of forming the additional conductive layer, the first conductive layer and the second conductive layer are electrically connected to a negative electrode of a power source and are connected to the first conductive layer and the second conductive layer. By maintaining a state where an electrode arranged so that a plating solution containing copper ions is interposed is electrically connected to the positive electrode of the power source for a specified time, copper is deposited on the first conductive layer. The method for manufacturing a light-emitting diode substrate according to claim 5, wherein the first additional conductive layer and the second additional conductive layer are formed. In the step of connecting the light emitting diodes, a plurality of the light emitting diodes are connected by a connecting member so that a current flows from the first additional conductive layer to the second additional conductive layer through the third conductive layer. The manufacturing method of the light emitting diode substrate of Claim 5 or 6. In the step of forming the plurality of catalyst layers, the plurality of catalyst layers are formed such that the number of the specified intervals is the same as the number of light emitting diodes arranged at the specified intervals,
The method for manufacturing a light-emitting diode substrate according to claim 1, wherein in the step of connecting the light-emitting diodes, the light-emitting diodes are connected by a connecting member so that the light-emitting diodes are arranged at the predetermined intervals. In the step of connecting the light emitting diode, a connection member is applied on the conductive layer and the additional conductive layer, and the light emitting diode is connected to the conductive layer and the additional conductive layer using the applied connection member. The manufacturing method of the light emitting diode substrate as described in any one of Claim 1 to 8.   The manufacturing method of the illuminating device which has a manufacturing method of the light emitting diode substrate as described in any one of Claim 1 to 9.

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