JP2015528196A - Structure of continuous and discontinuous base region of high efficiency back contact solar cell and method of forming the same - Google Patents

Abstract

Fabrication methods and structures for multilevel metallization of solar cells are described. In one embodiment, the back contact solar cell includes a substrate having a light receiving front and back to form a patterned emitter and a non-nested base region. The comb doped emitter and base region are formed on the back surface of the crystalline semiconductor substrate. A patterned electrically insulating layer stack including a combination of at least a doped layer and an undoped capping layer is formed on the patterned doped emitter region and the base region. A contact metallization pattern is formed that includes an emitter metallization electrode that contacts the emitter region and a non-nested base metallization electrode that contacts the base region, and the non-nested base metallization electrode extends beyond the base region in the solar cell. It can overlap at least a portion of the aforementioned patterned insulator without causing an electrical shunt. [Selection] Figure 2A

Description

(Cross-reference of related applications)
This application is filed on US provisional application 61 / 658,833 filed May 29, 2012, US provisional application 61 / 816,830 filed April 29, 2013, and 2013. Claims priority to US Provisional Patent Application No. 61 / 827,252, filed May 24, 2005, all of which are hereby incorporated by reference in their entirety.

  This application is priority to US Provisional Application No. 61 / 521,754 filed on August 9, 2011 and US Provisional Application No. 61 / 521,743 filed on August 9, 2011. Filed on August 9, 2012. C. 35 U. of T application PCT / US12 / 00348. S. C. This is a partially pending application of US Patent Application No. 13 / 807,631, filed December 28, 2012, National Stage, all of which are incorporated herein by reference in their entirety.

(Technical field)
The present disclosure relates generally to photovoltaic electric fields. More particularly, the present disclosure relates to methods, architectures, and apparatus associated with high efficiency back contact photovoltaic photovoltaic cells (solar cells).

  Obtaining high cell and module efficiencies with low fabrication costs is important in solar cell development and manufacturing. In some examples, a back contact back junction solar cell architecture (back contact / back junction or BC / BJ) can achieve very high conversion efficiency. In many cases, due to the presence of a back contact, a back junction solar cell has a patterned emitter junction and is formed on the non-sun-facing side (back side) and the sun-struck side (front side). There is no metallization in the metallization layer to achieve maximum coupling that is unobstructed by sunlight.

  In a typical back contact / back junction crystalline silicon architecture (hereinafter BC / BJ) solar cell, the emitter junction and the highly doped base diffusion region provide contact to the bulk of the base solar cell substrate volume. Therefore, it can be formed on the back surface of the solar cell (the side not exposed to the sun). In addition, a highly doped base diffusion region is formed below the base metal contact region to reduce contact recombination and reduce base metal contact resistance. In a typical high efficiency BC / BJ solar cell, the base metal and emitter metal are patterned in the base and emitter diffusion regions such that they extend above the emitter diffusion, respectively, even if the base metal is separated by oxide. Be trapped. This is hereinafter referred to as a nested metal approach, where the various metals are nested in their respective diffusions. The advantage of the nested approach is that it provides resistance to the metal shunt against the heteropolar diffusion. The disadvantage is that the minimum metal width of the base determines the minimum base diffusion width, which results in base diffusion becoming a relatively large fraction of the backside of the solar cell, reducing emitter fraction and electrical Causes increased shielding. This results in a very high minority carrier lifetime (eg,> 1 millisecond) for the wafer or silicon absorber to ensure that minority carriers are in the base but do not recombine under base diffusion. It is necessary to have a range of Thus, the overall manufacturing cost of solar cells is higher due to the higher cost of higher quality wafers.

  Accordingly, there is a need for fabrication methods and designs for doped regions and metallization of solar cells. In accordance with the presently disclosed subject matter, methods, structures, and apparatus for non-nested base diffusion and metallization of solar cells are provided. These improvements substantially reduce or eliminate the disadvantages and problems associated with previously developed solar cells.

  According to one aspect of the presently disclosed subject matter, a fabrication method and structure for multilevel metallization of solar cells is described. In one embodiment, the back contact solar cell includes a substrate having a light receiving front and back to form a patterned emitter and a non-nested base region. The comb doped emitter and base region are formed on the back surface of the crystalline semiconductor substrate. A patterned electrically insulating layer stack including at least a combination of doped and undoped capping layers is formed on the patterned doped emitter and base regions. A contact metallization pattern is formed that includes an emitter metallization electrode that contacts the emitter region and a non-nested base metallization electrode that contacts the base region, and the non-nested base metallization electrode extends beyond the base region in the solar cell. It can overlap at least a portion of the aforementioned patterned insulator without causing an electrical shunt.

  These or other advantages of the disclosed subject matter, as well as additional novel features, will be apparent from the specification provided herein. The intent of this summary is not to be a comprehensive description of the subject, but rather to provide a short overview of some of the features of the subject. Other systems, methods, features and advantages provided herein will be apparent to those of ordinary skill in the art in view of the accompanying drawings and detailed description. All such additional systems, methods, features and advantages contained within this specification are intended to be within the scope of the claims.

  The features, characteristics and advantages of the disclosed subject matter will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like shapes indicate like feature elements.

Fig. 6 shows a plan view of the back side of a solar cell showing a nested base design. FIG. 6 shows a plan view of the backside of a solar cell showing a non-nested base design. FIG. 6 shows a plan view of the backside of a solar cell showing a uniformly distributed continuous / non-nested base design. FIG. 5 shows a plan view of the backside of a solar cell showing a uniformly distributed selectively discontinuous / non-nested base design. FIG. 6 shows a plan view of the backside of a solar cell showing a uniform base pattern with a parallel base design. FIG. 3B is a diagram of a corresponding screen printing design for forming the pattern of FIG. 3A. FIG. 6 shows a plan view of the backside of a solar cell showing an alternative uniform base pattern with alternating base designs. FIG. 3B is a diagram of a corresponding screen printing design for forming the pattern of FIG. 3A. FIG. 6 shows a plan view of the backside of a solar cell showing an alternative non-nested base pattern. FIG. 6 shows a plan view of the backside of a solar cell with a non-nested base pattern focused on exemplary dimensions. Fig. 3 shows a distributed emitter and base laser pattern. 2 is a photograph showing a selective emitter (SE) and a base opening. FIG. 6 is a photograph showing a selective emitter (SE) and base opening within an emitter and base contact. Figure 3 shows laser annealing damage at a selective emitter aperture. Figure 5 shows laser annealing damage at a selective base opening. Fig. 5 shows laser annealing damage of contacts at selective emitter openings. Fig. 5 shows laser annealing damage of a contact at a selective base opening. It is a photograph which shows the laser ablation spot before annealing. It is a photograph which shows the laser ablation spot after annealing by 30 nanosecond UV laser. FIG. 5 is a minority carrier lifetime (MCL) map of a silicon substrate after oxide ablation, specifically showing the MCL improvement obtained after laser annealing of the ablation spot. 1 is a multi-station substrate laser processing tool. FIG. 10B is a diagram of the tool of FIG. 10A holding multiple wafers. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. It is sectional drawing which shows the solar cell after the process step in an amorphous silicon mask process flow. FIG. 4 is a minority carrier lifetime (MCL) map of a silicon substrate after oxide ablation, specifically showing the improvement in MCL obtained when amorphous silicon is used as a hard mask. It is the general process flow regarding formation of a back contact back junction solar cell. It is a typical manufacturing process flow regarding formation of a back contact / back junction cell.

  The following description should not be construed in a limiting sense, but is made for the purpose of illustrating the general principles of the present disclosure. The scope of the present disclosure should be determined with reference to the claims. Exemplary embodiments of the present disclosure are illustrated in the drawings, wherein the same reference numerals are used to refer to the same and corresponding parts of each drawing.

  While this disclosure is described with reference to specific embodiments such as crystalline silicon and other fabrication materials, those skilled in the art will appreciate the principles discussed herein without undue experimentation. Can be applied to any material, technology area, and / or embodiment.

  The disclosed subject matter specifically uses a thin crystalline semiconductor absorber such as single crystal silicon having a cell absorbing layer (or substrate), preferably from less than about 1 micron (1 μm) to up to about 100 microns. Various structures for high-efficiency back-junction / back-contact solar cells ranging in thickness up to (100 μm), and more particularly from about 1 micron (1 μm) to about 50 microns (50 μm) And a manufacturing method. Also, the cell structures and fabrication methods provided range from about 100 μm to about 200 μm thick (this also includes the thickness range of more conventional CZ or FZ wafers), thicker crystalline semiconductor substrates or absorbers Applies to Crystalline solar cell substrates can be produced by chemical vapor deposition (CVD) methods including epitaxial growth (such as atmospheric pressure epitaxy) or other crystalline silicon material formation techniques (but not limited to so-called slices without slicing or delamination methods). , Metal stress induced delamination, or laser). In connection with all aspects of processing very thin crystalline semiconductor solar cell substrates, various embodiments of the fabrication method include other types of materials, including cut-free cleavage methods such as implantation-assisted wafer cleavage methods, and May extend to a wafer-based approach. Important attributes of the various cell embodiments provided are substantially reduced semiconductor (eg, silicon) material consumption, very low manufacturing costs, high cell efficiency, and relatively high energy production, and thus solar The improvement of photovoltaic module performance is presented. Specifically, this arises from the specific cell design architecture and fabrication method embodiments of the disclosed subject matter, which require the fabrication of back junction / back contact solar cells using thin crystalline semiconductor layers and are thin It brings very high conversion efficiency to the crystalline semiconductor substrate and becomes very inexpensive.

  The present disclosure is also described with respect to particular embodiments such as back contact solar cells using single crystal silicon substrates having a thickness in the range of 10-200 microns and metallization layers of other described fabrication materials. However, those skilled in the art will understand that alternative semiconductor materials (gallium arsenide, germanium, polycrystalline silicon, etc.), metallization layers with metallization stacks, technology areas, and / or without undue experimentation The principles discussed herein can be applied to other fabrication materials, including embodiments. Embodiments of the novel doped region formation of the present invention that can be applied to any architecture, such as front contact, back contact / back junction, or even back contact / front junction solar cell, specifically include back contact / back junction crystalline silicon It is shown in the present invention in terms of architecture (hereinafter BC / BJ).

  The present application provides a robust method to achieve a non-nested base metal design. Non-nested metal makes the high concentration base diffusion less than the width of the base metal, ensuring that there is no path between the base metal and the underlying emitter to break the electrically insulating layer such as an oxide. Can be small. This is achieved by ensuring that there are no through-dielectric pin holes in the dielectric stack that separates the base metal from the emitter diffusion, allowing a non-nested base metal design without creating an electrical shunt. . In certain embodiments, this can be achieved using multiple (eg, at least two) APCVD deposited doped and undoped (capping) dielectric layers. These are typically silicon dioxide (SiO2) layers, but can include silicon nitride (SiNx) and / or amorphous silicon (a-Si), and / or aluminum oxide (Al2O3) layers. (Doped and / or undoped in each example). By depositing multiple (at least two) APCVD layers in different runs, the statistical probability of alignment of any pin hole through the entire dielectric stack is dramatically reduced. In another embodiment, a thermal oxide step can be added after, before, or during the APCVD dielectric layer to further provide robustness to ensure that shunt pin holes are not present. (See in detail US patent application Ser. No. 13 / 807,631, which is hereby claimed and incorporated by reference in its entirety).

  Non-nested metallization designs can be used with either continuous or discontinuous (discrete base array) based diffusion. For continuous base diffusion, the base can be a series of straight lines (columns). The base metal overlaps with these diffusion parts, but is not necessarily contained within the diffusion part. In the case of discontinuous base diffusion, these diffusions can be only surrounding isolation islands that require isolation base contacts. The diffusers can be circular, rectangular or other geometric shapes, but can be connected to each other by base metal lines.

  The advantage of discontinuous base diffusion is that the base resistance can be minimized through silicon while maintaining the emitter fraction constant (at a relatively high level) for a given metal pitch. Decreasing the base diffusion region increases the distance between base diffusions for a given metal pitch while allowing material relaxation life for BC / BJ cells, and thus the curve of the solar cell with increased base resistance. Causes a potential decrease in factors. Possible embodiments of the present invention alleviate these limitations and facilitate the design and fabrication of highly efficient solar cells. The present invention allows a non-nested base design architecture to effectively provide a relatively low base resistance due to the greater flexibility of the discontinuous selective / distributed base diffusion.

  In one embodiment, the base islands are isolated (discrete base islands) but connected on the same straight line by a single base metal line that is periodically connected to the silicon base by a base contact inside the isolated base island (Or arranged along a column). Inevitably, this design is non-nested because the connecting base metal line extends between isolated base diffusion islands above the emitter region (on the dielectric layer covering the doped emitter region). Thus, the success of a discontinuous base pattern is highly dependent on the ability to run a non-nested base metal without shunting. This is ensured by the process technique described above. In another case, the distributed base islands under a given base metal line have more than a single collinear row (or column) and two or more rows (or more) with offset island locations (or Column). The general architecture provides flexibility to improve electrical performance. Details of the structure and advantages of these discontinuous schemes are shown schematically in the following sections.

  Distributed discontinuous base diffusion (such as the discrete base islands shown in US patent application Ser. No. 13 / 807,631, this application claims priority and incorporates in its entirety) and contact formation schemes are novel In the context of non-nested metal architecture, the base metal (defined as the metal in contact with the base diffusion region) is a robust, non-shunted method of dielectric passivation layer. It extends freely over the upper emitter diffusion region (covered by a dielectric layer above the doped emitter region) (and vice versa if desired). This design can also be referred to as spot-in-spot (SIS). This name stems from the fact that the isolated and discontinuous contact spots become open inside the discontinuous base diffusion region. The doped dielectric film is patterned to form discontinuous regions of the heavily doped region (n-type or p-type) of the same type (n-type or p-type) as the relatively lightly doped base. Discontinuous (or discrete islands) heavily doped base structures are arranged in a geometrically optimal manner, but are still under the base metal and seem to minimize each other's distance, Diffusion resistance loss due to lightly doped base is minimized. Also, for very thin solar cell absorbers, the combination of these diffusion patterns and optimal diffusions with doped dielectric films function as good electrical insulators, and the electrical cell between the base and emitter regions of the solar cell. The risk of mechanical shorts or shunts can be reduced.

  As described in detail below, there are inherent independent advantages of these aspects. Applicants present several design concepts to illustrate non-nested and / or discontinuous base architectures. Solar cells are similarly described in the context of the advantages of the present invention, particularly high efficiency crystalline semiconductors (including back contact / back junction single crystal or polycrystalline silicon).

  A) In a commonly used architecture, the base metal is nested inside the base diffusion to avoid cell shunting (specifically, it is injected to contact the lightly doped base). This metallization nesting limitation and the consequences of the resulting design rules require a minimum high concentration base diffusion region determined by the minimum base metal width. This results in reduced emitter fractions and costly long-life wafers to ensure that photoexcited carriers can reach the emitter without recombination under long base diffusion. The non-nested base allows for a larger emitter fraction area on the back surface, which is a desirable cell design attribute for high cell efficiency. The non-nesting of the metallization pattern and the resulting enhancement of the emitter region fraction leads to a slight carrier recombination loss (ultra-thin cells having an absorber thickness of less than about 100 microns, preferably less than 80 microns, and / Or as particularly highly desirable for large area cells having a cell area of at least 125 mm × 125 mm and preferably 156 mm × 156 mm or greater). Non-nested base metal results from good dielectric insulation resulting from the dielectric layer. The evolution of cell design is based on the following constraints. The minimum base and emitter metal widths are based on the desired metal line resistance requirements and are one of the methods used to pattern the line width using direct patterning picosecond or femtosecond laser ablation. First determined based on available resolution. For a given cell size (area) and maximum thickness of metal (limited by cost and stress on the absorber substrate), a minimum metal line width is determined. This is the case for conventional single metal level metallization. For multilevel cases (one embodiment of the present invention for multilevel cell metallization is dual level), the metal lines in contact with the cell contacts can be made more resistive (these are interlayer dielectrics). The current is locally removed before being taken vertically through a via connected to a second level metal or metal-2 (M2), separated from metal-1 (M1) by a body or electrically isolated backplane. (Because it transmits a short distance), it provides the flexibility of a smaller width. With the metal width fixed using the above criteria, the traditional nested architecture requires the base diffusion to be wider than this metal width due to the required design rules governed by the patterning alignment resolution, which is relatively large. This leads to a relative loss of the base diffusion region and the emitter region fraction. This results in stricter requirements on the minority carrier lifetime or electrical quality of the absorber substrate, making it more expensive. The proposed non-nested approach overcomes the above limitations and allows a very large emitter fraction. This results in reduced lifetime requirements for equivalent efficiency performance, thus reducing substrate cost. Also, embodiments of the present invention can allow backside junction and backside contact architectures to be compatible with thinner substrates, which do not require quality, i.e. severe high bulk life without losing performance. Can grow moderately. An example of this substrate is silicon grown epitaxially on porous silicon that can provide a bulk lifetime that exceeds 300 μs to 500 μs for n-type epitaxial silicon growth, but typically does not exceed 1 ms. Other embodiments start with a relatively low lifetime (200-500 μs) CZ wafer and are generally thinned to a range of 5 μm to 100 μm, preferably 20 μm to 80 μm. Thus, the present invention not only reduces the cost of conventional backside contact architecture (lower requirement for silicon substrate quality), but also a very efficient backside contact backside junction thin single crystal or multiple. Priority is given to enabling crystalline solar cells.

B) Non-nested architectures can have either a continuous or discontinuous (discrete island) base. In discontinuous base (also called distributed base or discrete island base design), the dielectric is patterned to form discrete base diffusion islands sporadically and discontinuously (base diffusion in the continuous sea of emitters). Thus, the need for a highly efficient design provides the flexibility to place these diffusions to guarantee contact. Discontinuous schemes, along with non-nested bases, provide myriad design possibilities.
1. In one embodiment of the design, for a given metal pitch, it allows a reduction in the distance from one base diffusion island to the nearest island (and hence a reduction in base resistance).
2. The majority of BC / BJ cells are covered with an emitter region on the back side of the solar cell (the side not exposed to the sun) with a base diffusion region tied at the sea of the emitter. With the non-nested and discontinuous base concept, all emitter regions can remain contiguous with a much larger emitter fraction that effectively increases the total carrier collection efficiency of the solar cell.
3. Non-nested and discontinuous base designs offer the possibility of increasing the emitter fraction region by reducing the heavily doped base diffusion region needed to reduce contact recombination, which in turn has some penalty on the diffusion resistance. Helps minimize electrical shielding without.

  C) The ability to provide a wider metal width with a discontinuous base design allows for significant cost savings. This provides design flexibility without a fully connected base, i.e., base split diffusion or discrete islands, resulting in a larger emitter fraction area and shorter base pitch.

There are various requirements for the design and fabrication of highly efficient and cost effective solar cells. These are described below with respect to non-nested discontinuous bases (ie, distributed or discrete base islands). The general method can extend to multi-level metallization schemes and is equally applicable to both conventional thick solar cells as well as very thin silicon solar cells. Very thin (e.g., thinner than about 80 micron thick absorber layers) solar cells utilizing the methods and structures of the present invention are epitaxial lift-off, chemically etched based thinned wafers (130 micron to 200 micron starting). CZ wafer), ultrathin crystalline silicon with a crystalline silicon absorber layer in the thickness range of a few microns to tens of microns formed by proton implantation, stress induced splitting, laser splitting, or other thin silicon slicing techniques Includes solar cells.
1. A method of placing an electrically insulating dielectric layer underneath the metal and diffusion (deposition, screen printing, etc.), this layer is a very effective dielectric to separate the metal from the silicon, and the base and emitter regions of the solar cell It functions as both a source of dopant for forming a diffusion part.
2. A method of patterning base diffusion and forming a contact region with a dielectric to connect to metal.
3. A method for depositing and patterning metal.

  In step 1, techniques such as atmospheric chemical vapor deposition (APCVD) or patterned screen printing can be utilized to deposit the doped dielectric film. Care must be taken in choosing the dielectric film and technique to be suitable to ensure good optical quality and good contact for both n-type and p-type diffusion of silicon. For APCVD (and / or plasma grown CVD), high temperature furnace annealing can be used to drive in the dopant. After deposition of the diffusion source dielectric, these films are preferably annealed at a relatively high temperature (typically 900 ° C. to 1150 ° C.) to drive the dopant into the silicon substrate. Furnace annealing is an important aspect of forming the diffusion. Care must be taken to change these dopant concentrations and drive in furnace annealing to achieve very low surface recombination rates to form these diffusions by forming good emitters. In one embodiment of the present disclosure, the base and emitter diffusion dielectric material comprises an undoped dielectric (p-type or n-type silicon dioxide called boron-doped glass, p-type BSG, or phosphorus-doped glass, n-type The doped APCVD silicon oxide with at least one of the doped dielectric layers having a capping layer of PSG), which is then patterned using a pulsed picosecond (or pulsed femtosecond) laser. Once formed, this can remove the oxide while stopping on silicon without causing significant ablation damage to it. Following patterning of a kind of doped APCVD layer (such as BSG), the deposition of other dopant type (such as PSG) APCVD layer was pre-designated for both types of doped layers (BSG and PSG). It is possible to make contact with silicon in the pattern formation region. These doped oxide layers function as boron and phosphorus sources that ultimately diffuse into silicon to form the emitter and base diffusions, respectively. The fractional area of contact with each layer of silicon is determined by the pattern geometry. When this system with a doped layer is annealed at high temperature, the resulting back side of the resulting solar cell consisting of both the emitter (made from BSG) and base (made from PSG) diffusions is formed simultaneously. Is done. The individual fractions of these diffusers are precisely controlled and determined by a predetermined laser direct write ablation pattern. Alternatively, screen printed dopant paste / ink can be used to form the patterning diffusion. An important requirement of these dielectric layers is to electrically insulate the absorber layer by diffusion from the metal layer. The metal layer need only be in contact with the absorber, in which case it is intended to do so by opening a clear contact hole. The choice of dielectric material needs to be conductive to produce a good rearview mirror with no cell holes and a cell metallization layer for optimal light absorption within the solar cell. The presence of pin holes is undesirable because it provides a current shunt path between the non-nested base metal and the emitter.

  With regard to step 2 for the patterning method for the diffuser, patterning can be performed using blanket deposition followed by laser ablation or using standard lithography / etching techniques. The dielectric layer can also be directly patterned with a suitable dopant paste or liquid using screen printing or stencil printing or ink jet printing (or aerosol jet printing). The conventional BC / BJ solar cell of FIG. 1 has a comb-shaped nested metal design in which the emitter and base metal lines are inside the emitter and base diffusions, which are alternately and alternately combined. An important embodiment of the invention relates to the formation of non-nested base diffusion patterns in both comb and non-comb emitters and base diffusions. As explained in the previous section, the base diffusion can be either continuous or discontinuous.

  The base pattern for continuous / non-nested design and discontinuous / non-nested design is described in FIG. An important enabling factor for non-nested designs is the very insulating dielectric that allows the base metal to extend over the emitter diffusion without the risk of killer shunts. As mentioned above, a discontinuous base is not limited, but can be used for a variety of purposes, such as reducing the base diffusion resistance to obtain a fill factor and reducing the base diffusion region to improve electrical shielding. Can be used for. After formation of the base diffusion region, the contact holes are formed by laser ablation or using standard lithography and etching techniques. Various designs in the foregoing discontinuous example are shown in FIGS. 3a, 3b and 3c. As shown in FIG. 3a, the emitter fraction region increases to reduce current collection loss in the base diffusion region due to a decrease in electrical shielding. The pitch between the base diffusion and the contact area percentage can be further optimized to obtain the same diffusion resistance with better current collection capability. Alternatively, this design can be modified as shown in FIGS. 3b and 3c to further reduce the base diffusion resistance without compromising electrical shielding. This design embodiment is particularly advantageous for thin single crystal solar cells where the fill factor is limited by a high base resistance and / or the front field is not desired or possible.

Finally, several methods can be introduced with respect to step 3 for metal deposition and patterning (or direct writing deposition of patterned metal layers). This includes techniques such as metal sputtering or vapor deposition on top of the aforementioned dielectric layer. The deposited metal can then be patterned and isolated to form base and emitter metals using techniques such as picosecond based laser ablation. Alternatively, a plurality of direct writing techniques such as, but not limited to, screen printing, stencil printing, mask thermal (or arc or plasma) metal spraying, ink jet or aerosol printing, followed by an annealing or activation step. Thus, base and emitter metals can be formed. For a continuous design, the base and emitter pitch can be the same, making the metal pattern symmetrical for both the ideal emitter and base metal for optimal solar cell current collection. In the following description, specific process methods are described in detail to achieve a non-nested and discontinuous solar cell design. The method is described in connection with a thin single crystal silicon solar cell with back contact / back junction using an epitaxial silicon lift-off method, which can be of any thickness (including standard crystal silicon wafer based cells). For example, it can be used for solar cells (with a thickness range of 100 μm to 200 μm using CZ or FZ wafers). The flow is described in Table 1 below.

A thin doped dielectric layer of similar dopant type (in one embodiment, p-type boron) as needed for the emitter can be obtained using APCVD, PECVD, thermal diffusion (from a gas-based dopant source), Alternatively, it is deposited on the substrate using direct patterning, writing methods such as screen printing, ink jet or aerosol jet printing. For dopant film blanket deposition after deposition, the dielectric film is etched using picosecond laser ablation. The etch pattern reflects the silicon base and emitter regions (emitter derived from the patterned layer, and base derived from subsequent dielectric film deposition) and can be either continuous or discontinuous. This is followed by a second dielectric film with an opposite type of dopant (including phosphorus) to form a highly doped base diffusion region. Alternatively, the second dopant layer can be deposited using a direct writing method. This is followed by thermal annealing to activate both types of dopants in one step. This anneal can be an inert gas environment such as nitrogen or argon, optionally followed by a short-term anneal at the same temperature in an oxygen-containing environment. The purpose of the oxygen environment is to form a thermal oxide interface through the dielectric layer with the dopant diffused. This is followed by another picosecond laser ablation of the oxide to form contact openings for subsequent metallization connections to the base and emitter regions of the absorber layer. Thin metals (preferably including aluminum or alloys containing aluminum and silicon) are deposited using blanket plasma sputtering or evaporation or ion beam deposition. This requires subsequent patterning that can be accomplished using a myriad of techniques including, but not limited to, picosecond laser ablation using a suitable laser wavelength, such as near infrared wavelengths. . Alternatively, use direct writing or screen printing (or aerosol printing, ink jet printing, and stencil printing) of a pre-patterned metal layer (eg, suitable screen printable aluminum and / or aluminum-silicon alloy paste). Can do. In some cases, this metal deposition needs to be followed by sintering or annealing to harden and activate the patterned metal layer. In certain processes that produce thin single crystal silicon solar cells using an epitaxial silicon lift-off method, the thin silicon layer is then subjected to a second permanent to continue the remaining cell processes such as texture, passivation, and metallization. Can be attached to the carrier. Variations of the process flow are described in Table 2 below. In this flow, the process flow is the same up to the last metallization step. The copper plating flow is replaced with dry PVD (such as evaporation and / or plasma sputtering) based metal deposition in combination with the use of a laser (which can be a pulsed nanosecond laser) to insulate the PVD metal layer. Pattern formation.

Yet another process flow is a variation of the above flow for a thin wafer based solar cell and is shown in Table 3 below. Here, instead of grown epitaxial silicon, a standard CZ wafer can be thinned to make a very efficient solar cell. Note that instead of the absence of porous silicon, epitaxy and stripping steps, these steps are replaced by post-lamination saw damage removal and etch back steps to thin the wafer.

  Finally, it is possible to remove laser damage caused by using picosecond (or femtosecond) lasers for both continuous and discontinuous (SIS) architectures using either wet or dry processes. is there. A dry method to reduce / eliminate laser damage is to perform laser annealing after opening the laser contacts. This can be done using a nanosecond laser. Another method for removing laser damage is to use a hard mask (usually a-Si), pattern the hard mask, and wet etch the oxide using the hard mask. Thus, the picosecond laser does not “see” the silicon.

Laser annealing of laser induced ablation damage Laser ablation of the transparent passivation layer results in at least some laser induced damage to the silicon substrate. Since passivation layers such as silicon oxide and aluminum oxide are transparent to wavelengths up to UV (355 nm), the removal of the transparent layer is performed by melting and depositing the underlying silicon. Using ultrashort pulse lengths and UV wavelengths minimizes the depth of affected silicon, but some damage still exists. FIG. 5 is a representative pattern of distributed selective emitter and base openings with contacts centered inside these regions. 6A and 6B are SEM micrographs showing selective emitter and selective base openings, and contacts in these openings, respectively. These ablation spots were made using a laser with a pulse length of 10 picoseconds and a UV wavelength. Still some surface damage can be seen.

  As disclosed herein, the ablation region is annealed to reduce or eliminate damage that occurs during the ablation process. After completion of the pulsed laser ablation, the ablation region is annealed with another suitable pulsed laser beam that anneals the damage. For the distributed selective emitter and base openings, each ablation spot is annealed using a synchronized laser that originates from an annealing laser. For annealing, suitable lasers typically have a pulse length in the long nanosecond range, preferably in the range of about 10-500 nanoseconds and a wavelength of 532 nm. However, other lasers with shorter or longer pulse lengths and other wavelengths can be used depending on the extent of the ablation laser damage to be annealed. 7A and 7B schematically show spots due to spot annealing of damaged silicon in selective emitter (SE) and selective base (SB) ablation, while FIGS. 7C and 7D use laser annealing. Similar spots are shown by spot annealing of laser damage in the contact ablation region. Corresponding optical micrographs are shown in FIGS. 8A and 8B. FIG. 8A shows the laser ablation spot before laser annealing, while FIG. 8B shows the spot after laser annealing. The removal of laser damage of the ablation spot by laser annealing can be clearly seen.

  FIG. 9 shows the effective minority carrier lifetime (MCL) improvement obtained with laser annealing, where half of the wafer was patterned by laser ablation compared to half that did not receive the laser annealing treatment.

  In one scheme, laser annealing of the ablation region is performed with at least one doped oxide layer covering the ablation region. In this case, melting to silicon during laser annealing results in melt uptake or absorption of p-type (eg, boron) and n-type dopants (eg, phosphorus) from the overlying BSG and PSG films to the molten silicon, respectively. This is driven in by furnace annealing, resulting in a high concentration of these dopants near the surface in addition to dopants having a diffusion error function profile from a relatively constant dopant source. This results in a high-low junction for these doped junctions, leading to a reduction in carrier absorption at the silicon surface and consequently improving cell efficiency.

  A preferred cost effective laser device configuration is a multi-station platform that allows parallel processing at different stations. FIG. 10 shows the configuration of a tool having four stations. The wafer rotates from one chuck to another performing different steps of the ablation / annealing process. As shown in FIG. 10, the wafer is mounted on station 1 and moved to station 2 for reference detection of the accuracy of laser ablation patterning and alignment laser annealing. Laser ablation is performed at station 3 and then annealing is performed at station 4. Note that this scheme allows parallel processing on different chucks, and throughput is controlled by the slowest process in this sequence. In order to improve throughput, the number of wafers on the chuck can be increased with simultaneous increases in laser ablation and laser annealing to multi-wafer capability. FIG. 10B shows four wafers per chuck.

Application of an Ablation Mask to Prevent Laser Ablation Damage A scheme is disclosed herein that uses a thin layer of mask material to absorb the laser beam during ablation to prevent laser damage. Such open areas (with the mask material removed) can be further opened to silicon by wet etching the underlying dielectric layer. In practice, in this scheme, the mask thin layer is first patterned using an ablation laser, and then this pattern is transferred to the silicon by wet etching of the opening dielectric. Since the intensity of the laser beam reaching the silicon substrate is low, there is no laser damage and the silicon minority carrier lifetime (MCT) is not affected. Any non-conductive film that is resistant to wet etching used to pattern the dielectric can be used as a mask.

  11A-11I schematically illustrate a solar cell structure in a process step that uses a thin layer of amorphous silicon (α-Si) as a patterning mask for laser ablation.

  FIG. 12 shows the minority carrier lifetime map of the wafer, the upper half does not use the ablation mask scheme, but the lower half uses the α-Si mask scheme. No lifetime degradation was seen in the lower half of the wafer.

  The disclosed subject matter can be directly applied to the formation of highly efficient back contact back junction solar cells utilizing multilayer back surface metallization. Compared to the front contact solar cell, the all back junction back contact solar cell has all the metallizations (both base and emitter metallization and busbar) placed on the cell back side, Sunlight shielding due to metal runners on the contact side) (emitter metal finger and busbar optical shielding losses in the case of conventional front contact solar cells) can be eliminated. Cell metallization (both base and emitter contacts) can also be formed on the same side (opposite to the sun) to eliminate optical shielding losses, but both base and emitter electrodes May need to be contacted on the same side, so in some backside contact designs, cell metallization can be more complex (however, in some examples, base and emitter contacts on the same side are May simplify the interconnection of solar cells at the module level).

  In some examples, a comb metallization scheme that requires high fidelity of the metal pattern can be used. Also, since the metallization pattern geometry may be made smaller and smaller to increase cell efficiency, the required thickness of the metallization layer is also similar, for example, solar having dimensions of 125 mm × 125 mm to 156 mm × 156 mm. As a highly conductive metallization layer (such as copper or aluminum) on the cell, it can increase significantly, such as 30-60 microns.

  In addition, cell metallization can be partitioned into two metal layers / levels to reduce the required metallization thickness, and the backplane material (such as a polymer sheet) can be between two metallization layers. To reduce the stress induced from the thick, high conductance second metallization level. In other words, the backplane material separates the two metallization layers, provides structural support to the solar cell substrate, and allows scaling to large area back contact solar cells. Thus, each layer, i.e., the first metallization layer, the backplane material, and the second metallization layer can be separately optimized for cost and performance. Also, in some dual level metallization embodiments, the two metal levels are patterned orthogonal to each other, and the second (last) metal level is compared to the first (on-cell) metal level. Has very few rough fingers.

  Also, the following exemplary back-junction back contact solar cell design and manufacturing process described herein includes two metallizations separated by a backplane layer that is electrically isolated and mechanically supported. Although levels (double layer metallization) can be utilized, the disclosed subject matter requires a real-time in-situ process laser with perforation endpoint detection and multi-level metallization patterns and methacrylate stacks (eg, , Al / NiV / Sn first level metallization layer), which can be applied to any manufacturing embodiment. In some examples, any combination of backplane and metallization layer functions as a permanent structural support / reinforcement without significantly impairing solar cell output or increasing solar cell manufacturing costs. , Embedded high conductivity (aluminum and / or copper) interconnects for high efficiency thin crystalline silicon solar cells can be provided. A laser process using a scheme for producing high efficiency solar cells, particularly sub-50 micron thick silicon substrates based on thin film crystalline silicon solar cells is presented herein.

  In some examples, the non-nested base region designs and methods disclosed herein can be applied and integrated into current back contact back junction solar cell structures and fabrication processes. FIG. 13A is a general process flow for forming a back contact back junction solar cell that can utilize a non-nested base region, for example. Specifically, FIG. 13A is a general process flow focused on the main process of a thin crystalline silicon solar cell manufacturing process that is tested using a thin epitaxial silicon lift-off process, which significantly increases silicon usage. Therefore, the conventional manufacturing step is eliminated, and a low-cost and highly efficient backside junction / backside contact single crystal cell is created. The process flow of FIG. 13A shows a reusable template and epitaxial silicon deposition on a porous silicon release layer that can be integrated using non-nested base region design and formation methods as disclosed herein. FIG. 4 illustrates the fabrication of a solar cell having a stacked backplane for smart cell and smart module design formed using the same.

  The process shown in FIG. 13A typically starts with a reusable silicon template made from a p-type single crystal silicon wafer, on which a thin sacrificial layer of porous silicon is formed (eg, current). In the presence of HF / IPA wet chemistry by an electrochemical etching process with a surface modification process). The starting material or reusable template can be, for example, a single crystal silicon wafer formed using a crystal growth method such as FZ, CZ, MCZ (magnetically stabilized CZ), and further on the silicon wafer. Including a grown epitaxial layer; The semiconductor doped type may be either p-type or n-type, and the wafer shape (most commonly square), but any geometric or non-geometric shape such as quasi-square or circular Can do.

  Once a porous sacrificial silicon layer is formed that serves as both a high quality epitaxial seed layer as well as a subsequent isolation / lift-off layer, a thin layer of in-situ doped single crystal silicon (eg, from a few microns) A layer thickness in the range of up to about 70 microns, or a thickness of less than about 50 microns) is formed, also referred to as epitaxial growth. In-situ doped single crystal silicon layers can be formed by atmospheric pressure epitaxy using chemical vapor deposition or CVD processes in an ambient atmosphere containing, for example, silicon gas such as trichlorosilane or TCS and hydrogen and hydrogen. .

  Prior to backplane lamination, solar cell base and emitter contact metallization patterns, for example using screen printing or thin layers of sputtered (PVD) or deposited aluminum (or aluminum silicon alloy or Al / NiV / Sn stack) material layers Is formed directly on the back surface of the cell. A first layer of metallization (referred to herein as M1) defines a solar cell contact metallization pattern, eg, fine pitch IBC conductor fingers that define the base and emitter of a comb back contact (IBC) cell. The M1 layer takes the solar cell current and voltage and transmits the solar cell power to a second level / layer of higher conductivity solar cell metallization (referred to herein as M2) formed after M1. To do.

  After most of the solar cell processing steps are completed, the ultra-low cost backplane layer is bonded to a thin epi layer as a permanent cell support and reinforcement and to support the high conductivity cell metallization of the solar cell can do. The backplane material is thin (e.g., in the range of about 50-250 microns, and in some instances 50%, such as inexpensive prepreg materials commonly used for printed circuit boards that meet cell process integration and reliability requirements. (Thickness in the range of ~ 150 microns) can be made from a sheet of flexible, electrically insulating polymer material. Next, the majority treated back contact back junction backplane enhanced large area solar cell (eg, solar cell area at least 125 mm x 125 mm, 156 mm x 156 mm, or larger) is mechanically fragile. Although separated from the template and lifted off along the sacrificial porous silicon layer (eg, by a mechanical debonding MR process), the template may be reused many times to further minimize solar cell manufacturing costs Can do. Next, a final cell treatment can be performed on the sun-exposed side of the solar cell that is exposed after peeling from the template. Sun-side treatment can include, for example, completion of front organization and passivation, and an anti-reflective coating deposition process.

  As described with reference to the flow outlined in FIG. 13A, the formation of the backplane (at the top, inside, or near the M1 layer) followed by a mechanically fragile sacrificial porous silicon layer After removal of the backplane supporting solar cell from the template and completion of the front organization and passivation process, a more conductive M2 layer is formed on the backplane. Via holes (in some examples, up to hundreds or thousands of via holes) are drilled into the backplane (eg, by laser drilling) and can have diameters ranging from about 50 to up to 500 microns. These via holes are on a pre-designated region of M1 for subsequent electrical connections between the patterned M2 layer and M1 layer via conductive plugs formed therein. After or concurrently with via hole filling and conductive plug formation, a patterned higher conductivity metallization layer M2 is formed (eg, M2 including aluminum, Al / NIV, Al / NiV / Sn, or copper). (Using materials, by plasma sputtering, plating, vapor deposition, or a combination thereof). In a comb back contact (IBC) solar cell with fine pitch IBC fingers (eg, hundreds of fingers) on M1, the patterned M2 layer can be designed orthogonal to M1, in other words, rectangular Or the tapered M2 finger is essentially orthogonal to the M1 finger. Due to this orthogonal transform, the M2 layer can have much fewer IBC fingers than the M1 layer (eg, about 10-50 times less M2 fingers). Accordingly, the M2 layer can be formed with a much coarser pattern having a wider IBC finger than the M1 layer. The solar cell bus bar can be provided on the M2 layer rather than the M1 layer to eliminate the electrical shielding losses associated with the on-cell bus bar. Both base and emitter interconnects and busbars can be provided on the M2 layer of the solar cell backside backplane, so electrical access from the backside of the solar cell to both the base and emitter terminals of the solar cell on the backplane Is possible.

  The backplane material formed between M1 and M2 is a thin polymer material having a sufficiently low coefficient of thermal expansion (CTE) to avoid excessive thermal induced stresses on the thin silicon layer. It can be a sheet. Furthermore, the backplane material meets process integration requirements in the back-end cell fabrication process, in particular chemical resistance during wet organization of the cell front and thermal passivation during PECVD deposition of the ARC layer. There is a need to. The electrically isolated backplane material must also meet module level lamination processes and long term reliability requirements. A variety of suitable polymeric materials (plastics, fluoropolymers, prepregs, etc.) and suitable non-polymeric materials (glass, ceramics, etc.) can be used as backplane materials, but backplane material options are not limited Not, but depends on many considerations including cost, ease of process integration, reliability, flexibility, etc.

  A preferred material option for the backplane material is prepreg. The prepreg is used as a component of a printed circuit board and can be made from a combination of resin and CTE-reducing fibers or particles. The backplane material is an inexpensive, low CTE (usually CTE <10 ppm / ° C. or CTE <5 ppm / ° C.) thin prepreg (eg, in the range of 50-250 microns, and more specifically about 50-150 microns). The sheet can be a sheet, which is relatively chemically resistant to organized chemicals and is thermally stable at a temperature of at least 180 ° C. (or at least as high as 280 ° C.). The prepreg sheet can be attached to the backside of the solar cell using a vacuum laminator while on the template (before the cell lift-off process). Upon application of heat and pressure, a thin prepreg sheet is permanently laminated or attached to the backside of the treated solar cell. Next, a lift-off stripping boundary is defined around the solar cell (near the template edge) using, for example, a pulsed laser scrubbing tool and then separated from the reusable template using a mechanical stripping or lift-off process. . Subsequent process steps include: (i) completion of the solar cell's sun-organization and passivation process, (ii) solar cell on the back of the cell (which may include part of the solar cell backplane) Completion of high conductivity metallization. A highly conductive metallization M2 layer (including, for example, aluminum, copper, or silver) that includes both an emitter polarity and a base polarity is formed on the stacked solar cell backplane.

  In general, prepregs are reinforcing materials that are pre-impregnated with resin and ready to use to produce composite parts (prepregs can be used to produce composites faster and easier than wet layup systems. it can). The prepreg can be manufactured by combining a specially formulated pre-catalyst resin with a reinforcing fiber or fabric using requirements designed to ensure consistency. When the prepreg is covered with a flexible backing paper, it may be easy to handle and form at room temperature for a predetermined period (out-life). In addition, prepreg advances have produced materials that do not require refrigeration for storage, prepregs with longer shelf life, and products that cure at low temperatures. The prepreg laminate can be cured by heating under pressure. Conventional prepregs are formulated for high pressure steam curing, while low temperature prepregs can be fully cured using vacuum bag pressure alone at much lower temperatures.

  FIG. 13B is an exemplary manufacturing process flow for forming a back contact / back junction cell using an epitaxial silicon lift-off process and can include the following fabrication steps. 1) starting with a reusable template, 2) porous silicon on the template (eg, forming anodic etching to form double layer porous Si), 3) depositing epitaxial silicon by in-situ doping, 4) Backside contact / backside junction cell processing is performed while on the template, including M1 formation, 5) a backplane sheet is laminated on the backside contact cell, and 6) a laser scribing is performed on the peeling boundary near the backplane. Form epitaxial silicon layer and remove cell, 7) wet silicon etch / texture / clean, PECVD sun-side and trench edge passivation, laser drilling of via holes in backplane, metal (Al) PVD deposition or evaporation or Plating for M2 (Cu) and M2 Turning to the back-end process, including the final laser ablation complete over emissions formation.

  The described process flow of FIGS. 13A and 13B provides exemplary thicknesses ranging from about 10 to up to about 100 microns that can be easily and conveniently integrated with the non-nested base design disclosed herein. Resulting in a solar cell formed on an epitaxially deposited silicon thin film.

  Those skilled in the art will recognize that the disclosed embodiments relate to a wide range of areas in addition to these specific examples described above.

  The previous description of exemplary embodiments is provided to enable any person skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without using novel features. . Accordingly, the claimed subject matter is not limited to the embodiments set forth herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein. is there. Also, all such additional systems, methods, features, and advantages included within this specification are intended to be within the scope of the claims.

Claims (26)

A back contact back junction crystal semiconductor solar cell,
A crystalline semiconductor substrate including a light-receiving passivation front surface and a passivation back surface including a patterned comb-doped emitter region and a base region;
A patterned electrical insulator layer on the back surface comprising a doped layer adjacent to the back surface and an undoped layer on the doped layer;
A contact metallization pattern comprising an emitter metallization electrode in contact with the emitter region and a non-nested base metallization electrode in contact with the base region;
With
The back contact crystalline semiconductor solar cell, wherein the non-nested base metallization electrode overlaps at least a portion of the patterned insulator beyond the base region without causing an electrical shunt in the solar cell.   The back contact crystal semiconductor solar cell of claim 1, wherein the emitter and base metallization electrodes comprise aluminum.   The back contact crystal semiconductor solar cell of claim 1, wherein the emitter and base metallization electrodes comprise aluminum silicon.   The back contact crystal semiconductor solar cell of claim 1, wherein the emitter and base metallization electrodes comprise a comb pattern.   The back contact crystalline semiconductor solar cell of claim 1, wherein the solar cell uses a second patterned metallization layer separated from the contact metallization pattern by an electrically insulating backplane.   The back contact crystal semiconductor solar cell of claim 1, wherein the patterned electrical insulator layer comprises at least a combination of a doped glass layer and an undoped glass layer.   The back contact crystalline semiconductor solar cell of claim 1, wherein the patterned electrical insulator layer comprises a first layer of borosilicate glass and a second layer of phosphosilicate glass.   The back contact crystalline semiconductor solar cell of claim 1, wherein the patterned electrical insulator layer comprises a first layer of borosilicate glass, a second layer of borosilicate glass, and phosphosilicate glass. A back contact back junction crystal semiconductor solar cell,
A crystalline semiconductor substrate comprising a light-receiving passivation front surface including a doped emitter and a discrete base region that is discontinuous and a back surface of the passivation;
A patterned electrical insulator layer on the back surface comprising a doped layer adjacent to the back surface and an undoped capping layer on the doped layer;
A contact metallization pattern comprising an emitter metallization electrode in contact with the emitter region and a non-nested base metallization electrode in contact with the base region;
With
The back contact crystalline semiconductor solar cell, wherein the non-nested base metallization electrode overlaps at least a portion of the patterned insulator beyond the base region without causing an electrical shunt in the solar cell.   The back contact crystal semiconductor solar cell of claim 9, wherein the emitter and base metallization electrodes comprise aluminum.   The back contact crystal semiconductor solar cell of claim 9, wherein the emitter and base metallization electrodes comprise aluminum silicon.   The back contact crystal semiconductor solar cell of claim 9, wherein the emitter and base metallization electrodes comprise a comb pattern.   The back contact crystalline semiconductor solar cell of claim 9, wherein the solar cell uses a second patterned metallization layer separated from the contact metallization pattern by an electrically insulating backplane.   The back contact crystal semiconductor solar cell of claim 9, wherein the patterned electrical insulator layer comprises at least a combination of a doped glass layer and an undoped glass layer.   The back contact crystalline semiconductor solar cell of claim 9, wherein the patterned electrical insulator layer comprises a first layer of borosilicate glass and a second layer of phosphosilicate glass.   The back contact crystalline semiconductor solar cell of claim 9, wherein the patterned electrical insulator layer comprises a first layer of borosilicate glass, a second layer of borosilicate glass, and phosphosilicate glass. A method of forming a back contact back junction crystal semiconductor solar cell,
Forming a patterned comb emitter and base region on the back side of the crystalline semiconductor substrate;
Forming a patterned electrically insulating layer stack comprising a combination of at least a doped layer and an undoped capping layer on the patterned doped emitter region and base region;
Forming a contact metallization pattern comprising an emitter metallization electrode in contact with the emitter region and a non-nested base metallization electrode in contact with the base region;
Including
The method of claim 1, wherein the non-nested base metallization electrode overlaps at least a portion of the patterned insulator beyond the base region without causing an electrical shunt in the solar cell.   The method of forming a back contact back junction solar cell according to claim 17, wherein the electrically insulating layer stack is formed by a chemical vapor deposition process.   The method of forming a back contact back junction solar cell according to claim 17, wherein the electrically insulating layer stack is formed using an atmospheric pressure chemical vapor deposition process.   The method of forming a back contact back junction solar cell according to claim 17, wherein the electrically insulating layer stack is formed by a low pressure chemical vapor deposition process.   The method of forming a back contact back junction solar cell according to claim 17, wherein the electrically insulating layer comprises a combination of a doped oxide layer and an undoped oxide layer. A method of forming a back contact back junction crystal semiconductor solar cell,
Forming a patterned doped emitter and discontinuous discrete base regions on the backside of the crystalline semiconductor substrate;
Forming a patterned electrically insulating layer stack comprising a combination of at least a doped layer and an undoped capping layer on the patterned doped emitter region and base region;
Forming a contact metallization pattern comprising an emitter metallization electrode in contact with the emitter region and a non-nested base metallization electrode in contact with the base region;
Including
The method of claim 1, wherein the non-nested base metallization electrode overlaps at least a portion of the patterned insulator beyond the base region without causing an electrical shunt in the solar cell.   24. The method of forming a back contact back junction solar cell according to claim 22, wherein the electrically insulating layer stack is formed by a chemical vapor deposition process.   24. The method of forming a back contact back junction solar cell according to claim 22, wherein the electrically insulating layer stack is formed using an atmospheric pressure chemical vapor deposition process.   23. The method of forming a back contact back junction solar cell according to claim 22, wherein the electrically insulating layer stack is formed by a low pressure chemical vapor deposition process.   24. The method of forming a back contact back junction solar cell according to claim 22, wherein the electrically insulating layer comprises a combination of a doped oxide layer and an undoped oxide layer.