KR20150119262A - Monolithically isled back contact back junction solar cells using bulk wafers - Google Patents

Abstract

According to one aspect of the disclosed subject matter, there is provided a method of forming a monolithic island rear side contact rear junction solar cell using a bulk wafer. An emitter and a base contact region are formed on the rear side of the semiconductor wafer including the light reception front side and the rear side opposite to the front side. A first level contact metallization is formed on the rear side of the wafer, and an electrically insulating backplane is attached to the rear side of the semiconductor wafer. A separation trench for patterning the semiconductor wafer into a plurality of electrically isolated islands is formed in the semiconductor wafer, and the semiconductor wafer is thinned. A metallization structure is formed to electrically connect the plurality of islands on the electrical isolation backplane.

Description

{MONOLITHICALLY ISLED BACK CONTACT BACK JUNCTION SOLAR CELLS USING BULK WAFERS} BACKGROUND OF THE INVENTION [0001]

This application claims the benefit of US Provisional Patent Application No. 61 / 763,580, filed February 12, 2013, and US Provisional Application No. 61 / 859,602, filed July 29, 2013, which is incorporated herein by reference.

This disclosure relates generally to the field of solar cells (PV) and modules, and more particularly to monolithic island or tile solar cells (PV) and related modules that provide a number of advantages.

Crystalline silicon solar (PV) modules account for more than 85% of the global PV market annual demand and the global PV installed capacity since 2012. The manufacturing process of the crystalline silicon PV is a process in which a single crystal or a polycrystalline silicon wafer made of Czochralski silicon ingots or cast silicon bricks to be used is used as a crystalline silicon solar cell . Although non-crystalline silicon based thin film PV modules (e.g., CdTe, CIGS, organic, and amorphous silicon PV modules) provide the potential for low cost manufacturing processes, (Module efficiency is in the range of about 14% to about 20%, mainly in the range of 14% to 17%), and long-term track record of field reliability is not proven compared to stable crystalline silicon solar PV module. State-of-the-art crystalline silicon PV modules offer superior overall energy conversion performance, long-term field reliability, non-toxicity and life cycle sustainability compared to other PV technologies. In addition, with recent developments, the total manufacturing cost of the crystalline silicon PV module is less than $ 0.80 / Wp. In accordance with the innovative monocrystalline silicon technology, for example, a reusable crystalline silicon template, a thin film (e.g., a thickness of crystalline silicon absorber, from about 10 microns to about 100 microns, typically less than 70 microns) Thin film monocrystalline silicon solar cells fabricated using a thin film silicon support using an adhesion / lamination and a porous silicon lift-off technique are highly efficient (at least 20% solar cell and / or module efficiency under standard test conditions or STC, ), And the cost of manufacturing PV modules is expected to be less than $ 0.5 / Wp in terms of mass production scale.

Conventional crystalline silicon (or other semiconductor absorber material) solar cell structures and processing methods are often used in the field of crystalline silicon PV modules installed in the field and also during bowing and destruction / breakage during and / Causing a number of related problems. Solar cell processing often leads to significant stresses (e.g., thermal and / or mechanical stresses) on the semiconductor substrate and heat-induced warpage and cracking (by thermal cycling or mechanical stress) and propagation . Curved or nonplanar solar cell substrates can cause considerable problems, which can lead to reduced production during solar cell processing (for example, when processing crystalline silicon solar cells), and to flattening the solar cell substrate during the manufacturing process It is necessary to fix the substrate edge and / or the solar cell substrate on the supporting substrate carrier. The planarization method complicates the fabrication process of the solar cell, thus increasing manufacturing cost and / or reducing some manufacturing throughput and production. Curved or nonplanar solar cell substrates can cause cell microcracks and / or breakage problems (PV module power reduction or loss) during module lamination and then in the field of the PV module operation. This problem can be more serious in large area solar cells, for example, commonly used 156 mm x 156 mm format (square or quasi-square) solar cells.

In addition, conventional solar cells, particularly solar cells based on interdigitated back-contact or IBC designs, require a relatively thick metallization pattern due to the relatively high cell current, Complexity, increased material cost, and significant physical stress on the battery semiconductor material. (E. G., Screen printed aluminum and / or silver containing metallization pastes used in plated copper or conventional front-contact solar cells used in IBC battery metals) and semiconductor materials (e. G., Thin film crystalline < (E.g., a thickness range of a few tens of microns for IBC solar cell metallization) on the front and / or rear side of the solar cell, which is coupled to a thermal mismatch of the thermal expansion coefficient or the CTE The induced heat and mechanical stresses can be substantially reduced during and after solar cell processing (ie during and after solar cell metallization) and module processing (during and after interconnection and module lamination assembly between cells), field manipulation of installed PV modules That is, due to weather conditions, temperature changes, wind induced and / or snow load induction and / or installation related module buckling stress), microcracks, solar cell damage, This can increase the risk of eojim.

In addition, the crystalline silicon module has been used in many applications such as relatively expensive external bypass diodes are often used, to avoid potential reliability failures of the resulting solar cells and modules, and to eliminate hot-spot effects due to partial or total shading of the solar cell, A relatively high forward bias current in the range of a few amperes to about 10 amperes and a relatively high reverse bias voltage of about 10 V to 20 V should be able to be processed. This shade induced hot spot phenomenon is due to the reverse bias of the shaded cells or cells in the PV module and the affected PV cell may also permanently damage the interconnection between the PV module encapsulating material and the cell, , Even if solar light reaching the surface of the PV cell in the PV module is partially blocked in the PV module or is not sufficiently uniform due to the total or partial shading of one or more solar cells. Bypass diodes are often placed on the substrings of a PV module, typically one external bypass diode per substring of 20 solar cells in a standard 60-cell crystalline silicon solar module containing three 20-cell substrings, or 3 A number of other module formats and structures, including a different number of solar cells embedded, and one external bypass diode per substring of 24 solar cells in a 72-cell crystalline silicon solar module containing 24 battery cells, Lt; RTI ID = 0.0 > of cells. ≪ / RTI > Such a connection structure with an external bypass diode in a series-connected battery string prevents reverse bias hot spots by any shaded cell and allows the PV module to be relatively inexpensive for a lifetime under various real-life shading or partial shading & It can operate with high reliability. In the absence of solar cell shading or sorting, each cell in the string basically acts as a current source with a current that is relatively matched to the other cells in the series connection of the cell, and the external bypass diode in the substring serves as a sub- (E.g., 20 cells in a series connected string form a reverse bias of about 10-12 V at the bypass diode in the crystalline silicon PV system). The shaded cells are reverse biased according to the shading of the cells in the string, the bypass diode for the substrings including the shaded cells is turned on, and thus the current from the good / shaded solar cells in the unshaded substring To flow as an external bypass current. An external bypass diode (typically three external bypass diodes included in a standard 60-cell crystalline silicon PV module junction box) protects the PV modules and cells in the case of battery shading, And energy can be significantly lost.

Conventionally, most silicon solar cells are fabricated using p-type (e.g., boron-doped) crystalline silicon wafers (polycrystalline and monocrystalline). These cells are vulnerable and can easily be destroyed (and thus often have to be packaged in a rigid, frameed and glass-covered module), due to the iron-boron (Fe-B) and boron- (General p-type cell efficiency is limited to about 20%), efficiency reduction (e.g., light oil degradation or LID). Most of the work focuses on developing the underlying technology and converting to an n-type (for example, doped) starting wafer capable of higher efficiency cells compared to p-type starting wafers without causing the same efficiency reduction.

In addition, most solar modules installed or manufactured are front contact cells (with front or sun side fingers and bus bars) using polycrystalline or monocrystalline silicon solar cells. Such front contact cells include metallization fingers and bus bars, which can result in loss of light shading by front metallization. The rear contact structure avoids this problem.

The most efficient rear-side contact cell uses an interlocked rear-side contact (IBC), rear junction structure, which can approach near the havested carrier and terminal in the emitter, A weakly doped front provides a reaction. In addition, n-type wafers used in rear contact / rear junction (IBC) solar cells generally provide much higher carrier lifetimes and provide higher battery efficiency at the top than p-type wafers.

For best efficiency performance, an n-type wafer with a higher lifetime than a p-type wafer is more suitable for an IBC cell because the rear contact back junction IBC solar cell typically requires a very high fractional carrier lifetime wafer. This means that the average path that the generated minority carriers (e. G. Holes in the case of n-type wafer and n-type IBC cell base) are collected at the emitter junction located on the rear side of the cell is the thickness of the wafer or semiconductor absorption layer Due to the fact that it is relatively large due to the distance from the front side of the battery to the collecting end of the rear side controlled by the battery.

The specific thickness of the wafer (or semiconductor absorber layer) is advantageous for effectively collecting a large fraction of infrared photons (e.g., those having energy closer to the band gap energy of the crystalline silicon) Value, the bulk recombination loss, and the increased travel distance of the resulting minority carrier (which tends to lose recombination), is such that the cell absorber thickness is within a certain optimal range (e. G., About 20 To 90 [mu] m) is increased depending on the starting wafer quality (minority carrier lifetime or diffusion length), thereby deteriorating the overall cell efficiency performance. Thus, in terms of cell efficiency performance, a crystalline silicon absorber thickness of about 20 to 90 占 퐉 is optimal, and the actual optimum thickness may depend on the absorber quality measured by minority carrier lifetime or diffusion length, and is less than 20 占 퐉 Mu] m. The practical limitations of producing highly efficient crystalline silicon cells using very thin wafers (120 탆 or less of 156 mm x 156 mm wafer thickness) are the mechanical yields of these wafers throughout the cell manufacturing process (and also the next module laminating process) . Mechanical yield can be reduced due to cell fabrication processes and handling, such as breakage of these thin film wafers during screen printing and wet processes, as well as breakage from excessive film stress or excessive warpage, (For example, plated copper) back metallization (often a few tens of microns thick plated copper to deliver a relatively large cell current across the entire rear-side contact IBC finger engaged at low voltages).

The requirements for this thick metallization often require the use of a plating such as a stack of Ni, Cu, and Sn of the metal structure or electroplating of Cu. Solar cell companies are substantially difficult to introduce electroplating, including copper electroplating, into the product because of the inherent risk of inherent metal contamination of the metal and silicon absorber layer during further processing or aging, or from the plating solution no. Copper plating of IBC cells also requires a number of process steps (e.g., PVD seed layer, screen printed resist pattern, copper nickel tin electroplating, peeling resist pattern, wet etch exposed seed formation) Significant consumption costs to support the line are also cost of additional fabrication facility CAPEX / OPEX. The IBC cell requirement for relatively thick plated copper metallization is relatively large in terms of the stress introduced by thick copper due to thermal (CTE) mass matching between the relatively thick (e. G., 30 to 80 um thick) There is a danger.

These limiting requirements, etc., are relatively high in manufacturing cost of the preferred rear contact IBC cell structure and limit bulk adsorption.

A high efficiency solar cell fabrication method and design are required. Methods and structures of monolithic island solar cells and modules according to the disclosed subject matter are provided. These innovations can reduce or eliminate disadvantages and problems associated with solar cells that have been substantially developed in the past.

According to one aspect of the disclosed subject matter, there is provided a method of forming a monolithic island rear side contact rear junction solar cell using a bulk wafer. An emitter and a base contact region are formed on the rear side of the semiconductor wafer including the light reception front side and the rear side opposite to the front side. The first level contact metallization is formed on the rear side of the wafer, and the electrically insulating backplane is attached to the rear side of the semiconductor wafer. A separation trench is formed in a semiconductor wafer in which a semiconductor wafer is patterned with a plurality of electrically isolated islands, and the semiconductor wafer is thinned. The metallization structure is formed on an electrically insulated backplane that electrically connects the plurality of islands.

The technological advantages of the innovative type disclosed herein are improved flexibility and reduced cracking; Cell warpage reduction and planarity improvement; But are not limited to, a decrease in ohmic loss, and a decrease in battery metallization thickness requirements, depending on voltage increase and current decrease.

These and other advantages and further novel features of the subject matter disclosed herein will become apparent from the description provided herein. This summary is not a comprehensive description of the object, but rather a brief description of some of the functions of the object. Other systems, methods, features and advantages provided herein will become apparent to those skilled in the art from the following drawings and detailed description. All such additional systems, methods, features and advantages included in this description are intended to be included within the scope of the claims.

The features, characteristics, and advantages of the disclosed subject matter will become more apparent from the description set forth below with reference to the drawings, in which like reference numerals indicate like features:
1 is a top view of a square single island master cell;
Figure 2 is a top view of a square 4 x 4 island square master cell (or island cell "icell");
Figures 3a and 3b are cross-sectional views of a backplane-attached solar cell after a solar cell fabrication step comprising isolation trench formation;
4 is an exemplary process flow diagram for fabricating a backplane-attached solar cell using an epitaxial silicon lift-off process;
5A to 5C are a manufacturing process flow chart for forming a rear-side rear-side-junction solar cell. Figure 5a is a process flow diagram based on epitaxial silicon and porous silicon lift off processing, Figure 5b is a process flow diagram based on a starting crystalline silicon wafer, Figure 5c is a process flow diagram based on epitaxial silicon and lift off processing;
5D and 5E are cross-sectional views of a backplane-attached solar cell;
Figures 6a and 6b are top plan views of square 3x3 and 5x5 island quadrangle Iccels, respectively;
Figures 7a and 7b are top views of a square Icel embodiment of eight triangular islands;
Figures 7c, 7d, and 7e are top views of a square Icel embodiment of 16, 36, and 32 triangular islands;
8 is a schematic diagram of an equivalent circuit model of a conventional solar cell having an edge effect;
FIG. 9A is a rear view of a first metallization layer pattern M1 without a bus bar formed on a square 4x4 iscel cell, FIG. 9B is an enlarged view of the portion of FIG. 9A; FIG.
10A and 10B are rear views of a first metallization layer pattern M1 without bus bars formed on square 3x3 and 5x5 island islands;
FIG. 11A is a rear view of a first metallization layer pattern M1 without bus bars formed on a triangular 36-island iscel, FIG. 11B is an enlarged view of FIG. 11A;
12A is a rear view of a second metallization layer pattern M2 formed on a square 5x5 island iscel, FIG. 12B is an enlarged view of FIG. 12A; FIG.
Figure 13 is a rear view of a second metallized layer pattern (M2) unit cell in which the tapered base and emitter fingers are interdigitated;
14A is a rear view of a second metallization layer pattern M2 formed on a square 4x4 island iscel, FIG. 14B is an enlarged view of FIG. 14A; FIG.
15A and 15B are rear views of a second metallization layer pattern M2 formed on square 3x3 and 5x5 island islands;
16A is a top view of an island master cell (an icel), each island having a monolithically integrated bypass switch (MIBS); Fig.
FIGS. 16B and 16C are cross-sectional views of an MIBS rim or an all-pole diode solar cell embodiment of a rear-contact / rear-side-junction solar cell for one island (or a unit cell such as I _{11 in} FIG. 16A);
FIG. 17 is a schematic diagram of an Icel cell electrically connected in series; FIG.
Figures 18a and 18b are schematic diagrams of an Icel with a 4 x 4 array of islands connected electrically in both series and electrically hybrid parallel-to-serial (the design of Figure 18b is referred to as a 2x8 HPS design);
18c is a schematic of an Icel with an 8x8 array of islands electrically connected in series in a hybrid parallel (referred to as an 8x8 HPS design).
Figs. 19A, 19B and 19C show the positions of the shade management switches on the i-cells of Figs. 18A, 18B and 18C, respectively;
20 is a top view of a quasi-square master cell substrate;
21 is a schematic diagram of a pseudo-square i-cell electrically connected in a hybrid parallel-to-serial fashion;
22 is a schematic view of a quasi-square Icel cell electrically connected in series;
Figures 23a and 23b are schematic diagrams of the master cell and relative position of the emitter and base bus bar according to the number of islands and the M2 interconnect design;
Figures 24-27 are schematic illustrations of 60 battery module connection designs;
Figures 28A and 28B are schematic diagrams of module connections of a 600 VDC PV system using a 60-cell PV module including an i-cell in series with respect to a hybrid parallel-serial Icel cell;
29A and 29B are schematic diagrams of module connections for a 1000 VDC PV system using a 60-cell PV module that includes both in-line Icel cells as compared to a hybrid parallel-serial Icel cell;
30 is a view of a monolithic island solar cell having a 4 x 4 array of sub-cells;
31 is a graph of cell thickness vs. open circuit voltage;
32 is a graph of minority carrier lifetime vs. silicon thickness;
33 is a process flow chart showing a high-level solar cell building block;
34A-34D are process flow embodiments for fabricating a rear contact solar cell meshed without FSF or BSF;
35A-35D are process flow embodiments for fabricating a rear contact solar cell meshed with an embedded FSF;
36A-36D are process flow embodiments for fabricating a rear contact solar cell meshed with an embedded FSF;
37A is a cross-sectional view of a process including wafer thinning steps prior to wafer fission;
FIG. 37B is a cross-sectional view of a process including partial wafer segmentation before wafer thinning and wafer thinning and texturing; FIG.
38A-38D are process flow embodiments for fabricating a rear contact solar cell meshed with a laser doped FSF;
39A-39D are process flow embodiments for fabricating a rear contact solar cell with a pulsed laser FSF interlocked;
40A-40D are process flow embodiments for fabricating a rear contact solar cell meshed with an ion implanted FSF;
41A-41D are process flow embodiments for fabricating a rear contact solar cell meshed with a gas injection FSF;
42 is a process flow chart for manufacturing a rear contact solar cell in which a separation trench using PV-Al / NiV is coupled with a pulse ns laser scribing;
Figure 43 is a process flow embodiment for fabricating a rear contact solar cell meshed using a pulsed ns laser scribing of isolation trenches on a pre-etched thick silicon;
44A is a cross-sectional view illustrating the direct oxidation removal of a BSG (or PSG) layer on a silicon layer;
44B is a cross-sectional view showing removal of a hard mask layer on BSG (or PSG) on a silicon layer;
45-49 illustrate a number of exemplary process flow embodiments for fabricating a back-contacting, backside contact solar cell.

The following description is not intended to be exhaustive and to describe the general principles of the disclosure. The scope of the invention should be determined by the claims. Exemplary embodiments of the present disclosure are shown in the drawings, wherein like or corresponding parts of the various figures have the same reference numerals.

Importantly, the exemplary dimensions and computations disclosed in the multiple embodiments are provided for use as a general description of specific embodiments, and as a general guideline when forming and designing solar cells according to the disclosed subject matter.

(IBC) solar cell comprising a monocrystalline silicon substrate and the fabrication materials described elsewhere), the present disclosure may be applied to specific embodiments, for example backplane-attached / , But those skilled in the art will recognize that the principles discussed herein may be applied to other solar cells and other solar cells may include non-IBC back-side solar cells (e.g., Metallization Wrap- (For example, silicon, gallium arsenide, germanium, gallium nitride, other binary or ternary semiconductors, etc.), and other semiconductor materials But are not limited to, other fabrication materials, technical areas, and / or inadequate unexperienced embodiments.

In addition, the island (also referred to as a tile) master cell structure (also known as Icel, Isled Cell) and exemplary fabrication process flow descriptions are formed using a porous silicon lift-off process on a reusable monocrystalline template and a flexible backplane Thin-film epitaxial silicon back-contact / back-side-junction IBC solar cells, the novel concepts and embodiments disclosed herein are applicable to and can be efficiently applied to solar cells of other types (and solar PV modules obtained) In this type of solar cell,

Thin-film epitaxial silicon back-contact / back-side-junction IBC solar cells formed using reusable polycrystalline templates and porous silicon lift-off processing on flexible or rigid backplanes;

Thin-film epitaxial silicon back-contact / back-side-junction IBC solar cells formed using a porous silicon lift-off process on reusable single crystal templates and relatively hard backplanes;

A thin film epitaxial silicon heterojunction (SHJ) solar cell formed using a reusable polycrystalline template and a porous silicon lift-off process on a flexible or rigid backplane;

back-junction / rear-side contact IBC solar cells formed using wire-sawn Czochralski (CZ) or float zone (FZ) single crystal wafers and flexible backplanes;

back-junction / rear-contact IBC solar cells formed using wire-sawn Czochralski (CZ) or float zone (FZ) single crystal wafers and rigid backplanes;

- a back-junction / rear-side contact IBC solar cell formed using a wire-sawn cast or ribbon polycrystalline wafer, and a flexible backplane;

- a back-junction / rear-side contact IBC solar cell formed using a wire-sawn cast or ribbon polycrystalline wafer, and a rigid backplane;

- wire-sawn cast polycrystalline wafers, and rear-contact non-IBC (eg metallized lapthrough or MWT) solar cells formed using flexible backplanes;

- wire-sawn cast polycrystalline wafers, and rear-contact non-IBC (e.g. metallized lapthrough or MWT) solar cells formed using rigid backplanes;

- a back-contact non-IBC (e.g. metallized lapthrough or MWT) solar cell formed using a wire-sawn Czochralski (CZ) or float zone (FZ) single crystal wafer and a flexible backplane;

- wire-sawn Czochralski (CZ) or float zone (FZ) monocrystalline wafers, and rear-contact non-IBC (eg metallized lapthrough or MWT) solar cells formed using rigid backplanes;

- semiconductor heterojunction (SHJ) solar cells formed using wire-sawn Czochralski (CZ) or float zone (FZ) single crystal wafers and flexible backplanes;

- semiconductor heterojunction (SHJ) solar cells formed using wire-sawn Czochralski (CZ) or float zone (FZ) single crystal wafers and rigid backplanes;

- front-contact solar cells formed using wire-sawn Czochralski (CZ) or float zone (FZ) single crystal wafers and flexible backplanes;

a front-contact solar cell formed using a wire-sawn Czochralski (CZ) or float zone (FZ) single crystal wafer and a rigid backplane;

- front-contact solar cells formed using wire-sawn cast single crystal wafers and flexible backplanes;

a front-contact solar cell formed using a wire-sawn cast monocrystalline wafer and a rigid backplane;

- any of the solar cells described above using a different semiconductor material besides crystalline silicon.

&Quot; Island, road, tile, paving brick, subcell, and / or mini battery "refer to electrical and / or electronic devices formed monolithically from a master cell substrate (i.e., an initial continuous semiconductor substrate) attached to a common or continuous backplane layer or sheet. Are used interchangeably to describe individual semiconductor regions that are physically separated. Means a plurality of islands or sub-cells formed from the same conventional semiconductor substrate layer and subsequent modified island solar cells. An existing semiconductor layer or substrate on which a mini battery is formed can be referred to as a master battery.

The term "backplane" also refers to a back side of a cell, for example, a metallization layer attached to the back of a solar cell and a layer of material on the electrically insulating layer that provides mechanical and structural support for the master cell Can be used to describe the combination and enable advanced solar cell interconnect design. Further, in some instances, a "backplane" may be used to describe a layer of material formed and positioned on the back side of a solar cell, for example, an electrically insulating flexible prepreg layer, Thereby forming a solar cell metallization structure included in the rear side of the battery. The backplane layer may be made of a rigid or flexible thin sheet material (e.g., a backplane sheet thickness of about 250 microns or less). For applications involving rear-side contact solar cells (meshed back-side-contact-IBC or metallized wrap throw-MWT), the backplane layer can be made of an electrically insulating material (flexible or rigid material). For applications involving front-contact solar cells, the backplane layer may be electrically or electrically conductive. In most instances, a "backplane" is referred to as a continuous thin sheet of support material that can be flexible or rigid, including, but not limited to, thin sheet of prepreg material. Using a flexible backplane sheet according to the disclosed subject matter, the solar cell can also be packaged in a flexible, lightweight PV module (no front, or a heavy glass cover sheet on the front and rear sides).

The present application provides various structures and methods of monolithic island solar cells and modules. A "monolithically integrated circuit" is used to describe a plurality of semiconductor devices and corresponding electrical interconnections fabricated on one semiconductor material layer slice, known as a semiconductor substrate. Thus, a monolithically integrated circuit is typically fabricated on a thin film continuous slice or layer of a semiconductor material (e.g., crystalline silicon). The monolithic Iicell structures described herein may be formed on a single semiconductor substrate layer slice (either from a starting semiconductor wafer or from a semiconductor layer grown by vapor phase or liquid phase epitaxy, e. G. Epitaxial deposition) It is a monolithic integrated semiconductor circuit when manufactured. Further, the combination of a continuous backplane attached to the rear side of the semiconductor substrate layer enables a monolithically integrated ICE embodiment according to the disclosed subject matter.

Physically or locally separated islands (i.e., an initial semiconductor substrate partitioned by a plurality of substrate islands supported on a shared continuous backplane) are formed from an initial continuous semiconductor layer or substrate, and thus the resulting islands Separate trenches that use trench isolation regions or cuts through the substrate) are monolithic and the continuous semiconductor layer or substrate is attached to and supported by a continuous backplane (e.g., a flexible backplane, e.g., Leg layer). The completed solar cell includes a plurality of monolithically integrated islands or miniature cells attached in some instances to a flexible backplane (e.g., a relatively good thermal expansion coefficient or CTE that matches the semiconductor substrate material) It is possible to increase solar cell flexibility and pliability while suppressing or eliminating micro cracks and propagation or breakage of cracks. In addition, a flexible monolithic island (or a group of monolithically integrated islands) cells (also referred to as Iicels) provides improved cell flatness and relatively small or negligible cell warping throughout the solar cell processing stage, The processing steps of the solar cell can be performed by any optional semiconductor layer thin film etching, texturing etching, post-texturing cleaning, PECVD passivation and anti-reflective coating (ARC) Solar-side-up PECVD processing of the substrate is possible) and final solar cell metallization. Although the solar cells disclosed herein can be used to fabricate rigid glass cover PV modules, the structures and methods disclosed herein provide a flexible, lightweight PV module formed from a monolithic island master cell (i.e., Icel) And microcracks in the solar cell are reduced or eliminated during operation of the PV module within the field. These flexible, lightweight PV modules can be used in a variety of markets and applications, including housing roofs (shingle / tiles in residential building integrated photovoltaics or BIPV roofs), commercial roofs, ground mounted utility scale power plants, portable and mobile PV power generation , Automobiles (e.g., solar PV sunroof), and other specialized applications.

As an innovative form disclosed herein, individually or in combination, the following advantages can be provided:

- island solar cells (icel) are capable of scaling the solar cell voltage and current, and more particularly, the solar cell voltage and current can be scaled, for example, based on the number of battery islands / tiles (or sub- (I. E., Decrease the master cell output current) and decrease the metallization sheet conductivity or decrease the thickness requirements (thus, the metallization material and processing cost < RTI ID = 0.0 > (E. G., Low current grade Schottky or pn junction diodes), or embedded maximum power point tracking (MPPT) power optimizers (e. G. Such as an embedded MPPT DC-to-DC microconverter or an MPPT DC-to-AC microinverter). This is due to the size of embedded power electronics components, such as bypass switches (bypass switches with high current ratings are generally more expensive than bypass switches with low current ratings) (E. G., MPPTs < / RTI > used to improve the collection of distributed power / energy from bypass switches used in shade management distributed from PV modules) Power optimizer) performance is improved due to the reduction of current (for example, current flowing through the bypass switch when the solar cell is shrouded to be activated and forward biased to protect the solar cell). Schottky barrier diodes, which typically have a much lower cost, can have much smaller packages, and a much lower power than the 10 A to 20 A Schottky barrier diodes (e.g., about 1 to 2 A) do. The embodiments described herein (e.g., the N x N island for a master cell or an Icel cell) are characterized by a high cell voltage (with an increasing factor of N x N or less) and a low cell current To reduce the solar cell current obtained to enable low cost, small and low power dissipation bypass diodes, and to increase the solar cell voltage of the same solar cell power. For example, the maximum power point voltage V _mp Consider a crystalline silicon master cell or an Icel cell having a maximum power point current I _mp ? 9.3 A of about 0.60 V (the solar cell produces a maximum power point power P _mp ? 5.6 W). A 5 x 5 array (N = 5) master cell or an i-cell of a mini-cell can be constructed such that all the islands or sub-cells are stacked on top of the first level metal (M1) on the back side of the solar cell and on the electrically insulated backplane layer (S = 25) to form a reformed cell having Vmp = 15V and Imp = 0.372A, which is connected in an electrical series using a combination of second level metal (M2) The master cell or the icel voltage is increased by a factor of 25, and the master cell or the icel current is reduced by the same factor 25, compared to the solar cell of the master cell size;

(MPPT) power optimizer (DC-to-DC or DC-to-AC) with high conversion efficiency, embedded / distributed low cost, and small footprint with excellent performance such as dynamic range response. The chip is directly integrated / integrated on the back side of the solar cell (for example, the backplane of the backplane-attached Icelel disclosed herein) due to the high voltage and low current of the master cell (Icel) composed of a plurality of islands or mini batteries May be embedded within the module stack. In one embodiment, the Icel can use an inexpensive single-chip MPPT power optimizer (DC-to-DC fine converter or DC-to-AC fine inverter);

* With embedded bypass switch connected to each Icelet, distributed battery level integrated shade management can be performed inexpensively and provides high efficiency energy of installed PV modules in the field. In one embodiment, the affected / shaded tiles or mini-cells of the partial shading are shunted and include a monolithically integrated bypass switch (MIBS) formed around each Icelet to generate and transmit power Can be;

The reduced current of the island solar cell (icel) (e.g., reduced the factor of the N x N island) reduces the required patterned metallized sheet conductivity and thickness due to reduced ohmic losses. That is, the metallization sheet conductivity and thickness requirements are mitigated by virtually reduced ohmic losses. Thinned solar cell metallization structures provide many advantages in solar cell processing, and include CTE mismatching between conductive metal and semiconductor material, and relatively thick (e.g., several tens of microns of intertwined rear side-contact or solar cells) Can provide significant reduction in manufacturing cost (e.g., much less metallization material needed per cell) as well as reduced thermal and metallic stresses on the metallized structure. Generally, metallization materials such as copper or aluminum have a much higher CTE than semiconductor materials. For example, the linear CTEs of aluminum, copper, and silver (high conductive metal) are about 23.1 ppm / ° C, 17 ppm / ° C, and 18 ppm / However, the linear CTE of silicon is about 3 ppm / 占 폚. Thus, the CTE mismatch between such a highly conductive metallization material and silicon is relatively large. The relatively large CTE mismatch between the metallization material and the silicon is particularly important when using relatively thick metallized structures of solar cells (for example, when using thick plated copper used in IBC solar cells) Production and PV module reliability problems;

In the multilayer metallization pattern, in the double layer metallization pattern described herein for meshed back side-contact (IBC) solar cells, the second level metal (M2), which comprises aluminum or copper, (For example, a dry treatment method such as physical vapor deposition method (for example, a method of physical vapor deposition (for example, a vapor deposition method), a vapor deposition method, PVD), for example, metal deposition and / or plasma sputtering or metal ink printing or metal paste screen printing by inkjet printing);

- In some instances, the cost of the material forming the backplane (e.g., prepreg) is reduced because the Icel structure using a plurality of flexible islands reduces / mitigates the CTE requirements of the prepreg. The relative CTE matching requirement between the backplane sheet and the semiconductor substrate is reduced because the continuous cell area attached to the backplane is small (due to the trench isolation region that divides the semiconductor substrate into a plurality of islands or subcells on the continuous backplane sheet) The continuous mini-cell area attached to the backplane is defined by the island area or area enclosed by the trench isolation;

The trench-separated and electrically-partitioned substrate regions with respect to the islands provide relative flexibility, reduce cell warpage, and allow the master cell (all of the cells in the cell to be processed) during cell processing (which in some instances allows battery passivation processing such as solar cell PECVD deposition) Iceless area) and reduces long-term material stresses during operation of the PV modules in the field under various weather conditions, after battery fabrication and module lamination.

The innovative and important applications disclosed include building-integrated photovoltaic systems (BIPV) in residential roofs, commercial buildings, commercial roofs, ground-mounted utility-scale power plants, automotive applications, portable electronics, portable and mobile power generation, But are not limited to, flexible solar cells for application and flexible, lightweight PV modules. Embodiments disclosed herein include rigid or flexible solar cells that may be packaged or laminated in a solar PV module of a rigid glass cover for a wide range of applications and may be used in a wide range of applications such as the residential roof, commercial roof, BIPV, Utilities, automobiles, portable and portable power generation, and other specialized applications.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a representative schematic view of a square single island cell pattern that does not include a plurality of islands to form an icel and is a conventional standard solar cell shape. Although shown as a complete square cell, the solar cell may be formed in a pseudo-square, rectangular, other polygonal shape, or any other shape of interest. 1 is a schematic top view of a single island I (or non-island or non-tile) standard square solar cell 10 defined by a cell perimeter boundary or edge region 12 and having a length L of sides. Conventional or predominant crystalline silicon solar cells are often rectangular / square (mostly complete squares or quasi-square wafers), cell square areas are XxX (X is generally about 100 mm to 210 mm or less) For example, 125 mm x 125 mm, 156 mm x 156 mm, or 210 mm x 210 mm. The square solar cell is used herein as an example of the master cell shape (the master cell is defined as a single solar cell composed of a conventional continuous semiconductor substrate), the master cell has various shapes (for example, quasi-square) Dimension.

The cell periphery boundary or edge region 12 has an overall length of 4L, and thus the solar cell 10 has a total peripheral dimension of 4L. Assuming that the thickness of the absorber of the solar cell semiconductor (for example, silicon substrate layer) is W (see the sectional view in FIG. 3A), the cell edge area as a fraction of the active area of the battery is defined as R ratio, R is (4LW) (L ² ) = 4W / L. Thin film silicon solar cells with a thick silicon substrate (e.g., epitaxially grown silicon epi, a layer or alternatively from a conventional wire-sawn CZ or polycrystalline silicon wafer with L = 156 mm and W = R = 4 x 40 x 10 ^-3 / 156, and therefore R = 0.0010 (or 0.10%), for the silicon layer formed. R = 0.0050 (0.50%) for a thick silicon substrate (e.g., for a conventional standard solar cell from a CZ monocrystalline wafer or cast polycrystalline wafer). In general, the solar cell structure has a relatively small edge area (also referred to as the edge to cell ratio) relative to the active cell area, e.g., less than about 5%, in some cases less than about 1% And / or to reduce edge-related photovoltaic cell recombination losses that can reduce solar cell conversion efficiency by reducing short circuit currents. The edge induction loss can be reduced by proper passivation of the solar cell edge region that substantially isolates / isolates the emitter junction region from the edge region (thus enabling large edge region fractionation without loss of solar cell efficiency) .

FIG. 2 shows an example of an Icel pattern (shown as a square island and a square Icel) with a square island of uniform size (same size) for N x N = 4 x 4 = 16 islands (or sub- (Front side or sun side). This schematic view shows a plurality of islands (4 x 4 = 16 islands) delimited by trench isolation regions. 2 is a schematic top view or plan view of a 4x4 uniform island (tile) master solar cell or an icel 20, defined as a cell perimeter boundary or edge region 22 and having sides of length L, And sixteen uniform square islands formed as a continuous substrate and identified as I ₁₁ through I ₄₄ attached to successive backplanes on the rear side of the master cell (unshown solar cell rear side and backplane). Each island or sub-cell or mini-cell or tile may have an inner island perimeter boundary (e.g., the isolation trench shown as a trench isolation or island partition border 24, cutting the master cell semiconductor substrate thickness, Less than about 100 microns, and in some instances less than about 100 microns, e.g., from about a few microns to about 100 microns). The peripheral edge or edge region 22 of the main cell (or the icel) has a total peripheral length of 4L; The overall Icel edge boundary length, including the perimeter dimensions of all the islands, includes the cell perimeter 22 (also referred to as the cell periphery) and the trench isolation border 24. [ Thus, for an Ixel containing an NxN island or mini-cell in a square Icel cell embodiment, the overall Icel edge length is the Nx cell periphery. In a representative example of FIG. 2, which shows an Icel with 4x4 = 16 islands (N = 4), the overall cell edge length is 4x the cell circumference 4L = 16L Which is four times larger than the standard prior art battery shown. For a square master cell or icel of 156x156 mm dimensions, the dimensions of the sides of the square island are approximately 39x39 mm, and the area of each island or subcell is 15.21 cm ² per island.

3A and 3B are representative schematic cross-sectional views of a backplane-attached solar cell during different solar cell processing steps. 3A is a simple cross-sectional view of a backplane-attached solar cell after the cell fabrication step and before the formation of the partitioned trench region. FIG. 3B is a simplified cross-sectional view of a backplane-attached solar cell after some fabrication steps and the formation of partitioned trench regions to define a trench isolation island. Figure 3b shows an example of an Icel pattern (shown for square islands and square Icel cells) representing a uniform size (same size) square island of N x N = 4 x 4 = 16 islands (or subcells, mini batteries, tiles) 2 is a schematic cross-sectional view of the eyecell of FIG. 2 along the field of view A of FIG. 2. FIG.

Figures 3a and 3b are schematic cross-sectional views of a monolithic island cell or a tile solar cell on a backplane formed from a monolithic master cell semiconductor substrate on a backplane and a master cell after forming a trench isolation or partition region before formation of a trench isolation or partition region. Figure 3a includes a semiconductor substrate 30 attached to a backplane 32 similar to that shown in Figure 1 and having a width (semiconductor layer thickness) W (e.g., an electrically isolated continuous backplane layer, e.g., Thin flexible sheet of prepreg). FIG. 3B is a cross-sectional view of an island solar cell (an Icel) cut along the A axis of the cell of FIG. 3B includes islands or mini-cells I ₁₁ , I ₂₁ , I ₃₁ , and I ₄₁ attached to the backplane 32 and having a trench compartment semiconductor layer width (thickness) W. FIG. The semiconductor substrate region of the mini-cell is physically and electrically separated by the inner circumferential partition boundary and the trench partition border 24. [ The semiconductor regions of the islands or minicells I ₁₁ , I ₂₁ , I ₃₁ , and I ₄₁ may be monolithically formed from the same continuous semiconductor substrate shown in FIG. 3A. 3B is trenched through a semiconductor layer attached to the backplane to form an inner cell (for example, a square mini cell or island) in a desired mini cell shape Can be formed from the semiconductor / backplane structure of Fig. 3A by forming the partition boundaries. The trench section of the semiconductor substrate for forming the islands is such that the backplane sheet is not continuously partitioned so that the resulting islands are supported by a continuous backplane layer or sheet and remain attached. The trench compartment formation process through the initial continuous semiconductor substrate thickness may be performed, for example, by pulsed laser ablation or by dicing, mechanical dicing, ultrasonic dicing, plasma dicing, water jet dicing, (Dicing, cutting, scribing, and trenching may be used interchangeably to mean a process of trench isolation to form a plurality of islands or mini-cells or tiles on a continuous backplane) . Again, the backplane structure comprises a combination of the patterned metallization structure and the backplane support sheet, and the backplane support sheet is formed from the resulting i-cell (a semi-flexible solar cell using a semi-flexible backplane sheet or a rigid solar cell using a rigid backplane sheet Or a flexible solar cell using a flexible backplane sheet). ≪ Desc / Clms Page number 2 > Again, a "backplane" can be used for a combination of a continuous backplane support sheet and a patterned metallization structure, and typically, the backplane is attached to the back of the semiconductor substrate and includes an Icelermemory substrate region and an entire patterned solar cell metallization structure May be used to mean a backplane structure sheet (e.g., an electrically insulating thin sheet of prepreg) that supports it.

As described above, crystalline (monocrystalline and polycrystalline) silicon photovoltaic (PV) modules account for more than about 85% of the total global solar PV market, and the cost of starting crystalline silicon wafers in these crystalline silicon PV modules is lower (Exact rates vary depending on technology type and various economic factors). Although the first embodiment provided herein is described as a rear-side / rear-side-junction (meshed rear side-contact or IBC) solar cell, the innovation of the monolithic island solar cell (or Icel) described herein, (MWT) back-contact solar cell, a semiconductor heterojunction (SHJ) solar cell, a front-side / rear-side-junction solar cell, a front-side / All cell designs described above include crystalline silicon (e. G., A final cell silicon layer thickness < RTI ID = 0.0 > (Single crystal or polycrystalline) semiconductor absorber material (germanium, germanium, or polycrystalline silicon) ranging from a few microns to less than about 200 microns) It uses arsenic, gallium nitride, or a semiconductor material, or a combination thereof). The monolithic island solar cell (or Icel) innovation disclosed herein is broadly applicable to composite semiconductor multiple junction solar cells.

The advantages of the disclosed monolithic island solar cells or Icel can be monolithic during the fabrication of the cell and can be easily integrated into existing solar cell fabrication processes. The island-master cell embodiments described herein can be used with numerous backplane-attached solar cell designs, processing methods, and semiconductor substrate materials, and the rear-side solar cell attached to the backplane can be used with the epitaxial silicon lift - off process flow. 4 is a schematic diagram of a typical rear-side contact solar cell fabrication process for a crystalline silicon solar cell fabrication process using this battery fabrication process-a relatively thin-film epitaxial silicon lift-off process, wherein the epitaxial silicon lift- Can eliminate many process steps and reduce the use of silicon materials in a typical crystalline silicon solar cell fabrication step to form high efficiency, back-side / junction-side-contact crystalline silicon solar cells and modules. Specifically, the process flow of FIG. 4 includes a photovoltaic cell that selectively permits smart cell and smart module design (i.e., permits embedded and distributed electronics components to improve power collected from solar cells and modules) Attached crystalline silicon solar cell comprising a backplane (e.g., a prepreg backplane sheet stacked on the back side of a solar cell) attached to the rear side of the solar cell for the module, wherein the seeds of the polycrystalline silicon (Monolithic or polycrystalline) silicon templates and epitaxial silicon deposition on a separate layer and using and integrating the monolithic island cell (Icel) structures and methods disclosed herein.

The solar cell process flow of FIG. 4 can be used to form a monolithic island solar cell or an Icel cell. The process illustrated in FIG. 4 begins with a crystalline silicon template, such as a p-type single crystal or polycrystalline silicon wafer, which is reusable (at least several times reused, in some cases less than 10 to 100 times) A thin layer of the porous silicon (with a few microns to a few microns or less) sacrificial layer is formed (e.g., by an electrochemical etch process for template surface modification in HF / IPA or HF / acetic acid wetting reagents in the presence of an electric current) . The porous silicon layer may comprise at least two layers and comprises a surface layer of small pores and a buried layer of high pores. The starting material or reusable crystalline silicon template may be a single crystal (also known as a polycrystalline) silicon wafer, which may be, for example, a crystal growth method such as a float zone (FZ), a Czochralski CZ), self-stabilizing CZ (MCZ), and optionally an epitaxial layer on such a silicon wafer. In addition, the starting material or reusable crystalline silicon template can be, for example, a polycrystalline silicon wafer formed using casting or ribbon and can comprise an epitaxial layer on such a silicon wafer. The template semiconductor doping form may be p or n (often a relatively heavy p-type doping for promoting porous silicon formation), and wafer shape, but most square shapes may be arbitrary, such as quasi-square (quasi-square), hexagonal, Shape or non-shape.

A high quality epitaxial seed layer may also be formed in the formation of a sacrificial porous silicon layer that functions as a lower isolating / liftoff layer of the resulting epitaxial silicon layer, in situ doped (e.g., to form an n-type epitaxial silicon layer (E. G., A layer thickness in the range of from several microns to less than about 100 microns, and in some instances, an epitaxial silicon thickness of less than about 50 microns) of crystalline (monocrystalline or polycrystalline) Which is called epitaxial growth. In-situ doped polycrystalline (polysilicon layer on the single crystal layer or a polycrystalline template on the single crystalline template), a silicon layer is, for example, trichloromethyl silane or TCS and hydrogen (and the dopant gas of the desired, such as the n-type doping PH _3.) And May be formed by atmospheric pressure epitaxy using chemical vapor deposition or CVD in an atmosphere containing the same silicon gas.

(In some instances doped emitter formation, back passivation, contact of the doped base and emitter contact areas to the base and emitter areas for subsequent metallization, and solar cell metallization , The somewhat inexpensive backplane layer is attached to the thin film epi layer to permanently support and reinforce the cell and can also be attached to the thin film epi layer (e.g., after the backplane- Or M1, and a two-layered metallization structure using a second patterned metallization layer or M2 on the back side of the backplane-attached solar cell after lift-off separation of the backplane-attached solar cell from the backplane-attached and reusable template ) To form a highly conductive cell metallization structure of the solar cell. The continuous backplane material may be a thin film (e.g., a thickness in the range of about 50 microns to about 250 microns), flexible, and may include a sheet of electrically insulating polymer material, for example, a printed circuit board And may be formed of an inexpensive prepreg material generally used in the present invention. (IBC) backplane-attached solar cell (e.g., a solar cell area of about 100 mm x 100 mm, 125 mm x 125 mm, 156 mm x 156 mm, 210 mm x 210 mm or more, or about 100 cm ² to several hundreds cm ² or more) is lifted off (separated) from the reusable template along the mechanically deteriorated sacrificial porous silicon layer (e.g., by mechanical separation or MR lift off Separating the porous silicon interface with a high pore to enable lift-off separation through the process), the template can be adjusted (e. G., Cleaned) to reduce the manufacturing cost of the entire solar cell, It can be reused several times (for example, between 10 times and 100 times). The residual post-lift-off solar cell processing may be performed first on the exposed backplane-attached solar cell, e.g., the solar cell solar side (or front side) after being lifted off and separated from the template. Solar cell front or sun side processing can be used for front passivation, and antireflective coating (ARC), for example, using front side texturing (e.g., alkaline or acid texturing), surface preparation after texturing (cleaning) ≪ / RTI > The front passivation and ARC layer may be deposited using a plasma chemical vapor deposition process (PECVD) and / or additional suitable processing methods.

The monolithic island cell (icel) structures and methods described herein may be incorporated into a device fabrication process, such as, for example, the disclosed solar cell fabrication process flow, which may substantially alter or add manufacturing process steps or tools Does not substantially add to the manufacturing cost of the solar cell, and does not substantially change the main solar cell manufacturing process flow. Indeed, the monolithic island cell (Icel) structures and methods disclosed herein can be used to reduce metallization costs (using less metallization materials and lower cost metallization processes) and / or improving solar cell and module manufacturing yields The manufacturing cost of the solar cell can be reduced due to substantial microcracking or breakage of the solar cell.

In one embodiment, to form an inner island partition trench boundary, the thickness of the master cell silicon substrate layer (e.g., after epitaxial silicon substrate layer lift-off separation of the backplane-attached epitaxial silicon substrate layer) (For example, pulsed nanosecond laser scribing), a mechanical scribing method, or a plasma scribing method from the front side or the sun side The master cell semiconductor substrate may be scribed (known as trenching, cutting, or dicing) to form a plurality of trench compartment islands, minicells, subcells, or tiles. Pulsed laser ablation scribing (or any of the above-described suitable trench scribing techniques described above) can be achieved by scribing through the thickness of the semiconductor substrate layer to produce a relatively narrow trench isolation border (e. G., Less than 100 microns wide) Is formed in the entire thickness of the silicon layer, and in particular stops at the backplane (the removal of the continuous backplane material layer and the scribing is somewhat smaller or negligible), the fully segmented monolithic island supported on the continuous backplane layer A battery or a mini-cell or a tile) in a monolithic manner. A method for forming a plurality of islands and their associated trench compartment boundaries in a master cell substrate having a thickness of from several microns to about 200 microns (master cell substrate thickness or width shown as W in Fig. 2) Pulsed laser scribing (or dicing or trenching), ultrasonic scribing or dicing by pulsed nanosecond laser removal (using suitable laser wavelengths such as UV, green, IR, etc.); For example, mechanical trench formation using mechanical wafers or blades; Patterned chemical etching (wet and plasma etching); Etch paste activation after screen printing of the etch paste and etch paste residue cleaning, or any combination of the known or described trenching methods. The pulse laser removal process for forming traces can directly pattern a plurality of island or mini cell boundaries to have a relatively high process throughput and form relatively narrow trenches (e.g., less than about 100 microns trenches) And is advantageous in that it does not involve any process consuming (and therefore a very low process cost). Regardless of the trench formation method used to partition a plurality of islands or sub-cells, however, it should be noted that reducing or reducing the width of the trenches, for example, should be particularly careful, and it is desirable to have a trench width of less than about 100 microns This is because the solar cell area loss due to the partitioned Icel trench becomes a negligible fraction (for example, less than about 1% of the total Icel cell) that is relatively small compared to the entire Icel cell area. This will ensure that the overall area efficiency loss of the Icel can be negligible (e.g., less than 1%) due to the trench trench. The pulse nanosecond laser ablation process can form a high throughput trench with a trench width of less than 100 microns (e.g., from about 10 to 60 microns). For example, a trench having a master cell area (156 mm x 156 mm) and a 4 x 4 island (or mini battery) and having a trench width of 50 microns (0.05 mm) formed by, for example, The area ratio R of the entire trench plane surface area A _{trench to} the entire master cell area (or the Icel cell area A _icel ) can be calculated by the following equation: R = A _trench / A _Icel = 6 x 156 mm x 0.05 mm / (156 mm x 156 mm) or R = 0.00192. Thus, this means that the area ratio R is 0.00192 or about 0.2%. This ensures that if the trench area is delimited with a very small area ratio, the loss of the overall area efficiency of the icel is negligible. In fact, under these conditions, the loss of the overall area efficiency of the icel is less than 0.2%, because direct and / or diffuse solar radiation affecting the trench isolation or zone area is absorbed in most island semiconductor edge regions as the case may be, At least partially to the process.

The monolithic island (tile) solar cell fabrication methods and structures described herein may be applied to a variety of semiconductor (e.g., including, but not limited to, crystalline silicon, such as thin film epitaxial silicon or thin film crystalline silicon wafers) Contact or rear-contact solar cells of various designs having a battery semiconductor absorber having a thickness in the range of, for example, from about several microns to about 200 microns or less), and employing epitaxial silicon lift-off processing (CZ, MCZ, or FZ) wafers or polycrystalline wafers (cast or ribbon growth wafers) that are formed from a single crystal (e.g., silicon) wafer (described above) or a crystalline silicon wafer.

For a back-contact / back-side-junction square cell (e.g., a high efficiency rear-side / backside-junction-IBC cell formed using epitaxial silicon lift-off processing by backplane reinforcement or crystalline silicon wafer cells) The islands (also tiles, packaging materials, sub-cells, or mini-cells) may be fabricated from N x N square islands, N x M rectangular islands, K triangular islands, or any shape islands or combinations thereof on a continuous master cell (For example, using pulsed nanosecond laser scribing of a crystalline silicon substrate). In the case of solar cells fabricated using epitaxial lift-off processing, the island partition trench formation process may be performed after the liftoff isolation of the partially fabricated backplane-attached master cell and after the surface treatment, such as surface cleaning after front surface texturing and texturing , Or immediately after surface cleaning after front side texturing and texturing and prior to a process for forming a front passivation and anti-reflective coating (ARC) layer. (To form solar cell front side textures to reduce light reflection loss), pulsed laser scribing, or any other suitable method (such as, but not limited to, any of the other methods described above, such as mechanical dicing) (I.e., a trenching process) by performing a process for forming a trench or isolation trench (i. E., Trenching process), such that the trench sidewall is divided into several microns of silicon containing several microns of silicon Removal of any trench process induced silicon edge damage through wet etch (which etches the etch process), and wet texturing.

In some solar cell processing embodiments, including representative process streams described in detail herein, additional, separate manufacturing process equipment may not be required to form the monolithic island master cell (Icel). That is, the process of forming the trench section mini-cell or the island in each of the Icel cells can be easily and uniformly included in the solar cell manufacturing method. In some cases, the monolithic island solar cell (Icel) fabrication process does not require a copper plating process and related manufacturing equipment, for example, and facilitates the copper plating requirements, thereby reducing the cost of solar cell metallization, And the solar cell manufacturing process flow can be improved.

5A is a representative backplane-attached Icel cell fabrication process flow based on epitaxial silicon and porous silicon lift-off fabrication. This process flow is for fabricating a backplane-attached, rear-side / rear-side-junction solar cell (icel) using two patterned solar cell metallization layers M1 and M2. This example is shown for a solar cell with an optional emitter, and as a selective emitter, a light emitter doped main patterned field emitter formed by using light boron-doped silicate glass (A small boron doped first BSG layer deposited by a tool 5), and a heavy boron-doped emitter contact region (a large boron doped second BSG layer deposited by tool 5) using heavy boron-doped silicate glass . Although this example is shown for an IBC solar cell using a dual BSG selective emitter process, the Icel design is applied to a wide variety of other solar cell structures and process flows, which are not selective emitters (i.e., field emitters and And the same emitter doped IBC photovoltaic cells in the emitter contact region. This example is shown for an IBC i-cell having an n-type base and a p-type emitter. However, the polarity can be changed so that the solar cell has a p-type base and an n-type emitter instead.

5A is a representative manufacturing process flow embodiment for fabricating a rear-side back-side-junction monolithic islands crystalline silicon solar cell (icel). Specifically, FIG. 5A shows an epitaxial (epi) solar cell having a monolithically integrated bypass switch (MIBS) pn junction diode and a dual borosilicate glass (BSG) selective emitter. As shown in this flow, the mini-battery trench isolation region is formed before the texturing of the separation side (also referred to as the front side or the sun side of the obtained icicle) exposed after the battery separation border scribing in the tool 13. In addition, the mini-battery trench isolation region may be formed after texturing in tool 14, and after cleaning and after frontal passivation (indicated by PECVD). Performing pulsed laser scribing before wet etch texturing (cleaning after texturing and texturing with tool 14) can add the benefit of eliminating any laser induced scribed silicon edge damage and damaging silicon removal through wet etching have.

A typical process flow for forming a monolithic island (tile) rear-side / backside-junction (IBC) solar cell by epitaxial silicon lift-off processing includes the following fabrication steps: 1) reusable crystalline (single crystal or polycrystalline) Starting with silicon template; 2) formation of porous silicon on the template (using HF / IPA or HF / acetic acid anodic etching to form a low pore surface layer and a two-layer porous silicon containing high pore buried layer); 3) epitaxial silicon deposition (e. G., N-type doped epitaxial silicon) by in-situ doping; 4) Performing a rear-side / backside-side junction cell processing and positioning the epitaxial silicon substrate on the template to form a patterned field emitter junction, backside passivation, doped base for the next metal- (See FIG. 5A), and a dual BSG process (BSG is performed by atmospheric pressure chemical vapor deposition or APCVD process) for selective emitter formation (Including a lightly-doped field emitter and a heavily doped emitter contact region) using a boron-doped silicate glass or a boron-doped silicon oxide layer formed on the back-contact / rear side 5a for an example of a junction (IBC) solar cell fabrication process flow (other methods of selective emitter formation use screen printed dopant paste and dual BSG Process can be used); 5) attaching or laminating a backplane layer or sheet on the back side of the rear-side contacted cell; 6) Separation of the separating border at the epitaxial layer thickness around the backplane boundary, at least partially by laser scribing (lift-off of the separation boundary), followed by separation by a lift-off process (for example by mechanically degrading high pores Mechanical separation lift off to separate the backplane-attached epitaxial silicon substrate from the reusable template by separating the porous silicon layer); 7) Pulsed nanosecond laser removal from the solar cell side (opposite the backplane) to partition the silicon substrate monolithically with a plurality of mini-cells or islands, for example, 4 x 4 = 16 mini-cells (or any other suitable (Also scribing, cutting, or dicing) process (also optionally using a smooth smoothing cell boundary edge) to determine precise master cell or cell dimensions, such as a pulse Selectively adjusting the perimeter of the master cell using laser cutting; 8) Performing the remaining post-fabrication process, for example, wet silicon etching / texturing in alkaline and / or acidic chemicals (this process protects the back side of the solar cell from the texturing agent by the drug resistant backplane while performing texturing on the front side Surface preparation after texturing such as wet cleaning (this process protects the back side of the solar cell from the wet cleaning agent by a drug resistant backplane while performing front surface cleaning), front surface passivation and antireflective coating (ARC) coating, For example, a combination of additional processes such as plasma enhanced chemical vapor deposition (PECVD) or ARC deposition, such as PECVD (e.g., hydrogenated silicon nitride) and passivation layer deposition atomic layer deposition (e.g., A layer of aluminum oxide, amorphous silicon, or amorphous silicon oxide under the silicon nitride ARC layer on the silicon surface When using a two layer structure of one of the above described passivation layers covered with a film layer (less than 30 nm), a multilayer front side passivation / ARC structure, for example a silicon nitride ARC layer, the entire stack is subjected to PECVD using a vacuum integration process ). ≪ / RTI > The front side passivation and ARC layer deposition covers the front surface of the mini-cell or island and covers the sidewalls of the trench compartment island or mini-cell, and substantially the passivation and ARC characteristics of the icel are affected by the passivation of the trench sidewalls, And is improved by improving the collection characteristics. After the end of the front side texturing / cleaning / passivation and ARC deposition process, the remaining solar cell fabrication process step involves forming a second metallization layer M2 on the back side of the backplane-attached solar cell. For this task, the plurality of via holes may be formed by depositing a thin film (e.g., 25 micron to 250 micron backplane thickness), electrically insulating, continuous backplane layer (e.g., 25 microns to 100 microns thick (For example, a prepreg sheet laminated with a metal sheet) is drilled using, for example, a laser drill. The number of via holes on a solar cell (e.g., 156 mm x 156 mm Icel) backplane may be from hundreds to several thousand. The via holes may have an average diagonal hole dimension (e. G., An average diameter of each via hole) ranging from tens of microns to hundreds of microns (e. G., From about 100 microns to 300 microns). Laser drilled via holes through the electrically insulated backplane layer are formed by a first patterned metallization level by screen printing or physical vapor deposition of a metal paste and patterning of a metal layer such as a metal comprising aluminum or an aluminum- ) ≪ / RTI > on the meshed base and emitter metallization fingers. These via holes may be formed by a first patterned metallization layer formed directly on the back side of the solar cell prior to backplane-attach / lamination, or an interconnecting channel or plug between the second patterned metal layer or M2 formed immediately after formation of M1 and laser drilled via holes It will play a role. In some examples of the Icel's disclosed herein, the second patterned metallization level M2 may be formed by one of several methods, which may include (1) providing an inexpensive high conductivity metal (e.g., aluminum and / or copper, (E. G., Aluminum and / or copper, e. G., Aluminum, and / or copper) after physical vapor deposition or PVD (thermal evaporation, electron beam evaporation, and / or plasma sputtering) Physical vapor deposition of PVD (thermal evaporation, electron beam evaporation, and / or plasma sputtering) followed by metal etch patterning (e.g., screen printing of an etch paste or screen printing of a resist, Resist stripping followed by a metal wet etch process), (3) screen printing or stencil printing of suitable metal pastes (e.g., copper and / or aluminum Paste), (4) inkjet printing of suitable metal pastes or aerosol printing (e.g., a paste comprising copper and / or aluminum), (5) plating of a suitable patterned metal, But are not limited to, combinations thereof. The second patterned metallization layer M2 (e.g., aluminum and / or copper containing a high conductivity metal) protects the primary patterned M2 and, if necessary, provides an accurate surface to the solder or conductive adhesive (For example, a NiV or Ni thin film (less than 1 micron) trapping layer formed by plasma sputtering or screen printing or plating). The rear-side / rear-side-junction (IBC) solar cell described herein may utilize two patterned metallization layers M1 and M2, wherein the first patterned metallization layer M1 has a first pitch pattern Base-emitter M1 finger pitch in the range of about 200 microns to about 2 mm, in some cases in the range of about 500 microns to about 1 mm), forming base and emitter metallization fingers on each mini-cell or island, And the second patterned metallization layer M2 forms the final Icel metallization according to a predetermined current and voltage scale factor and interconnects the island or mini-cell. The patterned M2 may be patterned to be substantially perpendicular or orthogonal to the patterned M1 and may have a pitch between the fingers that is much larger than the patterned M1 finger. This makes it easy to fabricate the patterned M2 according to a substantially low cost, high yield manufacturing process. To interconnect M2 and M1 based on the desired icicle metallization structure, the patterned M2 forms the final Icel patterned metallization and forms an electrically conductive via plug through the laser drilled via hole.

The Icel concept is that the second patterned metallization layer M2 is used to monolithically interconnect a plurality of Icelels that share the same continuous backplane layer as well as form an individual master cell (or Icel) electrical interconnect, The monolithic module structure can be fabricated according to embodiments and can be extended to have many additional advantages. 5A shows a process flow for fabricating a monolithic Icel cell for an epitaxial silicon lift off-ice representative embodiment, wherein each Icel is attached to a separate pre-cut continuous backplane layer, and each individual backplane- After stacking the backplanes, they are processed through the entire back-end process flow. Using this approach, the processed Icel can be tested, aligned after the process, assembled into a PV module by interconnecting the Icelels, for example in an electrical series, using the tapping and / or stringing of the cell (Also including soldering and / or conductive adhesives to connect the plurality of solar cells together as part of the PV module assembly), module lamination, final module assembly, and testing. Referring to Figure 5a for a representative embodiment, a further embodiment of the Icel execution that forms the novel monolithic module structure is shown in Figure 5a in the backplane lamination (or attachment step) performed by the tool 12 (E. G., An icicle spacing in the range of 50 microns to about 2 mm, often in the range of 100 microns to 1 mm) of adjacent relatively large spaced backplane sheets of a plurality of relatively close spaced icicles on the back side. The remaining process steps after the tool 12 are performed on a plurality of Icelels sharing a common continuous backplane layer on the back side (instead of being performed on separate Icelels, each with a separate backplane). After the final metallization (the second patterned metal layer M2), the monolithic patterned M2 forms a metallization pattern for each of the Icsels among the plurality of Icsels sharing a large continuous backplane layer, and a plurality Interconnecting the Icel cells in a serial or parallel / serial hybrid arrangement, for example. This embodiment eliminates the need to fabricate the Iceland and electrically connect it to the continuous backplane layer shared among the plurality of Icelels in a monolithic manner and to subsequently solder / tabbing / stringing each other during the final module assembly. For example, to fabricate a 6x10 = 60 battery module, immediately after the formation of the first patterned metal layer (M1) in a backplane sheet (e.g., a sheet of prepreg) of appropriate size after the tool 11 process of Figure 5a, The array of 6 x 10 = 60 cells is attached / laminated and the remaining process steps (initiating the backplane lamination / attachment process shown as tool 12 through the remaining post process steps through the formation of the second patterned metal layer M2) For example, 6x10 = 60) is carried out on a large backplane-attaching sheet including the icel. In a monolithic module embodiment comprising 6x10 = 60 Icsels, each of the Icelels has a dimension of about 156 mm x 156 mm, the spacing between adjacent i-cells is about 1 mm, and the continuous (For example, aramid fibers / resin prepreg sheets in the range of about 50 to 100 microns thick) should have a minimum dimension of about 942 mm x 1570 mm (e.g., the sheet is 6x10 = 60 iCels May be somewhat enlarged to allow backplane expansion in the side margins of the monolithic module, which is about 1 m by 1.6 m backplane sheet dimensions in a monolithic module embodiment). As a further example, in order to fabricate a 6x12 = 72 battery module, the completion of the first patterned metal layer M1 on a suitably sized continuous backplane sheet (e.g., prepreg sheet) after the tool 11 process of Figure 5a Immediately afterwards, an array of 6x12 = 72 Icelels is attached / laminated and the remaining process steps (initiating the backplane lamination / attachment process shown as tool 12 through the remaining post process steps through formation of the second patterned metal layer M2) Is carried out on a large backplane-attaching sheet comprising a plurality (e.g. 6x12 = 72) of Icelels. In a monolithic module comprising 6x12 = 72 Iceluses, each of the Icelels has a dimension of about 156 mm x 156 mm, the spacing between adjacent Icelels is about 1 mm, and a continuous backplane to be used for attaching / laminating behind the 6x12 array of Icel's Layer or sheet (e.g., an aramid fiber / resin prepreg sheet in the range of about 50 to 100 microns thick) should have a minimum dimension of about 942 mm x 1884 mm (e.g., the sheet is 6x12 = 72 Iicell monolithic May be somewhat enlarged to allow backplane expansion in the side margins of the monolithic module, which is about 1 m by 1.9 m backplane sheet dimensions in the module embodiment). The monolithic interaction of a plurality of Icelels on the shared continuous backplane layer using the second patterned metal layer M2 not only reduces the cost of manufacturing the entire solar cell and PV module (solder tab, string removal) Improves the reliability of the PV module.

Embodiments of the present invention can be applied to solar cells using this type of process flow schematically illustrating the exemplary process flow of Figure 5A, as well as many solar cell designs (described above) and solar cell fabrication process flows, , A starting monocrystalline wafer (e.g., Czochralski or CZ, float zone or FZ) or a polycrystalline wafer (formed by a ribbon pooling process or by a casting brick) or by epitaxial growth or other substrate fabrication methods But are not limited to, fabricated solar cells. In addition, the Iceland embodiment can be applied to semiconductor materials other than the silicon described above, including, but not limited to, gallium arsenide, germanium, gallium nitride, other compound semiconductors or combinations thereof.

Figure 5b is a high level solar cell and module fabrication process flow embodiment using a starting (monocrystalline or polycrystalline) silicon wafer. Figure 5b shows a high level Icel process flow for fabricating a backplane-attached rear-side-contact / rear-side-junction (IBC) Icelel using two metallization layers: M1 and M2. The first patterned cell metallization layer, or level M1, is basically a multi-layered cell metallization layer or level M1 that is fabricated from a partially processed Icel (or a large continuous backplane attached to a plurality of partially processed Icelells when making the monolithic module described above) As a final process step in the shear cell fabrication process of FIG. The shear cell fabrication process schematically illustrated in the upper four boxes of FIG. 5B basically forms the rear-side / back-side-junction solar cell backside structure through the patterned M1 layer. The patterned M1 comprises a fine pitch meshing metallization pattern as described in the epitaxial silicon Icel process flow, which is designed to conform to an Icel (miniature cell) and schematically illustrated in Figure 5a. 5B, the fifth box from the top includes the attachment or lamination of the backplane layer or sheet to the partially processed Icel rear side (or to the rear side of a plurality of partially processed Icelels when making monolithic modules) The steps are basically the same as those performed by tool 12 in Figure 5a (in the case of an epitaxial silicon lift-off process). In Fig. 5B, the top sixth and seventh boxes are used to define the remaining front side (optional silicon wafer thinning, trench compartments, texturing, post-texturing cleaning, passivation and ARC to form a thin film silicon absorbing layer, (Or referred to as post lamination) cell fabrication process to form a metallized layer or level M2 that has been metallized. The post-lamination process (or the post-cell fabrication process performed after the backplane-attachment) schematically illustrated in the 6th and 7th boxes of FIG. 5B is performed by using the tools 13 through 18 for the epitaxial silicon lift- Lt; / RTI > The lower box in Figure 5b describes the final assembly in which the resulting icel was formed of a PV module of flexible lightweight PV module or rigid glass cover. The process flow is schematically illustrated in a bottom box of FIG. 5B, when forming a monolithic module comprising a plurality of Icel monolithic interconnections by patterned M2 (as described above for the epitaxial silicon lift-off process flow) The remaining PV module fabrication process shown can be simplified because patterned M2 metallization for interconnection between the cells and a plurality of interconnected Icelels sharing a large continuous backplane are already electrically interconnected, There is no need to tap, string, and / or solder. The resulting monolithic module can be either a flexible lightweight PV module (e.g. using a flexible thin film fluoropolymer cover sheet such as ETFE or PFE on the front side instead of a rigid / heavy glass cover sheet), or a PV module covered with hard glass Can be stacked.

FIG. 5C shows an additional high-level solar cell (Icel) and module fabrication process flow embodiment using epitaxial silicon and porous silicon lift-off processing as compared to the process flow of FIG. 5A. Figure 5c shows a high level of Icel process flow for fabrication of a backplane-attached rear-side-contact / rear-side-junction (IBC) cell using two metallization layers: M1 and M2. The first patterned cell metallization layer or level M1 basically comprises epitaxial silicon as the solar cell absorber and a partially processed icel (or a lift-off of the partially treated icel when fabricating the monolithic module described above) A large continuous backplane attached to a plurality of partially processed epitaxial Icel cells after separation), as a last process step in a plurality of shear cell fabrication processes prior to backplane lamination. The shear cell fabrication process schematically illustrated in the upper four boxes of Figure 5c basically forms the rear-side / back side-junction solar cell backside structure through the patterned M1 layer. The patterned M1 comprises a fine pitch meshing metallization pattern as described in the epitaxial silicon Icel process flow, which is designed to conform to an Icel (miniature cell) and schematically illustrated in Figure 5a. In Figure 5c, the fifth box from the top shows the backplane layer on the partially processed Icel rear side (or using a large continuous backplane sheet affixed to the rear side of a plurality of partially processed and discrete Iccells when making monolithic modules) Or sheet deposition or lamination, and this process step is basically the same as that performed by the tool 12 of FIG. 5A in the case of an epitaxial silicon lift-off process. In Figure 5c, the top sixth and seventh boxes are used to complete the remaining front side (Iceland trench compartment, texturing, post-texturing cleaning, passivation and ARC), also via holes and the second patterned metallization layer or level M2, Or post backplane-attaching (or post-lamination) cell fabrication process. The post lamination process (or the post-cell fabrication process performed after the backplane-attachment) schematically illustrated in the 6th and 7th boxes of Fig. 5c is performed on tools 13 through 18 for the epitaxial silicon lift- ≪ / RTI > The lower box in Figure 5c describes the final assembly in which the resulting icel is formed of a PV module of flexible lightweight PV module or rigid glass cover. The process flow is schematically illustrated in a lower box of Fig. 5C, when forming a monolithic module comprising a plurality of monolithic interconnected Icsels by patterned M2 (as described above for the epitaxial silicon lift-off process flow) The remaining PV module fabrication process shown can be simplified because patterned M2 metallization for interconnection between cells and a plurality of interconnected Icsels sharing a large continuous backplane are already electrically interconnected to connect the solar cells to each other There is no need to tap, string and / or solder. The resulting monolithic module can be either a flexible lightweight PV module (e.g. using a flexible thin film fluoropolymer cover sheet such as ETFE or PFE on the front side instead of a rigid / heavy glass cover sheet), or a PV module covered with hard glass Can be stacked.

5D is a high level cross-sectional view showing an enlarged and selective schematic of a mini-cell or island among a plurality of islands in an Icel cell after the solar cell fabrication step of an interwoven rear-side-contact (IBC) solar cell embodiment. Conductive doped emitter and base region, an optional front-side field (FSF) and / or an optional back-side field (BSF) region, contact and patterned M1 of M1 metallization to M2 patterned through an electrically insulating continuous backplane layer Via plugs are not shown.

5E is a detailed cross-sectional view showing an enlarged view of a mini-cell or island among a plurality of islands in an icel after a solar cell fabrication step in an interwoven rear-side-contact (IBC) solar cell embodiment. These cross-sectional views are provided in cross-sectional views as a detailed embodiment of a detailed battery structure that can be used according to the disclosed subject matter.

In practice, the primary initial continuous semiconductor substrate is divided into a plurality of mini-cells (or islands or sub-cells or tiles) on the continuous support backplane layer through the thickness of the substrate layer (from the epitaxially grown crystal layer or from the starting crystalline semiconductor wafer) The isolation trenches may have an average trench width and may be tens of microns (or from about 10 microns to about 100 microns). As described above, the trench isolation region that divides the backplane-attached semiconductor layer into a plurality of mini-cells (or an i-cell or a sub-cell or a tile) uses pulse laser ablation / scribing or another method, , Mechanical dicing / scribing or ultrasonic dicing / scribing or water jet dicing / scribing or by additional methods ("scribing, dicing, cutting and removing" Wherein the partition trench or isolation trench is supported by a continuous backplane layer or sheet attached to the partially processed semiconductor substrate prior to the compartment trench formation process, In the case of a trench pattern formed through a semiconductor layer thickness to form a plurality of islands or minicells, It is used interchangeably in old books). A suitable trench section or isolation forming process, for example a pulsed laser scribing or cutting process, is optionally cut through the semiconductor layer and is basically cut through the entire thickness of the semiconductor layer without substantially removing the backplane material Effectively stops on the backplane layer or sheet (thus negligible or relatively small trenches of the backplane layer to maintain integrity of the continuous backplane sheet). For example, a trench formation process, for example, a pulse nanosecond removal scribe process, can be performed to form a desired trench pattern by cutting through a semiconductor layer thickness based on a desired trench pattern, Limiting the backplane sheet material removal to a relatively small range between zero and less than the backplane layer thickness fraction (e.g., a backplane material trenching depth limited to between 0 and less than about 20% of the backplane layer thickness) Or a monolithic module when fabricating a monolithic module using a plurality of i cells attached to a shared backplane sheet).

The methods and structures described herein provide a master monolithic cell (icel), which includes trench compartments or trench isolation islands (also referred to as tiles, packaging materials, sub-cells or mini-cells). The shape of a typical master monolithic cell (icel) is square, but the master cell (icel) can be, for example, a square, quasi-square, rectangular, quasi-rectangle, parallelogram, hexagon, triangle and polygon, Such as a combination of < RTI ID = 0.0 > a < / RTI > Most common shapes used in crystalline silicon solar cells and modules are full-square and quasi-square solar cells. Further, the trench section islands may be formed in various and different shapes and sizes (area and side / diagonal dimensions), or may be formed in a uniform size (i.e., the islands formed in a uniform size have the same shape And area). One consideration in determining the shape and size of the islands that make up the solar cell is to reduce the generation of cracks or crack propagation in the resulting solar cell and solar cell metallization structure comprising the semiconductor absorbent layer, Battery flexibility or bending and compliance (when using a flexible backplane sheet, for example, a prepreg sheet). In some instances, during and after cell fabrication, during module stacking and during field operation of the resulting PV module, the solar cell edge may be susceptible to crack formation and propagation, so that the central region of the master cell (icel) It may be desirable to locate relatively small islands (e.g., small triangles or square islands) near relatively large islands (e.g., squares) and near the edge of the master cell (icel) In another example, depending on the electrical connection design of the islands, the islands (or subgroups connected in an electrically parallel arrangement) may have a uniform shape to produce a uniform current under uniform illumination. Importantly, the number of islands and / or sizes may be varied according to other considerations such as the electrical interconnection design between the islands and the master cell (Icel) flexibility / bendability to produce the desired Icel voltage and current scale factor .

For a square or rectangular master cell (Icel) having an array of square or rectangular islands attached to a shared continuous backplane, the islands may be N x N arrays, where N is an integer greater than or equal to 2 (e.g., N x N is at least 4, i. E. There are at least four islands in the icel). Generally, an Icel can have two islands or sub-cells (e.g., two sub-cells or a square Icel with an island may have two triangular islands). The Icel structure with N x N islands has the advantage of having a simple structure in terms of Iceland processing and interconnect design as well as excellent compatibility with full square and quasi-square solar cells. Also, the islands can be NxM arrays, and N and M are both integers (e.g., NxM is 2 or more, i.e., at least two islands). Using a flexible continuous (or continuous) backplane, the degree of icelin flexibility, bending, or wetting can be increased for large values of N x N or N x M and / or using relatively small size islands close to the cell edge region have. For example, for a 156 mm x 156 mm square or quasi-square i-cell, an i-cell having 4 x 4 = 16 islands (e.g., islands of uniform area) may have 3 x 3 = 9 islands (e.g., Will be more flexible or bent than an icel having an island of uniform area. The flexibility / bend of the improved Icelel is preferably due to the flexible, lightweight PV module. The number of islands of any shape can be increased or decreased depending on the flexibility, bending, or tortuosity of the desired master cell, but the area of the trench and the corresponding increased cell edge area (total trench sidewall area of the island or mini battery) Of the semiconductor material should be limited to, for example, less than about 2% of the area of the master cell (icel), and in some cases less than 1% of the area of the icel.

In some instances, it may be desirable to increase the cell porosity by forming islands (tiles, mini-cells) with, for example, mini-cells of a particular shape, for example triangular Icelels (mini-cells). For example, in order to increase battery flexibility or compliance with a variety of bending directions (e.g., X, Y, and diagonal axes) relative to a square or rectangular master cell (icel), the islands may be triangular or square (In some embodiments, a square island in the vicinity of the master cell center region and a triangular island in the vicinity of the cell edge region). Importantly, various combinations of islands shapes and arrangements in the master cell (icel) may be formed with the disclosed subject matter.

6A and 6B are views of a backplane-attached solar cell (Icel) embodiment showing an array of uniform square mini batteries (i.e., an icel or mini battery having essentially the same area). Figure 6a shows an Icel pattern (shown for square islands and square Icel cells) with square islands of uniform size (same size) for N x N = 3 x 3 = 9 islands (or sub- (Front side or sun side). This schematic drawing shows a plurality of islands (shown as 3 x 3 = 9 islands) delimited by trench isolation regions. 6B shows a cross-sectional view of an Icel pattern (shown for square islands and square Icel cells) with a square size (equal size) square island for N x N = 5 x 5 = 25 islands (or sub- (Front side or sun side). The schematic drawing shows a plurality of islands (5 x 5 = 25 islands) delimited by trench isolation regions.

6A is a schematic top or plan view of a 3 x 3 uniform island (tile) master solar cell or icel 30 defined by a cell perimeter boundary or edge region 32 and having a side length L, And nine uniform square islands identified as I ₁₁ through I ₃₃ attached to a continuous (continuous) backplane on the back side of the master cell (the backplane and the back side of the solar cell are not shown). Each island or subcell or mini cell or tile is defined by the inner island perimeter boundaries shown by the trench isolation or island partition border 34 (e.g., the isolation trench is cut through the master cell semiconductor substrate thickness, With trench widths less than a few hundred microns and often less than about 100 microns, e.g., from a few microns to about 100 microns). The overall cell (or cell) periphery or edge region 32 has a preform length of 4L, but the overall Icel edge boundary length, including the perimeter dimensions of all the islands, is the cell periphery 32 (also referred to as the cell periphery) And a border 34. Thus, for an Ixel containing an NxN island or mini-cell in a square island embodiment, the overall Icel edge length is the Nx cell periphery. In the representative example of FIG. 6A, which shows an Icel with 3x3 = 9 islands (N = 3), the total cell edge length is 3 x the cell circumference 4L = 12L Which has a peripheral dimension three times larger than that of the prior art battery). For a square master cell or icel with 156 mm x 156 mm, the dimensions of the square island are approximately 52 mm x 52 mm and the area of each island or subcell is 27.04 cm ² per island.

6B is a schematic top or plan view of a 5 x 5 uniform island (tile) master solar cell or icel 40 defined by a cell perimeter boundary or edge region 42 and having a side length L, And 25 uniform square islands identified as I ₁₁ through I ₅₅ attached to a continuous (continuous) backplane on the back side of the master cell (backplane and solar cell rear side not shown). Each island or sub-cell or mini-cell or tile is defined as the inner island perimeter shown by trench isolation or island partition border 44 (e.g., the isolation trench is cut by the master cell semiconductor substrate thickness and the trench width Is substantially less than the dimensions of the islands, less than a few hundred microns, and often less than about 100 microns, e.g., from a few microns to about 100 microns. The overall cell (or Icel) circumferential boundary or edge region 42 has a preform length of 4L, but the overall Icel edge boundary length, including the perimeter dimensions of all islands, is the cell perimeter 42 (also referred to as the cell periphery) And a border 44. Thus, for an Ixel containing an NxN island or mini-cell in a square island embodiment, the overall Icel edge length is the Nx cell periphery. In a representative example of Fig. 6B showing 5x5 = 25 islands (N = 5), the overall cell edge length is 5x the cell circumference 4L = 20L Lt; RTI ID = 0.0 > 5 times < / RTI > For a square master cell or an icel with 156 mm x 156 mm, the dimensions of the square island are approximately 31.2 mm x 31.2 mm and the area of each island or subcell is 9.73 cm ² per island. In some examples that balance with other considerations, the total cell edge length (the cumulative length of the sidewall edges of all the islands in the icel) is limited to 24 L (e.g., 6x6 arrays) to limit the overall Icel edge length and sidewall area May be desirable.

Figures 7A and 7E are representative plan views of a solar cell embodiment (Icel) having triangular islands or mini batteries. Figure 7a shows an example of a triangular island with a uniform size (same size) triangle island (or sub cell, mini cell, tile) having K = 2 x 4 = 8 triangle islands (a pair of triangle islands per square quadrant of the icel) And an exemplary schematic plan view (front or sun side) of the Icel pattern (shown for a square Icel cell). This schematic diagram shows a plurality of islands partitioned by trench isolation regions (shown as K = 2 x 4 = 8 islands). Figure 7b shows an example of a triangular island with a uniform size (same size) triangle (or sub-cell, mini-cell, tile) having K = 2 x 4 = 8 triangular islands (a pair of triangular islands per square quadrant of the i- And an exemplary schematic plan view (front or sun side) of the Icel pattern (shown for a square Icel cell). This schematic diagram shows a plurality of islands partitioned by trench isolation regions (shown as K = 2 x 4 = 8 islands). The trench isolation pattern for the Icel cell of Figure 7b is slightly different from that of Figure 7a. FIG. 7c shows an example of a triangular island with a uniform size (same size) triangle island (or sub-cell, mini-cell, tile) having K = 4 x 4 = 16 triangular islands (four triangular islands per square quadrant of the Icel) (Front or sun side) of the Icel pattern (shown for square Icel). This schematic diagram shows a plurality of islands partitioned by trench isolation regions (shown as K = 4 x 4 = 16 islands). In the present embodiment, the number of triangular islands (mini batteries) is twice as many as the number of triangular islands (mini batteries) in the Icel embodiment of Figs. 7A and 7B. FIG. 7d shows an example of a triangular island (or sub-cell, mini-cell, or tile) of uniform size (same size) having K = 4 x 3 x 3 = 36 triangular islands (four triangular islands per square quadrant of the Icel) (Front or sun side) of the icel pattern (shown for the islands and the square icel). This schematic diagram shows a plurality of islands partitioned by trench isolation regions (shown as K = 4 x 3 x 3 = 36 islands). In this embodiment, the number of triangular islands (mini batteries) is 4.5 times the number of triangular islands (mini batteries) in the Icel embodiment of FIGS. 7A and 7B.

FIG. 7E shows an example of a triangular island (or sub-cell, mini-cell, tile) of uniform size (same size) having K = 2 x 4 x 4 = 32 triangular islands (eight triangular islands per square quadrant of the i- (Front or sun side) of the icel pattern (shown for the islands and the square icel). This schematic diagram shows a plurality of islands partitioned by trench isolation regions (K = 2 x 4 x 4 = 32 islands). In the present embodiment, the number of triangular islands (mini batteries) is four times the number of triangular islands (mini batteries) in the Icel embodiment of FIGS. 7A and 7B.

7A is a top plan view of a uniform triangular island of an island master solar cell or an icel 50 defined by the cell perimeter boundary 52 and having a side length L and an island of eight uniform (identical area) I ₁ to I ₈ . Each island or sub-cell or mini-cell or tile is defined as the inner island perimeter boundary shown by trench isolation or island partition border 54 (e.g., the isolation trench is cut by the master cell semiconductor substrate thickness and the trench width Substantially less than the dimensions of the islands, less than a few hundred microns, and often less than about 100 microns-for example, from several microns to about 100 microns or less. The overall cell (or Icel) peripheral boundary or edge region 52 has a preform length of 4L, but the overall Icel edge boundary length, including the perimeter dimensions of all the islands, is the cell perimeter 52 (also referred to as the cell periphery) And a border 54. In the exemplary embodiment of Fig. 7A showing K = 2 x 4 = 8 triangular islands, the overall cell edge length is 3.4142 x the outer circumference of the cell 4L = 13.567 L (K = 8) Which is 3.4142 times larger than that of the standard prior art cell shown in FIG. For a square master cell or an Icelel with 156 mm x 156 mm, the dimensions of the triangular islands are approximately 78 mm x 78 mm (for two identical right-angled sides of the triangle) and each island or subcell has an area of 30.42 cm ² to be.

7B is a top view of a uniform triangular island of an island master solar cell or icel 60, defined by the cell perimeter 62 and having a side length L, compared to the triangular island or mini battery pattern of FIG. And includes islands I ₁ to I ₈ of eight uniform (equal area) triangular shapes. Each island or sub-cell or mini-cell or tile is defined as the inner island perimeter boundaries shown by trench isolation or island partition border 64 (e.g., the isolation trench is cut by the master cell semiconductor substrate thickness and the trench width Substantially less than the dimension of the islands, less than a few hundred microns, and in some cases less than about 100 microns, e.g., from a few microns to about 100 microns. The overall cell (or icel) perimeter boundary or edge region 62 has a preform length of 4L, but the overall Icel edge boundary length, including the perimeter dimensions of all the islands, is the cell perimeter 62 (also referred to as the cell periphery) And a border 64. (K = 8), the overall cell edge length is 3.4142 x the outer circumference of the cell 4L = 13.567 L (thus, the Icel is also used as a peripheral dimension). In the exemplary embodiment of FIG. 7B, which shows an Icel with K = 2 x 4 = 8 triangular islands, Which is 3.4142 times larger than that of the standard prior art cell shown in FIG. For a square master cell or an Icelel with 156 mm x 156 mm, the side dimensions of the triangular islands are approximately 78 mm x 78 mm (for two identical right-angled sides of the triangle) and each island or subcell has an area of 30.42 cm ² .

7C is a top plan view of a uniform triangular island of an island master solar cell or icicle 70, defined by the cell perimeter boundary 72 and having a side length L, an island of 16 uniform (equal area) I ₁ to I ₁₆ . Each island or sub-cell or mini-cell or tile is defined as the inner island perimeter shown by trench isolation or island partition border 74 (e.g., the isolation trench is cut through the master cell semiconductor substrate thickness and the trench width Substantially less than the dimension of the islands, less than a few hundred microns, and in some cases less than about 100 microns, e.g., from a few microns to about 100 microns. The overall cell (or Icel) circumferential boundary or edge region 72 has a preform length of 4L, but the overall Icel edge boundary length, including the perimeter dimensions of all the islands, is the cell perimeter 72 (also referred to as the cell periphery) And a border 74. In the exemplary embodiment of FIG. 7C showing K = 4 x 2 x 2 = 16 triangular islands, the overall cell edge length is 4.8284 x 4L = 19.313 L (hence, Which is 4.8284 times larger than that of the standard prior art battery shown in Fig. 1). For a square master cell or an icel with 156 mm x 156 mm, the triangular island or sub-cell in this embodiment has an area of 15.21 cm ² per island.

7D is a top plan view of a uniform triangular island of an island master solar cell or Icel 80 defined by the cell perimeter boundary 82 and having a side length L and of 36 uniform (equal area) triangular shapes And islands I ₁ to I ₃₆ . Each triangular island or sub-cell or mini-cell or tile is defined as the inner island perimeter boundaries shown by trench isolation or island partition border 84 (e.g., the isolation trench is cut by the master cell semiconductor substrate thickness, The width is substantially less than the dimension of the islands, less than a few hundred microns, and often less than about 100 microns-for example, from several microns to about 100 microns. The overall cell (or Icel) circumferential boundary or edge region 82 has a preform length of 4L, but the overall Icel edge boundary length, including the perimeter dimensions of all the islands, is the cell perimeter 82 (also referred to as the cell periphery) And a border 84. In the exemplary embodiment of FIG. 7D (K = 36) showing K = 4 x 3 x 3 = 36 triangular islands, the overall cell edge length is 7.2346 x battery circumference 4L = 28.970 L Which is 7.2426 times larger than that of the standard prior art battery shown in Fig. 1). For a square master cell or an icel with 156 mm x 156 mm, the triangular island or sub-cell in this embodiment has an area of 6.76 cm ² per island.

7E is a top plan view of a uniform triangular island of an island master solar cell or an icel 90 defined by the cell perimeter boundary 92 and having a side length L, 32 uniform (identical area) triangular islands I ₁ To I ₃₂ . Each island or sub-cell or mini-cell or tile is defined as the inner island perimeter boundaries shown by trench isolation or island partition border 94 (e.g., the isolation trench is cut by the master cell semiconductor substrate thickness and the trench width Is substantially less than the dimensions of the islands, less than a few hundred microns, and often less than about 100 microns, e.g., from a few microns to about 100 microns. The overall cell (or icel) circumferential boundary or edge region 92 is a preform length 4L, but the overall Icel edge boundary length, including the circumferential dimensions of all the islands, is the cell perimeter 92 (also referred to as the cell periphery) And a border 94. In the exemplary embodiment of FIG. 7E showing K = 2 x 4 x 4 = 32 triangular islands, the overall cell edge length is 6.8284 x 4l = 27.313 L in the exemplary embodiment (K = 32) Which is 6.8284 times larger than that of the standard prior art cell shown in Fig. 1). For a square master cell or an icel with 156 mm x 156 mm, the side dimensions of the triangular islands are about 39 mm x 39 mm (for two identical right-angled sides of the triangle) and in this embodiment, It has an area of seomdang 7.605 cm ^2.

Thus, the design of an island or mini battery may include various shapes such as square, triangular, rectangular, trapezoidal, polygonal, honeycomb hexagonal islands, or many other possible shapes and sizes. The shape and size of the islands in the icel, as well as the number, can be selected to provide optimal characteristics for one or a combination of the following considerations: (i) total crack removal or reduction in the master cell (icel); (ii) enhance smoothness and flexibility / bendability of the master cell (icel) without cracking and / or propagation and without loss of solar cell or module performance (power conversion efficiency); (iii) reduction in metallization thickness and conductivity requirements by decreasing the current of the master cell (icel) and increasing the icemole voltage (voltage increase and current decrease by series connection or hybrid parallel-to-serial connection in a monolithic icel) And (iv) a relatively optimal combination of the voltage and current of the obtained Icel cell in order to facilitate and enable the performance of the inexpensive electronic components embedded in the stacked PV modules on the Icel and the stacked PV modules. At least one bypass switch (e.g., a pn junction diode or Schottky barrier diode) per Icelet, a maximum power point tracking (MPPT) power optimizer (at least a plurality of MPPT power With the optimizer, each MPPT power optimizer comprises at least one or more serial and / or parallel connections ), PV module power switching (with remote control on the power line in the PV array installed to turn the PV module on or off as needed), module status during operation of the PV modules in the field Temperature). For example, in order to improve and / or improve the flexibility / bendability of the obtained icel and the flexible lightweight PV module, as described above, when considered in accordance with some requirements in some applications and examples, a master cell (For example, triangular) islands in the vicinity of the periphery of the substrate.

A complete square master cell (icel) having an array of N x N square islands of the same or uniform size or a plurality of uniformly sized triangular islands is formed to match the photogeneration current among the subgroups of islands or islands connected in series . Thus, a square master cell (an icel) is an N × N uniform (equal in size of island area) square or nearly square island (N is an integer of 2, 3, 4, Is an integer, for example, an integer of 4 or more).

8 is a schematic circuit diagram briefly showing the same circuit model of a conventional solar cell having an edge combination effect (also finite series resistance and shunt resistance, and finite dark current). Actual solar cells include parasitic series resistors and shunt resistors, edge recombination effects, and dark currents, all of which negatively affect solar cell performance. Ideal solar cells have zero series resistance, infinite shunt resistance, zero arm current, and negligible or zero edge recombination effects. For a known conventional crystalline silicon solar cell, the general ratio of crystalline silicon wafer solar cell edge area to cell active (solar side) area is at least about 0.50%.

An increase in the edge length of the monolithic island solar cell (icel) described herein can increase the solar cell edge recombination effect (though not necessarily) and substantially reduce the edge effect of the mini cell island boundary trench Very effective reduction measures can be used. Solar cell recombination currents can cause nonlinear shunts and linear or super-linear reverse currents instead of normal saturation behavior. Thus, it may be desirable to substantially reduce or mitigate the edge recombination effect to eliminate or reduce I _loss2 . The edge recombination current can be substantially reduced and / or reduced or eliminated by taking real and effective measures during processing and design of the solar cell.

The edge recombination currents are caused by the edge regions that are highly distributed and / or relatively passivated and edge regions that can be in direct contact with the pn junction (i.e., solar cell pn junctions and reduction regions in contact with the edge regions) will be. The edge loss is a function of cell damage (e.g., residual edge sidewall damage if not properly removed by an effective process such as during texturing wet etch after formation of the described icel trench), and solar cell edge sidewall area The peripheral sidewall area is also caused by poor or insufficient passivation of the sidewall trench sidewall area) and the solar cell pn junction (around the major sidewall surrounding cell and / or sidewall trench sidewall area in the icel) It can get worse if contacted. To reduce this problem, wet texturing (silicon etching) after formation of island isolation trenches may be used to pass any residual trench damage in the sidewalls of the crystalline semiconductor layer, and to passivate the sidewalls of the solar side / Removing / removing the dried passivation during the passivation process or removing the pn junction contact with the edge of the island substantially reduces or eliminates the edge recombination effect from the solar cell (icel). As measures for reducing or eliminating the trench isolation edge recombination current in a monolithic island (tile) solar cell (Icel) that can be used individually or in combination of the following methods, 1) a narrow base (for example, n-type Emitter junction of each island (or mini-cell, sub-cell, or tile) from the trench isolation edge (and major icel boundary edge) by the rim (eg, n-type base when using base and p + n emitter junctions) For example, a p + n emitter junction when using an n-type base), the separation may be 1 micron depending on the size of the master cell (icel) and the size of the island (and the resolution of the pattern formed during solar cell processing) To several hundred microns; 2) Wet Etching Prior to the texturing process, laser scribing was used to form trench isolation areas from the solar side of the cell (etched with a wet texturing etch chemistry, and any trenching in the sidewalls of the island or mini- Induced residual damage); 3) any process induction (e.g., pulsed laser removal induction or mechanical cutting induction) from the trench compartment edge (which may be performed with wet texturing processing using an alkali texturing etch and / or an acidic texturing etch) Performing wet etch texturing to remove a portion of the crystalline silicon (e.g., a few microns to a few microns of silicon) to remove; And 4) forming a solar cell (Icel) by ionic trench compartment and wet etch texturing / surface cleaning followed by, for example, plasma chemical vapor deposition (PECVD), and / or further suitable processes such as atomic layer deposition (ALD) Perform passivation / ARC processes on the sun side, which effectively passivate all sidewall edge regions including the trench sidewalls of all the icel and also the peripheral sidewalls of the main icel, and substantially reduce or eliminate edge recombination loss effects. These measures will further enhance the practical benefits of the Icel implementation.

The following example solar cell design and fabrication process uses a multilayer metallization structure and specifically two levels (or two layers) of solar cell metallization (i.e., a metallized bilayer), which is an electrically insulated backplane layer Layer is attached to the back side of the solar cell). For example, prior to backplane-attachment (e.g., lamination of thin film prepreg sheets), the solar cell base and emitter contact metallization pattern (first patterned metallization layer or Ml) may, for example, (For example, a paste containing aluminum or an aluminum-silicon alloy) or a plasma sputtering or vapor deposition (PVD) aluminum (or aluminum silicon alloy) material layer The photoresist is directly formed on the rear side of the solar cell using a photoresist pattern. The first patterned metallization layer (referred to herein as M1) defines a solar cell contact metallization pattern, which may be, for example, the base of an interwoven rear side-contact (IBC) cell and the emitter metal (IBC) conductor fingers that define fine pitch meshing regions that define the area of the articulation. The M1 layer draws solar cell electrical power (current and voltage of the solar cell) and converts the solar cell electrical power into a patterned second high conductivity solar cell metallization level / layer (referred to herein as M2) formed after M1 . The second patterned metallization layer or level M2 comprises a relatively inexpensive and highly electrically conductive metal layer, for example aluminum and / or copper (with a suitable thin capping layer of NiV or Ni or an additional suitable capping metal) can do.

4, attachment or lamination of the backplane to the back of the partially processed solar cell (complete attachment or lamination of the back side of the solar cell to and within the exposed areas of the rear passivation layer and the patterned M1 layer) (In the case of a solar cell carried out using an epitaxial silicon lift-off process) or the following optional silicon substrate thin film etching (in the case of a solar cell carried out using a starting crystalline silicon wafer) After the end of front side texturing (e.g., using a wet alkali or acid wet etch texturing process) and front passivation and ARC deposition processes, and after drilling of via holes through the backplane layer, the patterned high sheet conductive M2 layer is formed on the backplane (This is because the patterned M2 layer also has a transition between the patterned M2 and M1 metallization layers Forming a conductive via plug for coupled). The via holes (e.g., the range of several hundred to several thousand via holes on the backplane of each solar cell) are drilled (e.g., laser drilled) into the backplane. This drilled via hole is landed on a predetermined area of the patterned M1 for subsequent electrical interconnection between the M2 and M1 layers patterned through the conductive via plug formed in the via hole (the plug is part of the patterned M2 forming process And may be formed at the same time and partly or separately). The patterned high conductive metalization layer M2 is then patterned to form a relatively inexpensive high conductivity M2 (e.g., aluminum, aluminum, and / or copper), including screen printing, thermal or electric beam deposition, plasma sputtering, plating, Material). ≪ / RTI > For a solar cell (Icel) with M1 fine pitch meshed rear side-contact (Icel) finger (e.g., M1 finger interlocked several hundred per icel), the patterned M2 layer may be substantially orthogonal to the patterned M1 finger I.e. the patterned M2 rectangle or tapered (e.g., triangular or trapezoidal) fingers are basically perpendicular to the M1 finger. Because of this orthogonal transformation of the M2 finger to the M1 finger, the patterned M2 layer can have significantly fewer IBC fingers than the M1 layer (e.g., by some 10 to 50 M2 fingers per miniature cell or unit cell in some instances) have. Thus, the M2 layer can be formed in a much denser pattern with an IBC finger (and a much larger base-emitter metal finger pitch) much wider than the interleaved M1 layer. The solar cell bus bar may be located in the M2 layer (i.e., the patterned M1 layer without the bus bar) to eliminate the electrical shading losses associated with the on-cell bus bar. Since the base and emitter interconnects and bus bars can be located on the M2 layer patterned on the solar cell rear backplane, electrical access is provided from the back of the solar cell to the base and emitter end of the solar cell on the backplane .

The continuous backplane material formed between the patterned M1 and M2 layers may be a suitable polymeric material, such as a thin sheet of electrically insulating material, for example, an aramid fiber prepreg material, where excessive thermal inductive stresses do not occur on the thin silicon layer (CTE) of a semiconductor layer (e.g., a crystalline silicon of a crystalline silicon solar cell). The backplane layer also provides solar cell process integration requirements for the post-stage cell fabrication process, particularly superior wet chemical resistance during selective wet silicon thin film etch and wet texturing on the front side of the cell, and subsequent front passivation and ARC layer deposition, (E. G., Thermal stability of about 400 캜 or less) in the presence of a catalyst (if necessary). The electrically insulated continuous backplane layer must also meet module level lamination and long term PV module reliability requirements. Although a variety of suitable polymeric materials (e.g., plastics, fluoropolymers, prepregs, etc.) and suitable non-polymeric materials (e.g., glass, ceramics, etc.) may be used as electrically insulating backplane materials, The material is selected according to a number of considerations and these considerations include, but are not limited to, cost, ease of process integration, relative CTE matching to silicon, thermal stability, drug resistance, reliability, flexibility / .

One suitable selected material of the continuous backplane layer is a prepreg sheet (including combinations of fibers and resins). The prepreg sheet is used when mounting a block of a printed circuit board and can be made from a combination of resin and CTE reducing fibers or particles. The backplane material is relatively inexpensive and has a low CTE (typically less than 10 ppm / 占 폚), in some instances less than 5 ppm / 占 폚), a thin film (typically 50 microns to 250 microns, in some instances about 50 to 150 microns) , Which is relatively drug resistant to selective silicon thin film etching agents (e.g., alkali or acidic silicon etching agents) and texturing agents (e.g., alkali or acidic silicon texturing agents) And, in some instances, about 400 < 0 > C temperature during back end solar cell processing). In the case of a solar cell fabricated using an epitaxial silicon lift-off process, the prepreg sheet can be attached to the rear side of the solar cell after forming the patterned M1 layer to the rear side of the solar cell and can also be reused using a thermal vacuum laminator Template (before the battery lift-off separation process, if applicable). In addition, in the case of a solar cell fabricated using a crystalline silicon wafer (without epitaxial lift-off processing), the prepreg sheet is subjected to a post-processing of the solar cell through the formation of the M1 layer patterned by using the thermal vacuum laminating apparatus again, And can be attached to the rear side of the wafer. Upon application of heat and pressure combinations, a thin film continuous prepreg sheet (e.g., an aramid fiber prepreg sheet of 50 to 250 microns thick layer) is permanently laminated or attached to the back side of the processed solar cell (or monolithic module implementation Type solar cells). Then, the lift-off separation boundary is applicable to the case of a solar cell fabricated using an epitaxial silicon lift-off process, and therefore, it is possible to use a pulse laser scribing tool, for example, (Near the edge of the template), and the backplane laminated solar cell is lifted off and separated from the reusable template using a mechanical separation or lift-off process (the solar cell fabricated on the starting crystalline silicon wafer does not use a lift- off separation process Direct backplane solar cell processing after the backplane-attachment / lamination process). The following post-processing steps include (i) selective silicon thin film etching for solar cells fabricated on starting crystalline silicon wafers, wet texturing, passivation, and ARC deposition processes on the solar solar side, (ii) (solar cell backplane surface Forming solar cell backplane via holes on the back side of the backplane-attached solar cell and forming a highly conductive second metallization layer (M2). (Including, for example, aluminum and / or copper, unlike silver, to reduce overall solar cell fabrication and material costs), M2 < / RTI > metal fingers for emitter and base polarity, Is formed on a laminated solar cell backplane including a laser drilling via hole.

As described above, the backplane material may be relatively thin (e.g., about 50 to 250 microns thick), flexible, commonly used in electrically insulating polymer material sheets such as printed circuit boards (PCB) Can be composed of inexpensive prepreg materials, which meet the overall process integration and reliability requirements. In general, prepregs are pre-impregnated reinforcing materials with resin and are readily used to produce composite portions (prepreg can be used to produce compositions faster and easier than wet layup systems). Prepreg can be fabricated by combining pre-promoted resins and reinforcing fibers or fabrics that are specially formed using equipment designed to ensure consistency. Pre-coated with flexible baking paper can be handled easily and maintain flexibility / purity during a certain out-life at room temperature. In addition, according to the development of the prepreg, a material which does not require a refrigerator for storage, a prepreg having a long shelf life, and a product to be stored at a low temperature were produced. The prepreg material can be stored by heating under pressure (heat pressure lamination). Conventional prepregs are formed while preserving in an autoclave, while low temperature prepregs can be sufficiently preserved using vacuum bag pressures at much lower temperatures.

As described and discussed above, the monolithic island cell (icel) designs and fabrication methods disclosed herein can be incorporated into the known solar cell design and fabrication process flow, Since manufacturing process steps or tools are not changed or added, substantially no solar cell manufacturing cost is added. Indeed, the cost of manufacturing solar cells and modules can be reduced by innovation of the iSeal (also a monolithic module embodiment innovation including the icel). In one embodiment, the combination of the cell design with a continuous backplane and a metallization structure (specifically, two patterned metallization layers or levels-M1 and M2) provides a back-side / back side-contact solar cell structure. The various combinations of backplane and metallization layers, however, serve as permanent, flexible or semi-flexible or rigid structural supports / reinforcement, and can be fabricated with high efficiency crystalline silicon (E. G., Aluminum and / or copper metallization materials) interconnection of solar cells.

9A is a rear plan view schematically showing a first metallization layer pattern M1 without a bus bar formed on a master cell or a icel with a 4 x 4 square island (this iceless M1 pattern rear view is the same 4 x 4 square Corresponding to the front side shown in Fig. 2 of the icicle having a canonical island arrangement). FIG. 9B is an enlarged view of a selective schematic view of FIG. 9A and is a rear enlarged plan view of one of the islands of FIG. 9A (eg, an island designated as I ₁₄ ), an interlocked base of other islands in the ice cell, And the base and emitter metal fingers are electrically isolated from each other.

9A schematically shows a rear plan view of a rear metallization layer pattern M1 without a bus bar and shows a top plan view of the epitaxially grown porous silicon or crystalline wafer based semiconductor substrate on a template, A plurality of islands of the patterned fine pitch meshing bases and emitter metallization fingers (corresponding to a plurality of islands in the Iceloc - a 4 x 4 array in the representative example) formed on the master cell or the icel 100. This design corresponds to an Icelel having a square island of a 4 x 4 array shown in Fig. Figure 9b shows a patterned metallization layer M1 with meshed base and emitter metallization fingers that are free of fine pitch bus bars (e.g., for back-side / back side-contact or IBC icel or master cells) 9A is an enlarged rear view of the solar cell islands. 2, the partially processed master cell or the icel (processed through the first patterned metal layer or level M1) or the icel 100 is defined by the cell perimeter boundary 106, (Equal island area) square islands I ₁₁ to I ₄₄ defined by forming a division trench separation border in the exemplary embodiment (after stacking or backplane-mounting solar cell backside) and defining 4 x 4 = 16 uniform Is shown as a border 104 protruding from the front side to the rear side of the solar cell in which the partition trench is to be formed. Note that the trench is formed from the sun side of the semiconductor substrate on the opposite side of the backplane. 9A and 9B, the island-section borders 104 are formed by sandwiching M1 metalized islands (an interdigitated base formed by patterned M1 and an emitter A plurality of islands of the metalization finger). The 4x4 islands of the M1 fingers interdigitated can be physically separated (i.e., the fingers interdigitated do not traverse or infringe the compartment border 104) and can be electrically separated from each other. A total of a plurality of patterned M1 islands (a 4 x 4 array of M1 islands in this embodiment is a relatively high conductivity and cheap metal, such as aluminum, which can make good ohmic contact with n-type and p-type silicon, (Aluminum or aluminum-silicon alloy paste), or by suitable processes such as PVD and post PVD patterning (pulse laser ablation patterning or patterning etch). The islands, sub-cells, or mini-cells are mounted on a shared continuous or continuous backplane layer / sheet (the backplane will be laminated or attached to the back side of the solar cell, not shown, but including rear passivation and patterned on- (E. G., A starting crystalline silicon wafer to an epitaxially grown silicon layer or a silicon layer) of a semiconductor layer formed in a monolithic fashion from the same initial consecutive semiconductor layer). A plurality of islands (4 x 4 = 16 in this embodiment) of the patterned intermeshing M1 metallization fingers 102 correspond to the Icel pattern of the semiconductor islands partitioned by trenches on the front side of the solar cell, And the islands of the base and emitter metal fingers meshed with each other correspond to the M1 metallization of each island. The base and emitter metal fingers interdigitated on each M1 island are shown without the cell bus bar on the M1 pattern (before the backplane-attachment, the emitter M1 metal fingers 110 and / (Shown as alternating base M1 metal fingers 112), there is no on-cell bus bar. As shown in Figures 9a and 9b, the patterned intermeshed M1 metallization fingers of each M1 island (corresponding to the respective trench section islands for the resulting icel) are patterned intermeshed M1 And is physically and electrically separated from the metallization finger. Electrical interactions among the various trench isolation islands of the Icel cell are performed through the second patterned metallization layer M2 before back end machining of the solar cell after backplane-attachment to the partially processed solar cell backside . Some embodiments may use a patterned M1 layer to interconnect (e.g., electrically parallel and / or series connect) adjacent or neighboring trench isolation islands. In some instances, the M1 metallization layer may be formed on the solar cell substrate backside 108 in the case of a solar cell made from, for example, an epitaxially grown silicon substrate, as applicable and needed, The deposited epitaxial solar cell is attached to a crystalline silicon template structure supported on the solar solar side. This is described above in accordance with the epitaxial silicon solar cell fabrication process flow.

10A is a rear schematic plan view of a first metallization layer pattern M1 without a bus formed on a master cell or a cell having a 3 x 3 square islands (the rear view of the Iceland M1 pattern has a 3 x 3 square island arrangement Corresponding to the front view shown in Fig. 6A with respect to the icel). FIG. 10B is a rear schematic plan view of a first metallization layer pattern M1 without a bus formed on a master cell or a cell of 5x5 square islands (the rear view of the Iceland M1 pattern shows the same 5x5 square island arrangement Corresponding to the front view shown in Fig. 6 (b).

10A and 10B are rear schematic plan views of a first metallization layer pattern M1 without a bus bar (in this representative example, a 3 x 3 = 9 array of islands 10 a in the icel and 5 x 5 = 25 array) of a patterned fine pitch meshing base and emitter metallization fingers (corresponding to an array of 25 M1-25 arrays), which may be epitaxially grown (on a template) or backplane-attached to a crystalline wafer- Before lamination, it is formed on the master cell or the icel 120 of Fig. 10A and the master cell or the icel 130 of Fig. 10b. This design corresponds to the Icel (having the 5x5 array of islands shown in Figure 6b) with the 3x3 array of islands shown in Figure 6a. Consistent with the icel embodiments described above with respect to Figures 10a and 6a, the partially processed master cell or icel 120 (processed through the first patterned metal layer or level M1) (Identical island area) square Ics I ₁₁ to I ₃₃ defined by a trench isolation border formation in the representative embodiment (backplane-after attachment or lamination to the back of the solar cell) trench isolation border formation And such a border is shown as a border 124 projected from the front side to the rear side of the solar cell, and the partition trench will be formed through the semiconductor layer. Note that the trench is formed from the sun side of the semiconductor substrate on the opposite side of the backplane. In Fig. 10A, the section border 124 also includes M1 metallized islands (a plurality of islands of intermeshed bases and emitter metallization fingers) for the islands forming the icel (3 x 3 icel in this embodiment) define. The 3 x 3 islands of interlocked M1 fingers are physically separated from each other (i.e., the interdigitated fingers do not cross or infringe the compartment border 124) and can be electrically isolated. A total of a plurality of patterned M1 islands (a 3 x 3 array of M1 islands in this embodiment, a metal that is in ohmic contact with the n-type and p-type silicon with relatively high conductivity and cheap metal, e.g., aluminum) The process may be performed by screen printing or PVD of a suitable paste (e.g., a paste comprising aluminum or an aluminum-silicon alloy), and post-PVD patterning (by pulsed laser ablation patterning or patterned etching) Are simultaneously formed on the rear side. The islands or sub-cells or mini-cells are connected to a semiconductor layer (not shown) on a shared continuous or continuous backplane layer / sheet (the backplane is attached or laminated to the back side of the solar cell including a back passivation and patterned on- (From an epitaxially grown silicon layer or a starting crystalline silicon wafer, for example), and separated islands (from the same initial consecutive semiconductor layer) are monolithically formed. A plurality of islands (3 x 3 = 9 in this embodiment) of the patterned intermeshing M1 metallization fingers 122 are formed on the rear side of the solar cell, Each island of the base and emitter metal fingers corresponding to and corresponding to the pattern and interlocked with each other corresponds to the metallization region of each island. The interdigitated base and emitter metal fingers on each M1 island do not include a cell bus bar on the M1 pattern (shown as emitter and base M1 metal lines 122 alternately formed on the back side of the solar cell substrate before backplane attachment) The on-cell bus bar is shown to be nonexistent. As shown in FIG. 10A, patterned intermeshed M1 metallization fingers for each M1 island (corresponding to each trench isolation island of the resulting icel) are physically separated from the patterned interlocked M1 metal finger of the other neighboring island by physical And electrically separated. In some examples, the electrical interconnections among the various trench isolation islands of the Icelet are fabricated through a second patterned metallization layer M2 before the back end machining of the solar cell after the backplane-attachment to the solar cell backside. Some embodiments may use a patterned M1 layer, for example, to interconnect some adjacent or neighboring trench compartment islands in electrical parallel and / or connection. In some instances, the M1 metallization layer may be formed on the back side of the solar cell substrate in the case of a solar cell made from, for example, an epitaxially grown silicon substrate, as applicable and necessary, The solar cell is attached to a crystalline silicon template structure supported on the solar side of the cell. Which has been described above in accordance with the epitaxial silicon fabrication process flow.

FIG. 10B is consistent with the Icel cell embodiment described above with respect to FIG. 6B, wherein the partially processed master cell or icel 130 (processed through the first patterned metal layer or level M1) (Identical island area) square islands I ₁₁ to I ₅₅ defined by a trench isolation border formation (in the backplane-attachment or lamination on the back side of the solar cell) and defined by a trench isolation border formation in the exemplary embodiment , Such a border is shown as a border 134 projected from the front side to the rear side of the solar cell, and a partition trench will be formed. Note that the trench is formed from the sun side of the semiconductor substrate on the opposite side of the backplane. In Fig. 10B, the compartment border 134 also includes a plurality of M1 metalized islands (bases meshed with each other and a plurality of islands of emitter metallization fingers) for the islands forming the icel (5x5 = 25 iocels in this embodiment) ). The 5x5 = 25 islands of interlocked M1 fingers can be electrically isolated from one another (i.e., the interdigitated fingers do not traverse or infringe the compartment border 134). A total of a plurality of patterned M1 islands (a 5 x 5 = 25 array of M1 islands in this embodiment, a metal that is superior in ohmic contact with n-type and p-type silicon with relatively high conductivity and cheap metals, such as aluminum) Suitable processes may include, for example, screen printing of a suitable paste (e.g., a paste comprising aluminum or an aluminum-silicon alloy) or PVD and post-PVD patterning (by pulsed laser ablation patterning or patterned etching) As shown in FIG. The islands or sub-cells or mini-cells are connected to a semiconductor layer (not shown) on a shared continuous or continuous backplane layer / sheet (the backplane is attached or laminated to the back side of the solar cell including a back passivation and patterned on- (From an epitaxially grown silicon layer or a starting crystalline silicon wafer, for example), and separated islands (from the same initial consecutive semiconductor layer) are monolithically formed. A plurality of islands (5 x 5 = 25 in this embodiment) of the patterned M1 interdigitated metallization fingers 132 are formed on the rear side of the solar cell and the rear side pattern of the solar cell is formed on the trench side semiconductor island Each island of corresponding base and emitter metal fingers corresponding to and matching the icel pattern corresponds to the M1 metallization region of each island. The interdigitated base and emitter metal fingers on each M1 island (shown as emitter and base M1 metal lines 132 alternately formed on the back side of the solar cell substrate before backplane attachment) do not include battery bus bars on the M1 pattern (To prevent or minimize electrical shading losses), the on-cell bus bar is shown to be nonexistent. As shown in FIG. 10B, the M1 meshing fingers interlaced with each other for each M1 island (corresponding to each trench section island of the obtained icel) are sandwiched from the patterned intermeshed M1 metallization fingers of the other neighboring islands Physically and electrically separated. In some examples, the electrical interconnections among the various trench isolation islands of the Icelet are fabricated through a second patterned metallization layer M2 before the back end machining of the solar cell after the backplane-attachment to the solar cell backside. Some embodiments may use a patterned M1 layer, for example, to interconnect some adjacent or neighboring trench isolation islands with an electrical parallel connection. In some instances, the M1 metallization layer may be formed on the back side of the solar cell substrate in the case of a solar cell made from, for example, an epitaxially grown silicon substrate that is applicable and necessary, The solar cell is attached to a crystalline silicon template structure supported on the solar side of the cell. This is described above in accordance with the epitaxial silicon solar cell fabrication process flow.

11A is a rear schematic plan view of a first metallization layer pattern M1 without a bus bar formed on a master cell or icicle with 4 x 3 x 3 = 36 triangular islands (the rear view of the Iceland M1 pattern is 4 x 3 x 3 = Corresponding to the front view shown in Fig. 7 (d) for an icicle having a square island arrangement of 36). Figure 11b is (specified by, for example, the island _{I 1, I 2, I 3} , I 4) also as a schematic enlarged view of 11a, a rear close-up plan view of a group of triangular islands of Figure 11a, the free bus bar 1 metalized layer pattern M1, and the triangular islands are electrically isolated from one another, and the meshed bases and emitter M1 fingers of the other islands in the icel are shown, / RTI >

11A is a rear schematic plan view of a first metallization layer pattern M1 without a bus bar (in this exemplary embodiment, a plurality of 4 x 3 x 3 = 36 arrays of triangular islands in an icel Consisting of interdigitated bases and emitter metallization fingers of patterned fine pitch (corresponding to the islands) And comprises a plurality of islands, which are formed on the master cell or the icel 140 prior to epitaxial growth (on the template) or before backplane-attachment or lamination to the crystalline wafer-based semiconductor substrate. This design corresponds to an Icel with a 4 x 3 x 3 array of islands shown in Figure 7d. Fig. 11b is a rear enlarged view of the solar cell islands from Fig. 11a; the patterned M1 metallization layer is an intermeshed base and emitter metal without bus bars of fine pitch (for rear-side / rear-side contact or IBC solar cells) Thereby forming a fingering finger. Consistent with the Icel cell embodiment described above with respect to Figure 7d, the partially fabricated master cell or icel 140 (processed through the first patterned metal layer or level M1) (The same island region) triangle island I (which is defined by the formation of a trench trench isolation border through a semiconductor layer in a representative embodiment (backplane-attachment or lamination back of the solar cell)_One I₃₆Which are shown as various bordering lines 144 and 154 projected from the front side to the rear side of the solar cell semiconductor substrate (dark axes separating the triangular islands of M1 metal fingers interlocked with each other, , And bright diagonal border lines) will be formed through the semiconductor layer. Note that the trench is formed from the sun side of the semiconductor substrate on the opposite side of the backplane. 11A and 11B, horizontal and vertical (also referred to herein as axes) compartment borders 144 and triangular pattern compartments diagonal or angled borders 154 (horizontal and vertical or dark axis lines also diagonal bright lines-dark lines and bright Line separates the X-direction and Y-direction island partitioning borders from the diagonal direction island partitioning borders) is also connected to the M1 metallization islands (4 x 3 x 3 = 36 islands in this embodiment) A plurality of triangular islands of meshed bases and emitter metallization fingers). 4 x 3 x 3 = 36 islands of interlocking M1 fingers can be electrically separated from one another (i.e., the interdigitated fingers do not cross or infringe the segmented borders 144 and 154). A total of a plurality of patterned M1 islands (4 x 3 x 3 = 36 arrays of M1 islands in this embodiment, with a metal having excellent ohmic contact with n-type and p-type silicon with relatively high conductivity and inexpensive metal, Aluminum) may be applied to a suitable process, such as screen printing of a suitable paste (e.g., a paste comprising aluminum or an aluminum-silicon alloy) or PVD and post-PVD patterning (by pulsed laser ablation patterning or patterned etching) On the rear side of the solar cell. The islands or sub-cells or mini-cells are connected to a semiconductor layer (not shown) on a shared continuous or continuous backplane layer / sheet (the backplane is attached or laminated to the back side of the solar cell including a back passivation and patterned on- (For example, from the epitaxially grown silicon layer on the porous silicon or the silicon layer from the starting crystalline silicon wafer) on the template, and the isolated island is monolithically formed (from the same initial consecutive semiconductor layer). A plurality of islands 142 (4 x 3 x 3 = 36 in this embodiment) of the patterned intermeshed M1 metallization fingers are formed on the rear side of the solar cell, and the rear side pattern of the solar cell is formed on the trench compartment semiconductor Each island of corresponding base and emitter metal fingers corresponding to and corresponding to the island's Icel pattern corresponds to the M1 metallization of each island. The interdigitated base and emitter metal fingers on each M1 island (shown as emitter M1 finger 150 and base M1 finger 152 alternately formed on the solar cell substrate rear side 148 before backplane-attachment) There is no battery bus bar on the pattern (to prevent or eliminate electrical shading losses) and no on-cell bus bar. As shown in Figs. 11A and 11B, the patterned intermeshed M1 metallization fingers of each triangular M1 island (corresponding to each trench section triangular Icel isthm of the resulting Icel) are patterned intermeshed M1 And is physically and electrically separated from the metallization finger. Electrical interconnection among the various trench isolation islands of the Icel is fabricated through a second patterned metallization layer M2 before the post-treatment of the solar cell after backplane-attachment to the solar cell backside. Some embodiments may use a patterned M1 layer, for example, to interconnect adjacent or neighboring trench compartment islands in electrical parallel and / or in series. In some instances, the M1 metallization layer may be formed on the back side of the solar cell substrate in the case of a solar cell made from, for example, an epitaxially grown silicon substrate, as applicable and necessary, The solar cell is attached to a crystalline silicon template structure supported on the solar side of the cell. This is described above in accordance with the epitaxial silicon solar cell fabrication process flow. 11a and 11b, a set of four triangular islands form a square (e.g., an island group I_One I₄Forms a square and the island group I₃₀ I₃₆(Which form an additional square), can be electrically connected in parallel using a second patterned metallization layer M2 (not shown), and the entire set of square regions (3 x 3 regions in this embodiment, (For example, 3 x 3 = 9 square regions are electrically connected in series) and may be connected in a hybrid parallel-to-serial arrangement as needed . Thus, if the number of triangular islands is 4 x 3 x 3 = 36, then the number of subgroups S connected in series (an array of groups of four triangular islands connected in series) is 3 x 3 = 9, Three triangles, for example, I_One, I₂, I₃, And I₄ (P = 4 or four triangular islands are defined within a square electrically connected in parallel by M2, nine square regions each include four triangular islands connected in parallel, All triangular islands are connected in series).

representative M2 Metallization  Embodiment

12A is a rear schematic plan view of a second and final metallization layer pattern M2 formed on the rear side of the master cell or the Icel cell for an island having an array of 5 x 5 square islands. Lt; RTI ID = 0.0 &gt; M1 < / RTI &gt; The M2 pattern shown here provides an array for interconnecting arrays of 5 x 5 = 25 islands connected in series in an Icel cell. The patterned M2 layer is shown as a substantially rectangular finger (number of M2 fingers &lt; number of M1 fingers). Figure 12b is a rear enlarged plan view of the M2 pattern for some of the island that are connected in series in the schematic enlarged, quadrant area of Figure 12a of the selected M2 structure of Figure 12a (for example, I _14, I _15, I _24, I ₂₅ &Lt; / RTI &gt; represents the base and emitter M2 metal fingers interlocked with each other, including the M2 pattern for the islands designated &lt; RTI ID = 0.0 &gt;

12A is a rear schematic plan view of a second metallization layer pattern M2 formed on a master cell or an icel 160 (similar to the solar cell shown in Fig. 6B, including a 5 x 5 = 25 array of square islands And M1 patterned thereon is present as shown in FIG. 10B). Figure 12B is an enlarged view of the M2 metallization layer pattern in some islands within the quadrant of the solar cell of Figure 12A. 12A and 12B, as described above with respect to Figures 6B and 10B, the master cell or the Icel 160 is defined by the solar cell perimeter boundary 164 and the 5 x 5 &lt; RTI ID = 0.0 &gt; = 25 uniform square islands I ₁₁ to I ₅₅ . The patterned M2 metallization layer 162 is formed on a continuous backplane layer 177 that is attached or laminated to the back side of the solar cell after formation of the patterned M1 layer. The patterned M1 and M2 layers are separated from each other by a backplane layer 177 and are connected together via the conductive via plugs described above. The patterned M2 metallization layer 162 shown in Figures 12a and 12b includes a substantially rectangular interdigitated emitter and base metal finger which is connected to the bottom patterned M1 via a plurality of conductive via plugs Lt; RTI ID = 0.0 &gt; M2 &lt; / RTI &gt; metallization process via laser drilled via holes through the backplane layer). As illustrated, the patterned M2 interdigitated rectangular fingers (M2 emitter fingers 176 and M2 base fingers 174) are patterned to substantially orthogonal or perpendicular to the bottom patterned M1 interlocked base and emitter fingers And allows a smaller number of M2 base and emitter fingers than the number of M1 base and emitter fingers. In this embodiment, the islands (either the mini-cell or the master cell or the Icel including the 5 x 5 array of islands) in each column comprising a group of five islands are connected in an electrical series by the M2 series connection 170 The base M2 metal of the island is connected to the emitter M2 of the adjacent island and the emitter M2 metal of each island is connected to the base M2 metal of the adjacent island in the same column and is transferred from the end of one column to the beginning of the adjacent column If one corner island's base M2 bus bar and another diagonal opposite island corner island's emitter M2 bus bar do not use an extension of M2 or a monolithic module embodiment in a monolithic module embodiment, And serves as an Icel base and emitter bus bar for connecting the Icelet through tabletting, stringing and / or soldering). To provide a patterned M2 electrical series connection of a 5 x 5 array of islands arranged in a 5 column, the island column comprises a transverse M2 layer, alternately located at the top and bottom of the column of islands, using the patterned M2 layer The 5x5 = 25 islands in such an Icel are all interconnected in an electrical series using a patterned M2 layer, and the series connection is in the form of an Icelet (Fig. 12a) interconnected by a jumper or transverse connector 172, 160 and continuing to the bottom of the first column of the islands, the first left column is connected in series to the second column using a lower M2 jumper or transverse connector 172, After continuing on top of the second column of islands, the second column is connected in series to the third column using the upper M2 jumper or transverse connector 172 and the series connection is continued below the third column of the islands, The third column is divided into lower M2 jumper or transverse direction After continuing the series connection to the top of the fourth column of the island using connector 172 and continuing the fourth column to the fifth column using upper M2 jumper or transverse connector 172, And finally the series connection continues to the bottom of the fifth column of the island. 5 x 5 serial ahyisel having an array of the connected islands (all islands interconnected by patterned M2 layer and the final ahyisel metallization), an emitter lead or bus bars to the island I ₁₁ (the upper left corner island) 166 ( The base lead and bus bar 168 (base end) for I ₅₅ (lower right corner island) and I ₅₅ (lower right corner island) serve as the main bus bar of the Icel 160. As shown, adjacent columns of the patterned M2 layer corresponding to adjacent columns of the islands (five islands per column in this embodiment) are separated by the M2 column electrical separation gap region 178 (i.e., And the backplane layer 177 is exposed. The M2 column electrical isolation gap region 178 includes an emitter or bus bar 166 (emitter end) as part of the monolithically patterned M2 metallization layer as well as all M2 level patterned base and emitter fingers, Base lead or bus bar 168 (base end). The M2 series connection 170 between the adjacent islands in the column electrically connects the M2 base finger 174 from the island I ₁₁ to the M2 emitter finger 176 of the island I ₂₁ . M2 base fingers 174 of the island I is the island ₂₁ I ₃₁ , And connects to the island I ₅₁ vertically, thus terminating the electrical serial connection of the island in the first column. The M2 series connected transverse jumper 172 electrically connects M2 base finger 174 of island I ₅₁ (in column 1) to M2 emitter finger 176 of island I ₅₂ (in column 2).

Each mini-cell or island may be connected in series to at least one of the other islands in the array, and all the islands in the array of 5 x 5 islands are electrically connected in series, e.g., as shown in Figure 12A, Are referred to herein as all series connections. However, parallel and hybrid parallel-to-serial mini battery connection patterns can be used according to application and requirements.

As shown in FIG. 12A, each island (or a subgroup of M1 parallel connected islands) corresponds to I ₁₁ in FIG. 12A and is meshed with the lower one for island I ₁₁ in FIG. 6B corresponding to I ₁₁ in FIG. And has a corresponding M2 unit cell design of interdigitated rectangular fingers formed to be orthogonal to the M1 finger cell. In some instances, it may be designed to pattern the M2 finger in parallel with the lower interdigitated M2 finger.

Additionally and alternatively, the M2 unit cell design metal fingers for the Icel can be tapered, for example, in a triangular or trapezoidal shape, as shown in Fig. 13 is a rear schematic plan view of a second metallization layer pattern (M2) unit cell having a plurality of interdigitated tapered / right-angled triangular bases and emitter fingers. An example of an M2 unit cell design located on a square island or subgroup of each serially connected M1 parallel island is represented by F = 6 pairs of bases and emitter M2 metal fingers per island or subgroup of M1 parallel island.

13 is a schematic plan view of the rear side of the second metallization layer pattern M2 unit cell 180 in which six pairs of tapered and right angled triangular fingers and M2 tapered base fingers 184 And M2 taper emitter fingers 182 (all attached to the M2 emitter bus bar), which are separated by an electrical insulation gap 186 formed during M2 patterning. The word "tapered" is used to describe the M2 finger that widen and narrow in the island bus bar connection since it extends from the finger bus bar towards the other end of the island. In some instances, a tapered M2 finger design can reduce the M2 layer thickness requirement by about 30% and reduce ohmic losses compared to a rectangular M2 finger, thus thinning the M2 layer for some acceptable metallization ohm loss. The tapered base and emitter M2 fingers (tapered from the corresponding island M2 bus bar) may be formed in a substantially triangular shape (right angle, equilateral, or other desirable triangular shape) or nearly trapezoidal shape. Exemplary dimensional considerations for designing a square M2 unit cell with tapered fingers of a master cell or an icel include side dimensions L and N x N = S (corresponding to square Ixell area about L x L) &Lt; / RTI &gt; are connected in series by the patterned M2 metallization layer) and F pairs of M2 fingers per island (or per subgroup of M1 parallel connected islands): L = H x N; H = F x H; Island area = H ² ; Where F is the number of base and emitter finger pairs (F = 6 in FIG. 13), where H is the dimension of the M2 pattern per island connected in series (or island subgroup, h is the base width of the triangular M2 finger and F Is the number of base and emitter M2 finger pairs per island (or subgroup). The area of each series connected island (or subgroup of islands) is H ² .

13 is a rear view of a second metallization unit cell layer pattern M2 formed on the master cell island 180 (simultaneously and monolithically with the patterned M2 on all the other sides of the icel) (Formed as part of the patterned M2 formation) defined by the interdigitated bass finger 184 and the emitter fingers 182 and electrically separated by a separate metallization electrical isolation gap 186. [ The M2 metallization pattern shown in Fig. 13 may be applied to the M1 finger pattern, for example, perpendicular or orthogonal to the M1 finger patterned on an individual island (e. G., Each island is connected in series with the other island of the Icel) . The tapered fingers reduce the M2 thickness requirement (typically about 30% for a rectangular finger) and the M2 metallization layer can be thinned (due to reduced electrical sheet conductivity requirements).

14A is a rear schematic plan view of a second metallization layer pattern M2 formed on the rear side of the icicle (similar to the cell shown in Fig. 2 where patterned M1 is formed as shown in Fig. 9A). This shows the Icel M2 pattern for electrically connecting the 4x4 = 16 array of square islands electrically. The patterned M2 finger uses a triangular base and an emitter metal finger (number of M2 fingers less than the number of M1 fingers per island). In some examples, the M2 finger may be orthogonal or perpendicular to the M1 finger. The M2 finger may be a much wider and dense pitch than the M1 finger.

Figure 14b is of a part of the rear side schematic plan view of the solar cell from, Figure 14a having a patterned M2 metallization layer, specifically, the island (I _13, I _23, and I ₂₄₎ island (I ₁₄₎ with a partial diagram of the FIG.

14A is a rear plan view of a second metallization layer pattern M2 formed on a master cell or an icel 190 (similar to the cell shown in Fig. 2 where patterned M1 is formed as shown in Fig. 9A). Figure 14b is of a part of a schematic enlarged plan view of the solar cell from, Figure 14a having a patterned M2 metallization layer, specifically, the island (I _13, I _23, and I ₂₄₎ island (I ₁₄₎ with a partial diagram of the FIG. 14A and 14B, the master cell or the icel 190 is defined by the solar cell perimeter 208 and is divided into 4 x 4 = 16 and a homogeneous (same area) square ahyisel I ₁₁ to I _44. The patterned M2 metallization layer 192 is an emitter and base metal finger that is tapered (e. G., Shown in triangles) electrically connected to the bottom M1 layer through a plurality of conductive via plugs, Layer on the back side of the solar cell and a backplane layer on the back side of each island in the icicle. As shown, the patterned M2 interdigitated triangular fingers (M2 emitter fingers 206 and M2 base fingers 204 are electrically isolated within the M2 layer patterned by the separation gap 210) And is patterned to be substantially perpendicular or orthogonal to the lower M1 engaged fingers to have substantially less M2 fingers than the number of M1 fingers. Each of the islands in the column connected in series by the M2 series connection 200 and the island column (including the 4 x 4 = 16 array of mini batteries shown in Fig. 14A) are alternately arranged at the top and bottom of the island column And the array of 4 x 4 = 16 islands is connected by the M2 layer jumper 202 located at the base end of the emitter lead 194 Bus bar). As shown, each island column is separated by the M2 column isolation region 198 and is formed as part of the patterned M2 formation process. M2 series connection 200 is electrically connected to the M2 base fingers 204 of the island (I ₁₁₎ to M2 emitter fingers 206 of the island (I _21). Island (I ₂₁₎ M2 base fingers 204 are electrically connected to M2 emitter fingers 206 of the island (I ₃₁₎ and vertical connections to the island (I ₄₁₎ to. M2 series connected transverse jumper 202 is electrically connected to the M2 emitter fingers 206 of the (column 1 in a), the island (I ₄₁₎ of M2 base fingers 204, the (column 2 in), the island (I ₄₂₎ do.

15A is a schematic view of a master cell having 3 x 3 = 9 series connected islands (similar to the cell shown in Fig. 6A in which patterned M1 is formed as shown in Fig. 10A) Is a rear schematic plan view of the metallization layer pattern M2. The patterned M2 finger uses a triangular base and emitter metal finger (the number of M2 fingers per island is less than the number of M1 fingers). In some examples, the M2 finger may be orthogonal or perpendicular to the M1 finger. The M2 finger may be a much wider and dense pitch than the M1 finger.

15A is a rear plan view of a second metallization layer pattern M2 formed on a master cell or an icel 220 (similar to the cell shown in Fig. 6A where patterned M1 is formed as shown in Fig. 10A). The illustrated M2 pattern may be formed for a 3 x 3 = 9 series connection island (or a subgroup of M1 parallel connection islands) on the master cell and may be formed using a prior art single island master cell (e.g., The voltage increases and the current decreases. That is, the M2 metallization pattern can increase the solar cell voltages (V _mp and V _oc ) by nine factors compared to the prior art single island master cell and the solar cell currents I _mp and I _sc ) Can be reduced. As described above with respect to Figs. 6A and 10A in Fig. 15A, the icel or master cell 220 is defined by the cell perimeter boundary 238 and is defined as 3 x 3 = 9 uniform region) and a square ahyisel I ₁₁ to I _33. The patterned M2 unit cell metallization layer 222 includes an emitter tapered (e. G., Shown in triangle) electrically connected to the bottom patterned M1 layer finger through a plurality of conductive via plugs formed in the backplane, A base M2 metal finger, formed on a continuous electrically insulated backplane attached to the rear side of the solar cell after formation of a patterned M1 layer on the back side of each island. As shown, the patterned M2 interdigitated triangular fingers (M2 emitter fingers 232 and M2 base fingers 234 are electrically separated by a separation gap formed during the patterned M2 formation process) To be substantially perpendicular or orthogonal to the bottom patterned &lt; RTI ID = 0.0 &gt; M1 &lt; / RTI &gt; meshed fingers to have substantially less M2 fingers. Each of the islands in the column connected in series by the M2 series connection 230 and the island column (the master cell comprises a 3 x 3 = 9 array of mini batteries or islands in this embodiment) alternates between the top and bottom of the island column And each island is connected in series from the emitter lead or bus bar 224 (emitter end) to the base lead or bus bar 226 (base end). As shown, each island column is separated by the M2 column isolation region 228 and formed during the patterned M2 formation process. M2 series connection 230 is electrically connected to the M2 base fingers 234 of the island (I ₁₁₎ to M2 emitter fingers 232 of the island (I _21). Of the island (I ₂₁₎ M2 base fingers 234 are electrically connected to M2 emitter fingers 232 of the island (I _31). The M2 series connected transverse jumper 228 electrically couples the M2 base finger 234 of the island I ₃₁ (in column 1) to the M2 emitter finger 232 of the island I ₃₂ (in column 2) .

Fig. 15B is a cross-sectional view of a second (i. E., Second) cell formed on a master cell having 5 x 5 = 25 serially connected islands or subgroups of M1 parallel connected islands (similar to the cell shown in Fig. 6B in which patterned M1 is formed as shown in Fig. Is a rear schematic plan view of the metallization layer pattern M2. The patterned M2 finger uses a triangular base and emitter metal finger (the number of M2 fingers per island is less than the number of M1 fingers). In some examples, the M2 finger may be orthogonal or perpendicular to the M1 finger. The M2 finger may be a much wider and dense pitch than the M1 finger.

FIG. 15B is a rear plan view of a second metallization layer pattern M2 deposited on a master cell or an icel 240 (similar to the cell shown in FIG. 6B where M1 is deposited as shown in FIG. 10B). The illustrated M2 pattern can be formed for a 5x5 = 25 series connected island on the master cell, and the solar cell voltage increases and the current decreases compared to the prior art island master cell. That is, the M2 metallization pattern can increase the solar cell voltage (V _mp and V _oc ) by about 25 factors compared to the prior art single island master cell, and the solar cell currents (I _mp and I _sc ) can do. As Figs. Above for 6b and 10b in 15b, ahyisel or master cell 240 is defined by a cell near the boundary 258, the uniform square ahyisel I ₁₁ to I ₅₅ defined by a trench isolation border . The patterned M2 unit cell metallization layer 242 includes a tapered (e. G., Triangularly) meshed emitter electrically connected to the bottom M1 layer finger through a plurality of conductive via plugs through the backplane layer, As metal fingers, they are formed on a continuous electrically insulated backplane layer attached to the rear side of the solar cell after formation of a patterned M1 layer on the rear side of each island. As shown, the M2 interdigitated triangular fingers (M2 emitter fingers 252 and M2 base fingers 254 are electrically separated by a separation gap) is substantially less than the number of M1 fingers of each island M2 Is patterned to be substantially perpendicular or orthogonal to the M1 finger fingers that are bottom patterned to have fingers. The M2 series connection 250 and each island in the column connected in series by an island column (the master cell comprises a 5 x 5 = 25 array of mini batteries in this embodiment) are alternately located at the top and bottom of the island column , And each island is connected in series from the emitter lead or bus bar 244 (emitter end) to the base lead or bus bar 246 (base end). As shown, each island column is separated by an M2 column separation area 256. As shown in FIG. M2 series connection 250 electrically connected to the M2 base fingers 254 of the island (I ₁₁₎ to M2 emitter fingers 252 of the island (I _21). M2 base fingers of the island (I ₂₁₎ (254) is electrically connected to M2 emitter fingers 252 of the island (I ₃₁₎ being connected in perpendicular to the island (I _51). The M2 series connected transverse jumper 248 electrically connects the M2 base finger 254 of the island I ₃₁ (in column 1) to the M2 emitter finger 252 of the island I ₃₂ (in column 2) .

The M1 and M2 unit battery patterns disclosed herein may be designed for separate or similar square islands, triangular islands, or islands of various other shapes, and any combination. That is, the island design and connection pattern can dominate the patterned M1 and M2 designs.

The required electrical conductivity for M2 (or the total thickness of the M2 metal patterned for a given M2 material, such as Al or Cu) is a function of the current and voltage magnitude factor of S, Is smaller than a master cell having an S island (or an S subgroup of islands) connected in an electrical series (or hybrid parallel-to-serial) manner as compared to a master cell comprising an island. In general, if the value of S, i. E. The number of series connected sub-cells or islands, is large, the M2 thickness requirement becomes small because the cell current decreases by S factor and the cell voltage increases by the S factor Number of group islands). For example, the copper M2 layer thickness of an IBC solar cell may range from about 20 to 80 microns for a non-tile solar cell (e.g., 156 mm x 156 mm IBC solar cell) shown in Figure 1, (In some cases, less than 10 microns can be reduced to about 1 micron to 5 microns (thus, the voltage of the Icel cell increases by a factor S and the current decreases by a factor S).

The monolithic tile solar cells or the Iceland structures and fabrication methods disclosed herein provide substantially reduced metallized sheet conductivity and thickness requirements and are then used to reduce metal consumption, process costs, manufacturing process equipment costs, and corresponding capital expenditures . In addition, the byproducts generated in a significant waste by-product, such as a metal plating (e.g., copper plating), from a particular cell fabrication process can be reduced or eliminated due to reduced and relaxed metallized sheet conductivity and thickness requirements (Thus the ability to eliminate dependence on thick metal plating by replacing metal plating with a much simpler and less costly metallization process (e.g., deposition, plasma sputtering, and / or screen printing). The thin and simple M2 metallization pattern reduces the solar cell semiconductor layer microcracks and reduces the overall solar cell and module fabrication yields, for example, substantially reduced patterned M2 metallization tensile stress / mechanical stress reduction and metal plating treatment For example, copper plating) and related handling, eliminating dependence on edge encapsulation and plating electrical contact requirements. For applications required for flexible or bendable solar cells and PV modules, the thinner M2 metallization layer, which can be obtained by the innovation of the i-cell innovation, can improve the flexibility and bendability of the solar cell, and the flexibility, lightweight PV module And does not increase the risk of solar cell microcracks or breakage. The copper plating process used to form relatively thick (e.g., about 30 to 80 microns) copper metallization compared to prior art interlocked rear side-contact (IBC) solar cells is a copper plating process in the press- Plated and prevent the front side of the IBC solar cell from being exposed to the plating chemicals) and the clamping / sealing and declamping / unsealing of the solar cell during and after the plating process, as well as the risk of mechanical breakage of the battery, Lt; / RTI &gt; For example, copper plating of a solar cell having conventional microcracks may result in hard shunts or soft shunts by plating copper according to silicon microcracks, which may reduce yield or performance. In one embodiment, if the copper plating process is removed due to the substantially reduced M2 sheet conductivity (or M2 metal thickness), no special M1 design is required and the patterned M2 layer is recessed or offset from the edge of the solar cell When the edge-sealed copper plating is accommodated, that is, the M2 sheet conductivity requirements of the island master cell or the Icel are relaxed, the thick copper plating process is replaced by a dry non-plating process to form a patterned M2 layer, Clamping or sealing on the front side is not necessary and is not derived from the plating process. Thus, the bottom patterned Ml finger can extend between the edges of the islands or between the border of the segments. In addition, by eliminating dependence on copper plating metallization, any dry cell metallization process (e.g., using screen printing or PVD) can be performed to substantially reduce cell fabrication complexity.

In some metallization embodiments where a metallization material is used in addition to copper (e.g., aluminum), the projected long-term field reliability of solar cells and PV modules can be improved because copper , Penetration of sensitive solar cell surface areas in solar cells using copper metallization may result in deterioration of minority carrier lifetime (and efficiency) and long term reliability problems due to copper diffusion into semiconductor substrates.

The thinned solar cell metallization obtained by Icelel is advantageous compared to known solar cells using relatively thick (typically about 30 to 80 microns for IBC solar cells) plated metal, often plated copper, for example, Backplane laminated solar cells have reduced solar cell warping and mechanical stress. The reduction in M2 metal thickness (in one embodiment at least 30 to 80 microns to less than about 5 microns) in the dual level metallization structure improves solar cell and PV module flexibility / Cracks do not occur and PV module performance does not deteriorate. Also, as the M2 metal thickness and amount decrease, the mechanical stresses, e.g., the patterned metallization stresses on the sensitive solar cell semiconductor absorber, are substantially reduced and the subsequent solar cell and module processing (e.g., , Micro-cracking and reduced yields during field operation of the module stack (where lamination pressure and heat can be used) and installed PV modules. For example, the patterned M2 is a relatively inexpensive, highly conductive metal, For example, copper has a linear CTE of about 17 ppm / 占 폚 and crystalline silicon has a linear CTE of about 2.7 ppm / 占 폚 (bulk resistivity: 1.68 占 占 퐉) or aluminum The CTE difference between copper and crystalline silicon is approximately 14 ppm / ° C, and the 140 ° C module lamination process has a mismatch of dimensions of 0.25 mm or 250 μm for a 156 mm x 156 mm solar cell (ie, (Which extend about 250 microns from one side to the other, compared to silicon), resulting in very large tensile stresses on the silicon during the module stacking process. A monolithic mini-cell having a thin film M2 metallization pattern patterned according to the disclosed subject, For example, a layer thickness of less than about 10 microns, in some instances less than 5 microns) substantially reduces or eliminates the crack initiation and propagation modes, and the resulting throughput reduction.

In order to eliminate the plating process, for example, the copper plating process (and also cost, additional process complexity, thermal / mechanical stress, and potential production reduction) for the metal plating process, (S) may be selected from the group consisting of a low resistance or a high conductivity metal (a further high conductivity metal, for example silver, which can be used, for example low inexpensive high conductivity metals such as copper and / Is small enough to use a relatively low cost metal deposition process, such as plasma sputtering or vapor deposition (physical vapor deposition or PVD process), especially in this example having a thickness of M2 (e. G., Copper or aluminum thickness) , And in some instances less than 5 microns. In addition, further inexpensive metallization processes, such as screen printing, can be used instead of copper plating.

Further, in one embodiment, M2 can be patterned to be substantially orthogonal or perpendicular to Ml, and the number of M2 fingers (e.g., tapered fingers) can range, for example, from about 5 to 50 May be much smaller than the number of M1 fingers. In some instances, an M2 finger designed in a tapered finger shape, e.g., a triangular or trapezoidal shape, will have a reduced M2 metal thickness requirement (typically about 30%) as compared to a rectangular finger.

The main / master cell is divided into an array of islands or sub-cells (e.g., an array of N x N squares or similar squares or K triangles or a combination thereof), and a hybrid combination of series or electrical parallel and electrical series When connected, each island, or mini-cell, or entire master cell can be, for example, a factor of N x N = N ² (where all square islands are electrically connected in series) or K factor ). The main / master cell or ahyisel the maximum power (mp) current I _mp, and the maximum power voltage V is _mp, each series connection island (or sub-group of islands are connected in series after the parallel connection) is the maximum power current I _mp / N ² (Connected in series with N ² Island) and the maximum power voltage V _mp (no island voltage change). Designing the first and second metallization layer patterns M 1 and M 2 so that the islands on the shared continuous or continuous backplane are connected in series and in series, the main / master cell or the i-cell is connected to the maximum power current I _mp / N ² And the maximum power voltage N ² x V _mp or cell (Icel) Maximum power P _mp = I _mp x V _mp (the same maximum power as the master battery without a mini battery compartment).

Thus, a monolithic island-master cell or an Icel structure can reduce ohmic losses due to reduced solar cell current, and typically the thinness of the solar cell metallization structure, and the M2 layer can be much thinner if applicable or required. Also, due to the reduced current and increased voltage of the master cell or the Icel cell, relatively inexpensive, high efficiency, maximum power point tracking (MPPT) power optimizing electronics can be embedded directly on the PV module or integrated on the solar cell backplane.

The main / master cell or the Icelel has an S-square or similar square pattern of islands (assuming S is an integer and S = N x N) or a P triangular island (P is an integer, for example 2 or 4) It is assumed that each adjacent set of P trench isolation triangular islands form a square subgroup of islands. Each adjacent set of P triangular islands can be connected in an electrically parallel manner, and a series of S subgroups are electrically connected in series. The main cell thus obtained is the maximum power current I _mp / S and the maximum power voltage S x V _mp . Indeed, the reduced current and increased voltage of the island can be directly embedded in the PV module and / or integrated on the solar cell backplane, while relatively inexpensive, high efficiency, maximum power point tracking (MPPT) power optimized electronics. In addition, the innovative form of the i-cell enables distributed shade management based on the generation of inexpensive bypass diodes (e. G., Pn junction diodes or Schottky diodes) to the module, and, for example, Are embedded with each solar cell before lamination of the final PV module. In the metallization embodiment, the M1 metal layer is formed by Al and / or Al / Al / Al interfaced fine pitch (base pitch in the range of approximately 200 [mu] m to 2 mm, more specifically 500 [ Si metal finger pattern (formed by screen printing or PVD and post PVD patterning). For each island, the M1 finger may be slightly recessed from the trench isolation edge (e.g., it may be recessed or offset from about 50 microns to several hundred microns from the island trench isolation edge). That is, the M1 fingers of each island in the master cell are electrically and physically separated from one another (the M1 pattern corresponding to a particular island may be referred to herein as the M1 unit cell).

* The electrical connections of the islands (all in series, hybrid parallel-series, or all in parallel) can be defined by the M2 pattern design, M1 acts as the on-cell contact metallization of all master cell islands and M2 is high The conductive metal provides the electrical connection of the island and the high conductive metallization and electrical connection in the icel or master cell.

An M2 design (e.g., a M2 pattern using a rectangular or tapered meshed M2 base and emitter fingers) can provide all serial, hybrid parallel-to-serial, or all-in-parallel connections of the islands within the icel. In some instances, as described above, the M2 design, which provides all series or hybrid parallel-to-serial electrical connections of the islands, increases the main / master cell voltage and reduces the main / master cell currents (e.g., Where S is the number of sub-groups of islands or islands in series). Reducing the cell current while increasing battery voltage alleviates / reduces the metallization conductivity requirements, permits the metalized layer to be thinned and reduced in metal sheet conductivity (e.g., because there is no need for copper plating for battery metal formation ) Manufacturing costs, process complexity, manufacturing equipment and equipment costs, relatively thick metallization processing, for example cracks associated with thick metallization formed using copper plating, reliability problems, and overall yield reduction are reduced or mitigated .

In addition, an improved voltage / reduced current main / master solar cell or an Icel is a relatively inexpensive high performance, high efficiency maximum power point tracking (MPPT) power optimized electronics embedded within each module and associated with each of the Iceland and / Improved power and energy collection capability across the master cell with shaded, partially shaded, and unshaded islands. Likewise, each island in each Iceloc or each Icelel has an inexpensive bypass diode (pn junction diode or Schottky diode) to provide distributed shade management capability for improved solar cell protection and power collection under shaded and partially shaded conditions Barrier diode). All parallel electrical connections of the islands provided by all the parallel M2 patterns have some advantages of the many advantages of the monolithic island solar cells described above compared to all serial or hybrid parallel-to-serial connections, especially the increased flexibility of the obtained Icel and PV modules And bendability.

For example, if using a PVD aluminum for M2 (M2 layer less than 5 microns thick provides all serial or hybrid parallel-to-serial connections in the Icel), the metal stack may be used to provide M2 solderability (E.g., formed by plasma sputtering) Ni or NiV, and then optionally PVD Al (primary metal) capped with a relatively thin layer of Sn (formed by plasma sputtering, for example). The aluminum layer may be deposited using an electron beam or thermal deposition process.

S square islands are assumed to be connected in series. Each "island" electrically connected in series may comprise a sub-group of smaller islands connected in electrical parallelism, for example a triangular island. The N x N arrays of square islands are connected in series: S = N x N = N ² _.

Also, the M2 finger pattern may be substantially orthogonal or perpendicular to the M1 pattern, which may make the number of fingers of M2 substantially smaller (on the order of 5 to about 50 times the number of M1 fingers). For example, a 156 mm x 156 mm cell (tile or island member) with an inter-base M1 metal pitch of 750 microns may have about 416 M1 fingers and about 8 to 40 M2 orthogonal fingers.

Likewise, a reduction of a large factor by an M1 / M2 finger ratio can be applied to the M2 metal finger count for each island sub-cell (the M2 pattern corresponding to a particular island may be referred to as M2 unit cell). For example, for an S = 3 x 3 islands master cell design, each island has about 140 M1 fingers (running at a distance of about 52 mm from each island) and a M2 finger count 12 (e.g., M2 base and emitter The metal finger has a combined width or pitch of about 6.5 mm, much greater than about 750 microns of M1). In some instances, the M2 layer may provide a relatively large cell coverage ratio (close to 100%), and the M2 layer deposited in one example (e.g., with PVD) may be patterned using pulse nano- To form a finger-to-finger separation gap of less than 100 μm thick.

For a given metal (aluminum or copper) , the guidelines for M2 in the dual level metallization structure

For cell area = L x L = L ² , it is assumed that I _mp is the master cell maximum power point (MPP) current (base or emitter current) extracted from the entire M1 layer under STC conditions. The maximum power points of the solar cell operation, to extract from the cell contact metallization level M1 is passed through the conductive M2-M1 via plug flowing total current is I _mp for I _mp and the emitter to the base (without consideration current direction 2 _{&lt; / RTI} &gt;

Further, P _mp And V _mp are the maximum power point (MPPT) power and voltage of the cell. P _mp = V _mp x I _mp ; The total electrical cell current (including base and emitter current, regardless of flow direction) per unit area extracted from M1 = 2I _mp / L ^2, where half of the cell area produces I _mp base current and half of the cell area generating I _mp emitter current due to a: and MPP power = P _mp / S of the island (or sub-cells) connected in series, where S is the number of subgroups of the island or islands that are connected in series (for example: S = N x N = N ² ).

I _f is the current collected by each individual M2 triangular finger from the bottom M1 finger with respect to the triangular area covered by the M2 finger, I _f = I _mp / (FS), F is the Is the number of M2 triangular finger pairs per island; The finger current in the base or emitter triangular fingers on a series connection island is a function of x as follows: I (x) = {[2I _mp / L ² ]. [(X / H). H = L / N (for S = N x N) and h = H / F = L / (NF); Therefore, I (x) = {[ 2I mp / L 2]. [(X / F]}. From 0 to 0 x dx of integrals _{= {[2I mp / (FL} 2 )]. x.dx} from 0 to x integral value; Thus, I (x) = [2I _mp / (FL ² )]. (1/2) x ² = [I _mp / (FL ² )]. x ² ; And the total current per finger is I _f = [I _mp / (FL ² )]. H ² = [I _mp / (FL ² )]. (L / N) ² = [I _mp / (FN ² ) = I _mp / (FS).

Further, M2 is assuming a resistance ρ, thickness t, and M2 sheet R _s = ρ / t, the power loss per M2 fingers per island P _lf (i.e., power dissipation per M2 fingers per M2 unit cell) is P _lf = {{ (ρ.dx) / [(txh) / H]}. [I mp / (FL 2)] 2 .x 4} represents the integral value from 0 to x, therefore P _lf = [(ρ.H) / (th)]. [I _mp / (FL ² )] ^2. (1/4) .H ⁴ = [(? H) / (th)]. [I _mp / (FL ^{2 )] 2. (1/4).} (L / N) P lf = ⁴ when _inde, h = H / F, and H / h = F (ρ.F / t). [I _mp / (FL ² )] ² (1/4). (L / N) ⁴ ; Therefore, the power loss per finger _{P lf = (ρ / t)} .FI mp 2. (1 / F 2 L 4). (1/4) .L 4. (1 / N 4) = (ρ / t) .I _mp ^2. [1 / (4.FN ⁴ )]; If there are 2F fingers per island, the total M2 power loss (P _M2isle ) per island under the MPP condition is P _M2isle ... = (R / t ) .I mp 2 [1 / (4.FN 4)] 2.F = (ρ / t) .I mp 2 [1 / (2N 4)] represented by; Total N x N = N ² If there is an island, the total M2 power loss at the MPP is P _M2loss = (ρ / t) .I _mp ^2. [1 / (2N ⁴ )]. N ² . = (Ρ / t) .I mp 2 [1 / (2N 2)] represented by; Therefore, P _{M2loss = (Ρ / t) .I mp} 2. [1 / (2N 2)] a.

Assume, for example, that the average solar cell efficiency P _mp = 5.50 Wp is approximately 22.5% and V _mp = 0.59 V, I _mp = 9.3. The M2 metal layer thickness requirement for aluminum and copper is that the allowable relative ohmic loss factor k of the overall maximum thickness M2 is 0.01, 0.005, or 0.0025 (as a P _mp factor for the cell), power loss factor = k = (P _M2loss / P _The required M2 metal thickness based on the allowable k and t in K (at the maximum permissible M2 loss) = (ρ / t). (I _mp ² / P _mp ) [1 / (2.N ² ) is t = (ρ / k). (I mp 2 / P mp) [1 / (2.N 2)] can be expressed as a, k is the maximum permissible loss as a factor P _mp.

Table 1 below shows the required M2 thicknesses calculated for copper or aluminum M2 metallization for various acceptable loss factors (k) and various N master cell embodiments, and this embodiment illustrates a series of N x N island arrays S = N x N), and the value of N is equal to or less than 1 (for example, a cell having a single island, i.e. no divided trench) to 6 or less ), Assuming the following: ρ = 1.68 μΩ.cm for copper metallization and ρ = 2.82 μΩ.cm for aluminum metallization and P _mp = 5.5 W, I _mp = 9.3 A, acceptable loss factor k 0.01, 0.005, or 0.0025.

Thus, the patterned M2 metal layer thickness (when formed using PVD, such as evaporation or sputtering) is limited to less than about 5 microns, and in some instances the M2 PVD metal layer thickness is limited to less than about 3 microns , And many economies (for example, PVD material cost reduction and processing simplification) also provide fabrication advantages.

In some instances, electron beam evaporation or thermal evaporation or DC Marktron plasma sputtering (physical vapor deposition or PVD processes) may be performed using high throughput, inline, evaporation and / or plasma sputtering tools available for high productivity solar PV applications Can be used to deposit a high quality M2 metal layer having nearly bulk material resistance (e.g., a bulk resistance to copper of 1.68 mu O. O.cm or a bulk resistance to aluminum of 2.82 mu O.cm). For example, in-line evaporation and / or DC marketron plasma sputtering (PVD) tools for aluminum M2 sputter deposition can be used to (i) provide laser-assisted deposition for low M2-M1 via plug contact resistance and improved metal adhesion to the backplane, Argon plasma sputter etching to clean drilled through backplane vias; (ii) electron beam evaporation or thermal evaporation of pure aluminum or DC magnetron sputtering; the M2 layer may be based on a loss factor design rule of aluminum with a thickness of, for example, 3 to 5 microns; (iii) thin DC magnetron sputtering, such as, for example, a layer thickness of 0.05 [mu] m to 0.25 [mu] m of a NiV or Ni capping layer; And (iv) DC magnetron sputtering of a Sn, Sn alloy or suitable solder material having a layer thickness of approximately 0.5 microns to several microns.

In addition, an in-line DC magnetron plasma sputtering (PVD) tool for copper M2 sputter deposition can be fabricated by (i) exposing via laser drilled backplane via holes for low M2-M1 via plug contact resistance and improved M2 adherence to the backplane Argon plasma sputter etching to clean the M1 contact area; (ii) DC magnetron sputtering of a NiV or Ni film (e.g., a layer thickness of 0.05 to 0.25 m) as a diffusion barrier and adhesion layer; (iii) DC magnetron sputtering of pure copper (copper thickness may be based on a loss factor design rule); And (iv) DC magnetron sputtering of Sn, Sn alloy, or another suitable solder material (layer thickness from about 0.5 [mu] m to several [mu] m).

In some embodiments, N may be selected to meet specific design criteria of a desired desired loss factor k and a corresponding maximum allowable M2 thickness. If M2 copper or aluminum thickness is kept below about 5 [mu] m, M2 can be easily patterned using pulsed laser ablation.

The M2 metal layer is formed using laser ablation patterning while DC magnetron plasma sputtering of aluminum or copper, and also applicable barrier and / or capping layers, and the additional M2 metal layer formation method is performed using PVD of aluminum or copper Possible barrier and / or capping layer) then wet patterning (screen printing mask, wet etch metal / release mask); But are not limited to, screen printing (high conductivity, low temperature cured metal plates, e.g., high conductivity silver paste, copper paste, aluminum paste, etc.).

If aluminum is used instead of copper for M2, the cell manufacturing line and the resulting cell do not include copper, and in some instances all of the drying process can be used to make the cell. Thus, the risk mitigation of the battery module in the field of battery fabrication is improved (due to the inherent complexity involved, for example, in copper processing, such as copper plating), which results in long term reliability problems due to copper contamination, Because it is removed. In addition, the M2-M1 contact (metallization in a via hole or via plug) is a contact between the aluminum and does not require a diffusion barrier between M2 and M1. In addition, additional suitable metal stacks, including M2Sn / NiV / Al stacks or aluminum as the main M2 conductor metal, allow pulsed laser ablation patterning, provide all dry cell back end metallization processes and increase battery yield.

In some embodiments, the monolithic island master cell or the Icel is integrated with a monolithically integrated bypass switch (MIBS) with each island in each of the Icel and / or Icelels to provide distributed shade management, For example, it provides a high performance lightweight, thin film format, flexible, high efficiency (e.g., more than 20%) solar module in a pn junction mode, e.g., a rim pn junction diode. In addition, the MIBS device may be a rim Schottky diode formed around a metal-contact Schottky diode, for example, an aluminum or aluminum-silicon alloy Schottky contact on n-type silicon. The pn junction MIBS diode pattern can be one of many possible pattern designs. For example, in one MIBS diode pattern, the rim diode p + emitter region is a continuous closed loop band interposed (or supported) between n-type base regions.

Although standard rigid glass modules (e.g. copper plating cells and individual shade management components) can be used to reduce module fabrication costs for island solar cells (Icel), weight and cost savings can be achieved by MIBS integration Copper plating and individual bypass diode components may not be used. The MIBS integration benefits of monolithic island master cells (for example, by removing discrete components from the cell) result in substantial manufacturing risk mitigation (much less cracking and less cracking) due to improved overall projected reliability and process simplification, Includes reduced material costs along with production. Thus, the monolithic island MIBS integrated master battery module reduces the weight, volume / size (and thickness), increases the power density (W / kg) of the module by a significant factor, and increases the installed system balance Can be reduced.

The monolithic island MIBS integrated master battery module may provide some or all of the following advantages: management of distributed MIBS shades without external components; For example, about 1.2 kg / m &lt; ² &gt; A relatively small average module weight per unit area on the substrate (~ 0.25 lb / ft ² ) may be at least 10 times lighter than a standard rigid c-Si module; The module power density of about 155 W / kg (~ 70 W / lb) is at least 10 times higher than standard rigid c-Si modules; High efficiency (over 20%) lightweight flexible modules for a variety of applications; About 10 times and 40 times less module transfer weight and volume (per transferred MW); Reduced overall BOS cost, enabling the installed PV system cost to be lower than the installed PV system cost using standard solid c-Si modules; And reduced BOS and miscellaneous costs, labor, installation hardware, and wiring costs for handling and handling.

The MIBS formation can be integrated and performed with the divided trench isolation forming process. When the rim diode design is used, the monolithically integrated bypass switch (MIBS) rim provides the additional benefit of reducing or eliminating microcracks and / or propagation in the solar cell during and / or after manufacturing the solar cell can do.

The pre-strained silicon zone trenches separating the rim bypass diodes from the islands can be formed, for example, by using a laser beam diameter (or a trenching process when using a process other than laser trenching) Ability) and the semiconductor layer thickness. A typical trench isolation width formed by a pulse nanosecond (ns) laser scribing may be small, but may be about 20 to 50 microns. Pulsed laser ablation or scribing is proven by a method that is efficient and forms a trench isolation region, but instead of laser scribing, other non-mechanical and mechanical scribing techniques are used to isolate trench isolation Regions can be formed. Other non-laser methods include plasma scribing, ultrasonic or sonic drilling / scribing, waterjet drilling / scribing, or other mechanical scribing methods.

16A is a schematic view of a solar-side view of a island master cell having a plurality of islands (for example, 4 x 4 islands) and a bypass switch or an MIBS device monolithically integrated on an island. This is an embodiment of an MIBS using a photovoltaic by-pass diode that is separated from the solar cell using a pre-isolated trench for the icel that shares a continuous backplane.

16A is a schematic diagram of an island MIBS (monolithically integrated bypass switch) master cell 270 (an Icel embodiment shown as a 4 x 4 array of square islands) and a plurality of star closed loop MIBS bypass diodes, Electrically disconnected MIBS bypass diode 272 is electrically isolated from island I ₁₁ by island partition isolation trench 274. Each of the island (I ₁₁ to I ₄₄₎ preferably includes (or is formed by the laser ablation / scribing the scribing by the more suitable technique described) jeonjubu compartment trench, for example, cell separation trenches 276 To form an icicle having a 4 x 4 array of islands that share a common continuous backplane formed from a conventional, continuous, next compartmented solar cell semiconductor substrate.

16A shows the sun side of an MIBS capable solar cell (Icel) having a mini battery or island and a closed loop rim diode (pn junction diode or Schottky barrier diode). Each mini cell island (I ₁₁ to I ₄₄₎ is separated jeonjubu corresponding trench 276 and jeonjubu MIBS rim diode (e.g., MIBS bypass diode for cells (I ₁₁₎ (272) and around the separation trench ( 274), each mini-cell or island having a corresponding MIBS rim diode, i. E. There is one MIBS rim diode per island or mini-cell. The islands or mini-cells may be electrically connected in series through a battery metallization pattern design, but other connections, for example, parallel or series and parallel hybrid combinations may be possible.

As a representative example, FIG. 16A shows a 4 x 4 array of mini batteries of the same size and shape, each mini battery having a corresponding preformed closed loop rim diode. In general, such a structure may use an N x N array of mini batteries and a corresponding monolithic closed loop rim diode, where N is at least two integers to form a mini battery array. Figure 16 shows a symmetric N x N mini battery array of complete square solar cells, but a mini battery or island array design may have an asymmetric array of N x M mini batteries. The mini battery or island may be a square (N = M for a square master cell) or a rectangle (where N is not equal to M and / or the master cell is rectangular instead of square), or a variety of other shapes.

Further, the mini-cell of the master cell (again, the master cell means an array or island of mini-cells sharing a common continuous backplane, and all originating from the same conventional solar-cell semiconductor substrate, followed by a plurality of mini- Trench) may optionally have substantially the same area, but is not necessary. The semiconductor layers for the array of islands or mini-cells are electrically isolated from one another by using trench isolation formed by a suitable scribing technique such as laser scribing or plasma scribing. In addition, each mini-cell or island semiconductor substrate is partitioned and separated using a trench isolation from a monolithic closed loop MIBS diode semiconductor substrate. All trench isolation regions on the master cell may be formed during the same fabrication process step, for example during a single laser scribing process step in the cell fabrication process flow.

Figures 16b and 16c illustrate one island (or unit cell, or unit cell) on a continuous backplane 288 that is shared after the fabrication process to form an MIBS capable rear-side / rear-side-junction island master cell as shown in Figure 16a. for example, the rear side of the I ₁₁ of Fig. 16a), - contact / rear side - with joint embodiment MIBS rim or jeonjubu diode aspect of the battery cell forms detailed cross-sectional view, which passivation / ARC coating layer (280 in the solar cell in the MIBS device) And an ARC coating on the textured surface of a solar cell (and an MIBS device) as shown. Solar cell and MIBS structural details, for example, the patterned M1 and M2 metallization layers, are not shown in the figure. 16B shows an MIBS implementation using a pn junction peripheral rim diode bypass switch. The trench isolation MIBS rim pn junction diode region 282 (separated from island I ₁₁ by a corresponding isolation trench 274) is formed by an n-doped (e.g., an indium doped) region and a p + doped For example, heavily doped with boron), and is used as a pn junction diode bypass switch. The MIBS rim pn junction diode region 282 may be a full rim diode having a width in the range of about 200 to 600 microns (a smaller or larger dimension as described above is also possible). Relative dimensions of the MIBS rim diode and solar cell are not shown to be exact dimensions. 16B illustrates a backplane laminated (or backplane-attached) MIBS capable solar cell after completion of the fabrication process for an MIBS capable rear-side / back side-junction (IBC) solar cell, After back-contact / back-end cell processing through patterned metallization levels or M1 (e.g., screen printing or PVD aluminum or another suitable metal such as aluminum-silicon alloy or nickel), backplane lamination, crystalline silicon reuse Epitaxial Silicon Lift-Off Separation and Isolation from Possible Templates (If an epitaxial silicon lift-off process is used to form a substrate, this process is not applicable when using starting crystalline silicon wafers), an MIBS rim diode border The formation of trench isolation regions (e.g., by pulsed laser scribing or cutting) to define, (E.g., PECVD or a combination of ALD and PECVD), and fabrication of the final second patterned metal level or M2 on the backplane (along the conductive via plug) after optional silicon etching, texturing and texturing, passivation and ARC deposition do.

As is known in Fig. 16B, the process for forming the p + emitter region (field emitter region and / or heavily doped emitter contact region) of the solar cell may include forming p + junction doping for forming the MIBS pn junction Lt; / RTI &gt; For example, a patterned M1 metal (not shown) made of aluminum or an aluminum alloy, e.g., some silicon-doped aluminum (not shown) may be applied to the MIBS pn junction diode as well as the contact metallization or first metallization level for the solar cell (In the p + region and the n-type substrate region through the n + doped contact window). An n-doped silicon region of the MIBS pn junction diode is formed from the same n-type silicon substrate serving as the base region of the solar cell (for example, when starting n-type crystalline silicon wafer is used without epitaxy) Or formed from an in-situ doped n-type crystalline silicon layer formed by epitaxial deposition when using epitaxial silicon lift-off processing to form solar cells and an MIBS substrate), substrate bulk region doping is referred to as background doping of the substrate can do. The patterned M1 and M2 metallization structures complete the required monolithic solar cell and MIBS junction diode electrical interconnections and the MIBS diode ends are connected to each solar cell to provide continuous solar cell protection for shade management and shading, Base, and emitter ends of the device. 16B, the top and sidewall edges of the MIBS pn junction diode are passivated using the same passivation layer and process to passivate the solar side and edge of the solar cell, the passivation / ARC coating layer 280, do. FIG. 16A illustrates an exemplary embodiment of the present invention, including, for example, patterned M1 and M2 metallization, a rear passivation layer, an M1 contact hole, an M-M2 via hole through the backplane, and an n + doped contact window for n-type substrate M1 connection in the MIBS device structure Some details of the same solar cell and MIBS structure are not shown.

16C shows an MIBS implementation using a peripheral Schottky rim diode bypass switch. The isolated Schottky rim diode bypass switch region 286 (separated from the island I ₁₁ by a corresponding isolation trench 274) includes an n-doped region and an inner, outer n + region, and a Schottky diode bypass switch . The Schottky rim diode bypass switch region 286 can be a full rim diode having a width in the range of 200 to 600 microns (these dimensions can be selected to be larger or smaller than this range).

In one fabrication embodiment, FIG. 16C illustrates a method of fabricating a silicon-on-insulator (e. G., Silicon-on-insulator) Epitaxial lift off from a crystalline silicon reusable template when using an epitaxial lift-off silicon substrate at the first patterned metallization level, or the termination of the back-contact / rear-end cell through M1, backplane lamination, And isolation (this process is not applicable or necessary when using starting crystalline silicon wafers instead of epitaxial lift off substrates), trench isolation formation (e.g., pulse laser scriber) to define the MIBS rim Schottky diode borders Formed by ice or cutting), selective silicon thin film etching, (E.g., PECVD or another combination of processes such as PECVD and ALD), and a final second patterned metal level on the backplane (with a conductive M1-M2 via plug) after cleaning, passivation and ARC formation Or backplane-attached MIBS capable solar cells after the fabrication of the MIBS capable rear-side / rear / side-junction island master cell fabrication process, including fabrication of the backplane or backplane-attached solar cell.

As is known in Fig. 16C, an n-type silicon substrate used as the base region of the solar cell (e.g., formed through in-situ doped epitaxial deposition when using epitaxial lift-off processing, or formed by epitaxial lift off Formed from a starting n-type crystalline silicon wafer when processing is not used) is used as the n-type silicon substrate region for the MIBS Schottky diode. For example, an M1 metal (not shown) made of a suitable aluminum alloy, such as aluminum or some silicon-doped aluminum, is deposited on the base region through n + doped contact openings and through the p + (As well as contact of the non-ohmic Schottky barrier to the less heavily doped n-type silicon substrate region and to the n-type silicon through the heavily doped n + doped region) Ohmic contact) forms a metallization contact on the MIBS Schottky diode. The less doped n-type silicon substrate region of the MIBS diode is the region from the same n-type substrate used for the solar cell and serves as its base region (for example, when using epitaxial silicon lift- Type substrate can be formed by in-situ doped n-type epitaxial silicon deposition or formed from a starting n-type crystalline silicon wafer when epitaxial silicon lift-off processing is not used). heavily doped n + diffusion doping can be formed in the n-type silicon region for the MIBS Schottky diode ohmic contact on the n-type silicon substrate and for the solar cell using the same process (in the following patterned M1 metallization) Doped n &lt; + &gt; doped base contact regions. The combination of the patterned M1 and M2 metallization structures terminates the solar cell and MIBS Schottky diode electrical interconnects and the MIBS diode ends are properly connected to the solar cell ends to provide battery level integrated shade management and solar cell protection. As is known in Figure 16C, the top and sidewall edges of the MIBS Schottky diode are the same passivation and ARC layers used to form the passivation and ARC layers on the edge and sun side of the solar cell, Attention is paid to the passivation / ARC coating layer 280. Figure 16C does not show some structural details of the solar cell structure, including, but not limited to, the patterned M1 and M2 metallization layers.

The monolithic island solar cell disclosed herein, and alternatively the MIBS embodiment, can be used to form electrical isolation and compartments between a semiconductor substrate region (island), an island for an MIBS device, and an adjacent island or solar cell region Trench isolation is used with the backplane substrate. One method for forming trench isolation is pulse (nanosecond) laser scribing. Laser features and points using a laser scribing process to form a trench isolation region that divides and electrically isolates a substrate region are described below.

Pulsed laser scribing for trench isolation formation can be performed at a suitable wavelength (either green to remove a semiconductor layer with relatively good selectivity to cut through the semiconductor substrate layer for the backplane material, or infrared or additional suitable wavelength) (ns) laser source can be demonstrated to be commonly used to scribe and cut through silicon. The laser source may have a flat top (known as a top hat) or a non-flat top (e.g., Gaussian) laser beam profile. Although the pulsed laser source wavelengths that are very absorbent to silicon can be used, they can be partially or fully transmitted through the backplane (thus, after the through semiconductor layer laser cutting is complete and the beam reaches the backplane sheet, Without cutting the semiconductor layer). For example, a pulsed nanosecond IR or green laser beam can be used that can effectively cut the silicon substrate layer and partially propagate through the backplane material. (Thus, a very small amount of backplane material is removed during trench isolation cutting ).

The pulsed laser beam diameter and other characteristics of the pulsed nanosecond laser source can be selected such that the discrete scribe width is in the range of a few microns to tens of microns, and a width greater than about 100 microns is too large to be used for the unnecessary Waste is generated and the total area efficiency of the solar cell and module is slightly reduced. Therefore, it is advantageous to reduce the trench isolation region compared to the highly desirable solar cell area. Indeed, the pulse nanosecond laser cutting can form a trench isolation region having a width within a preferred range of about 20 microns to about 60 microns. For example, for a 156 mm x 156 mm solar cell, a trench isolation width of 30 microns corresponds to an area ratio of 0.077% to the trench isolation area as a fraction of the cell area. This represents a somewhat negligible area relative to the area of the solar cell, that is, this small ratio ensures that the waste in the solar cell area is negligibly small and that the total area solar cell and module efficiency losses are very low.

Pulsed nanosecond laser scribing or cutting to form the trench isolation may be performed by a backplane lamination process when a starting crystalline silicon wafer is used to fabricate a solar cell in the above described rear-side / back side- (And in the case of solar cells using epitaxial silicon lift-off processing, before and after the back-plane lamination process and then the lift-off separation of the stacked cells from the reusable template and after the pulsed laser control of the solar cell) . In the case of a solar cell fabricated using epitaxial silicon lift-off processing, the trench isolation scribing or cutting process is optionally used for pre-isolated scribing of the epitaxial silicon layer to define a lift-off isolation boundary and / The same pulsed laser tools and sources used for the post-separation adjustment of the used or laminated solar cells can be used. Thus, additional laser processing tools may not be required to form the trench isolation region.

Pulsed nanosecond laser scribing to form the trench isolation can be used to define the island and to define a fully isolated MIBS rim diode region outside the defined isolated solar cell island surrounded by the rim . The pulsed ns laser scribing process can also form other designs of MIBS diodes, for example, within a plurality of MIBS diode island designs and many other possible MIBS pattern designs.

Pulsed laser scribing can be used to cut thin layers (e.g., less than 200 microns and specifically less than 100 microns) of a silicon substrate layer (from the sun side) and substantially stop on the backplane material sheet. Optionally, a simple real-time, in-situ laser scribing process endpointing, such as using reflection monitoring, can be used to control the process control and the end of the process to minimize trenching or material removal in the backplane sheet, It can be used for pointing.

The sidewalls of the solar cell and the MIBS rim diode region may be subjected to subsequent wet etch (e.g., part of the solar cell wet etch / texturing process of the solar cell) during the remaining solar cell fabrication process steps, cleaning after texturing, Lt; RTI ID = 0.0 &gt; deposition). &Lt; / RTI &gt;

The MIBS diode may be a pn junction diode used as an MIBS bypass device or as a shade management switch. The pn junction MIBS diode fabrication process for fabricating an MIBS capable solar cell may have the following advantages among other features and advantages:

In some solar cell processing designs, it may be minimally altered or fundamentally unchanged for the main solar cell fabrication process flow to perform MIBS (e.g., using a crystalline silicon starting wafer or a back-junction using epitaxial silicon / Rear-contact crystalline silicon solar cell fabrication and porous silicon / lift-off processing with reusable crystalline silicon templates and electrically insulated backplanes). Therefore, the processing cost may not be basically added to perform the MIBS together with the solar cell (Icel) disclosed herein.

In the post-contact / rear-junction epitaxial silicon lift-off cell process, the following process can be performed after completion of the on-template cell process including most of the post-contact, back- Provided as an example of a process flow): (i) stacking a backplane on the back side of a solar cell; (ii) to define the epitaxial silicon liftoff separation boundary (e.g., using a pulsed nanosecond laser scribing tool or an additional scribing tool, e.g., plasma scribing). The thin film epitaxial silicon substrate Of pre-separation trench scribing; (iii) mechanical lift-off separation and desorption of backplane supported cells from a reusable crystalline silicon template; (iv) laser conditioning (using a pulsed nanosecond laser source) of the backplane laminated cell to form the final desired dimensions of the solar cell with the associated MIBS and for accurate adjustment; (v) pulsed nanosecond laser scribing (or plasma scribing or an additional suitable scribing method) on the sun side of the solar cell to define the inner solar cell islands and peripheral rim diode area, , This step may be followed by additional cell processing steps such as, for example, PECVD solar side passivation and antireflection, such as providing island and corresponding MIBS areas, and (vi) after subsequent cell processing such as cleaning after sun side texturing and texturing, Coating (ARC) layer deposition and final cell metallization (e.g., a second patterned metallization level, if applicable). If a starting crystalline silicon wafer is used instead of an epitaxial silicon lift-off process, the process flow is very similar to the flow described above except that it does not include a reusable template, porous silicon, epitaxial silicon, or isolation process. In the process flow described above for a solar cell fabricated using epitaxial silicon lift-off processing, the trench isolation scribing process and tool can be used to pre-release trench scribing and / or post-ply lamination solar cells and post- It can be the same as the process and tool for precision control.

The laser scribed trench isolation process can be performed to form thrown semiconductor trenches in the semiconductor layer (e.g., using a pulsed nanosecond laser source) through the entire thickness of the crystalline silicon layer, To form an n-type silicon island region for the solar cell assuming an electrically isolated n-type silicon rim region of the MIBS diode and an n-type base and a p + emitter solar cell (rear-contact / rear-junction IBC solar cells) A typical doping form of the battery).

In all series-connected cells, the M2 cell metallization design, which produces sufficiently small or negligible ohmic losses, should be used due to the current flow on the transverse M2 connector between adjacent series-connected columns. A lateral M2 jumper or connector (which may be formed with the patterned M2 layer) is used to connect adjacent columns of the series connection.

17, all of the series-connected icel or master cells 300 are connected to the island buses I ₁₁ to I ₄₄ (the external battery boundaries (not shown)) electrically connected in series from the emitter bus bar 308 to the base bus bar 310 (N rows and N columns, shown as 4 x 4 in the representative example) of the islands defined by the electrical isolation trenches 304 and 302) and each island in the column has an M2 serial connection 306 (Briefly indicated by arrows), and each column is electrically connected in series by the lateral M2 jumper 312. [0035] The master cell 300 has N columns (N = 4 in this embodiment) and N-1 lateral M2 jumpers 312 (N-1 = 3) of length 2H and width W, respectively. The lateral M2 jumper half segments have a length H (H is the lateral dimension of each square island) and a width W. M2 metallization pattern may correspond to the units M2 cells, each of the island (I ₁₁ to I ₄₄₎ shown in, but not shown in FIG. 13 to FIG.

M2 metal layer thickness t and resistance p (or sheet resistance rho / t). The master square cell has an area L2, a maximum power P _mp , and a non-island (non-tile) maximum power point MPP current I _mp (assuming a single island cell, The MPP, MPP currents for island master cells containing connected islands are N ² ). It is assumed that the island master cell has an N x N series connected island, and P _s Is an ohmic power loss per half segment of the transverse M2 jumper, and P ₁ is the assumption that the total ohmic power loss of all the lateral jumper M2 segment, therefore _{P l = 2 (N-1} ) .P of _s. The internal column current flow ohmic losses in all series-connected N x N master cells can be calculated by the equation: P _s = {[(ρ.dx). (Wt)] [(I _mp / N ² ). x / H)] ^2} from the zero integral of _{H P s = [ρ / (} Wt)]. [I mp / (N 2 .H)] ^2. When the integral from 0 [x ² .dx] to _{H, P s = [ρ /} (Wt)]. [I mp / (N 2 .H)] 2. (H 3/3) = (1/3) . [(ρ.H) / (Wt )]. If ^{_{(I mp / N 2) 2}} , P l = 2 (N-1) .P s, P l = [2 (N-1) / 3]. [(? H) / (Wt)] (I _mp / N ² ) ^2; And, if H = L / N, since the _{P l = [2 (N-} 1) / 3]. [(Ρ.L) / (NWt)]. (I mp / N 2) 2, P l = [ 2 (N-1) / (3.N ⁵ )]. [(? L) / (Wt)] I _mp ² . The total lateral M2 jumper power dissipation factor (ratio) is given by k _j = P _l / P _mp .

Assuming a solar cell with approximate 22.5% average cell efficiency and P _mp = 5.50 Wp and assuming V _mp = 0.59 V, I _mp = 9.3 A, the M2 metal thickness requirements for aluminum and copper are as described And the maximum permissible total lateral M2 jumper power loss factor is assumed to be 0.01, 0.005, or 0.0025 (as a fraction of P _mp for the cell). Power Loss factor _{= k j = (P l /} P mp) and K _j (permitted by the maximum possible losses M2) = [2 (N-1 ) / (3.N 5)]. [(Ρ.L) / ( Wt)] (I _mp ² / P _mp ).

Therefore, the lateral width W jumper M2 and / or M2 metal thickness t necessary based on the allowable k _j is Wt = [2 (N-1 ) / (3.N 5)]. (Ρ.L). (I mp ² / P _mp ) / k _j where k _j is the maximum allowable total lateral M2 jumper ohm loss as a fraction of P _mp .

Tables 2 through 7 show the lateral M2 jumper Wt and W values calculated for copper with bulk resistivity p = 2.82 mu O.cm (Tables 2 through 4) and bulk resistance p1.68 mu O.cm, where N The value is 3 to 5 and L = 156 mm.

Calculated from aluminum M2 metallization Wt value (cm ² )

Aluminum M2 metallization and t = 3 [mu] m Al W value (cm)

Aluminum M2 metallization and t = 5 [mu] m Al W value (cm)

Copper M2 metallized Wt value (cm ² )

W value (cm) calculated by copper M2 metallization and t = 3 mu m Cu

Copper M2 metallization and W value (cm) calculated with t = 5 mu m Cu

Based on the calculation of the above example, we can conclude that for the ohmic loss of the transverse M2 jumper between adjacent island columns:

- Actual and optimal M2 design with sufficient transverse M2 jumper width does not need to solder outer copper ribbon taps on transverse M2 jumper between island columns and limits overall lateral M2 jumper ohm power loss to less than about 1% Lt; / RTI &gt;

For a given M2 metal thickness, the total lateral M2 jumper ohm power loss is reduced for high N values and / or low resistance metals;

- for aluminum or copper M2 metallization within the island cell design of N = 4, the M2 jumper width is limited to less than 1 cm for M2 metal thickness of 3 or 5 占 퐉 (or any width within this range) The total lateral M2 jumper power loss is maintained below about 0.50% relative ohm loss, which corresponds to an absolute cell efficiency loss of about 0.1% due to the M2 jumper;

The ability to limit the maximum lateral M2 jumper ohm loss to less than 1% by using an M2 metal (aluminum or copper) thickness of 5 μm or less or 3 μm or less and using a side jumper width of less than 1 cm is a high performance, M2 metallization, and there is no need to solder the copper ribbon tabs on the lateral M2 jumpers. Therefore, it is possible to manufacture a low cost, reliable island cell, and an excessively large N value is not required. That is, N = 4 is sufficient (N x N = 4 x 4 Icel design) and in some instances N = 5 is more advantageous because it provides low losses.

As described above, the islands (designed in any shape) can be electrically connected in any serial, all parallel, or hybrid serial parallel M2 connection design. The M2 interconnect pattern maintains the advantage of a substantially reduced RI ² ohm loss in the cell, module, and system due to current reduction and voltage increase in the master cell.

The following exemplary embodiments are provided to illustrate high battery efficiency (e. G., About 22% cell efficiency) connection design for a vaporized aluminum M2 pattern wherein the layer thickness is less than about 5 microns, Similar square substrate formats are comparable. Specifically, the design to describe a master cell with a 4 x 4 array of monolithic trench isolated islands has a hybrid parallel-to-island island design and has all the series island-connected designs, the master cell voltage is similar to about 5V The current is similar to approximately 1A.

Although the island design is generally described as a square shape, it should be noted that the island may be formed in any shape with the disclosed object. In most instances, it is desirable to design and pattern the array of islands symmetrically to eliminate area-related current mismatch between series connected islands, i. E. To maintain the same area between sub-groups or islands of islands connected in parallel.

In addition, the M2 interconnect design disclosed herein provides a relatively optimal range of current voltage parameters to integrate low cost, embedded, high performance distributed MPPT power optimizer and / or shade management electronics components, It is assumed that the maximum power voltage V _mp is in the range of about 5 V to 10 V and the master cell maximum power current I _mp is in the range of about 0.5 A to 1 A.

In addition, the M2 interconnect provided herein may support a variety of installed PV arrays, such as, for example, 600 VDC and 1,000 VDC PV systems, for maximum system level efficiency, for example, in residual and commercial roofs and also in ground mount utility scale applications .

The following variable assumption is:. Is provided for a master cell or an Icel cell with an efficiency of about 22% with a 4 x 4 array of islands connected in parallel (all referred to herein in parallel). Battery Power 5.35 W _p (Full square 156 mm x 156 mm master cell); V _oc = 685 mV, and V _mp = 575 mV, then V _mp / V _oc = 0.84 or 84%; I _oc = 9.90 A, and I _mp = 9.30 A, then V _mp / V _oc = 0.94 or 94%; Fill factor = (V _mp x I _mp / V _oc x I _oc ) = 0.79 or 79%.

In a design for all series-connected 4 x 4 master cells (complete square 156 mm x 156 mm master cell) designs referred to herein as 1 x 16 S (1 x 16 series), an example thereof is shown in FIG. 18 a and can assume the following: V _oc = 685 mV x 16 = 10.96 V and I _oc = 9.90 A / 16 = 0.619 A; V _mp = 575 mV x 16 = 9.20 V, and I _mp = 9.30 A / 16 = 0.581 A. Also, for a 60-cell module using a 1x16 all-serial-connected master cell design, the module variables can be assumed as: Module V _oc = 10.96 V x 60 = 657.6 V And module V _mp = 9.20 V x 60 = 552.0 V; And I _oc = 0.619 A, and I _mp = 0.581A.

A hybrid parallel-serial (HPS) 4 x 4 master cell (assuming a full square 156 mm x 156 mm master cell) containing eight pairs of islands is referred to as a 2x8HPS (2x8 hybrid parallel-serial) design, 18B, and can be assumed as follows: V_oc  = 685 mV x 8 = 5.48 V and I_oc = 9.90 A / 8 = 1.238 A; V_mp = 575 mV x 8 = 4.60 V, and I_mp= 9.30 A / 8 = 1.163 A. Also, for a 60 battery module using a 2x8 hybrid master cell design, the module variable can be assumed to be: Module V_oc = 5.48 V x 60 = 328.8 V, and module V_mp = 4.60 V x 60 = 276.0 V; And I_oc = 1.238 A, and I_mp = 1.163 A.

Figures 18a, 18b, and 18c illustrate a hybrid serial-to-serial (2x8) design, referred to as a 2x8 HPS design (Figure 18b), all serial (1x16) master cell structures (4x4 arrays of islands) Serial (8x8) master cell or an Icel structure (island 8 x 8 array), referred to herein as an 8x8 HPS design (Fig. 18c), and a master cell or an Icel structure A square master cell or an icel.

18A, all the serial master cells or the Icel structure (1x16S) 320 are connected to the serial connection islands I ₁₁ to I ₄₄ ), Each island in the column being electrically connected by an M2 series connection 328, and each column being electrically connected in series by a lateral M2 jumper 326.

18B, the hybrid parallel-serial master cell structure 2x8HPS 340 is connected to the base of the island buses 341 to 344 of the islands I ₁₁ to I ₄₄ connected in series and in parallel from the emitter bus bar 342 to the base bus bar 344. [ x 4 arrays, adjacent islands in the column are connected in parallel by an M2 parallel connection 350, and each island in the column is electrically connected by an M2 serial connection 348 and adjacent islands connected in parallel are connected in a lateral direction M2 And are connected in series by a jumper 346. In some applications, the 2x8HPS design of Figure 18B may be particularly suitable for a master cell having a thin film silicon absorbing layer (e.g., having a thickness in the range of about a few microns to 100 microns).

As shown in Figure 18c, a hybrid parallel-in serial master cell structure 8x8HPS (352) is the island (I ₁₁ to I ₈₈₎ connected from the emitter bus bar 354 in electrical series and parallel to the base busbar 356 Adjacent islands in the column are connected in parallel by an M2 parallel connection, islands in a column are electrically connected by an M2 serial connection, and adjacent islands connected in parallel are electrically connected in series by a lateral M2 jumper 358 Lt; / RTI &gt; In some applications, the 8x8 HPS design of Figure 18c may be particularly suitable for a master cell having a rather thick silicon absorber layer (e.g., having a silicon thickness in the range of about 50 to 150 microns). This is due to the fact that the 8x8HPS design provides a high degree of flexibility / bend and may be suitable for a wide range of silicon thicknesses (although it accommodates thick silicon for flexible solar cells without cracks). The 2x8HPS solar cell of Figure 18b and the 8x8 HP solar cell of Figure 18c provide the same current and voltage scale factor 8.

Figures 19a, 19b, and 19c illustrate examples of relatively small shade management bypass switches (e.g., pn junction diodes or Schottky barrier diodes) on the M2 interconnect design of the master cell shown in Figures 18a, 18b, Layout / position.

19A, all of the series master cell structures 1x16S (360) have a 4 x 4 array of electrically serially connected islands I ₁₁ through I ₄₄ from the emitter bus bar 362 to the base bus bar 364 And each island in the column is electrically connected by an M2 series connection 368 and each column is electrically connected in series by a lateral M2 jumper 366. The lateral M2 jumper 370 has been offset from the marginal edge of the master cell for connection and direct placement of the relatively small package bypass switch 376 to the emitter bus bar 362 and the base bus bar 364. [ Bus bar extension 374 connects emitter bus bar 362 and bus bar 364 to bypass switch 376.

19B, the hybrid parallel-to-serial master cell structure 2x8HPS 380 is connected to the base bus bar 384 of the islands I ₁₁ to I ₄₄ electrically connected in series and in parallel to the base bus bar 384 Adjacent islands in the column are connected in parallel by an M2 parallel connection 390 and each island in the column is electrically connected by an M2 serial connection 388 and adjacent islands connected in parallel are connected in a lateral Direction M2 jumper 386. In this case, The bypass switch 392 is located and directly connected between the emitter bus bar 382 and the base bus bar 384.

19C, a hybrid parallel-to-serial master cell structure 8x8HPS 394 is connected between the emitter bus bar 395 and the base bus bar 396 in electrical series and in parallel with the islands I ₁₁ to I ₈₈ The adjacent islands in the column are connected in parallel by M2 parallel connection, the islands in the column are electrically connected by M2 serial connection, and the combined parallel connected adjacent islands are electrically coupled by the lateral M2 jumper 397 Respectively. The bypass 398 is located and directly connected between the emitter bus bar 395 and the base bus bar 396.

In fact, single crystal semiconductor wafers (especially CZ and FZ monocrystalline silicon wafers) are often made from crystal ingots and often in circular form. In order to maximize semiconductor material usage and minimize waste, the master cell may be formed of a pseudo-square solar cell as shown in Fig. 20 is a schematic top view of a quasi-square master cell substrate made from a crystal ingot (shown by the perimeter of a cylindrical ingot).

Thus, in order to maintain symmetrical and sub-groups of islands or islands connected in series with the same size (same series connected island region), the islands in the pseudo-square master cell can be individually designed into various shapes and structures.

20 is a top view of a quasi-square master cell substrate 400 fabricated from a crystal ingot (shown by a cylindrical ingot periphery 402). The excluded corners 404 have been removed and / or eliminated from the quasi square master cell substrate design to minimize ingot waste while providing an almost (not perfect) square wafer with area a 'per corner and solar cell fabrication.

Actually, the quasi-square master cell substrate 400 has dimensions of 156 mm x 156 mm (L = 156 mm), diagonal dimensions 220 mm (D _square = 220 mm), and the final polishing ingot diameter (D _ingot = 200 mm). Assuming the dimensions described above, the complete square substrate has an area A _sq ) = L ² = 156 mm x 156 mm = 243.36 cm ² . A quasi-square substrate has an area (A _psq ) = A _sq - 4a ', wherein _{a' ≒ (D square - D} ingot) 2/4, then a '≒ (220 mm -200 mm ) 2/4 ≒ 1 cm 2 And A _psq ? 243.36 -4 x 1 cm ² = 239.36 cm &lt; ^{2 &} gt ;. Therefore, L = 156mm case of a standard wafer is similar to square in cell area of 239.36 cm ² compared to the cell area of 243.36 cm ² in a standard 156mm x 156mm square wafer, about 1.64% less (4 / 243.36).

21 is also from an emitter bus right, similar to the cell shown in 18b hybrid parallel with a 4 x 4 array of the base bus directly series connected and parallel connected to the island (I ₁₁ to I ₄₄₎ - serial similar square master cell structure 2x8HPS (The emitter bus bar, the base bus bar, and the lateral M2 jumper are not shown in FIG. 21). Similar to the quasi-square master cell shown in Fig. 20, the quasi-square master cell 420 has a side length L (for example, 156 mm of a 156 mm x 156 mm quadrangular icel) and a sewing corner 422).

The following dimensions are provided by way of example to balance the master cell current of the quasi square master cell structure 2x8HPS 420; As noted above, the islands design principles disclosed herein may be applied in a variety of cell shapes and dimensions. As shown, the master cell 420 is horizontally and vertically symmetric (forming eight pairs of islands connected in parallel) and the dimension representation is one quadrant (e.g., I ₁₁ , I ₂₁ , I ₁₂ , and I ₂₂ ). Each set of serially connected islands can be designed or sized to have the same area (corresponding equal voltage and current), i.e. the area is I ₁₁ + I ₁₂ = I ₂₁ + I ₂₂ .

L = about 156 mm, L ₁ and L ₂ are calculated as follows, to form a sufficient current balancing master battery: [(L / 4) .L 1 -a '+ (L / 4) .L 1 = 2. (L / 4) .L ₂ And L ₁ + L ₂ = L / 2. Thus, for L = 15.6 cm (or L / 4 = 3.9 cm) and a '= 1 cm ² , 3.9 L ₁ - 1 + 3.9 L ₁ = ₂ x 3.9 L ₂ and L ₁ + L ₂ = 15.6 / 2 . Thus, L ₁ - L ₂ = 0.1282 cm and L ₁ + L ₂ = 7.8 cm. L ₁ = 3.964 cm and L ₂ = 3.836 cm.

22 is a schematic view of an island (I _{11 &lt}; RTI ID = 0.0 &gt; (I _{11 &lt}; / RTI &gt; To I ₄₄ ) of a serial-like square master cell structure 1 x 16S (430) having a 4 x 4 array of cells. Similar to the pseudo-square master cell shown in Fig. 20, the quasi-square master cell 420 has a side length L (for example, 156 mm for a 156 mm-156 mm pseudo-square solar cell) And a sewing corner 422.

The following dimensions are provided as an example for sufficiently balancing the master cell current of a pseudo-square master cell structure 1 x 16S (430) with a side length L (156 mm) with successive isolation trenches defining each island, Guidelines are provided for area islands. In some instances, it may be desirable to provide continuous isolation trenches (trench isolation lines formed continuously with common crossing points) to maximize master cell flexibility and minimize cracking and propagation for simple processing during scribing. As shown in FIG. 22, all the trench isolation line intersections have a right angle other than the specific ones.

In the island design of FIG. 22, the islands (I ₁₂ , I ₂₂ , I ₃₂ , I ₄₂ , I ₁₃ , I ₂₃ , I ₃₃ , I ₄₃ ) in the second and third columns are rectangular, / ₄ ) .W ₂ . The islands in the first and fourth columns are non-rectangular: the islands _I21 , I ₃₁ , I ₂₄ , and I ₃₄ are trapezoidal in shape; Corner Island (I ₁₁ , I _41, I _14, and I ₄₄₎ is a polygon. The three vertical scribe lines (isolation trenches) and the central horizontal scribe lines (isolation trenches) are straight lines connecting the edges of the master cell. The two outer horizontal scribe lines - the upper and lower scribe lines - are vertical and horizontal between the two central columns (columns 2 and 3) It is inclined about angle?. Thus, the master cell 430 is horizontally and vertically symmetric (forming 16 connected cells with the same area and four symmetric quadrants). The dimensional representation is for one quadrant (e.g., I ₁₁ , I ₂₁ , I ₁₂ , and I ₂₂ ). Each set of serially connected islands is designed to have the same area (corresponding equivalent voltage and current), i.e. I ₁₁ = I ₂₂ = I ₂₁ = I ₂₂ .

For the master cell lateral dimension L (156 mm), the island dimensions of the master cell 430 can be calculated as follows: The area of the islands I ₁₂ (islands I ₂₂ , I ₃₂ , I ₄₂ , I ₁₃ , I ₂₃ , I ₃₃ , I ₄₃ ) have the same rectangular shape and area) as A _rectangle = W ₂ (L / 4); The area of island (I ₁₁ ) (the same polygonal shape and area as islands I ₄₁ , I ₁₄ , I ₄₄ ) = A _corner = W ₁ (L / 4) + [W ₁ ² / tan (?)] / 2-a '; ₂₁ I of the island area (island I _31, I _24, the same trapezoidal shape and area as _{I 34) = A trapezoid = W} 1 (L / 4) -. A ^{_{[W 1 2 / tan (θ}} )] / 2. A _rectangle = A _{corner ^{= A trapezoid = (L 2 -}} 4.a '.. / 16), thus _{W 2 (L / 4) =} W 1 (L / 4) + [W 1 2 / tan (θ)] / 2-a' = W ₁ (L / 4) - [W ₁ ² / tan (?)] / 2 = (L ² - 4.a '/ 16 = (15.6 cm x 15.6 cm -4.0 cm ² ) / 16 = 14.96 cm ^2. each island is an area of 14.96cm ^2.

Then, W ₂ (L / 4) = 14.96 cm ² , W ₂ .L = 59.84 cm ² , W ₂ = 59.84 / 15.6 cm, thus W ₂ = 3.836 cm. _{W 1. (L / 4)} + [W 1 2 / tan (θ)] / 2-a = 14.96 cm2, W1.L + 2 [W 1 2 / tan (θ)] = 63.84 cm 2, W 1. (L / 4) - [W ₁ ² / tan (?)] / 2 = 14.96 cm 2, and W ₁ .L 2 [W ₁ ² / tan (?)] = 59.84 cm ² . Therefore, 2W ₁ .L = 63.84 + 59.84 cm ² = 123.68 cm ² , W ₁ = 123.68 / (2 x 15.6) cm, thus W ₁ = 3.964 cm. 4 [W ₁ ² / tan (θ)] = 63.84 - 59.84 cm ² , 4 [3.964 ² / tan (?)] = 4.00 cm ² , tan (?) = 15.7133, and therefore? = 86.36?. L _T = L / 4 - W ₁ /tan(T))15.6/4 - 3.964 / 15.7133, L _T = 3.9 - 0.252 cm, thus L _T = 3.648 cm.

Thus, in an exemplary embodiment that provides dimensions and angles for current matching in a 1 x 16 S all-serial 4 x 4 quad-square substrate master cell of Fig. 22, each island area = 14.96 cm ² , a polygonal island (four corners) ₁₁ , I ₄₁ , I ₁₄ , and I ₄₄ ; A trapezoid island (4); Island _{I 21, I 31, I 24} , and I _34; Rectangular islands (8 central): I ₁₂ , I ₂₂ , I ₃₂ , I ₄₂ , I ₁₃ , I ₂₃ , I ₃₃ , I ₄₃ ; L / 4 = 39.00 mm; W ₂ = 38.36 mm ^; W ₁ = 39.64 mm ^; L _T = 36.48 mm; L _p = 41.52 mm; And [theta] = 86.36 [deg.].

PV  Within the module Monolithic  Island Master Battery Interconnect

The island master cells disclosed herein may be connected in an electrical serial, parallel, or hybrid parallel-to-serial array within a PV module. Such interconnections may be performed using the monolithic module embodiment described above (e.g., a plurality of Icelels are attached to a continuous backplane and an electrical connection between the Icelels is performed using a patterned M2 layer). The master cell interconnect design choices in the module (serial, hybrid parallel-serial or parallel) determine the master cell maximum power point (MPP) current and voltage (I _mp and V _mp ), the number of master cells in the module, Current and voltage. Often, standard crystal Si modules consist of 60 cells arranged in six columns, with 10 cells in each column (6x10), and other module structures, including 6 x 12 = 72 cells, Safety, BOS (e.g., wiring) cost, and the like.

One exemplary modular architecture embodiment (assuming N is at least 3) for a master cell interconnect in a module of a 6x10 (or better) master cell is a hybrid parallel-to-serial architecture. Depending on the specific application and market, the master cell interconnect can be optimized using a hybrid parallel-to-serial design to provide the desired maximum module MPP current or the desired maximum module MPP current. Although all parallel structures are possible, in some instances, all parallel structures generate significant module currents, resulting in significant ohmic losses. In addition, although all of the series structures are possible, in some instances all series structures can cause safety problems due to too high a module voltage (e.g., more than a few hundred volts) (module V _mp ) and / High wiring cost may be required.

Figures 23A and 23B emphasize the number of islands (odd or even number of islands) in the master cell or ice cell schematic and also the location of the emitter and base bus bars according to the M2 interconnect design. Master cell 452 in Fig. 23A and master cell 462 in Fig. 23B have an array of S = N x N islands (or N x N subgroups of parallel connected islands), and individual islands are not shown. In the master cell 452, N is an odd integer and N in the master cell 462 is an even integer. 23A, when N is an odd integer and the islands (or subgroups of parallel connection islands) are electrically connected in series, the master cell emitter and the base bus bar are connected to each other Two opposing quadrants, shown as emitter bus bar 454 and base bus bar 456, are positioned facing each other in a battery diagonal (see, for example, the master cell shown in Figs. 15A and 15B). In master cell 462, N is an even integer and the islands (or subgroups of parallel connected islands) are electrically connected in series, and the master cell emitter and base bus bar are connected to the emitter bus bar 464 and the base bus Are located at two opposing corners on the same side of the square cell as shown by bar 466 (see, for example, the master cell shown in Fig. 14A).

24-27 illustrate various 60 battery modules of a master cell design having even and odd serial connected islands (or sub-groups of parallel connected islands) as shown in Figure 23a (N is an odd number) and 23b It is a drawing of the connection design. 24-27 are top module views (showing the front side of the master cell) showing the base bus bar and the emitter bus bar for each master cell, although the bus bar is actually located on the rear side of the master cell. That is, the emitter and base bus bar and module interconnections show through the front side of the master cell to emphasize the connection design between the various cells. The exemplary modules respectively, through a patterned M1 layer after the solar cell rear machining a plurality of islands, each (e. G., In a 6 x 10 array shown in this embodiment, 60 ahyisel) for attaching to the continuous backplane sheet or laminate And then forming a patterned M2 layer on a large continuous backplane sheet containing a plurality of Icelels to fabricate the post backplane-laminated back-end solar cell remaining on the continuous multiple-cell backplane substrate, as a monolithic module. This approach will connect the Icelels to each other according to the desired electrical connection arrangement (all series connections or hybrid parallel-serial connections) using a monolithic patterned M2 metallization layer. This is because it is not necessary to form monolithic modules and to tablet, string and / or solder the solar cells to each other for module assembly (because patterned M2 connects the cells together based on the monolithic module embodiment) . Of course, such representative modules may be fabricated without the monolithic module embodiments described herein by conventional tableting, stringing, and / or soldering of solar cells to each other for module assembly.

24 is an example of a module connection design for a master cell or an icel (the module connection design is manufactured using a patterned M2 layer when using the monolithic module embodiment disclosed herein), emitter and base bus The bars are located at the diagonally opposite corners of the master cell (ie, N is an odd number) and all Icel cells are electrically connected in series (all in series). For the 60 serial master cells connected in series as shown in Fig. 24 Module voltage and current can be calculated as follows: Module voltage = 60 x Master cell voltage. Therefore, for N = 4 and S = 16: the master cell voltage V _mp ? 16x0.59? 9.4 V; Module V _mp = 60x9.4 = 564 V; And module I _mp ? 9.3 A / 16? 0.58 A.

25 is an example of a module connection design for a master cell (the module connection design is fabricated using the patterned M2 layer when using the monolithic module embodiment disclosed herein), the emitter and base bus bar Are located at the corners of the same side of the master cell (i.e., N is even) and all cells are electrically connected in series (all in series). For N = 4 and S = 16, the module voltage and current can be calculated as shown in FIG.

Figure 26 is an example of a module connection design for a master cell (the module connection design is fabricated using a patterned M2 layer when using the monolithic module embodiment described herein), emitter and base bus bars Located at the same corner of the master cell (i. E., N is an even number) and all batteries are connected in an electrical hybrid parallel-to-serial fashion. In this embodiment, each master cell is connected in series in one row of 10 master cells and six rows of 10 master cells are connected in parallel. In the hybrid parallel-serial module connection shown in Fig. 26: module voltage = 10 x master cell voltage. Therefore, for N = 4 and S = 16: the master cell voltage V _mp ≒ 16 x 0.59 ≒ 9.4 V and the module voltage V _mp = 10 x 9.4 = 94 V.

Figure 27 is an example of a module connection design for a master cell (the module connection design is fabricated using a patterned M2 layer when using the monolithic module embodiment described herein), the emitter and base bus bar Located at the same corner of the master cell (i. E., N is an even number) and all batteries are connected in an electrical hybrid parallel-to-serial fashion. In this embodiment, each master cell is connected in series in one row of six master cells, and ten rows of six master cells are connected in parallel. In the hybrid parallel-to-serial module connection shown in FIG. 27: module voltage = 6x master cell voltage. Therefore, for N = 4 and S = 16: the master cell voltage V _mp ? 16x0.59? 9.4 V; Module voltage V _mp = 6x9.4 = 56.4 V; And module current I _mp ? (9.3 A / 16) x 10? 5.81 A.

In some instances, the monolithic island structure disclosed herein may incorporate embedded module-level or battery-level DC-to-DC (or DC-to-AC) power optimizations, which may be applied to the master cell backplane Can be directly mounted or embedded within the module stack. The MPPT power optimizer may be a monolithic or hybrid chip with high conversion efficiency (e.g., greater than 97% efficiency) (including at least some individual components, including at least inductors and capacitors) Switch to DC or AC output at a specific voltage or constant current (range). For example, a battery level MPPT power optimizer chip can be used to fabricate an AC cell while performing the maximum power point tracking (MPPT) by converting the master slave DC voltage and current (V _{mp and} I _mp ) to AC voltage and current .

When all the master cells in the module are connected in series, the battery level embedded MPPT can be set to produce a predetermined fixed output current in each master cell under all illumination conditions while performing the MPPT power optimization function. This can ensure that all the master cells connected in series are current-matched. Likewise, when the master cell in the module is connected in a hybrid parallel-to-serial arrangement, the battery-level embedded MPPT performs the MPPT power optimization function (under certain lighting conditions) To produce a predetermined fixed output current in each master cell. This can ensure that all the series connected master cells or the icel are current matched and the parallel string is voltage matched.

28A and 28B are diagrams showing some representative examples of module connection embodiments of a 600 VDC PV system. Figure 28a shows the 1x16S (both series) module design (battery module 60), and V _oc = 657.6 V and V _mp = 552.0 V, Figure 28b shows a module connection embodiment of a 2x8 HPS (hybrid parallel-serial) design (60-battery module), V _oc = 657.6 V and V _mp = 552.0 V. Figures 29a and 29b are schematic diagrams showing module connections for a 1000 VDC PV system. 29A shows a module connection of a 1x16S (all serial) design (60 battery module), V _oc = 657.6 V and V _mp = 552.0 V, Figure 28b shows the module connections for a 2x8 HPS (hybrid parallel-serial) design (60 battery module), V _oc = 986.4 V and V _mp = 828.0 V. Therefore, V _os and V _mp are increased in the 2 × 8 HPS design for a 600 VDV PV system or in a 2 × 8 HP design for a 1000 VDV PV system compared to a 1 × 16 SV design for a 600 or 1000 VDV PV system.

Thus, in some specific embodiments, a 2x8 hybrid parallel-to-serial (2x8HPS) connection design can be selected for the following advantages:

A quasi-square crystalline silicon wafer can be used to fabricate the icel while maintaining the significant advantages of all series master cells (e.g., an M2 metal layer with a thickness of less than about 5 [micro] m and a straight, anisotropic trench isolation scribe Master cell flexibility due to line);

- current matching / balance of quasi-square crystalline silicon wafers achieved using L ₁ = 3.964 cm and L ₂ = 3.836 cm shown (for a 156 mm x 156 mm wafer), for example;

- Also, for example, it is comparable to a complete square master cell substrate with L ₁ = L ₂ = 3.9 cm;

- Provide an efficient PV system array for 600 VDC and 1,000 VDC systems (and other system voltages) with reduced BOS cost and high system efficiency. In some instances, a 1000 VDC PV system can have a higher system efficiency and lower BOS cost than a 600 VDC system (due to high efficiency and low BOS cost, the installed PV for a high string voltage (1,000 VDC vs. 600 VDC) The system can provide an economical value of about $ 0.10 / W). If desired, the module voltage can be set by the interconnection of the cells in the module according to the hybrid parallel-serial architecture (e.g., reduced compared to all serial module arrays);

- Integration of low cost distribution shade management (similar to 1x16S design);

- Integrated low cost remote module ON / OFF (similar to 1x16S design);

- low cost distribution battery level MPPT integration (similar to 1x16S design); And

- Compared to the 1x16S design, it can be considered that the durability of the master battery variable is larger.

Advantages of the innovative features disclosed herein include (i) reduced solar cell fabrication process equipment and equipment capital expenditures (CAPEX); (ii) substantially reduced hazardous waste by-products in solar cell fabrication; (iii) reduce solar cell microcracks and / or breakage (for example, copper plating and its associated handling, sealing, and contact requirements are not required); And increased overall manufacturing yield; (iv) improved projected long-term PV module field reliability; but not limited to, warp reduction and mechanical stress reduction for backplane laminated solar cells because thick (typically tens of microns for IBC solar cells) copper electrodeposited on the back side of (v) is not needed.

In operation, the disclosed subject provides a monolithic island master cell (Icel), which provides any combination of the following advantages; Improved flexibility and crack relaxation; Battery warpage reduced and planarity improvement; Reduced RI2 ohms loss by increasing voltage and current; The reduction in cell metallization thickness (also 10 times) can be copper plating removed as needed, which can reduce the cost of battery metallization (for example, Al of 5 탆 or less); Thick metallization, e. G., Removal of thick copper, reduces stress effects (and cracks) during module lamination; Battery parameters distributed in experiments and alignments; Reduced current allows the use of inexpensive shade management switches; Low cost, high efficiency (> 98%) MPPT DC-DC buck converter; And sufficient plating member solar cell formation.

The present application relates to a cost-effective, high-efficiency solar cell and related modules, their device structures and their manufacturing methods. Specifically, the disclosed subject matter includes a solar cell structure and a starting thickness of a wire-sawn, standard thickness crystalline silicon wafer (e.g., 125 mm x 125 mm or 156 mm x 156 mm, or a starting thickness in the range of about 120 to about 250 microns) (E.g., a flexible polymer backplane permanently attached to a thin film silicon cell absorber), which may be thinned. The monolithic fabrication process may be used to divide the semiconductor absorbent layer to increase the standard operating voltage of a standard monolithic silicon cell while reducing the solar cell current of a given solar cell power as described above.

The disclosed subject deals with the limitations of known methods for bulk wafers and thin film solar cell fabrication problems and provides meshed rear side contact (IBC) solar cells with a combination of low cost and high efficiency made using starting crystalline silicon wafers .

Intermediate grade minority carrier lifetime n-type wafers can be fabricated using, for example, Czochralski (CZ) ingot growth, continuous or quasi continuous CZ growth, or other methods of dealing with intrinsic n-type doping concentration gradients throughout the n- And have a starting minority carrier lifetime of at least about 100 microseconds. In addition, quasi- single crystal cast n-type silicon ingots or even polycrystalline silicon materials can be selected depending on material quality and other process integration requirements. Some of the following processes, for example, texturing (although both acidic and alkaline textures can be used for any type of starting crystalline silicon material), can be applied to monocrystalline materials, for example, Note that it is necessary to adjust suitably depending on the choice of starting material, such as for alkaline textures.

It should be noted that although the n-type (generally doped) starting crystalline wafers are provided according to the illustrative purpose, the basic concepts shown herein are for p-type silicon wafers and may be applied to p-type silicon wafers by those skilled in the art. It should also be noted that while the basic concept shown is applicable to bulk wire-sawn wafer-based absorber cells, it is also possible, for example, to use epitaxial or otherwise chemical vapor deposition film growth after using porous silicon on the reuse template as a separate layer system, Note that the absorber cell can be converted to an absorber cell that is produced using a kerfless technique, such as that leading to the next emission to reuse the next template. The structures and methods disclosed herein can be used in other so-called cementless wafer methods, such as peeling or laser splitting after high dose hydrogen ion (photon) implantation, or mechanical stress induced peeling of thin silicon substrate from thick reusable starting substrate Can be applied.

The various solar cell processing steps can be applied to wafers and can be applied to a variety of photovoltaic cell fabrication processes, including backside machining steps, including patterned base contact and emitter diffusion formation (formation of emitter and base contact regions) and patterned thin film first metal layer to be. This base contact and emitter diffusion can be formed by a selective or non-selective emitter structure, for example by driving the laser removal of the doped dielectric. This patterned region formed by locally removing the doped dielectric layer can also be created by applying an etching paste by printing such as scribing. In addition, patterned regions of different dopant levels or of different polarities may also be formed by the local application step of the dopant paste, followed by a thermal drive step. The combination of such patterning methods can also be easily deduced.

A low cost backplane (e.g., a low cost prepreg or polymer material) having an expansion coefficient (CTE) that is relatively matched to the solar cell absorber material (e.g., crystalline silicon) is then deposited on the back side of the processed wafer. The crystalline silicon wafer may then be thinned to a desired absorber thickness range (e.g., using a chemical wet etch or dry etch process) that maintains an optimal balance between value added optical absorption and minority carrier lifetime. Providing thin film silicon (e.g., 20-90 um thick) absorbers and providing these thin silicon absorber cells with the ability to handle and process them in high mechanical yield through automated or partially automated solar cell production lines, Cost, high efficiency solar cell, and the structures and processes described herein are very attractive for low cost, high volume production.

The silicon substrate attached to the backplane may also be separated by forming a trench isolation region using, for example, pulsed laser cutting and electrically isolating individual silicon islands or segments (islands, sub-cells or mini-cells) as described above So that a monolithic solar cell can be manufactured.

Fig. 30 shows such a battery structure. 30 is a cross-sectional view of a sub-cell 502 that is defined as I ₁₁ through I ₄₄ in a 4 x 4 array and is electrically isolated by trench 504 and includes adjacent monolithic backplane sheets 506 (e.g., , A pre-warped sheet that is a flexible material, or any suitable polymer sheet). The islands are physically divided and electrically divisible sub-cell active absorber units, which are referred to as islands or sub-cells, that is, a group of sub-cell islands monolithically integrated is a main / master with a common backplane used in all sub- Thereby forming a battery.

After further processing steps such as wet chemical texturing (eg, alkaline texture) and front passivation layer deposition (eg, using PECVD), access or via holes are drilled through the backplane to access the embedded battery end For example, using laser drilling). Using the patterned second layer metal structure M2 on the back side of the backplane, the divided sub-cells can be connected in parallel, in series, or in parallel, depending on various considerations, including the desired master cell And in series with each other. Thus, the monolithic master cell itself is maintained at an operating voltage that is maintained together by the backplane, for example, by a 156 mm x 156 mm square or similar square factor and which increases the standard voltage range that a typical silicon solar cell can produce, For example, it is possible to provide N times of 0.6-0.7 V.

At the same time, the current output of the same cell is divided by the same factor N (N is an integer). Using these high voltage and low current designs, the requirement for the total metal thickness of the solar cell is substantially reduced due to the generally reduced ohmic I ² R losses, and the savings in metallization costs can be realized. Therefore, a metal (e.g., copper) plating difficult for a solar cell metallization is not necessary.

In addition, such voltage increasing current reduction solar cells can be an improved economical new solution for module power collection and energy yield optimization. This is partly due to the fact that the operating current and voltage of the individual cells can be selected within the same range as the current and voltage which are cost-optimal for low-cost commercial switches.

In addition, savings in module metallization can be realized because the individual module output currents are reduced and the module output voltage is increased to reduce thickness and electrical sheet conductivity requirements for final cell metallization.

In the present disclosure, the fabrication method and the resulting structure are fabricated by deposition from a deposition and then from a reuse template (where they are not explicitly related to the use of bulk crystalline silicon wafers, which can be thinned to a suitable thickness (after backplane lamination) Or by delamination of a thin silicon layer from a reusable thick wafer after processing the reusable wafer by a suitable technique such as laser plating or MeV scale hydrogen ion implantation, or thick metal plating for strain induced induction) It can be extended to a structure. In the epitaxial deposition process, an active silicon absorber layer can be created from a layer of crystalline silicon (typically doped with phosphorus for n-type silicon) that is in-situ doped rather than from a starting bulk wafer, For example, a chemical vapor deposition (CVD) process, such as epitaxy, on a reusable mono or multi or quasi-monocrystalline template having a layered structure of porous silicon, and then, for example, To form a patterned base contact and emitter junction structure and a patterned first metal layer (e.g., by screen printing or PVD and laser ablation patterning of a suitable metal paste, such as an aluminum-containing paste) and then laminating on the backplane , The same island division (trench separation) cutting after peeling by the release process, the front texture , Passivating, and ends in the rear side via drilling and the patterned second metal layer.

In order to better understand the advantages of thin film silicon from a device point of view, in particular the rear contact / rear junction solar cell is considered as follows.

A substantial advantage of the thin film absorber layer is that it has a high solar cell open circuit voltage or Voc limit if it reduces the cell thickness. As described herein, a thinner absorbing layer can be obtained by the illustrated cell structure and process flow. 31 is a _{graph showing} a relationship between V _oc (See M. Green of UNSW "Limits on the Open-Circuit Voltage and Efficiency of Silicon Solar Cells Imposed by Intrinsic Auger Processes."). Agar recombination imposes limitations on the efficiency and V _oc of Si solar cells. The open circuit voltage or V _oc limit increases from about 750 mV at W _Si = 300 to about 800 mV at W _Si = 20 μm. The larger the L _eff / W _Si ratio, the greater the V _oc limit, and thus the thin film silicon absorber ultimately increases the efficiency (and decreases the temperature coefficient of power or efficiency).

The final performance limitations for silicon based absorbers need to look at the bulk carrier lifetime, surface recombination rate (SRV), and efficient minority carrier lifetime. Bulk recombination life has several contributors. 1 / t _b = 1 / t _radiative + 1 / t _Auger + 1 / t _defects . Silicon lifetime is dominated by defect (SRH) and interband recombination. In euger recombination, a small number of carriers (holes for n-type silicon) combine with electrons and transfer their energy to a third charge (holes in electrons or VB in CB, or lattice photons). Augusta recombination is about N in high-quality polycrystalline Si _d> 1x10 ¹⁷ cm ^- and controlled in the case of ³ the background doping concentration of the effective life (t _eff) is the bulk lifetime t _b, effective surface recombination velocity S _eff, silicon absorber thickness (W _Si ). Small S _eff To _{1 / t eff "1 / t} b + 2S eff / W Si when the _{(S eff <Dh / 4W,} D h is the hole diffusion also within Si), which is highly desirable when using the thin film Si solar cells.

In the case of a large S _eff , 1 / t _eff 1 / t _b + (p / W _Si ) 2. D _h . This is very undesirable because t _eff = 0.14 μs at W _Si = 40 μm, which is too slow to fabricate high efficiency solar cells. Therefore, a thin-film silicon absorber IBC solar cell is very important because it can achieve high-quality surface passivation at very low S _eff .

In some cases, high-efficiency, thin film silicon solar cell IBC design rule, the higher _{V oc (≥ 700 mV) and} J sc in order to obtain the ^{(≥ 40 mA / cm 2)} , thickness of the silicon absorber W _si The effective minority carrier diffusion length L _eff = √D _h . t _eff . To achieve a high open circuit voltage and short circuit current density, L _eff ≥ 15.W _si . Therefore, it is preferable that the Si absorber having a thickness of about 40 탆 is L _eff ≥ 600 탆, and the hole diffusivity of D _h 12 12 cm ² / s satisfies an effective minority carrier lifetime requirement t _eff ≥ 300 μs.

In addition, high efficiency thin film Si absorber solar cells often require high quality surface passivation (especially front passivation for IBC cells) and S _eff = 5 cm / s for front passivation in thin film silicon IBC solar cells.

32 is a graph showing the final cell absorber thickness requirement (y-axis) versus the effective minority carrier lifetime requirement (x-axis) of a silicon absorber for a high efficiency solar cell, showing the high performance requirements of V _oc and J _sc . High V _oc In the case of requirements (high J _sc There is a stringent demand for maximum allowable silicon thickness and / or minimum required minority carrier lifetime).

After the etching of the silicon thin film showing the thickness and the texture process is specific J _sc and V _oc (E.g., the effective minority carrier diffusion length in the absorber is at least about 6 times the absorber thickness to meet the high J _sc requirement, and the absorber thickness to meet the high V _oc requirement) About 15 times that of.

The starting material of the thin film semiconductor absorber solar cell structure may be a quasi-square or complete square, an n-type monocast (or quasi-mono or cast mono) silicon or an n-type CZ silicon wafer (e.g., a CZ growth monocrystalline ingot or cast crystalline (Produced by a wire saw from the brick), or, depending on the material quality, polycrystalline silicon or upgraded metallurgical grade silicon. CZ silicon can be selected to use, for example, continuous CZ (CCZ) or quasi-continuous CZ growth of a silicon ingot when used in a growth method capable of a narrow distribution of dopant concentration and resistance.

The wafer size may be at least 156 mm x 156 mm and the starting average wafer thickness may be in the range of 80 to 250 μm. Thinner and / or lower cost wafers may be used if manufacturing yields are not compensated for with reduced mechanical yield due to improved wafer breakage during and after battery fabrication. The wafer bulk minority carrier lifetime is at least 100 μs, in some instances hundreds of μs, and can be obtained using inexpensive n-type CZ wafers.

The solar cell manufacturing process begins with one side inline or batch immersion cutting damage removal (SDR), which is a wet etching process, followed by a selective chemical polishing step to smooth the rough surface.

This polishing step may be carried out either on one side or on both sides, for example using a cool or room temperature mixture containing hydrofluoric acid (HF) and nitric acid (HNO ₃ ), or using an alkaline etching process, for example a hot Potassium hydroxide, and this etching is followed by a metal removal etch with a combination of HCl, HF or HCl / HF followed by removal of the native oxide with HF-containing rinse solution leaving surface hydrophobic and hydrogen ends.

Depending on the selection of the starting wafer source, it may be advantageous to produce a backside surface field or backside surface doping layer at this early stage of the process flow where the overall sheet resistance of the base, which is generally governed by the wafer resistance and thickness, is reduced. However, standard CZ growth of an n-type ingot generally involves a large gradient dopant due to dopant separation, and the wafer resistance varies greatly across the ingot (from the seed end to the tail end), and additional doping It may be advantageous to have a narrow range of base sheet resistance. A number of different embodiments are provided herein to achieve such increased doped regions. New ingot fabrication methods, such as continuous or quasi continuous CZ growth, deal with and reduce the ingot doping gradient to mitigate or reduce the need for the additional doping within the solar cell base region.

Next, a combination of dielectric deposition steps, such as doped glass deposition, is performed by performing most of the solar cell backside machining and specifically using, for example, atmospheric pressure chemical vapor deposition (APCVD) and / or plasma enhanced chemical vapor deposition (PECVD) To form patterned emitter and base contact diffusions and then to patterned and thermally driven (e. G., In a tubular tube or in-line fashion) to remove damage, for example by pulsed nanosecond, picosecond or femtosecond laser removal Laser patterning with less damage, formation of emitter junctions (and doped base and emitter contact diffusion regions as needed), i. E., Generally, emitter and base contact regions.

The laser beam of this process may be uniform or may be Gaussian distributed or may have an intermediate intensity distribution shape for the spatial top hat profile for high uniformity. The backside dielectric deposition may consist of doped or undoped silicon oxide glass (e.g., borosilicate glass (BSG), phosphorous silicate glass (PSG), or undoped silicate glass (USG)), For example, aluminum oxide or silicon nitride, a doped or undoped aluminum oxide, or a combination of silicon nitride.

In addition, the patterned first metal layer may be applied to the rear side of the battery, for example, a metal consisting of an aluminum or aluminum-containing alloy (for example, a screen-printable paste containing an aluminum-silicon or an inkjet printing ink). The first metal layer may be particularly annealed if it consists of a screen, ink jet or other printed paste. It is also possible to apply a DC magnetron plasma sputtering and / or evaporation of physical vapor deposition (PVD), e.g., one or more metal materials (e.g., aluminum or aluminum-silicon alloy) , The PVD layer is patterned using, for example, pulse picosecond or nanosecond laser ablation of PVD metal on dielectric glass. This forms contact metallization on the solar cell. Emitter and base structures. Also patterned first level relatively thin metal layers (e.g., sheet resistances in the range of about 0.01 ohms / square to 0.5 ohms / square) are formed by bus bar-meshed rear contact (IBC) Metal (metal-1 or M1 metal layer) schemes and can be patterned. The M1 structure must be physically and electrically isolated from the lower silicon after the next backplane lamination or attachment by providing the following splitting possibilities.

For backplane lamination or attachment, a suitable prepreg or polymer material within a thickness range of a flexible thin film backplane (e.g., about 50 탆 to 200 탆)) may be laminated to the IBC M1 metal side. The backplane sheet can be substantially the same size and shape as the wafer (or slightly larger if battery edge protection is required). The backplane has a number of important functions, such as the fabrication of high-yield thin-film silicon cells and the transfer of silicon wafers on a single bonded backplane to a permanent support for supporting the division into a plurality of physically and electrically- Function. A solar cell design referred to herein as an &quot; Icel &quot; or &quot; island cell &quot; includes an embedded electronic device.

The silicon wafer carried by the backplane is wet (with hot KOH or TMAH, or a mixture containing HF and HNO ₃₎ or dry (plasma or reactive ion etching RIE) The optimum thickness of using the silicon etching step (for example, about Lt; RTI ID = 0.0 &gt; microns &lt; / RTI &gt; depending on the particular application for a solar cell obtained from about 80 microns). In addition, a polishing process, such as polishing or lapping, or chemical mechanical polishing (CMP), can be used to reduce the silicon thickness. Other methods may be used, such as laser splitting or thin silicon splitting / stripping after MeV range hydrogen ion implantation, and the discrete substrates may be reused to produce additional solar cells depending on the starting wafer thickness.

The Icel (island solar cell) structure is then formed through pulse ns or ps (or fs) laser removal, ultrasonic drilling, or mechanical sawing of the silicon wafer to form silicon isolation trenches, Supported by a common backplane). The cutting or scribing process may be adjusted such that the trenches proceed through the silicon to the backplane or the trenches terminate in the thin silicon layer and then are removed during the next final wet etch and / or wetty texturing process. It is possible to eliminate side wall damage by the process).

The remaining cell processing steps can then be performed, for example, including the above-described sun side texturing (enhanced light trapping) followed by post-texturing cleaning.

The following description and corresponding process flow trenches can be used with a backplane capable of withstanding extended thermal processing in a temperature range of up to about 300 ° C in various embodiments for making a selective front field at this point in a battery manufacturing process In essence, a "low temperature" process is used.

Subsequently, after the front side passivation and antireflective coating (ARC) layer deposition is performed (e.g., after PECVD, the bias is drilled into the backplane to access the buried M1 layer) Patterning solar cell metallization (second level metallization: metal-2 or M2) process. M2 deposition can be performed as a blanket process by a patterning process (e.g., PVD by in-situ shadow masking) or by patterning the next (e.g., with any suitable nickel or nickel- Using a blaky PVD of aluminum and the capping layer comprising any top cap of tin (Sn) or other solderable surface material, followed by a pulsed laser to pattern the M2 metal.

The embodiments and descriptions described herein use crystalline silicon and other crystalline semiconductor materials can also be used, such as gallium arsenide (GaAs) or, for example, silicon and GaAs (optionally germanium (Ge) A silicon-germanium (Si _{1 - x} Ge _x ) buffer layer between GaAs. In addition, while the example provided is a rear contact battery, the inventive concept disclosed herein can be extended and easily applied to other battery designs, such as non-IBC rear contact cells or front contact cells, Integration can be applied as a choice for technical simplification.

In the case of still other modifications and embodiments of the solar cell structure according to the disclosed subject matter, the exemplary embodiment is provided in the cross-sectional views of Figs. 5D and 5E.

The structure of Figures 5d and 5e is an interlaced rear-side contact / rear-side bonded crystalline semiconductor solar cell comprising a crystalline silicon layer (e.g., less than 100 占 퐉 thickness in the range of from several microns to about 100 microns) crystalline silicon layer, Etching may be used to selectively etch the backside of the thick CZ or monocast (quasi mono) silicon layer, or by using a polishing thickness reduction such as grinding or lapping (or using a wafer with a starting thin film of less than 130 [ The rear process is not required).

The thin film / etch on the back side of the silicon after backplane lamination (other than any silicon thickness reduction by the texturing process) may be unnecessary in some instances when a wafer with suitably high lifetime and / or a sufficiently reduced starting thickness is used . Such a structure can optionally complete frontal processing, including texturing and passivating at one point prior to lamination. This results in the formation of a doped front field (FSF) layer (using phosphorous diffusion or phosphorus ion implantation and thermal annealing activation or other techniques) with a relatively high thermal budget incompatible with the flexible polymer-containing backplane, There is a promising advantage that passivating high temperature processes can be performed prior to lamination. For example, a diffused front field may be used (from diffused phosphosilicate glass: PSG, POCl ₃ or phosphorus implanted as a precursor). When a backplane is used, the need for thicker metallization schemes and the need for a thicker metal (e.g., copper / nickel / silver) solar cells with a high voltage-low current solar cell structure, Tin) plating process and the associated technical risks, for example contamination of active silicon by copper. Further, if the plating process is omitted, the total solar cell manufacturing cost and CAPEX (capital expenditures) can be reduced. The backside passivation may comprise a stack of materials such as phosphosilicate glass on the borosilicate glass.

The solar side of a thin film silicon solar cell includes the following PECVD process for forming a light trapping texture and passivation and anti-reflection coating (ARC) layer (formed by wet etch texturing and / or dry laser or plasma texturing).

The rear contact / rear junction solar cells of Figures 5d and 5e comprise a semiconductor absorber layer having a first level metal (M1), which includes an interlocking rear contact (IBC) emitter and a base metal finger pattern, (Low-cost and high-conductivity) metal layer, such as aluminum or aluminum silicon alloy, which forms a free IBC finger pattern (fine pattern pitch). Without the bus bar on M1, efficiency loss due to bus bar induced electrical shading can be eliminated. Based on a two-level metallization scheme, M1 acts as a contact metallization layer (with fine pitch meshed bases and emitter metal fingers), while M2 has a high sheet conductivity Lt; / RTI &gt; layer.

The back side of the thin film silicon solar cell may be a flexible polymer laminate sheet, for example a prepreg sheet, which is a thin film backplane sheet of, for example, 50 and 200 microns and contains fibers. The backplane sheet is relatively thermally expanded (or CTE matched) to silicon at each of its thermal expansion coefficients (CTE) to mitigate cell damage during thermal processing.

The meshed rear-side contact / rear-side junction solar cell comprises a patterned second level metal (M2), having a thickness in the range of about 1 to 55 micrometers and, in some instances, a pitch (and fewer fingers) And may have a pattern that is substantially perpendicular to Ml. The patterned M2 is electrically connected to the patterned M1 through a predetermined M1-M2 conductive via plug formed in the backplane. M2 may be any conductive material or a stack of materials comprising materials such as aluminum, copper or aluminum with Al / Zn or NiV.

FIG. 5E provides a high-level cross-sectional view of the final solar cell structure for the rear contact / rear junction thin-film silicon solar cell by etching a thick starting silicon wafer, a passivation on the sun side textured surface and an antireflective coating (ARC) A semiconductor cell absorber, for example, a stack made of amorphous silicon (a-Si) and silicon nitride or one of aluminum oxide and silicon nitride as a thin film semiconductor (for example, 100 탆 crystalline silicon) A backplane, such as a laminated flexible polymer sheet such as a prepreg, an interlocked M1 pattern, such as a bus bar-member thin film aluminum metal finger on the back side of the battery; The patterned orthogonal second level metal shown for M2 using patterned metal comprising aluminum and / or copper, wherein the M2 PVD metal has a thickness less than about 10 microns and in some instances in the range of 1 to 5 microns And a second level metal.

Each subcell or island in a monolithic IC cell may comprise at least one series of minibus bars of polarity with adjacent subcells connected in parallel or in series. Emitter and Base Diffusion Area The IBC metallization pattern can also be arranged in a beneficial structure to minimize electrical shading below the minus bus bar.

Various process flow options are provided to illustrate the capabilities of the various types of processes and structures disclosed.

The starting material of the n-type crystalline silicon may be selected from monocrystalline silicon (Czochralski or CZ), monocast (also referred to as cast mono or quasi mono or seed cast mono) or cast polycrystalline silicon. The starting wafer size may be a full square (or a complete rectangle), a quasi-square (or similar rectangular) or other shape (e.g., a hexagon, other polygons, etc.), an area of at least 150 cm ² , 240 cm ² . The starting wafer thickness may be less than about 250 [mu] m and, optionally, at the thinnest thickness, the lowest starting wafer cost and high fabrication yields, and the breakage is negligible.

The patterned, diffused interlocking backside region is covered by a suitable low surface recombellable dielectric, comprising a patterned contact opening to underlying silicon, wherein the first metal (M1) solar cell contact metallization is formed directly on the silicon contact area And the metal in this region may be larger than the silicon contact opening. The first metal (M1) layer may be deposited by any suitable method, for example, by screen printing of a paste, inkjet printing of ink, aerosol jet printing of ink, or physical vapor deposition (plasma sputtering, thermal evaporation, electron beam evaporation, ion beam deposition, Deposition). &Lt; / RTI &gt; The PVD of M1 may require a patterning step such as selective laser removal of metal after deposition, unless the patterned M1 layer is deposited using an in-situ shadow mask during the PVD process.

The backplane may be a sheet or a plate and may be a flexible thin film polymer or composite epoxy resin having a fiber-containing (e.g., prepreg) sheet laminated to the rear side of the cell after patterned M1 termination. The backplane can also be applied by screen printing, spray coating or another deposition method.

The back side of the silicon etch (wafer thinning) can be performed, for example, by wet etching or dry etching (plasma or RIE) or using a suitable grinding or lapping process. Such wafer thinning is economically performed using hot concentrated KOH (or NaOH) at a concentration of KOH in excess of 15% (and 45% or less) at a temperature of 90 ° C. or higher (in some cases, 150 ° C. or less under process control) can do.

The second metal layer M2 on the backplane may be patterned by, for example, PVD (e.g., plasma sputtering and / or thermal evaporation, e-beam evaporation, thermal or arc injection) By laser ablation), or by PVD via screen printing or in situ shadow masks of a high conductivity paste containing aluminum and / or copper. In the latter, the pattern size and alignment requirements for M2 (due in part to a substantially orthogonal arrangement of M2 to M1 in some instances) are substantially less than those for M1.

The thin film silicon n-type base parasitic resistors are formed by selective doped front field (FSF) formed by laser activation of phosphorus, arsenic or antimony implanted on a laser doped or textured surface of phosphorus (or arsenic, antimony or indium) , or in injection or in the following annealing of the shadow (e.g., POCl ₃₎ can be reduced by the formation of a blanket buried layer adjacent the emitter by diffusion.

The following paragraphs provide various embodiments of the process flow, including general approaches, as well as embodiments of the individual flow system.

For clarity, the process flow provided may be divided into seven building blocks, each building block comprising two or more process tools and two or more production process units. 33 is a process flow diagram illustrating a high level solar cell building block.

As shown in Figure 33, the first building block includes a starting wafer inspection, selection and fabrication. The second block includes backside engineering depending on whether a doped backside field (BSF) is added during the process sequence. The third block is a first level metal (M1) formation (known as contact metallization). The fourth block is a stack of backplanes for attaching a permanent reinforced backplane. The fifth block includes cleaning the wafer after it has been divided into sub-cell units or islands, etched, textured, and textured to form a full monolithic Iicell structure. The sixth block includes front engineering including front passivation depending on the presence or absence of an inner front field (FSF). The seventh block consists of an access to the buried back side, a second level metal (M2) formation and an optional final anneal (which can be performed in-situ during the M2 PVD process).

Each of these building blocks includes various process flow embodiments, and various embodiments will be described. Different process path options or embodiments within each building block may be combined with different process path options or embodiments of the other building blocks. As there is a large number of possible combinations, the disclosed subject matter encompasses all the broad range of embodiments of all such embodiments, even though the example does not include all possible process flow combinations.

Expanding Block 1 in Figure 33, first initiates an optional test on the starting wafer and then performs any pre-cleaning followed by an alkaline chemical such as, for example, hot KOH or NaOH, or an acid chemical such as HF / HNO3 The material is used for top damage removal (SDR).

Such wafers are optionally subjected to chemical polishing etching on one side or both sides, for example, using a highly concentrated mixture of HF and HNO3, and cooled in some instances. Following this abrasive etch, a short KOH etch is performed to remove etch spots, such as porous silicon, from the surface. The wafer is then subjected to metal removal, for example using HCl or a mixture of HCl and HF (or ozonated HF), followed by hydrophobicization of the surface and removal of the native silicon dioxide (and dilute HF dipping treatment results End HF dipping in order to have a crystalline silicon surface hydrogen at the end.

Next, by expanding block 2 in FIG. 33, it is possible to increase the backside engineering or the improved backside base electrical sheet conductivity (to reduce the decisive influence on the parasitic base resistance and solar cell fill factor, depending on the presence or absence of the backside field ). The aggregate block of such a process consists of multiple process steps. Such a process may be initiated to improve any backside conductivity, designed to overcome the large resistivity width or variations in the ingot, in the starting wafer as a whole, and in the ingot. This resistive width is either a non-optimal (reduced) solar cell fill factor, or an insufficient fraction of the starting wafer, where the bulk resistance is a smaller value for high doping for insufficient minority carrier lifetime, Can occur in the case of high doping (or high background doping concentration) for carrier lifetime. However, with available ingot growth methods, such as adjacent CZ ingot growth techniques, it provides sufficient resistivity detail and width to avoid the need for backside conductivity enhancement. Exemplary flows using ingots and wafers with dense resistive detail are shown in Figures 34 to 34d. Where backside conductivity enhancement is desired, a number of exemplary embodiments are presented. The first embodiment is shown in the example flow of Figures 35a to 35d and provides the introduction of an n-type dopant such as phosphorus, which is doped with a POCl3 thermal furnace with a thermal driving step and doped glass Silicate glass or PSG). The second embodiment is shown in the example flow of Figures 36A-36D and provides an ion implantation step of an n-type dopant species such as phosphorous (P), arsenic (As), antimony (Sb) or (In). This implant (e.g., phosphorous implant) is then thermally annealed as part of the furnace anneal step described below and has a number of purposes.

For another embodiment after the cutting damage removal step (block 1 step) or after the backside electrical sheet conductivity improving step, atmospheric pressure chemical vapor deposition (referred to as APCVD) or PECVD of the first layer of boron doped glass is performed. The BSG layer may have a relatively low boron concentration and may have a relatively high sheet resistance throughout the cell and may optionally form a lightly doped emitter followed by a pulse picosecond (ps) or femtosecond (fs) laser or It can be patterned using a laser capable of removing the BSG dielectric so that there is little damage to the underlying silicon. If the BSG is removed during laser ablation, a high boron doped emitter (used for the low resistance emitter contact region) will be formed in another process. The second layer of BSG then has a relatively high concentration of boron and is deposited by APCVD (or PECVD), and can function as a precursor of selective emitter contact.

Subsequently, an additional patterning step using a pulsed picosecond or femtosecond laser can be used to remove the BSG in the region where the n + doped base contact region is to be formed. A layer of phosphosilicate glass (PSG) may be deposited (by APCVD or PECVD) to serve as a precursor for the doped base contact region (with n + doping for low base contact resistance).

The developing solar cell structure then performs the high temperature annealing and drives the patterned n-type and p-type diffusion regions to the rear side of the structure. Such annealing may be carried out in a stepwise mixture of inert and / or oxidizing atmospheres or inert and oxidizing atmospheres at a temperature above 800 ° C, specifically between 850 ° C and 1100 ° C. For example, additional steps such as gettering at a temperature of about 550 ° C to 650 ° C or gas anneal formation typically performed at 400 ° C to 500 ° C (eg, 450 ° C) may be integrated into the annealing step have. When the backside is previously filled with dopant, for example implanted with phosphorus and arsenic, this thermal annealing step serves to anneal, activate and diffuse the implanted region.

However, the fast heating and cooling rates can be tailored to capture precipitates from the wafer material, and it may be advantageous to push and pull the furnace at relatively high temperatures to improve process throughput. The example pushing temperature is chosen such that the boat is pushed and tilted above 600 ° C, in some instances 800 ° C to 850 ° C. The step of pushing and pushing the boat of the furnace at such a high temperature can be carried out in lieu of or together with the low temperature gettering and FGA shown in the examples of most flow embodiments.

Subsequent to annealing, a laser, e. G., A pulse picosecond or Femto second laser, is used to open contact with each emitter and base contact area for the next M1 contact metallization process. Optionally, additional annealing, for example in an inert non-oxidizing atmosphere, may be performed to reduce potential damage from the laser contact opening step.

The above-described removal process for locally removing a dielectric such as doped glass using a laser to produce the desired pattern can be accomplished using a suitable etchant paste. For this unit process of etchant paste, the etching paste is applied locally, for example, using screen printing. Depending on the nature of the etchant paste (eg, with or without hydrofluoric acid), the etchant mechanism may require thermal activity (for pastes that are not based on hydrofluoric acid). Such activation may be accomplished, for example, in a belt or roller furnace, and may be part of the etch dimension and depth adjustment. Following etching, the etch paste may be removed, for example, by a cleaning and cleaning step using a photo-alkaline solution followed by any metal removal step, such as DI water wash and short HCl containing wet scrubbing.

The rear contact structures engaged by local diffusion with different concentrations and opposite polarities can be formed using a dopant paste applied using screen printing by the following thermal drive. This replaces the deposition of a dielectric dopant precursor such as doped glass and the following patterning. The combination of the processes is easily derivable.

Block 3 of Figure 33 includes first level metallization (M1 or solar cell contact metallization) formation. For M1, two clearly different path embodiments or process embodiments are provided. First, the patterned first level metal M1 is applied in one printing step, or optionally in two or more coats, in the form of a paste or ink in the form of a screen, stencil, inkjet or print, followed by an optional drying step , Followed by a primary curing process followed by a resistance reduction sintering step after multiple curing processes in a curing tool, such as a tube or in-line, to first release or burn the binder from the paste. Suitable pastes may be made of aluminum, an alloy of aluminum and silicon and / or germanium, as well as nickel, silver or other conductive material. An example of the process of printing the M1 layer is shown in Figs. 34A to 36D and Figs. 38A to 41B. The first level metal may also be deposited in a blanket manner using, for example, PVD (e.g. DC magnetron plasma sputtering), for example aluminum, an alloy of aluminum and silicon and / or germanium, or nickel or nickel vanadium (NiV) Can be deposited. After PVD deposition, the blanket metal layer is patterned using, for example, pulsed nanoseconds, picoseconds, or femtosecond lasers to remove metal between the ends or other undesirable portions. An example of such a process flow is shown in Fig. The combination of printing and PVD is feasible and it is also feasible to add conductive dots such as paste or ink dots in areas where additional thicknesses and / or alternating metals are required.

Embodiments of the second and third process blocks are also provided below. For example, the selective emitter designs described above (including less heavily doped dominant field emitters and heavily doped emitter contact regions) use dual-layer BSG deposition and have a pulse picosecond or femtosecond laser patterning step Generates a lightly doped emitter region using a single BSG layer and performs a selective pulse nanosecond laser drive and alloy step on the highly doped portion of the emitter (using p ++ doping from the M1 aluminum layer next) , Which serves as an emitter contact. For this process, the first BSG patterning and the second BSG deposition process are omitted. Instead, a first level metal (in this case aluminum or an alloy of aluminum and silicon and / or germanium underneath silicon) is driven (serving as p-type heavy emitter contact doping), deposited using a pulsed nanosecond laser, The surface of the layer, for example Al, is dissolved and a eutectic Al-Si melt is formed and an alloy is formed with the lower silicon. The deposited M1, for example Al, may be deposited using PVD and patterned with laser ablation, or may be formed using a screen printing or inkjet printing (or another printing) process using a frit member aluminum containing paste. In the case of PVD with the following laser ablation, it can be patterned with the same tool or the same steps as the laser emitter contact alloy using pulsed laser ablation, i. E. The same two, two different laser processes.

Also for the laser-based contact opening of the emitter and base regions for the next M1 metallization after the second process block, a suitable M1 paste with frit or other etch components can be used, And can contact the emitter and base region without the need for dielectric removal of the laser-based contact region. The M1 paste-containing frit can be divided into dual printing pastes having different pastes for different polar regions (emitter and base) and can be thermally annealed in two or simultaneous or different stages depending on the optimal annealing conditions of high quality ohmic contact And can maintain reasonably low contact recombination for the two polarities.

After the above described back-end engineering and first level metal (M1 or contact metallization) formation, the wafer is stacked on the back side of the structured wafer with a backplane, for example a flexible backplane, which is the fourth process block in block 4 of Figure 33 Is ready for. Although the backplane is made of a variety of materials, it may be desirable for the backplane to meet a number of requirements, depending on the method of making the solar cell and the application of the battery obtained, such requirements being as follows: 1) the backplane is matched to the bottom patterned silicon stack Have a similar thermal expansion coefficient; 2) the backplane may have flexibility; 3) The backplane may be chemically resistant to subsequent wet and dry processing steps such as silicon etching and texturing (unless all wet processing is performed prior to the laminating process); 4) The backplane should be able to withstand the thermal budget of passivation dielectric annealing, and sufficiently high temperature processing (eg up to 300 or even 400 ° C or less) is allowed. The laminating process may be a vacuum deposition process to avoid bubble formation at the interface between the backplane sheet and the silicon layer with the structured M1-metallized rear side. Sufficient pressure (10-400 psi, or in some cases 50-250 psi) is applied during lamination, and flow is possible to planarize the cell structure in which the resin is laminated from the prepreg laminate. The size of the prepreg may be selected to a size that closely matches the cell for lamination, although a slightly larger or smaller size may be advantageous for subsequent fabrication. The backplane sheet may have a thickness ranging from about 50 microns to about 250 microns. After lamination, any edge adjustment can be performed, for example, using a pulsed nanosecond laser.

The fifth step of Fig. 33, the fifth step, is a step of forming the wafer into any sub-cell (island) to form an icel (or island master cell), for example a wet or dry chemical etching or silicon thinning using a polishing method, And cleaning after texturing and texturing. After the lamination is completed, the wafer rear structure is laminated on the backplane and the backplane itself protects the buried rear structure from the following process. The wafer can then be: 1) thinned to use a wafer with a short lifetime to fabricate a highly efficient rear contact solar cell with a thinning absorber, and 2) the absorber material is electrically isolated (via trench isolation) Separated into individual integrated sub-cells (islands) and later electrically connected in series or parallel or in series and parallel combination; 3) For example, a textured surface is formed on the front surface to form a random pyramid structure, and then the textured surface is cleaned, followed by a PECVD passivation process.

Various different embodiments are possible for the array of developed cells on the backplane to be thinned, divided and textured. The cross-sectional views of Figs. 37A and 37B show different process sequences during and after the sequence as well as the structure. FIG. 37A is a cross-sectional view of a process including wafer separation after wafer thinning (e.g., using laser trench formation), FIG. 37B is a cross-sectional view of a process including wafer thinning and after wafer thinning and texturing Sectional view of a process including partial wafer separation.

In one embodiment, the segment / islands are first formed to have a pulsed laser separation trench either fully through the complete absorber layer or partially through the absorber layer (e.g., with a suitable trench depth, the next absorber layer is trench- And trench depth that is removed / thinned by etch and etch texturing sufficient to effectively form sub-cells / islands). In yet another embodiment, the absorber layer (e.g., a silicon wafer) may first be thinned to a final thickness (and silicon to be textured later), and then split so that the remaining thinned absorber layer passes thoroughly or nearly completely, The texturing process is sufficient to separate the individual subcells or islands. The third embodiment uses a combination between the two sequences, and after the most thinning etching is performed in the first step, etching and sun side texturing are performed, followed by complete or almost complete trench-separated partitioning.

In the fourth embodiment, the separation cutting is performed after the thinning and the texturing are finished. This embodiment may include two additional options. In one option, after the split cut, the wafer surface is immediately faceted. This has the advantage of reducing the overall number of wet processing steps. Another option is to perform some cleaning steps to remove debris and potential damage from the laser stage. Such a cleaning step may be briefly immersed in an alkaline agent such as a texturing agent, followed by appropriate cleaning after texturing, or mild debris removal such as megasonic cleaning.

The trench isolation splitting process itself is relatively complete with the backplane material to maintain the structural integrity of the cell, and the battery sandwich has a 156 mm x 156 mm square with a respective automated instrument capable of handling this standard size, Can be fabricated using a battery form factor.

In the case of the prepreg backplane and silicon absorber, the absorbency of the prepreg is poor (i.e., transmitted and / or reflected by the prepreg with low absorbency) - it has the concept of maintaining other backplane / absorber material combinations, It may be desirable to cut the absorber with a laser source using a laser wavelength with excellent absorbency within the laser source. Many prepregs do not strongly absorb at the infrared (IR) wavelength to improve the relative selectivity of the silicon cut for prepreg cutting by cutting by IR. Cutting or scribing using IR lasers is also relatively inexpensive because the capex (capital expenditure) and maintenance costs of IR lasers (e.g., pulsed nanosecond lasers) are generally inexpensive for UV lasers. However, the cutting quality of a UV laser tends to be superior to the cutting of an IR laser, and the degree of damage zone affected by heat near the cutting is smaller than in a UV laser. In each case, such a factor must be weighed to select the optimal laser source for the trench isolation process.

Further, the isolation trench may be formed using a water jet guide laser, for example, a water jet guide green or an IR laser. A water jet guide laser cut has a selective advantage of a low wavelength laser because it exhibits a cutting area with low damage while maintaining absorption. Other methods of splitting to create an ion cell solar structure with a monolithic backplane include focused laser beams embedded for splitting where the focus can be placed within a material and temperature gradient and consequently induced by internal vapor pressure Lt; / RTI &gt; This induced splitting can be assisted by a closely traced laser source followed by splitting by a cooling source such as water or dry ice jets. Dicing methods, such as diamond wheel cutting cuts, can be used for splitting, but tend to be costly. This dicing, when used, cuts the silicon just inside the prepreg to separate.

Silicon wafer thinning itself is a wet etching solution such as deep KOH, or other hydroxides (e.g., NaOH, TMAH, NH ₄ ) at a high etch rate at relatively high temperatures OH or LiOH). Mixtures containing other wetting agents such as at least HF and HNO3 and optional additives (e.g., acetic acid, phosphoric acid or sulfuric acid) can be used, but are generally more expensive. Such acid etching may be performed at room temperature or below and may be cooled in a solution to remove heat generated from the exothermic etching reaction.

In order to take full advantage of the etch chemistry, the flocculating agent is not limited to the case of alkaline etching, in particular the potassium silicate (in the case of silicon etching) and KOH etchant or hexafluorosilicic acid (in the case of HF / HNO3 based etchant) , And then introduced into the process to aid mechanical separation of the reaction product, for example, by a sedimentation layer or by centrifugal demixing. Another way to remove byproducts in the solution is to thermocycle the solution (i.e., cool down to lower solubility, remove components from the solution such as silicate, and reheat). By separating the silicate, the by-product is separated from the ettant and the remainder of the spent etchant (e.g., KOH or NaOH) is supplied to the bath from a solid brick or flake (or other hydroxide) of KOH or a highly concentrated aqueous solution , The etchant's bath life can be increased.

Another option for silicon thin film formation by etching is to use a plasma such as a halogen-containing plasma for silicon etching. In addition, molecular radical etching with a high etch rate is contemplated. Other options for silicon wafer thinning include mechanical grinding or lapping of silicon. In some instances, the ground silicon may be easily separated for potentially recovery and recycling.

After the sun side (front) texturing, a surface cleaning process such as one containing HCl, HF, or HNO3, or ozonated HF, followed by a final dilute HF etch process is performed and any final HF containing process is performed with the original oxide May not exist.

In the case of performing split cutting before silicon thinning (e.g., by laser), a predetermined process flow may include cutting about 30 to 70% of the thickness, followed by a subsequent etch to extend to the depth pre- Showing the step of completing the separation. The initial split cut may be a complete cut (as opposed to an etch that provides separation by full split) as in the process flow shown in FIG.

Block 6 of FIG. 33 includes solar cell front engineering including front passivation applications with or without additional doped front field (FSF). In order to carry out the doped front field, in various embodiments, it is desirable to have a dopant source containing an arsenic or antimony or indium dopant, which is generally for an n-type absorber cell, such as pulsed nanosecond laser annealing or pulsed nanosecond laser doping It is provided with a drive and / or a dopant activation mechanism. The dopant source may be provided by a variety of methods, including ion implantation, pre-deposition of a layer of a material containing a dopant, pre-deposition of a jet containing a dopant, such as plasma immersion ion implantation using PH3 or gas immersion laser doping (GILD). Process flow embodiments that perform a doped front field (FSF) are shown in Figures 38a-38d, 39a-39d, 40a-40d, and 41a-41b. In this way, it is desirable to have an effective low temperature drive mechanism, which is pulsed nanosecond laser annealing or melting, or melting (GILD) in a dopant atmosphere, concentrating heat on the front of the solar cell, It is maintained in a relatively unheated state and is not affected by the front-side pulse laser machining. For a laser source, a pulse source, for example a pulsed nanosecond laser, can be used in the form of a doped FSF. To solve topological problems such as random pyramid texture surfaces, annealing may be performed using pulsed nanoseconds (pulse lengths ranging from about 10 nanoseconds to several hundreds nanoseconds) green lasers capable of distributing heat to the top several microns of the absorber, Lt; RTI ID = 0.0 &gt; UV &lt; / RTI &gt; laser that transfers most of the heat to the pyramid tip. Top hat or flat top homogenized laser beams may also be used.

Various options of the front passivation layer include various options such as a stack of amorphous silicon (a-Si) and silicon nitride from silicon nitride, or specifically a-Si, then n-doped a-Si and then silicon nitride have. Instead of silicon nitride, an oxide nitride or oxynitride having a fixed oxygen content or a varying oxygen content can be used. Instead of a-Si, the initial layer may contain an amorphous silicon-oxide (also possibly with a sub stoichiometric content of oxygen) having a fraction of oxygen, or an amorphous silicon-carbon with a relatively small fraction of carbon. Another alternative to a-Si is that aluminum oxide (Al ₂ O ₃ ) can be produced on p and n-type silicon at very low surface recombination rates (such as ALD, PECVD, or APCVD Al ₂ O ₃ Deposition), easily recombined with silicon nitride, and then silicon nitride is deposited as a second layer. If silicon nitride is used, the stoichiometric ratio between nitrogen and silicon can be fixed or varied to have optimal optical and electrical performance throughout the film, wherein optimal optical performance is achieved at low or zero absorption in the film and is accurate Effective film thickness and refractive index and best electrical performance can be achieved with a sufficient hydrogen content and a relatively large fixed amount of charge density (for n-type based cells).

Block 7, which is the seventh building block of Figure 33, includes the formation of an access hole (bias) to contact the buried metal 1 (M1) layer and to deposit and structure metal 2 (M2). Metal (M2) forms the interconnected final high-conductivity solar cell metallization between the islands by the cell bus bar.

At this stage, if via holes are formed to interconnect M2 and M1 during cell fabrication, the buried M1 layer may be deposited on the stacked backplane, for example during the wet process step, such as backside etching, texturing, and post- Lt; / RTI &gt; The via hole can be drilled using a laser such as a pulsed CO2 laser or a pulsed UV laser. In some instances, the bias may be located on the M1 layer finger, which is arbitrarily widened to have an allowed array tolerance. The arrangement of the vias in the lower engaged M1 finger and also the arrangement of the trench isolation split cut in the structure on the rear side of the absorber wafer can utilize infrared irradiation of the alignment mark through the silicon absorber layer and also with sufficient transmission through the backplane .

M1 After the formation of a via hole in the backplane by a via hole landed on a designated portion of the fingered finger, the structure is ready for M2 deposition and patterning and is pre-deposited using an in-situ sputter etch cleaning (e.g., Or other plasma or ion) to etch the lower conductive surface layer, such as aluminum oxide or carbon residue on the M1 contact, and to promote M2 adhesion on the backplane surface.

This process can be performed in a vacuum PVD system, including vacuum integrated plasma sputtering and vacuum process capability. The M2 layer can then be deposited, preferably without vacuum breakdown. The M2 layer can be deposited, for example, using PVD, such as evaporation of aluminum (thermal or electron beam evaporation of aluminum) or plasma sputtering, followed by deposition of a thin film (about 100 nm to 500 nm thick) nickel or nickel- Antioxidant, and at least one capping layer that functions as a contact layer, such as a tin (Sn) or other solderable material coat.

After PVD deposition of M2, the cell can be annealed after or in accordance with the original heating to improve surface passivation properties, reduce surface recombination speed, and reduce cell metallization contact and via resistance. M2 is then patterned using, for example, pulsed laser ablation to separate the emitter from the base contact area and to provide a suitable pre-designed interconnect (serial, parallel, or combination thereof) between the individual islands or sub- (Completely maintained). The patterned M2 may include a final solar cell bus bar. Other deposition techniques, such as screen or inkjet printing, or thermal spray coating, or arc plasma spray coating, or plating, may be used for PVD (plasma sputtering and / or evaporation) of M2.

The following detailed process flow for fabricating the rear contact solar cell is provided as an exemplary embodiment, highlighting various core features of the disclosed subject matter. Note that this process flow relates to island master cells (Icel), but they can be applied to form a rear contact solar cell that does not use a monolithic island solar cell structure. A particular example of each process flow follows a generic building block provided in Figure 33 and shares the sign of a common element,

- Cutting Damage Reduction (SDR), Tool 1 reduces silicon wafer thickness and overall surface roughness on both sides of the wafer. The SDR may be a bilateral or one side etching tool (batch or inline design).

Patterned screen printed M1 paste (for example a suitable highly conductive frit member paste containing aluminum). Patterned M2 (plasma sputtering, and / or evaporation and / or another suitable PVD method, e.g., arc or thermal spray) formed by PVD followed by pulsed laser ablation patterning of the deposited metal layer; M2 is represented by PVD AL / NiV, but other material options include Al / Ni, Al / Zn, Cu / Ni, Cu / Zn, If desired, PVD copper can be used as the primary M2 conductor instead of aluminum.

A compartment laser scribing step (which can be referred to as "Icel" cutting / scribing / trenching in the process flow) to form the trench isolation region of the island of monolithic solar cells of the icel. Referring to FIG. 34A, in this laser compartment scribing (tool 12), it is possible to remove from the flow and tools 11 and 13 associated with a single wet processing equipment (i.e., Compare with 17 process tools including the island compartments in the flow) - Process removal steps corresponding to all process flow steps

-Silicon backside etching step, a thin or thick absorber Si can be formed, but the absorber thickness is reduced to a range of about 50 to 80 microns (tool 11 of Figure 34 (a), this tool designation being used in different process flow embodiments (Note that these symbols change in different process flow embodiments in FIG. 34A), and the final silicon absorber thickness is about &lt; RTI ID = 0.0 &gt; about &lt; 35 to 75 microns.

The trench isolation region can be formed at any point after the Si etch back side (wafer thinning), between the Si back side etch and the solar sun side (front side) texturing, or according to the process flow confinement and desired cell structure (Also referred to as "icel " scribing / cutting / trenching in the process flow).

- The process flow can be initiated with quasi mono or CZ n-type Si wafers.

- The isolation trenches are formed using Si n-side etching (wafer thinning) followed by pulse ns laser scribing.

- Al patterned M1 is formed using an Al paste and a furnace annealing process.

34A-34D are process flow embodiments of fabricating a meshed rear-side contact solar cell in which no FSF or BSF is formed for base conductivity, i.e. no additional n + doping is used in the n-type base to reduce the base resistance . Flows 34a and 34b describe the flow according to the presence or absence of in-situ masking of PVD for M2 and the islands laser cutting ("Icel pulse ns laser scribing") is performed between cleaning after Si thinning backside etching and sun side texturing / do. Flow 34a illustrates PVD M2 using laser ablation patterning and without in-situ PVD masking of M2. Flow 34b shows PVD M2 including an in-situ PVD shadow masking for patterned M2. Flows 34c and 34d describe the flow with and without in-situ shadow masking of PVD for M2, and the islands laser cutting is performed before the Si backside etch (reducing the tool count by one). Flow 34c depicts PVD M2 without pulsed laser ablation patterning and M2's in-situ PVD shadow masking. Flow 34d shows PVD M2 including the in-situ PVD shadow masking of the patterned M2.

Figures 35a through 35d illustrate a process flow embodiment for fabricating an intertwined rear side contact solar cell comprising buried BSFs for base conductivity, i.e. additional n + doping in an n-type base to reduce base resistance, POCl after SDR ₃ doping followed by a POCl3 glass etch + Si etch. Flows 35a and 35b describe the flow with and without in-situ shadow masking of PVD for M2, and island laser cutting is performed between cleaning after Si backside etching and texturing / texturing. Flow 35a illustrates PVD M2 employing pulsed laser ablation patterning and not including in-situ PVD shadow masking of M2. And flow 35b shows PVD M2 including an in-situ PVD shadow masking of patterned M2. Flows 35c and 35d describe the flow with and without in-situ shadow masking of PVD for M2, where the islands laser cutting is performed prior to Si backside etch (reducing the tool count by one). Flow 35c shows PVD M2 using pulsed laser ablation patterning and using no in-situ PVD shadow masking of M2. Flow 35d shows PVD M2 containing the in-situ PVD masking of the patterned M2.

36A-36D illustrate a process flow embodiment for fabricating a meshed rear-side contact solar cell, including buried BSFs for base conductivity, i.e. with additional n + doping of the n-type base to reduce the base resistance, And a process using annealing with the following shadows (ion implantation places the P peak after the next emitter base junction). Flows 36a and 36b describe flows with and without in-situ masking of PVD for M2 and describe island laser cutting between cleaning after Si back side etching and texturing / texturing. Flow 36a illustrates PVD M2 that does not include the in-situ PVD shadow masking of M2 using pulsed laser ablation patterning. Flow 36b shows PVD M2 including an in-situ PVD shadow masking of patterned M2. Flows 36c and 36d describe flows with and without in-situ masking of PVD for M2, wherein the islands laser cutting is performed prior to Si backside etch (reducing by tool count 1). Flow 36c illustrates PVD M2 employing pulsed laser ablation patterning and not including in-situ PVD shadow masking. Flow 36d shows PVD M2 containing an in-situ PVD shadow masking for the patterned M2.

38A-38D illustrate a process flow embodiment for fabricating a meshed rear-side contact solar cell comprising a laser-doped FSF for base conductivity, i. E. To reduce the base resistance, , Using laser doping on the front side after Si backside etching and texturing / cleaning (pulse ns laser doping is done after applying a porous liquid source after texturing). The laser doped FSF has two purposes: improved front passivation and reduced base resistance (e.g., a doping depth of 0.1 to 0.5 microns, a surface concentration of 1E17 to 5E19 cm ^-3 , Low surface concentration for deep doping and vice versa)

Figures 38A and 38B describe the flow with and without in-situ masking of PVD for M2, where the island laser cutting is between cleaning after Si back side etch and texturing / texturing. Flow 38a illustrates PVD M2 employing pulsed laser ablation patterning and not involving in-situ PVD shadow masking of M2. Flow 38b shows PVD M2 containing an in-situ PVD shadow masking for the patterned M2. Flow 38c is for PVD M2 that uses pulsed laser ablation patterning and does not include the in-situ PVD shadow masking of M2. Flow 38d shows PVD M2 including the in-situ PVD shadow masking of the patterned M2.

39A-39D are process flow embodiments for fabricating a meshed rear-side contact solar cell comprising a pulsed laser FSF for base conductivity, i.e. additional n + doping of the n-type base to reduce the base resistance, (A pulse ns or ps laser is applied after depositing a thin film layer of 250 nm or less of n + phosphorous or arsenic doped amorphous Si, , Surface concentration ~ 1E17 to 5E20 cm ^-3 , low surface concentration for thick n + amorphous Si, or vice versa).

Figures 39a-39b illustrate the flow with and without in-situ masking of PVD for M2, and island laser cutting is between cleaning after Si backside etch and texturing / texturing. Flow 39a illustrates PVD M2 employing pulsed laser ablation patterning and not including in-situ PVD shadow masking of M2. And flow 39b shows PVD M2 including in-situ PVD shadow masking for patterned M2. Flows 39c and 39d describe the flow with and without in-situ masking of PVD for M2, and the island laser cutting is before the Si backside etch (the tool count is reduced by one). Flow 39c illustrates PVD M2 employing pulsed laser ablation patterning and not including in-situ PVD shadow masking of M2. Flow 39d shows PVD M2 containing an in-situ PVD shadow masking for the patterned M2.

Figures 40A-40D illustrate a process flow embodiment for fabricating a meshed rear-side contact solar cell comprising an ion implanted FSF for base conductivity, i.e. using additional n + doping in the n-type base to reduce the base resistance, Or arsenic is implanted on the textured sun side and then laser annealed to activate the Si backside etched and textured / cleaned implanted dopant (thin film of n + phosphorous or arsenic doped layer, e.g., less than 500 nm After implanting the injection layer, a pulsed ns laser is applied to reduce the base resistance, surface concentration ~ 1E17 to 5E20 cm ^-3 , low surface concentration for thick n + amorphous Si, and vice versa.

Flows 40a and 40b describe flows with and without in-situ masking of PVD for M2, and island laser cutting is performed between cleaning after Si backside etching and texturing / texturing. Flow 40a illustrates PVD M2 employing pulsed laser ablation patterning and not including in-situ PVD shadow masking. Flow 40b shows PVD M2 using in-situ PVD shadow masking for patterned M2. Flows 40c and 40d describe flows with and without in-situ masking of PVD for M2, and island laser cutting is performed before the Si etch back side (tool count is decremented by 1). Flow 40c illustrates PVD M2 employing pulsed laser ablation patterning and not using in-situ PVD shadow masking of M2. Flow 40d shows PVD M2 using in-situ PVD shadow masking for patterned M2.

Figures 41a-41d illustrate a process flow embodiment for fabricating a meshed rear-side contact solar cell comprising a gas immersion FSF for base conductivity, i.e. using additional n + doping of the n-type base to reduce the base resistance, (FSF depth ~ 0.1-0.3 mu m) using PH3 laser gas immersion doping on the front side after backside etching and texturing / cleaning (a pulse ns laser is used for gas immersion laser doping to reduce the base resistance, Surface concentration ~ 1E18 to 5E20 cm ^-3 , low surface concentration is used for the deep doping region, and vice versa).

Flows 41a and 41b describe the flow with and without in-situ masking of PVD for M2 and island laser cutting is performed between cleaning after Si backside etching and texturing / texturing. Flow 41a illustrates PVD M2 without using pulse laser ablation patterning and without using in-situ PVD shadow masking of M2. Flow 41b shows PVD M2 using in-situ PVD shadow masking for patterned M2.

Figure 42 illustrates the fabrication of a meshed rear contact solar cell that performs pulsed ns laser scribing of the isolation trenches using FSF or BSF for the base resistor and laser ablation patterning of PV-Al / NiV and &lt; RTI ID = &Lt; / RTI &gt;

Figure 43 is a process flow embodiment for fabricating a meshed backside contact solar cell using pulsed ns laser scribing of isolation trenches on a pre-etched thick silicon.

Of these, the different metallization options for the first metal (M1) layer may be deposited using physical vapor deposition (PVD) such as screen printing or stencil printing, or a DC marketron plasma sputtering process including the following sintering steps, For example, deposition using pulsed laser ablation patterning. Among them, the M1 material selection is selected from the group consisting of screen printed aluminum (Al), aluminum, aluminum and silver combinations with silicon and / or germanium content (different metals are used for the emitter and base) &Lt; / RTI &gt; and nickel deposited by blanket method. Material selection for M1 PVD also includes Al, Al and Si and / or Ge followed by Ni or NiV. The concentrations shown below are weights for material selection for M1.

Screen Printing Patterning Advantages of using PVD Al / NiV instead of Al paste and furnace annealing (1 to 2 탆 Al and relatively thin NiV of 0.1 탆 to 0.50 탆) - a bulk Al resistance to 2.7 [micro] [Omega], a factor of about 15x to 100x nearly lower than the cured Al resistance to reduce the required Al layer in a fraction of about 1 [mu] m to about 2 [ 30 + mu m).

Much thinner PVD Al compared to paste reduces M1 stress on thin silicon and much thinner PVD Al compared to screen printed Al pastes facilitates backplane lamination due to reduced surface topography on patterned M1 with a much thinner PVD Al layer do. Removing the screen printing process from the process stream can increase the mechanical yield in the production line because screen printing can be a major cause of wafer breakage in the production line (a tool in contact form only in flow). By eliminating screen printing, a thin, low-cost starting wafer can be used without severe breakage. PVD A1 is also much more pure than Al paste (for example, impurities such as Fe are much smaller) and potentially high Voc high cell efficiency can be obtained. PVD Al reduces overall M1 resistance and provides a lower M2-M1 through plug / contact resistance, reducing the number of required via holes drilled in the backplane and increasing productivity for backplane laser drilling processes.

The disadvantage of using PVD Al / NiV and pulsed laser removal instead of screen printed Al is the risk of punching through much thinner PVD Al M1 during backplane drilling. For example, in the case of laser removal, the required patterning step is a risk of damage to the Al / NiV laser, and a small number of carrier lifetimes in the solar cell are reduced. In addition, PVD and laser removal toolset also have higher capex costs compared to the following hard-cured screen prints.

In the process flow described previously, the screen printed aluminum layer for M1 is replaced by PVD Al / NiV followed by pulsed laser ablation of Al / NiV. Process, for example using a low PVD layer for good, low contamination contact formation, and then using a screen printed thick layer, to provide a thick landing pad layer of laser through the hole drilling process. This second layer process can serve as a mask for subsequent etching and patterning processes to remove undesirable thin PVD layers and thus avoid the risks associated with damaging the laser removal process and back passivation. That is, the screen printing layer functions as a mask of PVD etching by selective etching and metal bonding, and enables selective etching of the PVD layer at a higher rate than the screen printing layer. Also, the etching can be performed by a less selective agent, and depending on whether the metal in the screen printing area is much thicker than the metal in the area of the PVD alone. In the latter case, the etching needs to be performed in a timely manner.

Additional known options for the M1 layer can be incorporated into the disclosed process flow. For example, a very thin layer can be deposited that can be converted to suicide using a rather low temperature process. For example, the formation of nickel or cobalt and nickel suicide or cobalt suicide. Other materials such as titanium and other heat resistant metals can be used, and nickel is preferable because it consumes less silicon and has a low silicidation reaction temperature. The nickel suicide is formed only in the contact area, for example, only in the previously opened (oxide-free) contact area using a pulse picosecond or femtosecond laser ablation process. After nickel deposition (by PVD) and thermal annealing, the nickel suicide is formed only in the open region where the nickel contacts the silicon. The remaining unreacted nickel may then be stripped from the dielectric region and form a local self-aligned contact. Since the contact resistance with silicide is relatively small, this process can reduce the overall contact area ratio, thereby reducing the overall rearrangement speed (BSRV), increasing the open circuit voltage and increasing the cell efficiency obtained. This silicidation can be done, for example, with local nickel deposition using inkjet deposition of the nickel dots to be reacted, thereby eliminating the need to selectively wet etch unreacted nickel from other regions.

The process presented and the resulting cell structure can utilize a flexible CTE-matched backplane to provide a cell design with increased flexibility, particularly with a thinner or thinner absorber layer. The absorber layer can be an already thin film (less than about 80 [mu] m) formed, for example, as an epitaxial thin film growth deposited on a template obtained by a cuffless process. Or may require thinning after thick deposition epitaxial growth on, for example, reusable templates, or after lamination in the case of thick (about 100 to 180 μm) starting CZ or otherwise crystalline wafers. Battery flexibility is provided in the glass module itself, which provides a flexible module capsule concept, for example a very thin, light and flexible module. This same flexible module characteristic can reduce the cost of equipment and overall balance of system (BOS) costs for such manufacturing modules.

A method of patterning the rear structure is also provided (the emitter and base junction regions for M1 also contact region openings can contact the emitter and base contact regions). Generally, the rear recombination rate is kept low for a high performance IBC cell. Damage to the structure area, which can be caused by laser machining, may be disadvantageous for BRSV and may be disadvantageous to the open circuit voltage performance that can be achieved. Care must be taken to reduce and / or avoid damage from the laser process, since the rearward structuring depends on the removal of selective oxides by pulse laser ablation, for example, the removal of doped glass from the central region using a laser. Pulse picosecond and femtosecond lasers can avoid this damage, but still have a large number of residual damage, which can reduce the efficiency of the resulting cell.

As yet another process, the use of layer masking and layer masking patterning with subsequent lasers is provided, e.g., oxide removal is performed using wet etch steps such as buffered or unbuffered hydrofluoric acid. The cross-sectional views of Figures 44A and 44B illustrate this concept. 44A is a cross-sectional view illustrating direct oxide removal using a PS laser of BSG (or PSG) on a silicon layer. The laser ablation opening 520 is formed by a laser beam distribution 526 in a BSG (or PSG) layer 522 that exposes a Si layer 524. A damaged Si region in the Si can be formed in the glass-Si interface 528 and the excess beam energy region 530. [

44B is a cross-sectional view illustrating the wet etch opening of the BSG (or PSG) layer on the silicon layer and the removal of the hard mask using a ps or ns laser. A laser ablation opening 548 is formed by the laser beam distribution 546 in the hard mask layer 540 on the BSG (or PSG) layer 542 on the silicon layer 544. The hard mask layer 540 may be a temporary hard mask such as a resist or polymer or a permanent hard mask such as a-Si. The wet etch forms a wet etch opening 552 that exposes an intact region 550 in the silicon layer 544. For example, the masking layer may be applied in the form of amorphous silicon on the deposited glass and, in some instances, may be applied with the same atmospheric pressure deposition tool or using PECVD or PVD. The thin amorphous Si (a-Si) (from about 50 to about several hundred Angstroms) is selectively laser etched and provides a hard mask layer for the next etching step. The a-Si not removed in the untreated region need not be removed, but may be oxidized as part of a subsequent furnace anneal step. Such a process can be easily performed in the case of the selective emitter window and the base window opening process.

As an alternative to the use of a-Si, for example, the masking layer may also consist of a polymer such as a resist or photoresist or other organic material. The thickness of the polymer can be less than 1 micron and the application method can include a very high polymer or resist utilization rate, such as roller coating or spray coating. A key requirement of the polymer or resist is that it can sustain an oxide etch process using HF that is well adhered to the glass and is not cushioned or buffered.

In one embodiment, the subsequent laser step removes the resist or polymer, then the bottom of the glass is locally etched, and then the resist polymer is stripped (in some instances with the same tool as the etch). This method requires large process margins for laser machining because the polymer is removed with a much smaller laser effect than a-Si or glass and the contact area is not damaged. This method can use nanosecond lasers that operate at a lower cost than picosecond lasers. This process can easily be performed for the contact open laser processing step prior to M1 contact because the polymer or resist is removed after glass etching.

In the disadvantage of a high material cost, the polymer or resist may be photosensitive, for example using a positive photoresist action and the laser process exposing the photoresist (rather than removing the photoresist). In this case, the wet etch step is to develop the resist in the batch or in-line bath, then etch the localized glass, then remove the resist and perform the cleaning step (all in one example performed with one wet tool).

45 to 49 illustrate a number of representative processes for fabricating a back contact solar cell with a backplane, wherein (i) no wet etching is performed after lamination, (ii) the silicon wafer is subjected to SDR and the thin film It is not thinned. This process flow forms a rear contact solar cell having a thicker absorber layer compared to the previous process flow (typically about 100 [mu] m to about 150 [mu] m). In Figures 45 to 49, the front passivation includes the thin film thermal oxide bottom layer with a hydrogenated silicon nitride field assisted passivation layer (also acting as antireflective coating or ARC). For example, the passivation layer may be a stack of PECVD hydrogenated amorphous silicon and silicon nitride (thin film thermal oxide member).

In Figures 45-49, the bulk CZ wafer backside contact solar cell process flow does not include an optional emitter and uses top-hat pulse laser ablation and does not use a laser ablation process. Figure 45 is a process flow using two APCVDs and three furnaces. 46 shows a process flow using two APCVD and three furnaces. Figure 49 is a process flow using one APCVD and two furnaces.

Although these process flows are shown without selective emitter formation, they can be extended to include selective emitters (e.g., by adding one APCVD BSG and one pulse laser removal process step). The major advantages of this process flow embodiment are:

- Wet chemical processing after lamination does not eliminate the risk of chemical attack on the backplane and the risk of desorption of the backplane.

Can be formed to conform to a frontal texture using a standard doping furnace without the need for pulsed laser doping to the FSF without any constraints associated with the backplane material.

- the five flows shown in Figures 45-49 form a rear contact cell with a thick absorber layer (compared to a thin film silicon absorber process flow) and they require a starting wafer and a relatively small carrier recombination lifetime, The same high efficiency as the thin film silicon solar cell produced by the provided process flow can be achieved.

The above description of the illustrative embodiments is provided to enable those skilled in the art to make or use the claimed subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of innovative facilities. Accordingly, the claimed subject matter is not limited to the embodiments shown herein but is consistent with a broad scope consistent with the novel features and principles disclosed herein.

Claims (16)

A method of forming a rear-side contact rear-side solar cell,
Forming an emitter and a base contact region on a rear side of a semiconductor wafer including a light reception front side and a rear side opposite to the front side;
Forming a first level contact metallization on the back side of the wafer;
Attaching an electrically insulated backplane to a rear side of the semiconductor wafer;
Forming an isolation trench in the semiconductor wafer to pattern the semiconductor wafer into a plurality of electrically isolated islands;
Thinning the semiconductor wafer;
Forming a metallization structure that electrically connects the plurality of islands on the electrically insulated backplane;
Wherein the rear-side contact rear-side junction solar cell comprises a back contact side rear junction solar cell.
The method according to claim 1,
Wherein forming the isolation trench in the semiconductor wafer comprises partitioning the semiconductor wafer into a plurality of completely electrically isolated islands.
The method according to claim 1,
Wherein forming the isolation trench in the semiconductor wafer comprises partitioning the semiconductor wafer into a plurality of partially electrically isolated islands wherein thinning the semiconductor wafer includes terminating the compartment and electrically isolating the islands Wherein the rear-side contact rear-side junction solar cell is formed by the following method.
The method according to claim 1,
Further comprising forming a backside field on the back side of the semiconductor wafer prior to forming the emitter and base contact regions.
5. The method of claim 4,
Wherein the backside field is formed using a thermal doping deposition and drive process.
5. The method of claim 4,
Wherein the backside field is formed using dopant ion implantation and thermal annealing.
The method according to claim 1,
Wherein the step of thinning the semiconductor wafer is a wet etching process.
The method according to claim 1,
Wherein the step of thinning the semiconductor wafer is a dry etching process.
The method according to claim 1,
Wherein the thinning step of the semiconductor wafer is a mechanical polishing process.
The method according to claim 1,
Wherein the thinning step of the semiconductor wafer is a dividing step using laser splitting or ion implantation.
The method according to claim 1,
Wherein the isolation trench is formed using a UV laser.
The method according to claim 1,
Wherein the isolation trench is formed using an IR laser.
The method according to claim 1,
Wherein the separation trench is formed using a mechanical saw.
The method according to claim 1,
Further comprising the step of forming a front field after thinning the semiconductor wafer.
15. The method of claim 14,
Wherein the front field is formed using gas immersion laser doping.
15. The method of claim 14,
Wherein the front field is formed using a dopant precursor that is driven by a laser and deposited on the front side.

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