JP2015519285A - Single crystal silicon ingot and wafer, ingot growth apparatus and method thereof - Google Patents

Abstract

The silicon single crystal ingot and wafer of the example predominate crystal defects having a size of 10 nm to 30 nm among crystal defects included in at least one of the vacancy dominant defect-free region and the interstitial dominant defect-free region. A transition region is formed. [Selection] Figure 3

Description

  Embodiments relate to single crystal silicon ingots and wafers and apparatus and methods for growing the ingots.

  In general, as a method of manufacturing a silicon wafer, a floating zone (FZ) method or a Czochralski (CZ) method is often used. When a single crystal silicon ingot is grown by applying the FZ method, not only is it difficult to manufacture a large-diameter silicon wafer, but there is a problem that the process cost is very high. Therefore, a single crystal silicon ingot is formed based on the CZ method. It has become common to grow.

  According to the CZ method, polycrystalline silicon is charged into a quartz crucible, a graphite heating element is heated and melted, and then a seed crystal is immersed in the melted silicon melt and melted. A single crystal silicon ingot is grown by pulling the seed crystal while rotating it so that crystallization occurs at the liquid interface. Thereafter, the grown single crystal silicon ingot is sliced, etched, and polished into a wafer shape.

  FIG. 1 is a diagram schematically showing the distribution of crystal defect regions due to V / G during the growth of a single crystal silicon ingot. Here, V represents the pulling speed of the single crystal silicon ingot, and G represents the temperature gradient in the vertical direction near the solid-liquid interface.

  According to the Voronkov theory, when a single crystal silicon ingot is pulled up at a high speed with a V / G equal to or higher than a predetermined critical value, a vacancy-rich region in which defects due to voids exist exists. A single crystal silicon ingot grows as (hereinafter referred to as “V region”). That is, the V region is a region where the vacancy becomes excessive due to a shortage of silicon atoms.

  Further, when the single crystal silicon ingot is pulled up with a V / G smaller than a predetermined critical value, the single crystal silicon ingot grows as an O-band region where an oxidation induced stacking fault (OSF) exists. .

  Further, when V / G is further lowered and the single crystal silicon ingot is pulled up at a low speed, a single crystal is formed as an interstitial region (hereinafter referred to as “I region”) due to a dislocation loop in which interstitial silicon is gathered. Ingot grows. That is, the I region is a region where there are many agglomerates of interstitial silicon due to excess of silicon atoms.

  Between the V region and the I region, there is a vacancy dominant defect-free region (hereinafter referred to as “VDP region”) and an interstitial dominant defect-free region (hereinafter referred to as “IDP region”). To do. The VDP region and the IDP region are the same in that there is no shortage or excess of silicon atoms, but the VDP region includes oxygen precipitation nuclei, but the IDP region is different from each other in that it does not include oxygen precipitation nuclei.

  There may be a small void region that belongs to the O band and has a vacancy defect of a fine size, for example, DSOD (Direct Surface Oxide Defect).

  At this time, in order to grow the single crystal ingot as the VDP region and the IDP region, the corresponding V / G must be maintained while the single crystal silicon ingot is grown. Therefore, during the growth of the single crystal silicon ingot, the silicon wafer is cut out from the growing ingot, the crystal defects of the cut out wafer are evaluated, and whether the ingot is growing as desired at the corresponding V / G. A single crystal ingot is grown as a VDP region or an IDP region by examining and adjusting V / G based on the examined result.

  As a method for evaluating crystal defects of a wafer, a reactive ion etching (RIE) method, a copper (Cu) deposition method, a Cu haze method, or the like is used.

  On the other hand, as the line width of semiconductor elements is gradually reduced and highly integrated, control and management of fine crystal defects generated during the growth of single crystal silicon ingots are becoming very important. For example, it is required to grow an ingot having only a crystal defect having a desired fine degree even in a defect-free region such as a VDP region and an IDP region. In particular, in the case of DRAM (Dynamic Random Access Memory), NAND flash (flash) memory, etc., it is required that the silicon wafer has a crystal defect smaller than 20 nm while the line width is narrowed to 20 nm or less. The

  However, the various existing crystal defect evaluation methods described above can only detect crystal defects having a size larger than 30 nm and cannot evaluate crystal defects having a size smaller than 30 nm. That is, the existing crystal defect evaluation method only evaluates crystal defects having a size smaller than 30 nm as defects having the same size collectively. Therefore, there is a problem that it is difficult to manufacture a silicon wafer or ingot having a crystal defect of a size smaller than 30 nm, for example, 10 nm to 29 nm.

  The embodiment provides a silicon single crystal ingot and a wafer having a crystal defect having a fine size smaller than 30 nm.

  Another embodiment provides an apparatus and method for growing a silicon single crystal ingot for producing a silicon wafer having a fine crystal defect.

  The single crystal silicon ingot and wafer of the example predominate crystal defects having a size of 10 nm to 30 nm among crystal defects included in at least one of the vacancy dominant defect-free region and the interstitial dominant defect-free region. Including transition regions.

  Among the total crystal defects included in the transition region, the crystal defects having a size of 10 nm to 30 nm are more than 50%.

  Of the total crystal defects included in the transition region, crystal defects having a size of 10 nm to 30 nm occupy 70% or more.

  The transition region does not include a ring-shaped oxidation-induced stacking fault.

  The single crystal silicon ingot and the wafer are manufactured by the Czochralski method.

  The crystal defects included in the transition region are 10 nm to 19 nm.

  In the single crystal silicon ingot and the wafer, the interstitial dominant defect-free region occupies 100x% (where 0 ≦ x ≦ 1) in the entire transition region, and the vacancy dominant defect-free region is in the entire transition region. It occupies 100 (1-x)%.

  Based on the diameter of the single crystal silicon ingot and the wafer, the interstitial dominant defect-free region occupies 70% or more of the entire transition region.

  Based on the diameter of the single crystal silicon ingot and the wafer, the vacancy dominant defect-free region occupies 30% or less of the entire transition region.

  In the transition region, the vacancy dominant defect-free region is located at a peripheral portion of the single crystal silicon ingot and the wafer, and the interstitial dominant defect-free region is a center inside the peripheral portion of the single crystal silicon ingot and the wafer. Located in.

  Based on the diameter of the single crystal silicon ingot and the wafer, the vacancy dominant defect-free region occupies 70% or more of the entire transition region.

  Based on the diameter of the single crystal silicon ingot and the wafer, the interstitial dominant defect-free region occupies 30% or less of the entire transition region.

  In the transition region, the interstitial dominant defect-free region is located at a peripheral portion of the single crystal silicon ingot and the wafer, and the vacancy dominant defect-free region is a center inside the peripheral portion of the single crystal silicon ingot and the wafer. Located in.

  The size of the crystal defect included in the transition region can be detected by the Magics method.

  The size of the crystal defect included in the transition region can be detected by the Magics method in a state where the single crystal silicon ingot and the wafer are not heat-treated.

  In an image photographed by the magics method, pixel number 1 indicates a crystal defect having a size of 10 nm to 19 nm.

  The single crystal silicon ingot growth apparatus according to another embodiment includes a crucible containing a silicon melt, a heater installed around the crucible to apply heat to the crucible, and a position of a maximum heat generating portion of the heater. And a magnetic field applying unit that applies a magnetic field to the crucible so that a maximum magnetic field plane (MGP) is formed at the position determined in this manner.

  The single crystal silicon ingot growth apparatus controls the heater to change the position of the maximum heat generating portion, and to adjust the MGP to a position adjusted according to the changed position of the maximum heat generating portion. And a second control unit that controls the magnetic field application unit so as to be formed.

  The heater generates heat uniformly in the vertical direction or can adjust the amount of heat generated in the vertical direction.

  The MGP is located at a position lower than the position of the maximum heat generating portion.

  The MGP is located at a position 20% to 40% lower than the position of the maximum heat generating portion with respect to the interface of the silicon melt.

  The MGP is located 50 to 300 mm lower than the interface of the silicon melt.

  The intensity of the magnetic field applied to the crucible from the magnetic field application unit may be 2000 to 3400 Gauss.

  The target pulling speed margin of the growing single crystal silicon ingot may be 0.010 mm / min to 0.030 mm / min.

  In addition, in a single crystal silicon ingot growth apparatus having a crucible containing a silicon melt, a heater that is installed around the crucible and that applies heat to the crucible, and a magnetic field application unit that applies a magnetic field to the crucible. The method for growing a single crystal silicon ingot according to an embodiment includes a step of determining a position of a maximum heat generating portion of the heater; and determining a position of a maximum magnetic field plane (MGP) according to the determined position of the maximum heat generating portion. Applying the magnetic field to the crucible so that the MGP is formed at the determined position.

  The method for growing a single crystal silicon ingot includes the step of adjusting the position of the MGP according to the changed position of the maximum heat generating portion when the position of the maximum heat generating portion is changed; and applying the magnetic field to the crucible And forming the MGP at the adjusted position.

  The magnetic field is applied to the crucible to form the MGP at a position lower than the position of the maximum heat generating portion.

  The magnetic field is applied to the crucible, and the MGP is formed at a position 20% to 40% lower than the position of the maximum heat generating portion with respect to the interface of the silicon melt.

  The magnetic field is applied to the crucible to form the MGP at a position 50 mm to 300 mm lower than the interface of the silicon melt.

  The intensity of the magnetic field applied to the crucible may be 2000-3400 Gauss.

  The target pulling speed margin of the growing single crystal silicon ingot may be 0.010 mm / min to 0.030 mm / min.

  In addition, a single crystal silicon ingot growth apparatus according to an embodiment includes a crucible containing molten silicon for growing a single crystal silicon ingot; and a heater that heats the crucible so that silicon in the crucible is melted. A pulling portion that pulls up the single crystal silicon ingot while rotating; a rotation angular velocity calculation unit that calculates a rotation angular velocity of the single crystal silicon ingot; the calculated rotation angular velocity is compared with a target rotation angular velocity and compared A first comparison unit that outputs a result as an angular velocity error value; and a flow rate control unit that adjusts the flow rate of the molten silicon in a portion where the diameter of the growing single crystal silicon ingot is sensed according to the angular velocity error value; A diameter sensing unit for sensing the diameter of the single crystal silicon ingot;

  The single crystal silicon ingot growth apparatus further includes a second comparison unit that compares the sensed diameter with a target diameter and outputs a comparison result as a diameter error value. The pulling unit includes the diameter error value. The single crystal ingot is pulled up while rotating at a pulling speed that is variable according to the above.

  Also, a crucible containing molten silicon for growing a single crystal silicon ingot, a heater for applying heat to the silicon in the crucible to melt the silicon, and rotating the single crystal silicon ingot A method for growing a single crystal silicon ingot according to an embodiment performed in a single crystal silicon ingot growth apparatus including a pulling unit for pulling up includes a step of measuring a rotational angular velocity of the single crystal silicon ingot; and a target of the measured rotational angular velocity Determining an angular velocity error value relative to a rotational angular velocity; adjusting the molten silicon flow rate to a portion where the diameter of the growing single crystal silicon ingot is sensed using the angular velocity error value; Sensing the diameter of a single crystal silicon ingot Including; steps and.

  The method for growing the single crystal silicon ingot includes a step of comparing the sensed diameter with a target diameter to determine a diameter error value, and using the diameter error value, a pulling speed of the growing single crystal silicon ingot Further varying.

  When the measured rotational angular velocity is larger than the target rotational angular velocity, the flow velocity is decreased and adjusted.

  The portion where the diameter is sensed corresponds to the meniscus of the molten silicon, and the flow of the meniscus is stabilized by decreasing the flow rate of the molten silicon.

  The growth rate margin of the growing single crystal silicon ingot may be 0.020 mm / min to 0.030 mm / min.

  Since the high-quality silicon single crystal ingot and wafer for semiconductor of the example can detect a crystal defect having a fine size smaller than 30 nm using the magics method, the size is smaller than 30 nm, for example, 10 nm to 19 nm. Since it can be formed as a transition region including a crystal defect having a size, it can be used for a semiconductor element having a line width narrowed to 20 nm or less.

  In addition, the single crystal silicon growth method and apparatus of the embodiment controls the pulling speed after stabilizing the flow of the meniscus where the diameter of the single crystal silicon ingot is sensed, so that the pulling speed is more accurately controlled. In addition to determining the position of the maximum magnetic field plane (MGP) with reference to the position of the maximum heat generating part, the convection of the silicon melt is controlled by adjusting the strength of the magnetic field as appropriate. It is possible to increase the margin of the IDP region by promoting the recombination with the char. Therefore, the productivity and growth rate of ingots are increased, such as improving the reproducibility of producing silicon wafers having high quality, such as the environment in which silicon wafers having crystal defects of 20 nm or less as described above are easily produced. Can be made.

FIG. 1 is a diagram schematically showing the distribution of crystal defect regions due to V / G during the growth of a single crystal silicon ingot.

FIG. 2 is a diagram illustrating a single crystal ingot growth apparatus according to an embodiment.

FIG. 3 is a diagram showing the growth rate and crystal defect distribution of the single crystal silicon ingot according to this example.

FIG. 4 is a plan view of the single crystal silicon ingot and the wafer according to the example.

FIG. 5 is a plan view of a single crystal silicon ingot and a wafer according to another embodiment.

FIG. 6A is a plan view of the wafer sample after the Cu haze method is applied to the wafer sample, and FIGS. 6B and 6C are views showing an image of the wafer sample taken by the Magics method.

FIG. 7 is a graph obtained by analyzing the relationship between each pixel and volume of an image acquired by the Magics method using a TEM.

FIG. 8 is a diagram illustrating an image of a crystal defect corresponding to the pixel 1 photographed using the TEM.

FIG. 9 is a graph showing a pixel histogram.

FIG. 10 is a flowchart for explaining a method of growing the single crystal silicon ingot according to the embodiment.

11A and 11B are graphs showing the trajectory of the ingot pulling speed.

FIG. 12 is a diagram showing a margin of the pulling speed according to the existing example and the present example.

FIG. 13 is a flowchart for explaining a method of growing a single crystal silicon ingot according to another embodiment.

FIG. 14A is a diagram illustrating a maximum value of the IDP margin depending on the position of the MGP, and FIG. 14B is a diagram illustrating a value 70% of the maximum value of the IDP margin depending on the position of the MGP.

FIG. 15A is a diagram illustrating a maximum value of the IDP margin depending on the strength of the magnetic field, and FIG. 15B is a diagram illustrating a value 70% of the maximum value of the IDP margin depending on the strength of the magnetic field.

  Hereinafter, the present invention will be described in detail by way of examples, and will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the invention. However, the embodiments according to the present invention can be modified in various forms, and the scope of the present invention should not be construed as being limited to the embodiments described in detail below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

  FIG. 2 is a diagram illustrating the single crystal ingot growth apparatus 100 according to the embodiment.

  A single crystal ingot growth apparatus 100 shown in FIG. 2 includes a crucible 10, a support shaft drive unit 16, a support rotary shaft 18, a silicon melt 20, an ingot 30, a seed crystal 32, a wire pulling unit 40, a pulling wire 42, and a heat shield. The member 50, the heater 60 disposed around the crucible 10, the heat insulating material 70, the magnetic field application unit 80, the diameter sensor unit 90, the rotational angular velocity calculation unit 92, the first comparison unit 94, the flow rate control unit 96, and the second comparison unit 110. The first and second control units 120 and 130 are included.

  Referring to FIG. 2, the single crystal silicon ingot growth apparatus 100 according to the present embodiment grows the single crystal silicon ingot 30 by the CZ method as follows.

  First, in the crucible 10, the high-purity polycrystalline raw material of silicon is heated to a temperature equal to or higher than the melting point temperature by the heater 60 to be changed into the silicon melt 20. At this time, the crucible 10 containing the silicon melt 20 has a double structure in which the inside is made of quartz 12 and the outside is made of graphite 14.

  Thereafter, the pulling unit 40 extends or pulls the pulling wire 42 so that the tip of the seed crystal 32 is brought into contact with or immersed in the substantially central portion of the surface of the silicon melt 20. At this time, the silicon seed crystal 32 can be held using a seed chuck (not shown).

  Thereafter, the support shaft drive unit 16 rotates the support rotation shaft 18 of the crucible 20 in the direction indicated by the arrow, and the pulling unit 40 raises and grows the ingot 30 while rotating the ingot 30 by the pulling wire 42. At this time, the columnar single crystal silicon ingot 30 can be completed by adjusting the speed V of pulling up the ingot 30 and the temperature gradient (G, ΔG).

  The heat shielding member 50 is disposed between the single crystal silicon ingot 30 and the crucible 10 so as to surround the ingot 30 and plays a role of shielding heat radiated from the ingot 30.

  FIG. 3 is a diagram showing the growth rate and crystal defect distribution of the single crystal silicon ingot according to this example.

  The defect distribution of the single crystal silicon ingot shown in FIG. 3 is the same as the defect distribution of the single crystal silicon ingot shown in FIG. 1 except that the transition region is further defined, so that the V region, small void region, O Detailed descriptions of the band region, the VDP region, the IDP region, and the I region are omitted. Here, the transition region is defined as a region having predominantly crystal defects having a size of 10 nm to 30 nm among crystal defects included in at least one of the VDP region and the IDP region. The degree of dominance can mean 50% or more. That is, more than 50% of crystal defects having a size of 10 nm to 30 nm may exist among the entire crystal defects included in the transition region. That is, out of the total crystal defects included in the transition region, crystal defects having a size of 10 nm to 30 nm can occupy k% (here, 50 ≦ k ≦ 100) or more.

  For example, the size of the crystal defect dominantly included in the transition region may be 10 nm to 19 nm. Such a transition region can be free from crystal defects belonging to the O band or the I region, which are ring-shaped oxidation-induced stacking fault regions.

  If the apparatus shown in FIG. 2 grows the ingot 30 with an arbitrary V / G selected within the range of the target V / G (hereinafter referred to as “T (VG)”), the ingot 30 according to this embodiment is used. Alternatively, the silicon wafer can predominantly have crystal defects with a size of 10 nm to 30 nm.

  FIG. 4 shows a plan view of the single crystal silicon ingot and the wafer 5A according to the embodiment, and FIG. 5 shows a plan view of the single crystal silicon ingot and the wafer 5B according to another embodiment.

  When the ingot 30 is grown at a V / G value of 4-4 ′ within T (VG) shown in FIG. 3, the ingot 30 or the silicon wafer 5A has a crystal defect distribution as shown in FIG. be able to. In this case, the transition region of the silicon wafer 5A is distributed over both the VDP region 142 and the IDP region 140.

  Alternatively, when the ingot 30 is grown at a V / G value of 5-5 ′ within T (VG) shown in FIG. 3, the silicon wafer 5B has a crystal defect distribution as shown in FIG. Can do. In this case, the transition region of the silicon wafer 5B is distributed only in the IDP region 150. That is, the transition region of the silicon wafer 5B is not distributed in the VDP region.

  Alternatively, when the ingot 30 is grown at a V / G value of 6-6 ′ within T (VG) shown in FIG. 3, the transition region of the silicon wafer is distributed only in the VDP region. That is, the transition region of the silicon wafer is not distributed in the IDP region.

  As a result, in the silicon wafer according to the present embodiment, the IDP region occupies m% as in the following Equation 1 in the entire transition region, and the VDP region accounts for n% as in the following Equation 2 in the entire transition region. Can occupy.

  Here, 0 ≦ x ≦ 1.

  For example, based on the diameter of the silicon wafer, the IDP region can occupy 70% or more of the entire transition region, and the VDP region can occupy less than 30% of the entire transition region. At this time, as illustrated in FIG. 4, in the silicon wafer 5A including the transition region, the VDP region is located at the peripheral portion of the silicon wafer 5A and the IDP region is located at the center inside the peripheral portion of the silicon wafer 5A. Can do. Alternatively, based on the diameter of the silicon wafer, the VDP region may occupy 70% or more of the entire transition region, and the IDP region may occupy less than 30% of the entire transition region. At this time, unlike the example of FIG. 4, in the transition region, the IDP region can be located at the periphery of the silicon wafer, and the VDP region can be located at the center inside the periphery of the silicon wafer. However, the present invention is not limited to this, and the VDP region and the IDP region can be positioned in various forms in the transition region of the silicon wafer.

  On the other hand, while the ingot is grown with V / G in the T (VG) described above, the ingot 30 may be grown with V / G that deviates from the initially set T (VG) due to various factors. Therefore, it is necessary to evaluate whether the ingot 30 is grown as a transition region in which crystal defects having a desired size of 10 nm to 30 nm are dominant. For this purpose, in this embodiment, the Magics method is used.

  In general, according to the existing Magics method, when a wafer sample is captured and an image is acquired, various pixels are displayed in the image in different colors. At this time, it is estimated whether a defect of the wafer sample is caused from a growth process, a slicing process, an etching process, or a polishing process through a pattern formed by the pixels. Thus, the existing Magics method was only used to assess the source of defects. However, the present applicant has detected the size of crystal defects by the following method using the above-mentioned Magics method.

  Hereinafter, whether or not a crystal defect having a size smaller than 30 nm is dominant among crystal defects included in a wafer sample cut from the growing single crystal silicon ingot 30 (that is, the wafer sample is formed as a transition region). A method for evaluating whether or not by the Magics method will be described with reference to the accompanying drawings as follows.

  First, while growing a single crystal silicon ingot having a diameter of 12 inches (300 mm), the ingot is cut in a horizontal direction perpendicular to the growing direction of the ingot to prepare a wafer sample.

  FIG. 6A shows a plan view of the wafer sample after the Cu haze method is applied to the wafer sample, and FIGS. 6B and 6C show images of the wafer sample taken by the Magics method. In FIGS. 6B and 6C, the images obtained by the magics method are displayed with pixels separated by different colors. However, since the figure looks black and white, in order to help understanding, the image of pixel 1 is displayed. The color was displayed as O, the color of pixel 2 was displayed as ☆, and the color of pixel 3 was displayed as Δ. 6B and 6C display only some pixels (that is, pixel 1 to pixel 3), but the present invention is not limited to this, and more pixels are displayed separately. Can do.

  If the existing crystal defect evaluation method, for example, the Cu haze method is used, as shown in FIG. 6A, in the wafer sample, the VDP region is displayed in black and the IDP region is only displayed in white. Therefore, according to the Cu haze method, it has not been possible to evaluate how dominant the crystal defects having a size smaller than 30 nm among the crystal defects included in the VDP region and the IDP region. That is, according to the existing crystal defect evaluation method, it was not possible to produce a silicon wafer including a transition region predominantly having crystal defects smaller than 30 nm, that is, having a size of 0 nm to 19 nm.

  However, according to the present embodiment, it can be evaluated as follows whether or not the crystal defects having a size of the wafer sample smaller than 30 nm are dominant.

  First, when a wafer sample is photographed by a camera (not shown), an image as shown in FIG. 6B or FIG. 6C showing pixels of different colors (for example, pixel 1 to pixel 3) is obtained.

  At this time, the applicant has reviewed the image shown in FIG. 6B or FIG. 6C with a scanning electron microscope (SEM), and then observed the image with a transmission electron microscope (TEM: Transmission Electron Microscope). The volume of crystal defects by pixel could be investigated. That is, it has been found that the size of crystal defects can be evaluated according to the type of pixel through an image photographed by the Magics method.

FIG. 7 is a graph in which the relationship between each pixel and volume of an image acquired by the Magics method is analyzed by TEM. The horizontal axis indicates the pixel number, and the vertical axis indicates the volume. Here, the correlation coefficient (R ² ) is 0.9, and the correlation equation may be y = 3427.7x ² -4700.4x + 23968.

は格子の方向を示す。 FIG. 8 shows an image of crystal defects corresponding to pixel 1 photographed using TEM. Here, [100], [011],

Indicates the direction of the lattice.

  Since the TEM is a device capable of detecting the size and type of crystal defects having a size of angstrom (Å), each pixel is photographed with the TEM as shown in FIG. The size could be evaluated. In addition, a large number of pixels were photographed with a TEM, and it was found that the size of each pixel defect has a correlation as shown in FIG. Referring to FIG. 7, it can be seen that the smaller the pixel number, the smaller the volume of crystal defects. This implies that the smaller the pixel number, the smaller the crystal defect size. Referring to FIG. 8, it can be seen that the size of the crystal defect of the pixel 1 is about 10 nm to 19 nm.

  Therefore, the specific size of a crystal defect having a size smaller than 30 nm that could not be evaluated can be detected through pixels displayed in an image photographed by the magics method.

  FIG. 9 is a graph showing a histogram of pixels, where the horizontal axis indicates the pixel number and the vertical axis indicates the frequency (or density) of each pixel.

  A histogram of each pixel as shown in FIG. 9 is generated from an image obtained by photographing the wafer sample. Thereafter, the frequency of each pixel number is evaluated in the histogram, and the size of the crystal defect included in the wafer sample can be confirmed.

  Hereinafter, a wafer sample having a crystal defect having a size corresponding to the pixel 1 is prevailing.

  For example, in the image of the wafer sample shown in FIG. 6B, the colors (O, ☆, Δ) from pixel 1 to pixel 3 are displayed at the peripheral portion, while the color of pixel 1 is at the center inside the peripheral portion. Only (O) is displayed. A histogram curve 200 shown in FIG. 9 is obtained from the video exemplified in FIG. 6B. At this time, since the frequency corresponding to the pixel number 1 is larger than the critical frequency, it is determined that the silicon wafer is formed as a transition region having a crystal defect having a size corresponding to the pixel 1 predominantly. Here, the critical frequency is determined according to the degree of dominance. For example, when the degree of dominance is k% as described above, the critical frequency means k% of the total number of pixels. That is, in this case, since the ingot 30 grows at V / G in T (VG), the wafer sample shown in FIG. 6B is formed as a transition region in which crystal defects of a desired size are dominant. The silicon wafer is acceptable.

  If V / G is further lowered within T (VG), an image of the wafer sample taken by the Magics method is as shown in FIG. 6C. In this case, since the silicon wafer is formed as a transition region in which crystal defects in the IDP region are predominately included, this is also acceptable.

  However, when the histogram curve 202 shown in FIG. 9 is obtained, the frequency corresponding to the pixel number 1 is smaller than the critical frequency, and instead the frequency corresponding to the pixel 2 is larger than the critical frequency. Since the crystal defect having a size corresponding to the pixel 2 is dominant, it is rejected. Therefore, the value of V / G that deviates from T (VG) is lowered by ΔV / G so that the ingot 30 grows at V / G in T (VG). A silicon wafer can be produced.

  If the size of the crystal lattice for each pixel number is predetermined based on FIG. 7 and V / G corresponding to the size of each crystal defect is predetermined, ΔV / G can be easily obtained. be able to. In the case of FIG. 9, ΔV / G is obtained by subtracting V / G corresponding to the size of the crystal defect corresponding to pixel 1 from V / G corresponding to the size of the crystal defect corresponding to pixel 2. be able to. At this time, when ΔV / G is adjusted so that the frequency of pixel 1 is greater than the frequency of pixel 2 (202 → 200), the frequency distribution increases. Therefore, the value of ΔV / G can be determined in consideration of this.

  As described above, according to the present embodiment, whether or not the size of the crystal defect included in the cut wafer sample is smaller than 30 nm, for example, 10 nm to 19 nm, is determined as described above. It can be evaluated by law. Therefore, when V / G for growing the single crystal silicon ingot 30 is out of the range of T (VG), it can be accurately adjusted so that V / G belongs to T (VG). It can be seen that such a silicon wafer is formed only as a transition region predominantly having a crystal defect having a size of 10 nm to 30 nm among crystal defects included in at least one of the VDP region and the IDP region.

  Furthermore, according to the present embodiment, when the size of crystal defects contained in the wafer sample is evaluated by the Magics method, it is not necessary to perform an additional pretreatment process such as heat treatment of the wafer sample. Therefore, the wafer sample can be evaluated more quickly and can be immediately fed back and reflected in the growing ingot growth process, so that the production time can be shortened.

  Hereinafter, a single crystal silicon ingot growth apparatus and method for manufacturing a silicon wafer according to the above-described embodiment will be described with reference to the accompanying drawings as follows. However, it is needless to say that the single crystal silicon ingot growth apparatus and method to be described later can be used for manufacturing a general silicon wafer in addition to the silicon wafer according to the present embodiment.

  FIG. 10 is a flowchart for explaining a method of growing a single crystal silicon ingot according to the embodiment.

  Referring to FIGS. 2 and 10, the rotational angular velocity of the single crystal silicon ingot 30 is calculated (step 302). Therefore, the rotation angular velocity calculation unit 92 calculates the rotation angular velocity of the ingot 30 using the rotation speed of the ingot 30 provided from the lifting unit 40 and the diameter of the sensed ingot 30 provided from the sensor 90. Can do.

  After step 302, the first comparison unit 94 compares the rotation angular velocity calculated by the rotation angular velocity calculation unit 92 with the target rotation angular velocity TSR, and outputs the comparison result as an angular velocity error value to the flow velocity control unit 96 (step). 304).

  After step 304, the flow rate control unit 96 reduces the flow rate of the molten silicon 20 in the portion 34 where the diameter of the growing single crystal silicon ingot 30 is sensed according to the angular velocity error value received from the first comparison unit 94. (Step 306). Therefore, the flow rate control unit 96 can control the pulling unit 40 and / or the support shaft driving unit 16 to decrease the flow rate. That is, the flow rate control unit 96 controls the rotational speed of the ingot 30 via the pulling unit 40, and controls the rotational speed of the crucible 10 via the support shaft drive unit 16. If it is determined that the measured rotational angular velocity is larger than the target rotational angular velocity TSR based on the angular velocity error value, the flow velocity control unit 96 decreases the flow velocity. When the portion 34 whose diameter is sensed corresponds to the meniscus of the silicon melt 20, the flow rate of the silicon melt 20 can be reduced to stabilize the meniscus flow.

  After step 306, the diameter sensing unit 90 senses the diameter of the single crystal silicon ingot 30 (step 308).

  After step 308, the second comparison unit 110 compares the diameter sensed by the diameter sensing unit 90 and the target diameter TD, and outputs the comparison result to the raising unit 40 as a diameter error value (step 310).

  After step 310, the pulling unit 40 varies the pulling speed of the growing single crystal silicon ingot 30 according to the diameter error value, and pulls up while rotating the single crystal silicon ingot 30 at the variable pulling speed (step 312). ). Therefore, the pulling speed of the growing single crystal silicon ingot 30 can be adjusted according to the diameter error value.

  11A and 11B are graphs showing the trajectory of the pulling speed V of the ingot 30, where the horizontal axis indicates time and the vertical axis indicates the pulling speed V.

  FIG. 12 is a diagram showing a margin of the pulling speed according to the existing example and the present example. Here, the P band indicates a boundary between the small void region and the O band shown in FIG.

  In general, the pulling unit 40 controls the pulling speed of the single crystal silicon ingot 30 according to the diameter sensed by the diameter sensing unit 90. For example, when the diameter of the ingot 30 sensed by the diameter sensing unit 90 is larger than the target diameter TD, the pulling unit 40 increases the pulling speed of the ingot 30 by the amount that the actually measured diameter of the ingot 30 is larger than the target diameter. However, when the diameter sensed by the diameter sensing unit 90 is smaller than the target diameter TD, the pulling unit 40 reduces the pulling speed of the ingot 30 by the amount that the actually measured diameter is smaller than the target diameter. At this time, the meniscus 34, which is a part whose diameter is sensed, may be unstable due to the influence of the strength of the flow rate of the molten silicon 20 and the nodes generated when the ingot 30 is grown. As described above, when the lifting speed is adjusted by the actually measured diameter sensed through the unstable meniscus 34 even though the meniscus 34 is unstable, as shown in FIG. VG), the width 322 that fluctuates outside the target trajectory 320 of the pulling speed in VG) may become very large. In this case, as shown in FIG. 12, an ingot that can be defectively processed by including crystal defects 336 in the P band (between small void region and O band region), crystal defects 334 in the V region, or I region. The frequency of 30 or silicon wafers may increase (see 330).

  In contrast, in this embodiment, in order to solve the above-described problem, after the flow of the meniscus 34 is stabilized through the above-described steps 302 to 306, the diameter is accurately sensed by the diameter sensing unit 90, Adjust the lifting speed based on the accurately sensed value. Therefore, as shown in FIG. 11B, the width 324 in which the pulling speed V fluctuates outside the target pulling speed locus 320 decreases. Therefore, referring to FIG. 12, the margin of the pulling speed of the growing single crystal silicon ingot 30 is from 0.015 mm / min to 0.016 mm / min of the existing L1 to 0.010 mm / min to 0.00 of the present embodiment L2. It can be greatly increased to 030 mm / min, for example, 0.025 mm / min. Therefore, as shown in FIG. 12, in the case of this example, when the frequency of the wafer sample is seen, it can be seen that there is no ingot 30 or silicon wafer that can be defectively processed by including crystal defects in the P region and the I region. (See 332). This not only increases productivity by 10% or more with the same amount of silicon melt 20, but also increases the growth rate of the ingot 30 by 10% or more.

  FIG. 13 is a flowchart for explaining a method of growing a single crystal silicon ingot according to another embodiment.

  Referring to FIGS. 2 and 13, the first controller 120 determines the position 62 of the maximum heat generating part of the heater 60 (step 402).

  After step 402, the second controller 130 determines the position of the maximum magnetic plane (MGP) according to the determined position 62 of the maximum heat generating part of the heater 60 received from the first controller 120. (Step 404). Here, the MGP means a portion where the horizontal component of the magnetic field generated from the magnetic field application unit 80 is maximum. The magnetic field application unit 80 is thermally insulated from the heater 60 by the heat insulating material 70.

  The heater 60 may generate heat uniformly in the vertical direction, and the amount of generated heat can be adjusted in the vertical direction. If the heater 60 generates heat uniformly in the vertical direction, the maximum heat generating portion is located at the center of the heater 60 or slightly above the center. However, when the heater 60 can adjust the heat generation amount in the vertical direction, the maximum heat generating portion can be arbitrarily adjusted.

  After step 404, the second controller 130 controls the magnetic field application unit 80 to apply a magnetic field to the crucible 10 so that the MGP is formed at the determined position (step 406).

  Thereafter, when the position of the maximum heat generating portion is changed in step 408, the position of the MGP is adjusted according to the changed position 62 of the maximum heat generating portion (step 410). The first control unit 120 can change the position 62 of the maximum heat generating unit by controlling the heater 60. When the heater 60 moves, the position 62 of the maximum heat generating portion can also change. The second control unit 130 confirms the changed position 62 of the maximum heat generating unit via the first control unit 120 and adjusts the position where the MGP is formed according to the changed position.

  After step 410, the second controller 130 controls the magnetic field application unit 80 so that the MGP is formed at the adjusted position, and applies the magnetic field to the crucible 10 (step 412).

  According to the embodiment, the MGP can be determined to be located at a position lower than the position 62 of the maximum heat generating portion. For example, the MGP may be located at a position 20% to 40% lower than the position 62 of the maximum heat generating portion with respect to the interface of the silicon melt 20. That is, when the position 62 of the maximum heat generating portion is separated from the interface of the silicon melt 20 by the first distance D1, the MGP is 20% to 40% lower than the first distance D1 from the interface of the silicon melt 20. Two distances D2 can be located apart. The second distance D2 may be 50 mm to 300 mm, for example, 150 mm.

  FIG. 14A shows the maximum value of the IDP margin according to the position of the MGP, and FIG. 14B shows a value that is 70% of the maximum value of the IDP margin according to the position of the MGP. In each graph, the horizontal axis indicates the position of the MGP, and the MGP position is set to “0” at the interface of the silicon melt 20, and the (−) value increases toward the lower side of the interface. REF of FIG. 14B shows the reference value compared with MGP which concerns on a present Example.

  Referring to FIGS. 14A and 14B, it can be seen that the MGP can be located between −50 mm and −300 mm, and the margin of the IDP is maximized when it is −150 mm.

  On the other hand, not only can the convection of the silicon melt 20 be controlled by adjusting the position 62 of the maximum heat generating portion and the position of the MGP, but also the convection of the silicon melt 20 can be controlled by the strength of the magnetic field applied by the magnetic field application unit 80. Can be controlled. For example, the magnetic field applied to the crucible 10 from the magnetic field application unit 80 may be 2000 to 3400 gauss, and it can be seen that the IDP margin is maximized at 2800 gauss.

  FIG. 15A shows the maximum value of the IDP margin due to the strength of the magnetic field, and FIG. 15B shows the value of 70% of the maximum value of the IDP margin due to the strength of the magnetic field. In each graph, the vertical axis indicates the IDP margin, and the horizontal axis indicates the magnetic field strength in gauss. REF in FIG. 15B indicates a reference value compared with Gauss according to the present embodiment.

  Referring to FIGS. 15A and 15B, when the magnetic field strength is 2800 gauss, the IDP margin can be increased from 0.007 mm / min to 0.010 mm / min to 0.030 mm / min, for example, 0 The IDP margin can be improved from 0.020 mm / min to 0.022 mm / min.

  As described above, when the IDP margin increases, the length range of 1250 ° C. to 1420 ° C., which is the temperature region in which the IDP region is formed, is expanded, and the above-described silicon wafer fabrication conditions become much easier.

  Generally, when the rotational angular velocity of the single crystal silicon ingot 30 is changed, the degree of expansion of the interface of the silicon melt 20 and the temperature gradient (G = Gs + Gm) in the growth direction of the ingot 30 (where Gs indicates the temperature gradient of the ingot). , Gm indicates the temperature gradient of the silicon melt 20), and the difference in temperature gradient in the radial direction of the ingot 30 at the portion where the ingot 30 and the silicon melt 20 are in contact (ΔG = Gse−Gsc) (where Gse and Gsc Represents the temperature gradient at the lower peripheral edge and the center of the ingot 30.), The concentration of oxygen contained in the ingot 30, and the size of the supercooling region formed between the ingot 30 and the silicon melt 20. Etc. are changed. For example, when the rotational angular velocity of the silicon ingot 30 is increased, the interface of the silicon melt 20 is greatly expanded, the temperature gradient G is increased, the temperature gradient difference (ΔG) is decreased, and the oxygen concentration is decreased. A good quality ingot 30 can be produced, but the pulling speed is difficult to control. On the contrary, when the rotational angular velocity of the silicon ingot 30 decreases, the interface of the silicon melt 20 becomes flat, the temperature gradient G decreases, the temperature gradient difference ΔG increases, the oxygen concentration increases, etc. Inferior quality ingot 30 may be generated, but the pulling speed can be easily controlled. However, this relationship may be disrupted by the magnetic field. In general, the silicon melt 20 shown in FIG. 2 is convected in the arrow direction 22 by the rotation of the ingot 30 and convected in the arrow direction 24 by the rotation of the crucible 10. However, the upper part and the lower part of the convection of the silicon melt 20 can be blocked based on the MGP.

  Unlike the existing one, according to the above-described embodiment, the MGP is determined in consideration of the convection of the silicon melt according to the position of the maximum heat generating portion, and the convection of the silicon melt 20 is adjusted by appropriately adjusting the strength of the magnetic field. To control. Accordingly, it is possible to compensate for the above-described problems that may occur while changing the rotational angular velocity. That is, when MGP is lower by 20% to 40% from the interface of the silicon melt 20 than the position 62 of the maximum heat generation site, the convection becomes stronger toward the center of the ingot 30 in the arrow direction 22, thereby Since it is possible to secure a recombination section with the stitching, the margin of the IDP region increases.

  In this example, the apparatus shown in FIG. 2 was used to grow a silicon wafer or ingot formed as a transition region having crystal defects having a size of 10 nm to 30 nm. However, the growth apparatus shown in FIG. 2 that performs the method shown in FIGS. 10 and 13 is merely an example, and an automatic growth controller (AGC) is used to perform each step. ) (Not shown) or an automatic temperature controller (ATC) (not shown) may be used.

  Moreover, the growth method of the single crystal silicon ingot shown in FIGS. 10 and 13 described above may be used at the same time, or only one of them may be used. Further, in order to manufacture the silicon wafer according to the present embodiment, in addition to the rotational angular velocity, MGP, magnetic field strength, and position of the maximum heat generation portion of the single crystal silicon ingot 30, an inert gas such as argon gas as a cooling gas is used. Of course, the pressure / flow rate, the gap between the heat shielding member 50 and the silicon melt 20, the shape of the heat shielding member 50, the number of heaters 60, and the rotational speed of the crucible 10 may be further used. is there.

  Although the embodiments have been described above, this is merely an example, and is not intended to limit the present invention. Any person who has ordinary knowledge in the field to which the present invention belongs will be described. It will be understood that various modifications and applications not exemplified above are possible without departing from the characteristics. For example, each component specifically shown in the embodiments can be modified. And the difference by such a deformation | transformation and application must be interpreted as being included in the scope of the present invention prescribed in the attached claim.

  This embodiment can be used to produce high-quality single crystal silicon ingots and wafers for semiconductors having crystal defects of a fine size smaller than 30 nm.

Claims (33)

  Single crystal silicon in which a transition region predominantly having a crystal defect size of 10 nm to 30 nm is formed among crystal defects included in at least one of a vacancy dominant defect-free region and an interstitial dominant defect-free region Ingots and wafers.   2. The single crystal silicon ingot and wafer according to claim 1, wherein crystal defects having a size of 10 nm to 30 nm are more than 50% of the total crystal defects included in the transition region.   2. The single crystal silicon ingot and wafer according to claim 1, wherein crystal defects having a size of 10 nm to 30 nm occupy 70% or more of the total crystal defects included in the transition region.   The single crystal silicon ingot and wafer according to claim 1, wherein the transition region does not include a ring-shaped oxidation-induced stacking fault.   The single crystal silicon ingot and wafer according to claim 1 manufactured by the Czochralski method.   The single crystal silicon ingot and wafer according to claim 1 whose size of said crystal defect contained in said transition region is 10 nm-19 nm.   In the single crystal silicon ingot and the wafer, the interstitial dominant defect-free region occupies 100x% (where 0 ≦ x ≦ 1) in the entire transition region, and the vacancy dominant defect-free region is in the entire transition region. The single crystal silicon ingot and wafer according to claim 1, which occupy 100 (1-x)%.   2. The single crystal silicon ingot and wafer according to claim 1, wherein the interstitial dominant defect-free region occupies 70% or more of the entire transition region based on the diameters of the single crystal silicon ingot and the wafer.   2. The single crystal silicon ingot and wafer according to claim 1, wherein the vacancy dominant defect-free region occupies 30% or less of the entire transition region based on the diameter of the single crystal silicon ingot and the wafer.   In the transition region, the vacancy dominant defect-free region is located at a peripheral portion of the single crystal silicon ingot and the wafer, and the interstitial dominant defect-free region is a center inside the peripheral portion of the single crystal silicon ingot and the wafer. The single crystal silicon ingot and wafer according to claim 1, which is located in   The single crystal silicon ingot and wafer according to any one of claims 1 to 10, wherein the size of the crystal defect included in the transition region can be detected by a magics method.   The single crystal silicon ingot and the single crystal silicon ingot according to claim 11, wherein the size of the crystal defect included in the transition region is detectable by the Magics method in a state where the single crystal silicon ingot and the wafer are not heat-treated. Wafer.   The single crystal silicon ingot and wafer according to claim 11, wherein pixel number 1 indicates a crystal defect having a size of 10 nm to 19 nm in an image photographed by the Magics method. A crucible containing a silicon melt;
A heater installed around the crucible to apply heat to the crucible;
A single crystal silicon ingot growth apparatus comprising: a magnetic field application unit configured to apply a magnetic field to the crucible so that a maximum magnetic field plane (MGP) is formed at a position determined according to a position of a maximum heat generation unit of the heater. The single crystal silicon ingot growth apparatus comprises:
A first control unit that controls the heater to change a position of the maximum heat generating unit;
The single crystal silicon according to claim 14, further comprising: a second control unit that controls the magnetic field application unit so that the MGP is formed at a position adjusted according to the changed position of the maximum heat generating unit. Ingot growth device.   The single crystal silicon ingot growth apparatus according to claim 14, wherein the heater is capable of adjusting a heat generation amount in a vertical direction.   The single crystal silicon ingot growth apparatus according to claim 14, wherein the MGP is located at a position lower than a position of the maximum heat generating portion.   The single crystal silicon ingot growth apparatus according to claim 17, wherein the MGP is located at a position 20% to 40% lower than a position of the maximum heat generating portion with respect to an interface of the silicon melt.   The single crystal silicon ingot growth apparatus according to claim 14, wherein the MGP is located at a position lower by 50 mm to 300 mm than an interface of the silicon melt.   The single crystal silicon ingot growth apparatus according to claim 14, wherein a target pulling speed margin of the growing single crystal silicon ingot is 0.010 mm / min to 0.030 mm / min. A single crystal silicon ingot growth apparatus, which is provided in a single crystal silicon ingot growth apparatus, includes a crucible for storing a silicon melt, a heater for applying heat to the crucible, and a magnetic field applying unit for applying a magnetic field to the crucible. A method for growing a crystalline silicon ingot, comprising:
Determining the position of the maximum heating portion of the heater;
Determining a position of a maximum magnetic field plane (MGP) according to the determined position of the maximum heat generating part;
Applying the magnetic field to the crucible so that the MGP is formed at the determined position. The method for growing the single crystal silicon ingot is:
Adjusting the position of the MGP according to the changed position of the maximum heat generating part when the position of the maximum heat generating part is changed;
The method for growing a single crystal silicon ingot according to claim 21, further comprising: applying the magnetic field to the crucible to form the MGP at the adjusted position.   The method for growing a single crystal silicon ingot according to claim 21, wherein the magnetic field is applied to the crucible to form the MGP at a position lower than the position of the maximum heat generating portion.   The single crystal silicon according to claim 21, wherein the magnetic field is applied to the crucible to form the MGP at a position 20% to 40% lower than the position of the maximum heat generating portion with respect to the interface of the silicon melt. Ingot growth method.   The method for growing a single crystal silicon ingot according to claim 21, wherein the magnetic field is applied to the crucible to form the MGP at a position lower by 50 mm to 300 mm than the interface of the silicon melt.   26. The method for growing a single crystal silicon ingot according to claim 25, wherein a target pulling speed margin of the growing single crystal silicon ingot is 0.010 mm / min to 0.030 mm / min. A crucible containing molten silicon for growing a single crystal silicon ingot;
A heater that applies heat to the crucible so that the silicon in the crucible is melted;
A pulling portion for pulling up the single crystal silicon ingot while rotating;
A rotational angular velocity calculator for calculating a rotational angular velocity of the single crystal silicon ingot;
A first comparison unit that compares the calculated rotational angular velocity with a target rotational angular velocity and outputs the compared result as an angular velocity error value;
According to the angular velocity error value, a flow rate control unit that adjusts the flow rate of the molten silicon in a portion where the diameter of the growing single crystal silicon ingot is sensed,
A single crystal silicon ingot growth apparatus including a diameter sensing unit that senses a diameter of the single crystal silicon ingot. The single crystal silicon ingot growth apparatus further includes a second comparison unit that compares the sensed diameter with a target diameter and outputs the compared result as a diameter error value.
28. The single crystal silicon ingot growth apparatus according to claim 27, wherein the pulling unit pulls up the single crystal ingot while rotating the single crystal ingot at a pulling speed varied according to the diameter error value. A crucible containing molten silicon for growing a single crystal silicon ingot, a heater that applies heat to the silicon in the crucible to melt the silicon, and a pull that pulls up while rotating the single crystal silicon ingot A method for growing a single crystal silicon ingot performed in a single crystal silicon ingot growth apparatus including a portion,
Measuring the rotational angular velocity of the single crystal silicon ingot;
Comparing the measured rotational angular velocity with a target rotational angular velocity to determine an angular velocity error value;
Adjusting the flow rate of the molten silicon to a portion where the diameter of the growing single crystal silicon ingot is sensed using the angular velocity error value;
Sensing a diameter of the single crystal silicon ingot, and growing the single crystal silicon ingot. The method for growing a single crystal silicon ingot compares the sensed diameter with a target diameter to determine a diameter error value;
30. The method for growing a single crystal silicon ingot according to claim 29, further comprising varying a pulling rate of the growing single crystal silicon ingot using the diameter error value.   30. The method of growing a single crystal silicon ingot according to claim 29, wherein when the measured rotational angular velocity is larger than the target rotational angular velocity, the flow rate is decreased and adjusted. The portion where the diameter is sensed corresponds to the meniscus of the molten silicon,
30. The method for growing a single crystal silicon ingot according to claim 29, wherein the flow of the meniscus is stabilized by decreasing the flow rate of the molten silicon.   30. The method for growing a single crystal silicon ingot according to claim 29, wherein a pulling rate margin of the growing single crystal silicon ingot is 0.020 mm / min to 0.030 mm / min.

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