KR101379799B1 - Apparatus and method for growing monocrystalline silicon ingots - Google Patents

Abstract

The single crystal silicon ingot growth apparatus of the embodiment includes a crucible containing molten silicon for growing a single crystal silicon ingot, a heater that heats the crucible so that the silicon in the crucible is melted, and an impression portion for rotating while pulling the single crystal silicon ingot, A rotational angular velocity calculator for calculating the rotational angular velocity of the single crystal silicon ingot, a first comparison unit for comparing the calculated rotational angular velocity with the target rotational angular velocity and outputting the result as an angular velocity error value, and growing in accordance with the angular velocity error value A flow rate control unit for reducing the flow rate of the molten silicon in the portion where the diameter of the single crystal silicon ingot is sensed, and a diameter sensing unit for sensing the diameter of the single crystal silicon ingot.

Description

Apparatus and method for growing monocrystalline silicon ingots}

Embodiments relate to a single crystal silicon ingot growth apparatus and method.

In general, as a method of manufacturing a silicon wafer, a Floating Zone (FZ) method or a CZ (CZochralski) method is widely used. In the case of growing a single crystal silicon ingot by applying the FZ method, it is difficult to manufacture a large diameter silicon wafer, and there is a problem in that the process cost is very high. Therefore, it is general to grow a single crystal silicon ingot according to the CZ method.

According to the CZ method, polycrystalline silicon is charged into a quartz crucible, the graphite heating body is heated to melt it, and then seed crystals are immersed in the silicon melt formed as a result of melting and crystallization occurs at the interface of the melt, So that the single crystal silicon ingot is grown. Thereafter, the grown single crystal silicon ingot is sliced, etched and polished into a wafer shape.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram schematically showing the distribution of crystal defect regions according to V / G when a single crystal silicon ingot is grown. Fig. Here, V represents the pulling rate of the single crystal silicon ingot, and G represents the vertical temperature gradient in the vicinity of the solid-liquid interface.

According to the Voronkov theory, when a single crystal silicon ingot is pulled up at a high speed with a V / G of a predetermined threshold value or higher, a vacancy rich region in which void- Quot; V region "). In other words, the V region is a region in which vacancy is excessive due to lack of silicon atoms.

In addition, when a single crystal silicon ingot is pulled up to a V / G smaller than a predetermined threshold, the single crystal silicon ingot is grown to an O band region in which an oxidation induced stacking fault (OSF) exists.

Further, when the single crystal silicon ingot is pulled up at a low speed by further lowering the V / G ratio, a monocrystalline ingot grows in an interstitial region (hereinafter referred to as an 'I region') caused by a dislocation loop in which interstitial silicon is gathered do. In other words, the region I is a region in which agglomerates of silicon between lattice are large due to excess of silicon atoms.

Between the V region and the I region, there is a vacancy dominant defect free region (hereinafter, referred to as 'VDP region') and an interstitial dominant defect region (hereinafter referred to as 'IDP region'). The VDP region and the IDP region are the same in that they are regions of no lack or excess of silicon atoms, but the VDP region contains oxygen precipitation nuclei, while the IDP region does not contain oxygen precipitation nuclei.

There may be a small void area that belongs to the O band and has a fine sized vacancy defect, for example a direct surface oxide defect (DSOD).

At this time, in order to grow the single crystal ingot into the VDP region and the IDP region, the corresponding V / G should be maintained during growth of the single crystal silicon ingot. To this end, while growing a single crystal silicon ingot, the silicon wafer is cut out from the growing ingot, and the crystal defects of the cut wafer are evaluated to examine whether the ingot is growing as desired at the corresponding V / G. Based on the V / G, the single crystal ingot is grown in the VDP region or the IDP region.

As a method for evaluating crystal defects of a wafer, reactive ion etching (RIE), copper (Cu) deposition, Cu haze and the like are used.

On the other hand, as the line width of semiconductor devices is gradually reduced and highly integrated, the control and management of fine crystal defects occurring during the growth of single crystal silicon ingots becomes very important. For example, growth of an ingot having only crystal defects having a desired fineness is required even in defect regions such as a VDP region and an IDP region. In particular, in the case of a DRAM (Dynamic Random Access Memory), a NAND flash memory, etc., it is required that the silicon wafer has a crystal defect of a size smaller than 20 nm while the line width is narrowed to 20 nm or less.

However, the various conventional crystal defect evaluation methods described above can only detect crystal defects having a size larger than 30 nm and cannot properly evaluate crystal defects smaller than 30 nm. In other words, the existing crystal defect evaluation method only evaluates crystal defects having a size smaller than 30 nm as defects having the same size in a batch. Therefore, there is a problem that it is difficult to manufacture a silicon wafer or ingot having a crystal defect of a size smaller than 30 nm, for example, 10 nm to 29 nm.

The embodiment provides a single crystal silicon ingot growth apparatus and method for fabricating a silicon wafer having fine size crystal defects.

A single crystal silicon ingot growth apparatus of an embodiment includes a crucible containing molten silicon for growing a single crystal silicon ingot; A heater for applying heat to the crucible so that silicon in the crucible is melted; An impression portion for pulling up while rotating the single crystal silicon ingot; A rotational angular velocity calculator configured to calculate a rotational angular velocity of the single crystal silicon ingot; A first comparing unit comparing the calculated rotational angular velocity with a target rotational angular velocity and outputting the compared result as an angular velocity error value; A flow rate controller which reduces a flow rate of the molten silicon in a portion where the diameter of the grown single crystal silicon ingot is sensed according to the angular velocity error value; And a diameter sensing unit configured to sense the diameter of the single crystal silicon ingot.

The single crystal silicon ingot growth apparatus further includes a second comparison unit which compares the sensed diameter with a target diameter and outputs the compared result as a diameter error value, wherein the pulling unit has a pulling speed that is variable according to the diameter error value. The single crystal ingot can be pulled while rotating.

According to another embodiment, a single crystal including a crucible containing molten silicon for growing a crystalline silicon ingot, a heater to heat the silicon in the crucible to melt the silicon, and an impression portion that is pulled while rotating the single crystal silicon ingot. A single crystal silicon ingot growth method of a silicon ingot growth apparatus includes measuring a rotational angular velocity of the single crystal silicon ingot; Determining an angular velocity error value by comparing the measured rotational angular velocity with a target rotational angular velocity; Using the angular velocity error value, reducing the flow rate of the molten silicon in a portion where the diameter of the grown single crystal silicon ingot is sensed; And sensing the diameter of the single crystal silicon ingot.

The single crystal silicon ingot growth method may further include determining a diameter error value by comparing the sensed diameter with a target diameter; And using the diameter error value, varying a pulling speed of the grown single crystal silicon ingot.

When the measured rotational angular velocity is greater than the target rotational angular velocity, the flow velocity may be reduced.

The diameter sensing portion corresponds to the meniscus of the molten silicon, the flow rate of the meniscus can be stabilized by reducing the flow rate of the molten silicon.

For example, the pulling speed margin of the above-described grown single crystal silicon ingot may be 0.020 mm / min to 0.030 mm / min.

The growth method and apparatus according to the embodiment controls the pulling speed after stabilizing the flow of the meniscus in which the diameter of the single crystal silicon ingot is sensed, so that the pulling speed can be controlled more accurately,

Promote the recombination of bacon and interstitial as it not only determines the location of the maximum gauge field (MGP) based on the position of the maximum heating part, but also controls the convection of the silicon melt by adjusting the strength of the magnetic field appropriately. To increase the margin of the IDP area,

The productivity and growth rate of the ingot can be increased, for example, by increasing the reproducibility of producing a silicon wafer having a high quality, which is easy to produce a silicon wafer having a crystal defect of 20 nm or less as described above.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram schematically showing the distribution of crystal defect regions according to V / G when a single crystal silicon ingot is grown. Fig.
2 is a view showing a single crystal ingot growth apparatus according to the embodiment.
3 is a diagram illustrating the distribution of single crystal growth rate and crystal defects according to the present embodiment.
4 is a plan view of a silicon wafer according to an embodiment.
5 is a plan view of a silicon wafer according to another embodiment.
6A shows a plan view of a wafer sample after applying the Cu haze method to the wafer sample, and FIGS. 6B and 6C show images of the wafer sample taken by the magic method.
7 is a graph in which a relationship between each pixel and a volume of an image acquired by the magic method is analyzed by TEM.
8 illustrates an image of a crystal defect corresponding to pixel 1 photographed using a TEM.
9 is a graph showing a histogram of pixels.
10 is a flowchart for explaining a single crystal silicon ingot growth method according to the embodiment.
11A and 11B are graphs showing the trajectory of the pulling speed of the ingot.
12 is a diagram showing the margin of the pulling speed according to the previous and the present embodiment.
13 is a flowchart for explaining a method of growing a single crystal silicon ingot according to another embodiment.
14A shows the maximum value of the IDP margin according to the position of the MGP, and FIG. 14B shows a 70% value of the maximum value of the IDP margin according to the position of the MGP.
FIG. 15A shows the maximum value of the IDP margin according to the strength of the magnetic field, and FIG. 15B shows the 70% value of the maximum value of the IDP margin according to the strength of the magnetic field.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate understanding of the present invention. However, the embodiments according to the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the invention are provided to more fully describe the present invention to those skilled in the art.

2 is a view showing the single crystal ingot growth apparatus 100 according to the embodiment.

The single crystal ingot growth apparatus 100 shown in FIG. 2 includes a crucible 10, a support shaft driver 16, a support rotation shaft 18, a silicon melt 20, an ingot 30, a seed crystal 32, and wire pulling. The part 40, the pulling wire 42, the heat shielding member 50, the heater 60 arrange | positioned around the crucible 10, the heat insulating material 70, the magnetic field applying part 80, the diameter sensing part 90 The rotational angular velocity calculator 92, the first comparator 94, the flow rate controller 96, the second comparator 110, and the first and second controllers 120 and 130 are included.

2, the single crystal silicon ingot growth apparatus 100 according to the present embodiment grows the single crystal silicon ingot 30 as follows by the CZ method.

First, in the crucible 10, a high-purity polycrystalline silicon raw material is heated by a heater 60 at a temperature not lower than the melting point temperature, and is converted into a silicon melt 20. At this time, the crucible 10 containing the silicon melt 20 has a double structure in which the inside is made of quartz 12 and the outside is made of graphite 14.

Thereafter, the lifting section 40 unwinds the pull-up wire 42 to bring the tip of the seed crystal 32 into contact with or immerse the roughly central portion of the surface of the silicon melt 20. At this time, the silicon seed crystal 32 can be held using a seed chuck (not shown).

The supporting shaft driving unit 16 rotates the supporting rotary shaft 18 of the crucible 20 in the same direction as the arrow and the pulling unit 40 rotates the ingot 30 by the pulling wire 42, . At this time, the circumferential single crystal silicon ingot 30 can be completed by controlling the speed V and the temperature gradients G and G to pull up the ingot 30.

The thermal member 50 is disposed to surround the ingot 30 between the single crystal silicon ingot 30 and the crucible 10 and serves to block heat radiated from the ingot 30.

3 is a diagram illustrating the distribution of single crystal growth rate and crystal defects according to the present embodiment.

The defect distribution of the single crystal silicon ingot shown in Fig. 3 is the same as the defect distribution of the single crystal silicon ingot shown in Fig. 2, except that the transition region is further defined, so that the V region, the small void region, the O band region, The detailed description of the IDP region and the I region will be omitted. Here, the transition region is defined as a region that predominantly has crystal defects having a size of 10 nm to 30 nm among the crystal defects included in at least one of the VDP region and the IDP region. The predominant degree may mean more than 50%. That is, among the total crystal defects included in the transition region, crystal defects having a size of 10 nm to 30 nm may be more than 50%. That is, among the total crystal defects included in the transition region, crystal defects having a size of 10 nm to 30 nm may occupy k% or more (where 50 ≦ k ≦ 100).

For example, the size of crystal defects predominantly contained in the transition region may be between 10 nm and 19 nm. Such a transition region may not include crystal defects belonging to an O band or an I region which is a ring-shaped oxidized organic stacked defect region.

If the apparatus shown in Fig. 2 grows the ingot 30 to any V / G selected within the range of the target V / G (hereinafter referred to as 'T (VG)'), the ingot according to the present embodiment (30) or the silicon wafer may predominantly have crystal defects of the size of 10 nm to 30 nm.

4 shows a plan view of the silicon wafer 5A according to the embodiment, and FIG. 5 shows a plan view of the silicon wafer 5B according to another embodiment.

When the ingot 30 is grown to a V / G value of 4-4 'within T (VG) shown in FIG. 3, the ingot 30 or silicon wafer 5A is crystalline defect as shown in FIG. It can have a distribution. In this case, the distribution of the transition region of the silicon wafer 5A spans both the VDP region 142 and the IDP region 140.

Alternatively, when the ingot 30 is grown at a V / G value of 5-5 'in T (VG) shown in FIG. 3, the silicon wafer 5B has a crystal defect distribution as shown in FIG. 5 . In this case, the distribution of the transition region of the silicon wafer 5B spans only the IDP region 150. [ That is, the distribution of the transition region of the silicon wafer 5B does not extend over the VDP region.

Alternatively, when the ingot 30 is grown to a V / G value of 6-6 'in T (VG) shown in FIG. 3, the distribution of the transition region of the silicon wafer spans only the VDP region. In other words, the distribution of the transition region of the silicon wafer does not span the IDP region.

As a result, in the silicon wafer according to the present embodiment, the IDP region may occupy m% in the entire transition region as in Equation 1 below, and the VDP region may occupy n% in the entire transition region as in Equation 2 below.

Where 0 ≦ x ≦ 1.

For example, based on the diameter of the silicon wafer, the IDP region may occupy 70% or more of the entire transition region, and the VDP region may occupy less than 30% of the entire transition region. At this time, in the silicon wafer 5A formed of the transition region as illustrated in FIG. 4, the VDP region is located at the edge of the silicon wafer 5A and the IDP region is located at the center of the inside of the edge of the silicon wafer 5A . Alternatively, based on the diameter of the silicon wafer, the VDP region may occupy 70% or more of the entire transition region, and the IDP region may occupy less than 30% of the entire transition region. 4, the IDP region may be located at the edge of the silicon wafer, and the VDP region may be located at the center of the inner edge of the silicon wafer. However, without being limited to this, in the transition region of the silicon wafer, the VDP region and the IDP region can be located in various forms.

On the other hand, while growing the ingot with V / G in the above-described T (VG), the ingot 30 can be grown to V / G out of the T (VG) initially set by various factors. Therefore, it is necessary to evaluate whether the ingot 30 is grown in a transition region which predominantly has crystal defects having a desired size of 10 nm to 30 nm. To this end, the present embodiment uses the Magics method.

In general, according to the conventional magic method, when a wafer sample is taken and an image is obtained, various pixels are displayed on the image in different colors. At this time, it is inferred that the defects of the wafer sample are caused in the growth process, the slicing process, the etching process, and the polishing process based on the pattern formed by the pixels. As such, the existing Magics method has only been used to evaluate the source of defects. However, the applicant has detected the size of the crystal defect by the following method using the above-mentioned magic method.

Hereinafter, whether the crystal defects smaller than 30 nm in the crystal defects included in the wafer sample cut out from the growing single crystal silicon ingot 30 is dominant (that is, whether the wafer sample is formed as a transition region) or not. The method of evaluation by a law is demonstrated with reference to attached drawing as follows.

First, while growing a 12-inch diameter (300 mm) single crystal silicon ingot, a wafer sample is prepared by cutting the ingot in a horizontal direction perpendicular to the growing direction of the ingot.

6A shows a plan view of a wafer sample after applying the Cu haze method to the wafer sample, and FIGS. 6B and 6C show images of the wafer sample taken by the magic method. In FIG. 6B, the image obtained by the magic method displays pixels separated by different colors, but since the drawing is shown in black and white, the color of pixel 1 is represented by a circle (o) for understanding. , And the color of the pixel 2 is indicated by dividing by ☆, and the color of the pixel 3 is indicated by dividing by Δ. In addition, the image of FIGS. 6B and 6C may display only a few pixels (ie, pixels 1 to 3), but may not be limited thereto.

If, according to the existing crystal defect evaluation method, for example, the Cu haze method, as shown in Fig. 6A, the VDP region is displayed in black and the IDP region is displayed in white in the wafer sample. Therefore, according to the Cu haze method, it was not possible to evaluate how predominantly a crystal defect having a size smaller than 30 nm among the crystal defects contained in the VDP region and the IDP region. That is, according to the existing crystal defect evaluation method, a silicon wafer formed of a transition region having predominantly only crystal defects having sizes of 10 nm to 19 nm smaller than 30 nm could not be produced.

However, according to this embodiment, it can be evaluated as follows whether the wafer sample predominantly has a crystal defect having a size smaller than 30 nm.

First, photographing a wafer sample with a camera (not shown) results in an image as illustrated in FIG. 6B or 6C showing pixels of different colors (eg, pixels 1 to 3).

At this time, the applicant reviewed the image shown in FIG. 6B or 6C with a scanning electron microscope (SEM), and then observed with a transmission electron microscope (TEM) to determine the pixel-by-pixel determination. The volume of defects could be identified. That is, it was found that the size of crystal defects can be evaluated according to the kind of pixels through the image photographed by the magic method.

7 is a graph in which the relationship between each pixel and volume of an image obtained by the magic method is analyzed by TEM, where the horizontal axis represents pixel number and the vertical axis represents volume. Here, the correlation coefficient (R ²⁾ is 0.9, the correlation equation was y = 3427.7x ² - may be 4700.4x + 23968.

8 illustrates an image of a crystal defect corresponding to pixel 1 photographed using a TEM. Here, [100] and [011] indicate the direction of the grating.

Since the TEM is a device capable of detecting the size and type of crystal defects having the size of Angstrom units, each pixel was photographed by a TEM as shown in FIG. 8 to evaluate the size of the crystal defects for each pixel. In addition, many pixels were photographed by TEM, and it was found that the size of each pixel defect had a correlation as shown in FIG. 7. Referring to FIG. 7, it can be seen that as the number of pixels decreases, the volume of crystal defects decreases. This suggests that the smaller the pixel number, the smaller the size of the crystal defect. 8, it can be seen that the size of the crystal defect of the pixel 1 has a size of approximately 10 nm to 19 nm.

Therefore, the specific size of the crystal defect with a size smaller than 30 nm which cannot be previously evaluated can be detected through the pixel displayed on the image photographed by the magic method.

9 is a graph showing a histogram of pixels, where the horizontal axis represents pixel numbers and the vertical axis represents the frequency of each pixel.

A histogram of each pixel as shown in FIG. 9 is generated from the image of the wafer sample. The frequency (or density) of each pixel number in the histogram can then be evaluated to determine the size of the crystal defects contained in the wafer sample.

Hereinafter, a wafer sample having predominantly crystal defects having a size corresponding to pixel 1 is prepared.

For example, in the image of the wafer sample shown in Fig. 6B, the colors (o, ☆, Δ) from pixel 1 to pixel 3 are displayed at the edges, while the color of pixel 1 (o is located at the center inside the edge. ) Is only displayed. The histogram curve 200 illustrated in FIG. 9 is obtained from the image illustrated in FIG. 6B. At this time, since the frequency corresponding to pixel number 1 is larger than the threshold frequency, it is determined that the silicon wafer is formed as a transition region having a crystal defect of the size corresponding to pixel 1 predominantly. Here, the critical frequency is determined according to the degree of preponderance. For example, when the degree of predominance is k% described above, the threshold frequency means k% of the total number of pixels. That is, in this case, since the ingot 30 is growing to V / G in T (VG), the wafer sample shown in Fig. 6B is a silicon wafer formed as a transition region in which crystal defects of a desired size are predominant.

If V / G becomes a little lower in T (VG), the image of the wafer sample taken by the magic method may be as shown in FIG. 6C. In this case, since the silicon wafer was formed into a transition region in which crystal defects in the IDP region predominantly included, the result is also passed.

However, when the histogram curve 202 shown in FIG. 9 is obtained, the frequency corresponding to pixel number 1 is smaller than the threshold frequency, and instead, the frequency corresponding to pixel 2 is greater than the threshold frequency, so that the silicon wafer is pixel 2. It fails because it has a predominantly crystal defect of the size corresponding to. Accordingly, the silicon wafer according to the present embodiment can be manufactured by lowering the V / G value out of T (VG) by ΔV / G so that the ingot 30 grows to V / G in T (VG).

If the size of the crystal lattice for each pixel number is predetermined through FIG. 7 and V / G corresponding to the size of each crystal defect is predetermined, ΔV / G can be easily obtained. In FIG. 9, ΔV / G can be obtained by subtracting V / G corresponding to the size of the crystal defect corresponding to the pixel 1 from V / G corresponding to the size of the crystal defect corresponding to the pixel 2. At this time, when DELTA V / G is adjusted so that the frequency of pixel 1 is greater than the frequency of pixel 2 (202-> 200), the frequency distribution increases. Therefore, in consideration of this, it is possible to determine the value of ΔV / G.

As described above, according to this embodiment, whether the size of the crystal defect included in the cut wafer sample is smaller than 30 nm, for example, 10 nm to 19 nm can be evaluated by the magic method as described above. . Therefore, when V / G growing the single crystal silicon ingot 30 is out of the range of T (VG), the silicon wafer according to the present embodiment can be precisely adjusted so that V / G falls within T (VG). It can be seen that only the transition region having a crystalline defect of 10 nm to 30 nm in size among the crystal defects included in at least one of the VDP region and the IDP region is formed.

In addition, according to the present embodiment, when evaluating the size of crystal defects included in the wafer sample by the magic method, an additional pretreatment step such as heat treatment of the wafer sample does not need to be performed. Therefore, the wafer sample can be evaluated more quickly and immediately fed back to reflect the growing ingot growth process, thereby reducing the production time.

Hereinafter, a single crystal silicon ingot growth apparatus and method for manufacturing a silicon wafer according to the above-described embodiment will be described with reference to the accompanying drawings as follows. However, the single crystal silicon ingot growth apparatus and method described below can be used not only for manufacturing the silicon wafer according to the present embodiment but also for manufacturing a general silicon wafer.

10 is a flowchart for explaining a single crystal silicon ingot growth method according to the embodiment.

2 and 10, the rotational angular velocity of the single crystal silicon ingot 30 is calculated (step 302). To this end, the rotational angular velocity calculation unit 92 uses the speed at which the ingot 30 provided from the pulling unit 40 rotates and the diameter of the sensed ingot 30 provided from the diameter sensing unit 90, thereby making the ingot 30 inert. The rotational angular velocity of 30 can be calculated.

After operation 302, the first comparator 94 compares the rotational angular velocity calculated by the rotational angular velocity calculator 92 with the target rotational angular velocity TSR, and compares the result to the flow rate controller 96 as an angular velocity error value. Output (step 304).

After the 304th step, the flow rate control unit 96 determines the diameter of the molten silicon 20 in the portion 34 where the diameter of the grown single crystal silicon ingot 30 is sensed according to the angular velocity error value received from the first comparator 94. Reduce the flow rate (step 306). To this end, the flow rate controller 96 may control the pull-up section 40 and / or the support shaft driver 16 to reduce the flow rate. That is, the flow rate control unit 96 controls the rotation speed of the ingot 30 through the lifting unit 40, and controls the rotation speed of the crucible 10 through the support shaft driving unit 16. If it is determined through the angular velocity error value that the measured rotational angular velocity is greater than the target rotational angular velocity TSR, the flow velocity control unit 96 reduces the flow velocity. When the portion 34 whose diameter is sensed corresponds to the meniscus of the silicon melt 20, the flow of the silicon melt 20 can be reduced to stabilize the flow of the meniscus.

After operation 306, the diameter sensing unit 90 senses the diameter of the single crystal silicon ingot 30 (operation 308).

After operation 308, the second comparator 110 compares the diameter sensed by the diameter sensing unit 90 with the target diameter TD, and outputs the compared result as the diameter error value to the pulling unit 40 ( Step 310).

After step 310, the pulling unit 40 varies the pulling speed of the grown single crystal silicon ingot 30 according to the diameter error value and pulls it while rotating the single crystal silicon ingot 30 at the variable pulling speed. Step 312). Thus, according to the diameter error value, the pulling speed of the grown single crystal silicon ingot 30 can be adjusted.

11A and 11B are graphs showing the trajectory of the pulling speed V of the ingot 30, wherein the horizontal axis represents time and the vertical axis represents the pulling speed V.

12 is a diagram showing a margin of the pulling speed according to the present embodiment and the present embodiment. Here, the P band represents a boundary between the small void region and the O band shown in FIG.

Generally, the pulling portion 40 controls the pulling speed of the single crystal silicon ingot 30 in accordance with the diameter sensed in the diameter sensing portion 90. For example, when the diameter of the sensed ingot 30 of the diameter sensing portion 90 is larger than the target diameter TD, the pulling portion 40 is positioned at a position where the ingot 30 ). However, if the sensed diameter of the diameter sensing portion 90 is smaller than the target diameter TD, the pulling portion 40 lowers the pulling speed of the ingot 30 because the actual diameter is smaller than the target diameter. At this time, the maniscus 34, the portion of which the diameter is sensed, may be unstable because the flow rate of the node or the silicon melt 20 generated during the growth of the ingot 30 is affected by the strength. As described above, even when the meniscus 34 is unstable, when the pulling speed is adjusted by the measured diameter sensed through the unstable meniscus 34, as shown in FIG. 11A, the pulling speed is T (VG). The width 322 that fluctuates outside the target trajectory 320 of the pulling speed within can be very large. In this case, as shown in FIG. 12, the ingot 30 or the silicon wafer, which may be defectively processed, including crystal defects in the V region or the I region may be increased (see 330).

On the contrary, in the present embodiment, in order to solve the above-mentioned problem, after stabilizing the flow of the meniscus 34 through the aforementioned steps 302 to 306, the diameter is accurately sensed by the diameter sensing unit 90. And adjust the pulling speed based on the accurately sensed values. Therefore, as shown in FIG. 11B, the width 324 in which the pulling speed V fluctuates out of the trajectory 320 of the target pulling speed is reduced. Therefore, referring to FIG. 12, the pulling speed margin of the grown single crystal silicon ingot 30 is 0.010 mm / min to 0.030 mm of the present embodiment L2 from 0.015 mm / min to 0.016 mm / min of the existing L1. / min, for example 0.025 mm / min. Accordingly, as shown in FIG. 12, in the case of the wafer sample, it can be seen that there are no ingots 30 or silicon wafers that can be treated poorly, including crystal defects in the P region and the I region (see 332). ). This not only increases productivity by 10% or more with the same amount of silicon melt 20, but also improves the growth rate of the ingot 30 by 10% or more.

13 is a flowchart for explaining a method of growing a single crystal silicon ingot according to another embodiment.

2 and 13, the first controller 120 determines the position 62 of the maximum heating part of the heater 60 (operation 402).

After operation 402, the second controller 130 determines the position of the maximum magnetic field plan (MGP) according to the determined position 62 of the maximum heating part of the heater 60 received from the first controller 120. (Step 404). Here, MGP means a portion where the horizontal component of the magnetic field generated from the magnetic field applying unit 80 becomes maximum. The magnetic field applying unit 80 is thermally isolated from the heater 60 by the heat insulating material 70.

The heater 60 may generate heat uniformly in the vertical direction or may control the amount of heat generated in the vertical direction. If the heater 60 uniformly generates heat in the vertical direction, the maximum heat generating portion is located slightly above the center or the center of the heater 60. However, in the case where the heater 60 can adjust the calorific power in the vertical direction, the maximum calorific portion can be arbitrarily adjusted.

After operation 404, the second controller 130 controls the magnetic field applying unit 80 to apply the magnetic field to the crucible 10 so that the MGP is formed at the determined position (operation 406).

Thereafter, when the position of the maximum heating unit is changed in operation 408, the position of the MGP is adjusted according to the changed position 62 of the maximum heating unit (operation 410). The first control unit 120 may control the heater 60 to change the position 62 of the maximum heat generating unit. When the heater 60 moves, the position 62 of the maximum heat generating portion can also be changed. The second controller 130 checks the changed position 62 of the maximum heating part through the first controller 120 and adjusts the position where the MGP is formed according to the changed position.

After operation 410, the second controller 130 controls the magnetic field applying unit 80 to form the MGP at the adjusted position and applies the magnetic field to the crucible 10 (operation 412).

According to an embodiment, the MGP may be determined to be located below the position 62 of the maximum heating portion. For example, the MGP may be located 20% to 40% lower than the position 62 of the maximum heating part based on the interface of the silicon melt 20. That is, if the position 62 of the maximum heat generating portion is spaced apart from the interface of the silicon melt 20 by the first distance D1, the MGP is 20% to 40 greater than the first distance D1 from the interface of the silicon melt 20. The second distance may be spaced apart by a second distance D2. The second distance D2 may be between 50 mm and 300 mm, for example, 150 mm.

14A shows the maximum value of the IDP margin according to the position of the MGP, and FIG. 14B shows a 70% value of the maximum value of the IDP margin according to the position of the MGP. In each graph, the vertical axis represents the position of the MGP, and the position of the MGP is set to '0' at the interface of the silicon melt 20, and the negative value increases toward the bottom of the interface.

Referring to FIGS. 14A and 14B, the MGP may be located at −50 mm to −300 mm, and when it is −150 mm, the margin of the IDP may be maximized.

On the other hand, not only the convection of the silicon melt 20 can be controlled by adjusting the position 62 of the maximum heat generating part and the position of the MGP, but also the silicon melt by the strength of the magnetic field applied by the magnetic field applying part 80. Convection of 20 can be controlled. For example, the magnetic field applied to the crucible 10 by the magnetic field applying unit 80 may be 2000 to 3400 gauss, and when it is 2800 gauss, the IDP margin may be maximized.

FIG. 15A shows the maximum value of the IDP margin according to the strength of the magnetic field, and FIG. 15B shows the 70% value of the maximum value of the IDP margin according to the strength of the magnetic field. In each graph, the vertical axis represents the strength of Gaussian, and the horizontal axis represents the strength of the magnetic field in Gaussian.

Referring to FIGS. 15A and 15B, when the intensity of the magnetic field is 2800 gauss, the margin of the IDP may be increased from 0.007 mm / min to 0.010 mm / min to 0.030 mm / min, for example, from 0.020 mm / min to IDP margins can be improved by 0.022 mm / min.

As such, when the margin of the IDP increases, the length section of 1250 ° C to 1420 ° C, which is a temperature region in which the IDP region is formed, is extended, which makes the silicon wafer fabrication conditions much easier.

In general, when the rotational angular velocity of the single crystal silicon ingot 30 is changed, the convexity at the interface of the silicon melt 20 and the temperature gradient in the growth direction of the ingot 30 (G = Gs + Gm) (where Gs is the ingot Gm denotes the temperature gradient of the silicon melt 20, and a radial temperature gradient difference (ΔG = Gse−) of the ingot 30 at the portion in contact with the ingot 30 and the silicon melt 20. Gsc) (where Gse and Gsc represent the temperature gradients at the edge and the center of the ingot 30, respectively), the concentration of oxygen contained in the ingot 30, between the ingot 30 and the silicon melt 20 And the size of the subcooled region formed in the. For example, when the rotational angular velocity of the silicon ingot 30 increases, the interface of the silicon melt 20 becomes very convex, the temperature gradient G becomes large, the temperature gradient difference DELTA G decreases, and the oxygen concentration decreases. Good quality ingots 30 can be produced but control of the pulling speed becomes difficult. On the contrary, when the rotational angular velocity of the silicon ingot 30 decreases, the interface of the silicon melt 20 becomes flat, the temperature gradient G decreases, the temperature gradient difference ΔG increases, and the oxygen concentration increases. Quality ingots 30 can be created but control of the pulling speed is easy. However, due to the magnetic field, these relationships can be distorted. Also, in general, the silicon melt 20 shown in FIG. 2 is convection in the arrow direction 22 by the rotation of the ingot 30 and in the arrow direction 24 by the rotation of the crucible 10. However, convection of the silicon melt 20 may be blocked at the top and bottom of the MGP.

Unlike the conventional method, according to the present embodiment described above, the MGP is determined in consideration of the convection of the silicon melt according to the position of the maximum heating part, and the convection of the silicon melt 20 is controlled by appropriately adjusting the intensity of the magnetic field. Therefore, it is possible to compensate for the above-described problem that may be caused while changing the rotational angular velocity. That is, when the MGP is 20% to 40% lower from the interface of the silicon melt 20 than the position 62 of the maximum heat generating site, convection becomes strong toward the center of the ingot 30 in the direction of the arrow 22 so that the baconsie It is possible to secure the recombination interval between the and interstitial, which increases the margin of the IDP region.

In this embodiment, the lacquer shown in FIG. 2 was used to grow a silicon wafer or ingot formed into a transition region predominantly having crystal defects of the size of 10 nm to 30 nm. However, the growth apparatus shown in FIG. 2 performing the method shown in FIGS. 10 and 13 described above is merely exemplary, and for performing each step, an Automatic Growing Controller (AGC) (not shown) ) Or an automatic temperature controller (ATC) (not shown) may be used.

Further, the above-described single crystal silicon ingot growth method shown in Figs. 10 and 13 may be used simultaneously, and only one of them may be used. In addition, in order to fabricate the silicon wafer according to the present embodiment, the pressure / flow rate of an inert gas such as argon gas, which is a cooling gas, in addition to the rotational angular velocity of the single crystal silicon ingot 30, the MGP, the strength of the magnetic field, and the position of the maximum heat generating site. , A melt gap between the interface of the heat shield member 50 and the silicon melt 20, the shape of the heat shield member 50, the number of heaters 60, and the rotational speed of the crucible 10 may be further used. Of course.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications are possible. For example, each component specifically shown in the embodiments can be modified and implemented. It is to be understood that all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

10: crucible 16: support shaft driving part
18: support rotating shaft 20: silicon melt
30: ingot 32: seed crystal
40: wire lifting part 42: pulling wire
50: heat shield member 60: heater
70: Insulation material 80: Magnetic field application part
90: diameter sensing unit 92: rotational angular velocity calculation unit
94: first comparator 96: flow rate controller
110: second comparison unit 120, 130: first and second control units

Claims (7)

A crucible for containing molten silicon for growing a single crystal silicon ingot;
A heater for applying heat to the crucible so that silicon in the crucible is melted;
An impression portion for pulling up while rotating the single crystal silicon ingot;
A rotational angular velocity calculator configured to calculate a rotational angular velocity of the single crystal silicon ingot;
A first comparing unit comparing the calculated rotational angular velocity with a target rotational angular velocity and outputting the compared result as an angular velocity error value;
A flow rate controller for reducing the flow rate of the molten silicon in a portion where the diameter of the single crystal silicon ingot is sensed according to the angular velocity error value; And
Single crystal silicon ingot growth apparatus comprising a diameter sensing unit for sensing the diameter of the single crystal silicon ingot. The apparatus of claim 1, wherein the single crystal silicon ingot growth apparatus is
Comprising a second comparison unit for comparing the sensed diameter and the target diameter, and outputs the comparison result as a diameter error value,
And the pulling portion is pulled while rotating the single crystal ingot at a pulling speed that is variable according to the diameter error value. A crucible containing molten silicon for growing a single crystal silicon ingot, a heater for heating the silicon in the crucible to melt the silicon, and an impression portion for pulling up while rotating the single crystal silicon ingot. In the silicon ingot growth method,
Measuring a rotational angular velocity of the single crystal silicon ingot;
Determining an angular velocity error value by comparing the measured rotational angular velocity with a target rotational angular velocity;
Reducing the flow rate of the molten silicon in a portion where the diameter of the single crystal silicon ingot is sensed using the angular velocity error value; And
The method of growing a single crystal silicon ingot comprising the step of sensing the diameter of the single crystal silicon ingot. The method of claim 3, wherein the single crystal silicon ingot growing method is
Comparing the sensed diameter with a target diameter to determine a diameter error value; And
And varying the pulling speed of the single crystal silicon ingot using the diameter error value. 4. The method of claim 3, wherein the flow rate is reduced when the measured rotational angular velocity is greater than the target rotational angular velocity. The method of claim 3, wherein the diameter sensing portion corresponds to a meniscus of the molten silicon.
Single crystal silicon ingot growth method to stabilize the flow of the meniscus by reducing the flow rate of the molten silicon. The method of claim 3, wherein the pulling speed margin of the single crystal silicon ingot is 0.020 mm / min to 0.030 mm / min.

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