JP2015513737A5 - - Google Patents

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Publication number
JP2015513737A5
JP2015513737A5 JP2014558964A JP2014558964A JP2015513737A5 JP 2015513737 A5 JP2015513737 A5 JP 2015513737A5 JP 2014558964 A JP2014558964 A JP 2014558964A JP 2014558964 A JP2014558964 A JP 2014558964A JP 2015513737 A5 JP2015513737 A5 JP 2015513737A5
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JP
Japan
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gpu
instructions
execution model
pipeline topology
platform
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JP2014558964A
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English (en)
Japanese (ja)
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JP6077018B2 (ja
JP2015513737A (ja
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Priority claimed from US13/777,663 external-priority patent/US9430807B2/en
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Publication of JP2015513737A publication Critical patent/JP2015513737A/ja
Publication of JP2015513737A5 publication Critical patent/JP2015513737A5/ja
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Publication of JP6077018B2 publication Critical patent/JP6077018B2/ja
Expired - Fee Related legal-status Critical Current
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JP2014558964A 2012-02-27 2013-02-27 異種cpu−gpu計算のための実行モデル Expired - Fee Related JP6077018B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201261603771P 2012-02-27 2012-02-27
US61/603,771 2012-02-27
US13/777,663 2013-02-26
US13/777,663 US9430807B2 (en) 2012-02-27 2013-02-26 Execution model for heterogeneous computing
PCT/US2013/028029 WO2013130614A1 (en) 2012-02-27 2013-02-27 Execution model for heterogeneous cpu-gpu computing

Publications (3)

Publication Number Publication Date
JP2015513737A JP2015513737A (ja) 2015-05-14
JP2015513737A5 true JP2015513737A5 (enExample) 2016-12-08
JP6077018B2 JP6077018B2 (ja) 2017-02-08

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JP2014558964A Expired - Fee Related JP6077018B2 (ja) 2012-02-27 2013-02-27 異種cpu−gpu計算のための実行モデル

Country Status (5)

Country Link
US (1) US9430807B2 (enExample)
EP (1) EP2820540B1 (enExample)
JP (1) JP6077018B2 (enExample)
CN (1) CN104137070B (enExample)
WO (1) WO2013130614A1 (enExample)

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US9983857B2 (en) * 2015-06-16 2018-05-29 Architecture Technology Corporation Dynamic computational acceleration using a heterogeneous hardware infrastructure
US9972063B2 (en) * 2015-07-30 2018-05-15 International Business Machines Corporation Pipelined approach to fused kernels for optimization of machine learning workloads on graphical processing units
US10387988B2 (en) * 2016-02-26 2019-08-20 Google Llc Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform
EP3520041A4 (en) 2016-09-30 2020-07-29 Rigetti & Co., Inc. SIMULATION OF QUANTUM SYSTEMS WITH QUANTUM CALCULATION
CN106776014B (zh) * 2016-11-29 2020-08-18 科大讯飞股份有限公司 异构计算中的并行加速方法及系统
US10614541B2 (en) 2017-06-29 2020-04-07 Nvidia Corporation Hybrid, scalable CPU/GPU rigid body pipeline
US10726605B2 (en) * 2017-09-15 2020-07-28 Intel Corporation Method and apparatus for efficient processing of derived uniform values in a graphics processor
US10580190B2 (en) 2017-10-20 2020-03-03 Westghats Technologies Private Limited Graph based heterogeneous parallel processing system
US11163546B2 (en) * 2017-11-07 2021-11-02 Intel Corporation Method and apparatus for supporting programmatic control of a compiler for generating high-performance spatial hardware
CN110401598A (zh) * 2018-04-25 2019-11-01 中国移动通信集团设计院有限公司 管线拓扑自动发现方法、装置及系统
EP3794520A4 (en) 2018-05-18 2022-03-23 Rigetti & Co. LLC COMPUTING PLATFORM WITH HETEROGENOUS QUANTUM PROCESSORS
WO2020140257A1 (en) * 2019-01-04 2020-07-09 Baidu.Com Times Technology (Beijing) Co., Ltd. Method and system for validating kernel objects to be executed by a data processing accelerator of a host system
US10997686B2 (en) * 2019-01-09 2021-05-04 Intel Corporation Workload scheduling and distribution on a distributed graphics device
CN111159897B (zh) * 2019-12-31 2023-11-03 新奥数能科技有限公司 基于系统建模应用的目标优化方法和装置
CN114330689B (zh) * 2021-12-29 2025-02-07 北京字跳网络技术有限公司 数据处理方法、装置、电子设备及存储介质
US20240095024A1 (en) * 2022-06-09 2024-03-21 Nvidia Corporation Program code versions

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