JP2015502618A5 - - Google Patents

Download PDF

Info

Publication number
JP2015502618A5
JP2015502618A5 JP2014547504A JP2014547504A JP2015502618A5 JP 2015502618 A5 JP2015502618 A5 JP 2015502618A5 JP 2014547504 A JP2014547504 A JP 2014547504A JP 2014547504 A JP2014547504 A JP 2014547504A JP 2015502618 A5 JP2015502618 A5 JP 2015502618A5
Authority
JP
Japan
Prior art keywords
queue
priority
processing
circuit
pipeline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2014547504A
Other languages
English (en)
Japanese (ja)
Other versions
JP2015502618A (ja
JP6189858B2 (ja
Filing date
Publication date
Priority claimed from US13/325,286 external-priority patent/US20130155077A1/en
Application filed filed Critical
Publication of JP2015502618A publication Critical patent/JP2015502618A/ja
Publication of JP2015502618A5 publication Critical patent/JP2015502618A5/ja
Application granted granted Critical
Publication of JP6189858B2 publication Critical patent/JP6189858B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2014547504A 2011-12-14 2012-12-14 シェーダコアにおけるシェーダリソース割当てのポリシー Active JP6189858B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/325,286 2011-12-14
US13/325,286 US20130155077A1 (en) 2011-12-14 2011-12-14 Policies for Shader Resource Allocation in a Shader Core
PCT/US2012/069836 WO2013090773A2 (en) 2011-12-14 2012-12-14 Policies for shader resource allocation in a shader core

Publications (3)

Publication Number Publication Date
JP2015502618A JP2015502618A (ja) 2015-01-22
JP2015502618A5 true JP2015502618A5 (enExample) 2016-02-04
JP6189858B2 JP6189858B2 (ja) 2017-08-30

Family

ID=47754935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014547504A Active JP6189858B2 (ja) 2011-12-14 2012-12-14 シェーダコアにおけるシェーダリソース割当てのポリシー

Country Status (6)

Country Link
US (2) US20130155077A1 (enExample)
EP (1) EP2791795B1 (enExample)
JP (1) JP6189858B2 (enExample)
KR (1) KR101922681B1 (enExample)
CN (1) CN103999051B (enExample)
WO (1) WO2013090773A2 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8578129B2 (en) * 2011-12-14 2013-11-05 Advanced Micro Devices, Inc. Infrastructure support for accelerated processing device memory paging without operating system integration
JP5238876B2 (ja) * 2011-12-27 2013-07-17 株式会社東芝 情報処理装置及び情報処理方法
US8977997B2 (en) * 2013-03-15 2015-03-10 Mentor Graphics Corp. Hardware simulation controller, system and method for functional verification
GB2524063B (en) 2014-03-13 2020-07-01 Advanced Risc Mach Ltd Data processing apparatus for executing an access instruction for N threads
US9779535B2 (en) 2014-03-19 2017-10-03 Microsoft Technology Licensing, Llc Configuring resources used by a graphics processing unit
US9766954B2 (en) 2014-09-08 2017-09-19 Microsoft Technology Licensing, Llc Configuring resources used by a graphics processing unit
US20160260246A1 (en) * 2015-03-02 2016-09-08 Advanced Micro Devices, Inc. Providing asynchronous display shader functionality on a shared shader core
US9652817B2 (en) * 2015-03-12 2017-05-16 Samsung Electronics Co., Ltd. Automated compute kernel fusion, resizing, and interleave
CN108536644B (zh) * 2015-12-04 2022-04-12 格兰菲智能科技有限公司 由装置端推核心入队列的装置
US10210593B2 (en) * 2016-01-28 2019-02-19 Qualcomm Incorporated Adaptive context switching
US20180109469A1 (en) * 2016-10-17 2018-04-19 International Business Machines Corporation Systems and methods for controlling process priority for efficient resource allocation
US10026145B2 (en) * 2016-12-13 2018-07-17 Qualcomm Incorporated Resource sharing on shader processor of GPU
US10147159B2 (en) 2017-04-07 2018-12-04 Microsoft Technology Licensing, Llc Ink render using high priority queues
US10282812B2 (en) 2017-04-09 2019-05-07 Intel Corporation Page faulting and selective preemption
US20180307533A1 (en) * 2017-04-21 2018-10-25 Intel Corporation Faciltating multi-level microcontroller scheduling for efficient computing microarchitecture
GB2563588B (en) 2017-06-16 2019-06-26 Imagination Tech Ltd Scheduling tasks
US10558418B2 (en) * 2017-07-27 2020-02-11 Advanced Micro Devices, Inc. Monitor support on accelerated processing device
CN109697115B (zh) * 2017-10-20 2023-06-06 伊姆西Ip控股有限责任公司 用于调度应用的方法、装置以及计算机可读介质
US10796472B2 (en) * 2018-06-30 2020-10-06 Intel Corporation Method and apparatus for simultaneously executing multiple contexts on a graphics engine
US11593311B2 (en) * 2019-09-24 2023-02-28 Ati Technologies Ulc Compression system with longest match processing for generating compressed data
US11210757B2 (en) * 2019-12-13 2021-12-28 Advanced Micro Devices, Inc. GPU packet aggregation system
US11403729B2 (en) * 2020-02-28 2022-08-02 Advanced Micro Devices, Inc. Dynamic transparent reconfiguration of a multi-tenant graphics processing unit
US12033275B2 (en) 2021-09-29 2024-07-09 Advanced Micro Devices, Inc. System and methods for efficient execution of a collaborative task in a shader system
US11941723B2 (en) 2021-12-29 2024-03-26 Advanced Micro Devices, Inc. Dynamic dispatch for workgroup distribution
US11941742B2 (en) 2022-06-23 2024-03-26 Apple Inc. Tiled processor communication fabric
US20240419482A1 (en) * 2023-06-16 2024-12-19 Advanced Micro Devices, Inc. GPU Circuit Self-Context Save During Context Unmap
US20250110776A1 (en) * 2023-09-29 2025-04-03 Advanced Micro Devices, Inc. Hardware queue priority mechanism
US20250217195A1 (en) * 2023-12-30 2025-07-03 Advanced Micro Devices, Inc. Local launch in workgroup processors
CN119127314B (zh) * 2024-11-08 2025-03-04 湖南进芯电子科技有限公司 一种数字信号处理器的指令执行方法及数字信号处理器

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4953081A (en) * 1988-12-21 1990-08-28 International Business Machines Corporation Least recently used arbiter with programmable high priority mode and performance monitor
US5371887A (en) * 1989-09-05 1994-12-06 Matsushita Electric Industrial Co., Ltd. Time-shared multitask execution device
JPH0535509A (ja) * 1991-07-29 1993-02-12 Nec Corp 階層構造キユーのチエーン破壊ガード方式
US5884077A (en) * 1994-08-31 1999-03-16 Canon Kabushiki Kaisha Information processing system and method in which computer with high load borrows processor of computer with low load to execute process
US6055579A (en) * 1997-11-17 2000-04-25 Silicon Graphics, Inc. Distributed control and synchronization of multiple data processors using flexible command queues
US6781956B1 (en) * 1999-09-17 2004-08-24 Cisco Technology, Inc. System and method for prioritizing packetized data from a distributed control environment for transmission through a high bandwidth link
US7234144B2 (en) * 2002-01-04 2007-06-19 Microsoft Corporation Methods and system for managing computational resources of a coprocessor in a computing system
US7673304B2 (en) * 2003-02-18 2010-03-02 Microsoft Corporation Multithreaded kernel for graphics processing unit
US7421694B2 (en) * 2003-02-18 2008-09-02 Microsoft Corporation Systems and methods for enhancing performance of a coprocessor
US7337443B2 (en) * 2003-06-30 2008-02-26 Microsoft Corporation Method and apparatus for processing program threads
JP2006119796A (ja) * 2004-10-20 2006-05-11 Matsushita Electric Ind Co Ltd キャッシュメモリシステムおよび動画処理装置
US7830389B2 (en) * 2006-10-03 2010-11-09 Honeywell International Inc. Dual processor accelerated graphics rendering
US8085272B1 (en) * 2006-11-03 2011-12-27 Nvidia Corporation Method and system for improving data coherency in a parallel rendering system
US20090160867A1 (en) * 2007-12-19 2009-06-25 Advance Micro Devices, Inc. Autonomous Context Scheduler For Graphics Processing Units
DE102008007723A1 (de) 2008-02-06 2009-08-20 Osram Gesellschaft mit beschränkter Haftung Beleuchtungsmodul, Leuchte und Verfahren zur Beleuchtung
US8368701B2 (en) * 2008-11-06 2013-02-05 Via Technologies, Inc. Metaprocessor for GPU control and synchronization in a multiprocessor environment
US8854381B2 (en) * 2009-09-03 2014-10-07 Advanced Micro Devices, Inc. Processing unit that enables asynchronous task dispatch
US20120324462A1 (en) 2009-10-31 2012-12-20 Rutgers, The State University Of New Jersey Virtual flow pipelining processing architecture
US8549524B2 (en) * 2009-12-23 2013-10-01 Sap Ag Task scheduler for cooperative tasks and threads for multiprocessors and multicore systems

Similar Documents

Publication Publication Date Title
JP2015502618A5 (enExample)
US9996386B2 (en) Mid-thread pre-emption with software assisted context switch
CN102822802B (zh) 多核处理器系统以及控制方法
CN102750132B (zh) 多线程虚拟流水线处理器的线程控制和调用方法及其处理器
US9507632B2 (en) Preemptive context switching of processes on ac accelerated processing device (APD) based on time quanta
US9632559B2 (en) Delaying execution in a processor to increase power savings
JP2016507849A5 (enExample)
JP2015075803A5 (ja) データ処理管理方法、情報処理装置およびデータ処理管理プログラム
JP2016511489A5 (enExample)
JP2018528524A5 (enExample)
JP2015515052A5 (enExample)
RU2016127443A (ru) Команда запуска виртуального выполнения для диспетчеризации множественных потоков в компьютере
CN102523153B (zh) 虚拟化环境下的负载均衡方法
KR101563576B1 (ko) 다중 스레드 프로세서에 대한 저 레이턴시 2 레벨 인터럽트 제어기 인터페이스
JP2017530453A5 (enExample)
JP2013156984A5 (enExample)
JP2017504106A5 (enExample)
US9898287B2 (en) Dynamic wavefront creation for processing units using a hybrid compactor
CN114514536A (zh) 分布式系统中的神经网络训练
CN110073342A (zh) 用于硬件加速的虚拟信道
KR20130080663A (ko) 멀티-쓰레딩을 사용하는 그래픽 처리를 위한 방법 및 장치
CN104820616A (zh) 一种任务调度的方法及装置
CN107015931A (zh) 用于中断处理的方法和加速器单元
CN110837415B (zh) 一种基于risc-v多核处理器的线程调度方法和装置
US20150286501A1 (en) Register-type-aware scheduling of virtual central processing units