JP2015233114A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2015233114A
JP2015233114A JP2014236862A JP2014236862A JP2015233114A JP 2015233114 A JP2015233114 A JP 2015233114A JP 2014236862 A JP2014236862 A JP 2014236862A JP 2014236862 A JP2014236862 A JP 2014236862A JP 2015233114 A JP2015233114 A JP 2015233114A
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Prior art keywords
groove
hole
region
edge
semiconductor device
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Inventor
貴博 中野
Takahiro Nakano
貴博 中野
元男 山口
Motoo Yamaguchi
元男 山口
大輔 馬嶋
Daisuke Mashima
大輔 馬嶋
智 中井
Satoshi Nakai
智 中井
憲二 松田
Kenji Matsuda
憲二 松田
正徳 近藤
Masanori Kondo
正徳 近藤
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Denso Corp
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Denso Corp
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Priority to JP2014236862A priority Critical patent/JP2015233114A/en
Priority to PCT/JP2015/002260 priority patent/WO2015174034A1/en
Publication of JP2015233114A publication Critical patent/JP2015233114A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which inhibits deterioration in connection reliability between a conductive plate and a conductive member.SOLUTION: A semiconductor device has a conductive plate 13, an electronic element 20 mounted on one surface 13a of the conductive plate, a conductive member connected to the one surface and a resin part for covering the conductive plate, the electronic element and the conductive member, in which a difference in linear expansion coefficients of the electronic element and the resin part is larger than a difference in linear expansion coefficients of the conductive member and the resin part. The conductive plate includes a restriction part 50 for restricting detachment of the resin part due to stress caused by the difference in linear expansion coefficients of the electronic element and the resin part from extending over a connection region 15 on the conductive plate with the conductive member. The restriction part has a groove 51 formed on the one surface and a through hole 52 which penetrates from the one surface to a rear face of the one surface, in which by coupling the groove and the through hole on the one surface, a space made by the groove continues to a space made by the through hole in a continuous manner.

Description

本発明は、電子素子を搭載した導電プレートが樹脂部によって被覆されて成る半導体装置に関するものである。   The present invention relates to a semiconductor device in which a conductive plate on which an electronic element is mounted is covered with a resin portion.

特許文献１に示されるように、リード部と封止用樹脂との接触部分における密着性を向上させることを目的としたリードフレームが知られている。リード部には溝、および、貫通孔が形成されている。これらが封止用樹脂によって被覆されることでアンカー効果が生じ、リード部と封止用樹脂との密着性が向上されている。   As shown in Patent Document 1, there is known a lead frame intended to improve adhesion at a contact portion between a lead portion and a sealing resin. A groove and a through hole are formed in the lead portion. When these are covered with the sealing resin, an anchor effect is produced, and the adhesion between the lead portion and the sealing resin is improved.

特開２００６−１０８３０６号公報JP 2006-108306 A

上記したように特許文献１に示されるリードフレームでは、リード部に溝と貫通孔が形成されている。しかしながら溝と貫通孔とはリード部において離れて形成され、連結されていない。本発明者が検証したところ、溝と貫通孔とが連結されていない構成では、リード部における溝と貫通孔との間にて応力集中が生じ、そこからリード部におけるボンディングワイヤの接続されるボンディング領域へと封止用樹脂の剥離が進行することが確認された。したがって特許文献１に記載の構成ではリード部（導電プレート）とボンディングワイヤ（導電部材）との接続信頼性が低下する虞がある。   As described above, in the lead frame disclosed in Patent Document 1, a groove and a through hole are formed in the lead portion. However, the groove and the through hole are formed apart from each other in the lead portion and are not connected. As a result of verification by the present inventor, in a configuration in which the groove and the through hole are not coupled, stress concentration occurs between the groove and the through hole in the lead portion, and bonding from which the bonding wire is connected in the lead portion. It was confirmed that peeling of the sealing resin progressed to the region. Therefore, in the configuration described in Patent Document 1, the connection reliability between the lead portion (conductive plate) and the bonding wire (conductive member) may be reduced.

そこで本発明は上記問題点に鑑み、導電プレートと導電部材との接続信頼性の低下の抑制された半導体装置を提供することを目的とする。   In view of the above problems, an object of the present invention is to provide a semiconductor device in which a decrease in connection reliability between a conductive plate and a conductive member is suppressed.

上記した目的を達成するために本願の第１発明は、導電プレート（１３）と、導電プレートの一面（１３ａ）に搭載される電子素子（２０）と、導電プレートの一面に接続される導電部材（３０）と、導電プレート、電子素子、および、導電部材それぞれを一体的に被覆する樹脂部（４０）と、を有する半導体装置であって、電子素子と樹脂部との線膨張係数差が導電部材と樹脂部との線膨張係数差よりも大きく、導電プレートには、電子素子と樹脂部との線膨張係数差に起因する応力による樹脂部の剥離が導電プレートにおける導電部材との接続領域（１５）にまで及ぶことを抑制する抑制部（５０）が形成されており、抑制部は、一面に形成された溝（５１）、および、一面からその裏面（１３ｂ）まで貫通する貫通孔（５２）を有し、溝と貫通孔とが一面で連結されることで、溝によって構成される空間と貫通孔によって構成される空間とが連続的に連なっていることを特徴とする。   In order to achieve the above object, the first invention of the present application includes a conductive plate (13), an electronic element (20) mounted on one surface (13a) of the conductive plate, and a conductive member connected to one surface of the conductive plate. (30) and a resin part (40) integrally covering each of the conductive plate, the electronic element, and the conductive member, wherein the difference in linear expansion coefficient between the electronic element and the resin part is conductive. It is larger than the difference in linear expansion coefficient between the member and the resin part, and the conductive plate has a resin region peeling due to stress caused by the difference in linear expansion coefficient between the electronic element and the resin part. 15), the suppression part (50) which suppresses extending to 15) is formed, and the suppression part includes a groove (51) formed on one surface and a through-hole (52) penetrating from one surface to its back surface (13b). ) The through hole and is by being connected on the one, and a space and is continuous with the continuous constituted by the space and the through-hole formed by the grooves.

このように本発明では溝（５１）と貫通孔（５２）とが連結されている。したがって溝（５１）と貫通孔（５２）とが連結されていない構成とは異なり、溝（５１）と貫通孔（５２）との間にて応力集中が生じることが抑制され、樹脂部（４０）の剥離が接続領域（１５）に及ぶことが抑制される。これによって導電プレート（１３）と導電部材（３０）との接続信頼性の低下が抑制される。   Thus, in this invention, the groove | channel (51) and the through-hole (52) are connected. Therefore, unlike the configuration in which the groove (51) and the through hole (52) are not connected, the occurrence of stress concentration between the groove (51) and the through hole (52) is suppressed, and the resin portion (40 ) Is prevented from reaching the connection region (15). This suppresses a decrease in connection reliability between the conductive plate (13) and the conductive member (30).

なお、貫通孔（５２）は溝（５１）と比べて樹脂部（４０）とのアンカー効果が高いために樹脂部（４０）の剥離を抑制する効果が強い。しかしながら貫通孔（５２）は溝（５１）と比べて導電プレート（１３）を削除する量が多いので、貫通孔（５２）の形成によって導電プレート（１３）の強度が低下し、それによって一面（１３ａ）に歪みが生じる虞がある。このような歪みが一面（１３ａ）に生じると、導電プレート（１３）に導電部材（３０）を正確に接続することが困難になる。これに対して本発明では上記したように導電プレート（１３）に溝（５１）と貫通孔（５２）を形成している。したがって樹脂部（４０）の剥離抑制、および、導電プレート（１３）の強度低下抑制それぞれが両立される。また繰り返しとなるが、上記したように溝（５１）と貫通孔（５２）とが連結しているので、両者が連結されていない構成と比べてより効果的に樹脂部（４０）の剥離が接続領域（１５）に及ぶことが抑制される、という顕著な作用効果が奏される。   Since the through hole (52) has a higher anchor effect with the resin part (40) than the groove (51), the effect of suppressing the peeling of the resin part (40) is strong. However, since the through hole (52) has a larger amount of removing the conductive plate (13) than the groove (51), the formation of the through hole (52) reduces the strength of the conductive plate (13). 13a) may be distorted. When such distortion occurs on one surface (13a), it is difficult to accurately connect the conductive member (30) to the conductive plate (13). In contrast, in the present invention, as described above, the groove (51) and the through hole (52) are formed in the conductive plate (13). Accordingly, both the suppression of the peeling of the resin portion (40) and the suppression of the strength reduction of the conductive plate (13) are achieved. Again, since the groove (51) and the through hole (52) are connected as described above, the resin part (40) can be more effectively peeled off compared to the structure in which both are not connected. There is a remarkable effect that the connection area (15) is suppressed.

本願の第２発明では、貫通孔は、電子素子から接続領域へと向かう進行方向に対して横断するように、導電プレートに形成されている。これによれば、界面から接続領域（１５）へと進行する樹脂部（４０）の剥離を貫通孔（５２）によって遮ることができる。   In the second invention of the present application, the through hole is formed in the conductive plate so as to cross the traveling direction from the electronic element toward the connection region. According to this, peeling of the resin part (40) progressing from the interface to the connection region (15) can be blocked by the through hole (52).

なお、特許請求の範囲に記載の請求項、および、課題を解決するための手段それぞれに記載の要素に括弧付きで符号をつけているが、この括弧付きの符号は実施形態に記載の各構成要素との対応関係を簡易的に示すためのものであり、実施形態に記載の要素そのものを必ずしも示しているわけではない。括弧付きの符号の記載は、いたずらに特許請求の範囲を狭めるものではない。   In addition, although the elements described in the claims and the means for solving the problems are attached with parentheses, the parentheses are attached to each component described in the embodiment. This is to simply show the correspondence with the elements, and does not necessarily indicate the elements themselves described in the embodiments. The description of the reference numerals with parentheses does not unnecessarily narrow the scope of the claims.

第１実施形態に係る半導体装置の概略構成を示す上面図である。1 is a top view illustrating a schematic configuration of a semiconductor device according to a first embodiment. 図１のＩＩ−ＩＩ線に沿う断面図である。It is sectional drawing which follows the II-II line | wire of FIG. 図１の破線で囲まれた領域Ａの拡大上面図である。It is an enlarged top view of the area | region A enclosed with the broken line of FIG. 図３のＩＶ−ＩＶ線に沿う断面図である。It is sectional drawing which follows the IV-IV line of FIG. 第１実施形態に係る半導体装置の作用効果を説明するための比較構成を示す上面図である。It is a top view which shows the comparison structure for demonstrating the effect of the semiconductor device which concerns on 1st Embodiment. 第１実施形態に係る半導体装置の作用効果を説明するための比較構成を示す上面図である。It is a top view which shows the comparison structure for demonstrating the effect of the semiconductor device which concerns on 1st Embodiment. 図５に示す比較構成にて生じる剥離を示す上面図である。It is a top view which shows the peeling which arises in the comparison structure shown in FIG. 第１実施形態に係る半導体装置にて生じる剥離を示す上面図である。It is a top view which shows peeling which arises in the semiconductor device which concerns on 1st Embodiment. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 接続領域の位置の変形例を示す上面図である。It is a top view which shows the modification of the position of a connection area | region. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 導電部材の変形例を示す上面図である。It is a top view which shows the modification of an electrically-conductive member. 導電部材の変形例を示す上面図である。It is a top view which shows the modification of an electrically-conductive member. 溝の変形例を示す断面図である。It is sectional drawing which shows the modification of a groove | channel. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 図１６〜図１９に示す抑制部が図１５に示す溝を有する構成を示す断面図である。It is sectional drawing which shows the structure in which the suppression part shown in FIGS. 16-19 has the groove | channel shown in FIG. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part. 抑制部の変形例を示す上面図である。It is a top view which shows the modification of a suppression part.

以下、本発明の実施形態を図に基づいて説明する。
（第１実施形態）
図１〜図８に基づいて、本実施形態に係る半導体装置を説明する。図１および図３〜図８では樹脂部を省略し、図２では樹脂部の剥離を模式的に示している。また図３および図５〜図８においては導電部材３０を省略して接続領域１５を破線で示している。そして図７および図８は超音波探傷装置にて得た画像データを線画に加工した図面であり、剥離の生じた領域を明瞭とするため、その領域を破線で囲むとともにハッチングを入れている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
The semiconductor device according to the present embodiment will be described with reference to FIGS. 1 and 3 to 8, the resin portion is omitted, and FIG. 2 schematically illustrates the separation of the resin portion. 3 and 5 to 8, the conductive member 30 is omitted and the connection region 15 is indicated by a broken line. 7 and 8 are drawings obtained by processing image data obtained by the ultrasonic flaw detector into a line drawing. In order to clarify a region where peeling has occurred, the region is surrounded by a broken line and hatched.

以下においては互いに直交の関係にある３方向を、ｘ方向、ｙ方向、ｚ方向と示し、ｘ方向とｙ方向とによって規定される平面をｘ−ｙ平面、ｙ方向とｚ方向とによって規定される平面をｙ−ｚ平面、ｚ方向とｘ方向とによって規定される平面をｚ−ｘ平面と示す。なお、ｘ方向が特許請求の範囲に記載の進行方向に相当する。   In the following, three directions that are orthogonal to each other are shown as an x direction, a y direction, and a z direction, and a plane defined by the x direction and the y direction is defined by an xy plane, and the y direction and the z direction. The plane defined by the yz plane and the plane defined by the z direction and the x direction are denoted by the zx plane. The x direction corresponds to the traveling direction described in the claims.

図１および図２に示すように半導体装置１００は、リード部１０と、電子素子２０と、導電部材３０と、樹脂部４０と、を有する。リード部１０に電子素子２０と導電部材３０とが設けられ、これらが樹脂部４０によって被覆保護されている。そしてリード部１０には後述する溝５１や貫通孔５２から成る抑制部５０が形成されている。   As shown in FIGS. 1 and 2, the semiconductor device 100 includes a lead portion 10, an electronic element 20, a conductive member 30, and a resin portion 40. An electronic element 20 and a conductive member 30 are provided on the lead portion 10, and these are covered and protected by the resin portion 40. The lead portion 10 is formed with a restraining portion 50 including a groove 51 and a through hole 52 to be described later.

リード部１０は、アイランド１１と、リード１２と、を有する。アイランド１１とリード１２とはリードフレーム（図示略）の一部であり、当初両者は連結部（図示略）によって連結されている。連結部が外部に露出される態様でリードフレームが樹脂部４０によって被覆保護された後、連結部が除去される。こうすることでアイランド１１とリード１２とが電気的に分離され、リード部１０が形成される。本実施形態に係るリード部１０はＣｕから成る。そしてリード部１０はアイランド１１として電子素子２０が搭載され、導電部材３０が接続される第１アイランド１３と、ＩＧＢＴ６０が搭載される第２アイランド１４と、を有する。図１に示すように第１アイランド１３の一面１３ａに電子素子２０と導電部材３０それぞれが固定されている。第１アイランド１３が特許請求の範囲に記載の導電プレートに相当する。   The lead part 10 includes an island 11 and a lead 12. The island 11 and the lead 12 are part of a lead frame (not shown) and are initially connected by a connecting portion (not shown). After the lead frame is covered and protected by the resin portion 40 in such a manner that the connecting portion is exposed to the outside, the connecting portion is removed. By doing so, the island 11 and the lead 12 are electrically separated, and the lead portion 10 is formed. The lead part 10 according to the present embodiment is made of Cu. The lead portion 10 includes the first island 13 on which the electronic element 20 is mounted as the island 11, the conductive member 30 is connected, and the second island 14 on which the IGBT 60 is mounted. As shown in FIG. 1, the electronic element 20 and the conductive member 30 are fixed to the one surface 13 a of the first island 13. The first island 13 corresponds to the conductive plate recited in the claims.

電子素子２０はシリコン（Ｓｉ）や炭化シリコン（ＳｉＣ）などの半導体材料にＩＧＢＴ６０を制御する制御回路が形成されたものである。電子素子２０はｘ−ｙ平面において矩形を成しており、ＩＧＢＴ６０と複数のワイヤ（図示略）を介して電気的に接続されている。図２に示すように電子素子２０は導電ペースト２１を介して第１アイランド１３の一面１３ａに搭載（固定）されている。   The electronic element 20 is formed by forming a control circuit for controlling the IGBT 60 on a semiconductor material such as silicon (Si) or silicon carbide (SiC). The electronic element 20 has a rectangular shape in the xy plane, and is electrically connected to the IGBT 60 via a plurality of wires (not shown). As shown in FIG. 2, the electronic element 20 is mounted (fixed) on the one surface 13 a of the first island 13 via the conductive paste 21.

導電部材３０は金属などの導電性部材から成るものであって、本実施形態ではＩＧＢＴ６０と第１アイランド１３とを電気的に接続する、Ｃｕ，Ａｌ，Ａｕなどから成るワイヤである。図２に示すように導電部材３０の一端３０ａは自身の一部が融解して成る溶融部３１を介して第１アイランド１３の一面１３ａ（接続領域１５）に接続され、図１に示すように導電部材３０の他端３０ｂがＩＧＢＴ６０に接続されている。なお、導電部材３０と樹脂部４０との線膨張係数差は電子素子２０と樹脂部４０との線膨張係数差よりも小さくなっている。   The conductive member 30 is made of a conductive member such as a metal, and in this embodiment is a wire made of Cu, Al, Au, or the like that electrically connects the IGBT 60 and the first island 13. As shown in FIG. 2, one end 30a of the conductive member 30 is connected to one surface 13a (connection region 15) of the first island 13 through a melting portion 31 formed by melting a part of itself, as shown in FIG. The other end 30 b of the conductive member 30 is connected to the IGBT 60. In addition, the linear expansion coefficient difference between the conductive member 30 and the resin portion 40 is smaller than the linear expansion coefficient difference between the electronic element 20 and the resin portion 40.

樹脂部４０はリード部１０の一部、電子素子２０、導電部材３０、および、ＩＧＢＴ６０を一体的に被覆保護するものである。上記したリードフレームに電子素子２０、導電部材３０、および、ＩＧＢＴ６０が設けられてそれぞれが電気的に接続された後、リードフレーム、電子素子２０、導電部材３０、および、ＩＧＢＴ６０それぞれが樹脂部４０によって一体的に被覆保護される。なお、リードフレームにおける外部接続端子として活用される部位は樹脂部４０から外部に露出されている。具体的に言えば、図１に示すリード部１０の全てが樹脂部４０によって被覆保護され、図示しない外部接続端子が樹脂部４０から外部に露出されている。   The resin portion 40 integrally covers and protects a part of the lead portion 10, the electronic element 20, the conductive member 30, and the IGBT 60. After the electronic element 20, the conductive member 30, and the IGBT 60 are provided and electrically connected to the above-described lead frame, each of the lead frame, the electronic element 20, the conductive member 30, and the IGBT 60 is formed by the resin portion 40. It is covered and protected integrally. In addition, the site | part utilized as an external connection terminal in a lead frame is exposed outside from the resin part 40. FIG. Specifically, all of the lead portions 10 shown in FIG. 1 are covered and protected by the resin portion 40, and external connection terminals (not shown) are exposed to the outside from the resin portion 40.

樹脂部４０と電子素子２０との線膨張係数差は樹脂部４０と導電部材３０との線膨張係数差よりも大きくなっている。したがって上記したように樹脂部４０によって電子素子２０と導電部材３０はそれぞれ被覆されるが、樹脂部４０と電子素子２０との界面では、樹脂部４０と導電部材３０との界面よりも、線膨張係数差に起因する応力が大きくなっている。そのため樹脂部４０との剥離が導電部材３０よりも電子素子２０において生じ易くなっている。さらに言えば、上記したように導電ペースト２１を介して電子素子２０が第１アイランド１３に固定されるが、この固定を行う際、流動性を有する状態の導電ペースト２１に電子素子２０が載置される。したがって図２に示すように電子素子２０に付着した導電ペースト２１の端部の形状がメニスカス状となり、導電ペースト２１に局所的に厚さの薄い箇所が形成される。この局所的に厚さの薄い箇所は強度が低いため、この部位が上記の線膨張係数差に起因する応力によって壊れ易く、ここから樹脂部４０の剥離が生じ易くもなっている。樹脂部４０の一部が剥離すると、図２に白抜き矢印で示すように樹脂部４０との接着界面にせん断応力が生じ、剥離がその接着面に沿って進行する。   The difference in linear expansion coefficient between the resin part 40 and the electronic element 20 is larger than the difference in linear expansion coefficient between the resin part 40 and the conductive member 30. Therefore, as described above, the electronic element 20 and the conductive member 30 are respectively covered by the resin portion 40, but the linear expansion is greater at the interface between the resin portion 40 and the electronic element 20 than at the interface between the resin portion 40 and the conductive member 30. The stress due to the coefficient difference is large. Therefore, peeling from the resin part 40 is more likely to occur in the electronic element 20 than in the conductive member 30. Furthermore, as described above, the electronic element 20 is fixed to the first island 13 via the conductive paste 21. When this fixing is performed, the electronic element 20 is placed on the conductive paste 21 in a fluid state. Is done. Therefore, as shown in FIG. 2, the shape of the end portion of the conductive paste 21 attached to the electronic element 20 has a meniscus shape, and locally thin portions are formed in the conductive paste 21. Since this locally thin portion has low strength, this portion is easily broken by the stress caused by the above-described difference in linear expansion coefficient, and the resin portion 40 is easily peeled off. When a part of the resin part 40 is peeled off, a shear stress is generated at the bonding interface with the resin part 40 as shown by a white arrow in FIG. 2, and the peeling proceeds along the bonding surface.

このように電子素子２０では樹脂部４０との剥離が生じ易くなっている。これに対して電子素子２０と導電部材３０が設けられる第１アイランド１３には上記した抑制部５０が形成されている。抑制部５０は電子素子２０と樹脂部４０との線膨張係数差に起因する応力による樹脂部４０の剥離が第１アイランド１３における導電部材３０との接続領域１５にまで及ぶことを抑制するものである。図２〜図４に示すように抑制部５０は、一面１３ａに形成された溝５１、および、一面１３ａからその裏面１３ｂまで貫通する貫通孔５２を有する。そして抑制部５０はｘ−ｙ平面における自身の幾何学的中心をｘ方向に貫く中心線（図示略）を介して対称な形状を成し、その中心線上に接続領域１５が位置している。抑制部５０は溝５１および貫通孔５２による樹脂部４０とのアンカー効果によってリード部１０と樹脂部４０との剥離がリード部１０における導電部材３０との接続領域１５まで及ぶことを抑制する。   As described above, the electronic element 20 is easily peeled off from the resin portion 40. On the other hand, the suppression part 50 mentioned above is formed in the 1st island 13 in which the electronic element 20 and the electrically-conductive member 30 are provided. The suppression part 50 suppresses the peeling of the resin part 40 due to the stress caused by the difference in linear expansion coefficient between the electronic element 20 and the resin part 40 from reaching the connection region 15 with the conductive member 30 in the first island 13. is there. 2-4, the suppression part 50 has the groove | channel 51 formed in the one surface 13a, and the through-hole 52 penetrated from the one surface 13a to the back surface 13b. The suppressing unit 50 has a symmetrical shape via a center line (not shown) passing through its own geometric center in the xy plane in the x direction, and the connection region 15 is located on the center line. The restraining part 50 restrains the peeling of the lead part 10 and the resin part 40 from reaching the connection region 15 with the conductive member 30 in the lead part 10 by the anchor effect with the resin part 40 by the groove 51 and the through hole 52.

図３に示すように溝５１はｘ−ｙ平面においてｘ方向に沿った形状を成している。そして図４に示すように溝５１はｙ−ｚ平面において凸形状を成している。より詳しく言えば、溝５１はｙ−ｚ平面において断続的に２段階に深さの掘られた形状を成している。このような溝５１は一面１３ａから裏面１３ｂに向かって所定深さ研削した後、この研削によって生じた研削面の中央をさらに所定深さ研削することで形成される。若しくは一面１３ａから裏面１３ｂに向かって所定深さ研削した後、この研削によって生じた縁部を先ほどよりも浅めに研削することで溝５１は形成される。図４に示すように第１アイランド１３の厚さ（ｚ方向の長さ）をｔとすると、本実施形態において溝５１の最大深さ（ｚ方向における一面１３ａからの研削深さ）はｔ／４となっている。このような溝５１や貫通孔５２は上記したリードフレームをプレス加工したりエッチング加工したりすることで形成される。   As shown in FIG. 3, the groove 51 has a shape along the x direction in the xy plane. And as shown in FIG. 4, the groove | channel 51 has comprised the convex shape in the yz plane. More specifically, the groove 51 has a shape that is intermittently deepened in two stages in the yz plane. Such a groove 51 is formed by grinding a predetermined depth from one surface 13a toward the back surface 13b, and further grinding the center of the ground surface generated by this grinding to a predetermined depth. Or after grind | pulverizing predetermined depth toward the back surface 13b from the one surface 13a, the groove | channel 51 is formed by grinding the edge part produced by this grinding shallower than before. As shown in FIG. 4, when the thickness (length in the z direction) of the first island 13 is t, in this embodiment, the maximum depth of the groove 51 (the grinding depth from the one surface 13a in the z direction) is t /. 4 Such grooves 51 and through holes 52 are formed by pressing or etching the above-described lead frame.

図３に示すように貫通孔５２はｘ−ｙ平面においてｙ方向に沿った形状を成している。すなわち、貫通孔５２の一面１３ａにおける開口端の形状がｙ方向に延びた形状を成している。そして図示しないが、裏面１３ｂにおいても開口端の形状がｙ方向に延びた形状を成している。このように貫通孔５２がｙ方向に延びた形状を成しているため、貫通孔５２は電子素子２０から接続領域１５へとｘ方向に沿って向かう仮想直線を横断している。また第１アイランド１３の一面１３ａが、電子素子２０が搭載される第１領域と導電部材３０が接続される第２領域とに貫通孔５２によって概略的に分けられている。なお貫通孔５２を構成する壁面はｚ方向に沿っており、本実施形態において第１領域とは一面１３ａにおいて図３に示す一点鎖線（貫通孔５２の一面１３ａにおける開口端の延びた方向（ｙ方向）に沿う仮想直線）よりも電子素子２０側、第２領域とは接続領域１５側である。   As shown in FIG. 3, the through hole 52 has a shape along the y direction in the xy plane. That is, the shape of the opening end on the one surface 13a of the through hole 52 is a shape extending in the y direction. Although not shown, the shape of the opening end also extends in the y direction on the back surface 13b. Thus, since the through hole 52 has a shape extending in the y direction, the through hole 52 crosses an imaginary straight line extending from the electronic element 20 to the connection region 15 along the x direction. Further, one surface 13a of the first island 13 is roughly divided by a through hole 52 into a first region where the electronic element 20 is mounted and a second region where the conductive member 30 is connected. In addition, the wall surface which comprises the through-hole 52 is along az direction, and in this embodiment, it is the 1st area | region with the one-dot chain line shown in FIG. The electronic element 20 side and the second region are closer to the connection region 15 side than the virtual straight line) along the direction).

本実施形態に係る抑制部５０は、上記した溝５１としてｘ方向に沿った形状を成す第１溝５３と第２溝５４を有する。第１溝５３は貫通孔５２における一面１３ａの開口端の一端から第２領域側へと延びた形状を成し、第２溝５４は貫通孔５２における一面１３ａの開口端の他端から第２領域側へと延びた形状を成している。図３および図４に示すように、溝５３，５４と貫通孔５２とが一面１３ａで連結され、溝５３，５４によって構成される空間と貫通孔５２によって構成される空間とが連続的に連なっている。この連続的に連なった空間は樹脂部４０によって満たされ、その壁面に樹脂部４０が接着している。そして図３に破線で囲って示す第１アイランド１３における導電部材３０との電気的な接続領域１５が、ｙ方向において第１溝５３と第２溝５４との間に位置している。このように接続領域１５は貫通孔５２と溝５３，５４とによって四方の内、三方を囲まれている。   The suppressing unit 50 according to the present embodiment includes a first groove 53 and a second groove 54 that form a shape along the x direction as the groove 51 described above. The first groove 53 has a shape extending from one end of the open end of the one surface 13 a in the through hole 52 to the second region side, and the second groove 54 is second from the other end of the open end of the one surface 13 a in the through hole 52. It has a shape extending to the region side. As shown in FIG. 3 and FIG. 4, the grooves 53, 54 and the through hole 52 are connected by one surface 13 a, and the space formed by the grooves 53, 54 and the space formed by the through hole 52 are continuously connected. ing. This continuous space is filled with the resin portion 40, and the resin portion 40 is bonded to the wall surface. And the electrical connection area | region 15 with the electrically-conductive member 30 in the 1st island 13 shown enclosed with a broken line in FIG. 3 is located between the 1st groove | channel 53 and the 2nd groove | channel 54 in the y direction. As described above, the connection region 15 is surrounded on three sides by the through hole 52 and the grooves 53 and 54.

次に、本実施形態に係る半導体装置１００の作用効果を説明する。上記したように溝５１と貫通孔５２とが連結されている。したがって溝と貫通孔とが連結されていない構成とは異なり、溝５１と貫通孔５２との間にて応力集中が生じることが抑制され、電子素子２０と樹脂部４０との間の界面にて生じた樹脂部４０の剥離が接続領域１５に及ぶことが抑制される。これによって第１アイランド１３と導電部材３０との接続信頼性の低下が抑制される。   Next, functions and effects of the semiconductor device 100 according to this embodiment will be described. As described above, the groove 51 and the through hole 52 are connected. Therefore, unlike the configuration in which the groove and the through hole are not connected, the occurrence of stress concentration between the groove 51 and the through hole 52 is suppressed, and at the interface between the electronic element 20 and the resin portion 40. The resulting peeling of the resin portion 40 is suppressed from reaching the connection region 15. Thereby, a decrease in connection reliability between the first island 13 and the conductive member 30 is suppressed.

本実施形態に係る半導体装置１００が上記した作用効果を奏することは本発明者が検証済みである。本発明者は上記した作用効果を検証するために、比較対象として図５および図６に示す半導体装置２００，３００を用意した。この半導体装置２００，３００それぞれの第１アイランド１３には溝５１と貫通孔５２とが形成されているが、両者は連結されていない。より詳しく言えば、半導体装置２００では貫通孔５２と溝５１とがｘ方向において離れ、半導体装置３００では一面１３ａにおける貫通孔５２の開口端のエッジと溝５１のエッジとが接触している。   The inventor has verified that the semiconductor device 100 according to the present embodiment has the above-described effects. The present inventor prepared the semiconductor devices 200 and 300 shown in FIG. 5 and FIG. 6 as comparison objects in order to verify the above-described effects. A groove 51 and a through hole 52 are formed in the first island 13 of each of the semiconductor devices 200 and 300, but they are not connected. More specifically, in the semiconductor device 200, the through hole 52 and the groove 51 are separated from each other in the x direction, and in the semiconductor device 300, the edge of the open end of the through hole 52 and the edge of the groove 51 in one surface 13a are in contact with each other.

これら半導体装置１００〜３００に対して本発明者は温度の上昇と下降を幾度も繰り返し、各材料の線膨張係数差に起因する応力を幾度も発生させた。すると図７および図８において破線で囲ったハッチングの施された領域にて樹脂部４０の剥離が生じた。上記したように樹脂部４０との剥離が導電部材３０よりも電子素子２０において生じ易くなっているため、樹脂部４０との剥離は電子素子２０にて始まり、その周囲へと広がっていく。図７に示すように溝５１と貫通孔５２とが連結されていない半導体装置２００の場合、両者の間を介して接続領域１５へと剥離が進む。これに対して図８に示すように溝５１と貫通孔５２とが連結された半導体装置１００の場合、剥離は抑制部５０にて止まり、接続領域１５へと剥離が及ぶことが抑制されている。本発明者は図７に示す接続領域１５まで及ぶ剥離が生じるまでに幾度も温度の上昇と下降を繰り返したが、その繰り返した回数の３倍以上温度の上昇と下降を繰り返しても、半導体装置１００では図８に示すように接続領域１５に剥離が及ぶことはなかった。また本発明者は溝５１と貫通孔５２との間にて生じるせん断応力を測定したが、図７に示す構成と比べて、図８に示す構成ではせん断応力が半分以下となっていた。なお、図６に対応する樹脂部４０の剥離の図示は省略するが、やはり溝５１と貫通孔５２との間を介して剥離が接続領域１５へと達することが予想される。   The inventors repeatedly increased and decreased the temperature for these semiconductor devices 100 to 300, and repeatedly generated stress due to the difference in linear expansion coefficient of each material. Then, peeling of the resin part 40 occurred in the hatched region surrounded by the broken line in FIGS. 7 and 8. As described above, the separation from the resin part 40 is more likely to occur in the electronic element 20 than in the conductive member 30, so that the separation from the resin part 40 starts at the electronic element 20 and spreads to the periphery thereof. In the case of the semiconductor device 200 in which the groove 51 and the through hole 52 are not connected as shown in FIG. 7, the separation proceeds to the connection region 15 through the both. On the other hand, as shown in FIG. 8, in the case of the semiconductor device 100 in which the groove 51 and the through-hole 52 are connected, the separation stops at the suppressing portion 50 and the separation to the connection region 15 is suppressed. . The inventor repeatedly increased and decreased the temperature several times before the peeling up to the connection region 15 shown in FIG. 7 occurred. Even if the temperature was increased and decreased more than three times, the semiconductor device In 100, the connection region 15 did not peel as shown in FIG. In addition, the inventor measured the shear stress generated between the groove 51 and the through hole 52, but the shear stress was less than half in the configuration shown in FIG. 8 compared to the configuration shown in FIG. Although illustration of the peeling of the resin portion 40 corresponding to FIG. 6 is omitted, it is expected that the peeling will reach the connection region 15 through the gap 51 and the through hole 52.

図３および図４に示すように貫通孔５２は溝５１と比べて深いために樹脂部４０とのアンカー効果が高く、樹脂部４０の剥離を抑制する効果が強い。しかしながら貫通孔５２は溝５１と比べて第１アイランド１３を削除する量が多いので、貫通孔５２の形成によって第１アイランド１３の強度が低下し、それによって一面１３ａに歪みが生じる虞がある。このような歪みが一面１３ａに生じると、第１アイランド１３に導電部材３０を正確に接続することが困難になる。これに対して本発明では上記したように第１アイランド１３に溝５１と貫通孔５２を形成している。したがって樹脂部４０の剥離抑制、および、第１アイランド１３の強度低下抑制それぞれが両立される。また繰り返しとなるが、上記したように溝５１と貫通孔５２とが連結しているので、両者が連結されていない構成と比べてより効果的に樹脂部４０の剥離が接続領域１５に及ぶことが抑制される、という顕著な作用効果が奏される。   As shown in FIGS. 3 and 4, since the through hole 52 is deeper than the groove 51, the anchor effect with the resin portion 40 is high, and the effect of suppressing the peeling of the resin portion 40 is strong. However, since the through-hole 52 has a larger amount to delete the first island 13 than the groove 51, the strength of the first island 13 is lowered by the formation of the through-hole 52, which may cause distortion on the one surface 13a. When such distortion occurs on the one surface 13a, it is difficult to accurately connect the conductive member 30 to the first island 13. In contrast, in the present invention, the grooves 51 and the through holes 52 are formed in the first island 13 as described above. Therefore, both peeling suppression of the resin part 40 and strength reduction suppression of the 1st island 13 are compatible. In addition, as described above, since the groove 51 and the through hole 52 are connected as described above, the separation of the resin portion 40 reaches the connection region 15 more effectively than a configuration in which both are not connected. It is possible to obtain a remarkable effect of suppressing the above.

貫通孔５２はｙ方向に延びた形状を成し、電子素子２０から接続領域１５へとｘ方向に沿って向かう仮想直線を横断している。これによれば、電子素子２０と樹脂部４０との界面から接続領域１５へと進行する樹脂部４０の剥離を貫通孔５２によって遮ることができる。   The through hole 52 has a shape extending in the y direction, and traverses an imaginary straight line extending from the electronic element 20 to the connection region 15 along the x direction. According to this, the peeling of the resin part 40 proceeding from the interface between the electronic element 20 and the resin part 40 to the connection region 15 can be blocked by the through hole 52.

溝５１はｘ方向に延びた形状を成している。プレス加工やエッチング加工などの制約から、貫通孔５２のｘ−ｙ平面における最小長さ（ｘ方向の長さ）は第１アイランド１３の厚さｔ程度となるが、溝５１のｘ−ｙ平面における最小長さ（ｙ方向の長さ）は、例えば図４に示すように第１アイランド１３の厚さｔよりも狭くすることができる。したがって上記したように溝５１がｘ方向に延びた形状を成している場合、一面１３ａのｙ方向において、抑制部５０の形成が厳しくなることが抑制される。   The groove 51 has a shape extending in the x direction. Due to restrictions such as pressing and etching, the minimum length (the length in the x direction) of the through hole 52 in the xy plane is about the thickness t of the first island 13, but the xy plane of the groove 51. The minimum length (the length in the y direction) at can be made narrower than the thickness t of the first island 13, for example, as shown in FIG. Therefore, when the groove 51 has a shape extending in the x direction as described above, the formation of the suppressing portion 50 is suppressed from becoming severe in the y direction of the one surface 13a.

第１溝５３は、ｘ方向に沿って貫通孔５２の一端から第２領域側へと延びた形状を成し、第２溝５４は、ｘ方向に沿って貫通孔５２の他端から第２領域側へと延びた形状を成している。そして接続領域１５がｙ方向において第１溝５３と第２溝５４との間に位置し、接続領域１５の四方の内の三方が貫通孔５２と溝５３，５４とによって囲まれている。このように本実施形態では、接続領域が第１溝と第２溝との間の領域よりも貫通孔から離れた構成とは異なり、接続領域１５の周囲の一部が抑制部５０によって囲まれている。そのため、樹脂部４０の剥離が接続領域１５に及ぶことが抑制部５０によってより効果的に抑制される。さらに言えば、第１溝５３は貫通孔５２の一端から延び、第２溝５４は貫通孔５２の他端から延びている。そのため第１溝と第２溝とが貫通孔の中央部から延びる構成と比べて、第１溝５３と第２溝５４との間の領域が広くなる。したがって第１溝５３と第２溝５４との間に導電部材３０を接続する場合、導電部材３０を接続するための面積の低減が抑制される。   The first groove 53 has a shape extending from one end of the through hole 52 to the second region side along the x direction, and the second groove 54 is second from the other end of the through hole 52 along the x direction. It has a shape extending to the region side. The connection region 15 is located between the first groove 53 and the second groove 54 in the y direction, and three of the connection regions 15 are surrounded by the through hole 52 and the grooves 53 and 54. As described above, in this embodiment, unlike the configuration in which the connection region is farther from the through hole than the region between the first groove and the second groove, a part of the periphery of the connection region 15 is surrounded by the suppressing unit 50. ing. Therefore, the suppression of the peeling of the resin portion 40 reaching the connection region 15 is more effectively suppressed by the suppression portion 50. More specifically, the first groove 53 extends from one end of the through hole 52, and the second groove 54 extends from the other end of the through hole 52. Therefore, the region between the first groove 53 and the second groove 54 is wider than the configuration in which the first groove and the second groove extend from the central portion of the through hole. Therefore, when the conductive member 30 is connected between the first groove 53 and the second groove 54, the reduction of the area for connecting the conductive member 30 is suppressed.

以上、本発明の好ましい実施形態について説明したが、本発明は上記した実施形態になんら制限されることなく、本発明の主旨を逸脱しない範囲において、種々変形して実施することが可能である。なお以下においては抑制部５０、接続領域１５、および、導電部材３０に関わる変形例については、その段落の冒頭に（変形例）という記載を番号を付けて記載する。   The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. In the following, regarding the modified examples related to the suppressing unit 50, the connection region 15, and the conductive member 30, the description of (modified example) is given a number at the beginning of the paragraph.

（変形例１）
本実施形態では第１溝５３が貫通孔５２の一端から延び、第２溝５４が貫通孔５２の他端から延びる例を示した。しかしながら例えば図９に示すように第１溝５３と第２溝５４とが貫通孔５２の中央部から延びた形状を採用することもできる。 (Modification 1)
In the present embodiment, the first groove 53 extends from one end of the through hole 52, and the second groove 54 extends from the other end of the through hole 52. However, for example, a shape in which the first groove 53 and the second groove 54 extend from the central portion of the through hole 52 as shown in FIG.

（変形例２）
本実施形態では接続領域１５がｙ方向において第１溝５３と第２溝５４との間に位置する例を示した。しかしながら例えば図１０に示すように接続領域１５が第１溝５３と第２溝５４との間に位置しなくとも良い。ただし図１０に示すように接続領域１５は、ｘ方向において溝５３，５４それぞれよりも貫通孔５２よりも離れていたとしても、ｙ方向の位置としては第１溝５３と第２溝５４との間である構成が好ましい。 (Modification 2)
In the present embodiment, an example is shown in which the connection region 15 is located between the first groove 53 and the second groove 54 in the y direction. However, for example, as shown in FIG. 10, the connection region 15 may not be located between the first groove 53 and the second groove 54. However, as shown in FIG. 10, even if the connection region 15 is farther from the through hole 52 than the grooves 53 and 54 in the x direction, the position in the y direction is the distance between the first groove 53 and the second groove 54. A configuration in between is preferable.

（変形例３）
本実施形態では図３に示すように溝５３，５４が一面１３ａにおけるｙ方向に沿う第２領域側の第１縁部１３ｃの手前まで延びた形状を成す例を示した。これとは異なり、図１１および図１２に示すように、溝５３，５４それぞれが貫通孔５２から一面１３ａのｘ方向に沿う縁部１３ｄ，１３ｅまで延びた構成を採用することもできる。これによれば、貫通孔５２と溝５３，５４それぞれによって、電子素子２０と樹脂部４０との界面から接続領域１５へと進行する樹脂部４０の剥離を遮ることができる。 (Modification 3)
In this embodiment, as shown in FIG. 3, the groove | channels 53 and 54 showed the example which comprised the shape extended to the near side of the 1st edge 13c of the 2nd area | region side along the y direction in the one surface 13a. Unlike this, as shown in FIGS. 11 and 12, it is also possible to adopt a configuration in which the grooves 53 and 54 extend from the through hole 52 to the edge portions 13d and 13e along the x direction of the surface 13a. According to this, the peeling of the resin part 40 proceeding from the interface between the electronic element 20 and the resin part 40 to the connection region 15 can be blocked by the through hole 52 and the grooves 53 and 54, respectively.

本実施形態では溝５３，５４それぞれがｘ方向に沿う例を示した。しかしながら溝５３，５４それぞれはｘ方向に沿っていなくとも良い。例えば図１１に示すように、溝５３，５４それぞれがｙ方向に沿った形状を採用することもできるし、図１２に示すように溝５３，５４それぞれがｘ方向に対して傾斜した形状を採用することもできる。特に図１１および図１２に示す構成では、第１溝５３は貫通孔５２の一端から第２縁部１３ｄまで延びた形状を成し、第２溝５４は貫通孔５２の他端から第２縁部１３ｄとｙ方向で対向する第３縁部１３ｅまで延びた形状を成している。これによって一面１３ａが電子素子２０の搭載される第１領域と導電部材３０の接続される第２領域とに完全に分断される。これによれば、第１領域にて発生した樹脂部４０の剥離が接続領域１５の位置する第２領域へと進行することを貫通孔５２と溝５３，５４によって遮ることができる。なお図示しないが、溝５３，５４それぞれがｘ方向に沿う場合、第１溝５３が貫通孔５２の一端から第１縁部１３ｃまで延びた形状を成し、第２溝５４が貫通孔５２の他端から第１縁部１３ｃまで延びた形状を成す構成を採用することもできる。これによれば、第１領域にて発生した樹脂部４０の剥離が接続領域１５へと進行することを貫通孔５２と溝５３，５４によって遮ることができる。上記した第２縁部１３ｄが特許請求の範囲に記載の第１縁部に相当し、第３縁部１３ｅが特許請求の範囲に記載の第２縁部に相当する。   In the present embodiment, an example in which the grooves 53 and 54 are along the x direction is shown. However, each of the grooves 53 and 54 may not be along the x direction. For example, as shown in FIG. 11, each of the grooves 53 and 54 can adopt a shape along the y direction, or each of the grooves 53 and 54 can be inclined with respect to the x direction as shown in FIG. You can also 11 and 12, the first groove 53 has a shape extending from one end of the through hole 52 to the second edge portion 13d, and the second groove 54 has a second edge from the other end of the through hole 52. It has a shape extending to the third edge portion 13e facing the portion 13d in the y direction. As a result, the one surface 13a is completely divided into a first region where the electronic element 20 is mounted and a second region where the conductive member 30 is connected. According to this, it is possible to prevent the peeling of the resin portion 40 generated in the first region from proceeding to the second region where the connection region 15 is located by the through hole 52 and the grooves 53 and 54. Although not shown, when each of the grooves 53 and 54 is along the x direction, the first groove 53 has a shape extending from one end of the through hole 52 to the first edge portion 13 c, and the second groove 54 is formed of the through hole 52. A configuration having a shape extending from the other end to the first edge portion 13c may be employed. According to this, the penetration hole 52 and the grooves 53 and 54 can block the peeling of the resin portion 40 generated in the first region from proceeding to the connection region 15. The second edge portion 13d described above corresponds to the first edge portion recited in the claims, and the third edge portion 13e corresponds to the second edge portion recited in the claims.

（変形例４）
本実施形態では導電部材３０がワイヤであって、一端３０ａが第１アイランド１３に接続され、他端３０ｂがＩＧＢＴ６０に接続される例を示した。しかしながら導電部材３０としては上記例に限定されず、導電部材３０と樹脂部４０との線膨張係数差が電子素子２０と樹脂部４０との線膨張係数差よりも小さいものであれば適宜採用することができる。例えば導電部材３０としてコンデンサを採用することができる。この場合例えば図１３に示すように導電部材３０の一端３０ａが第１アイランド１３に接続され、他端３０ｂが第２アイランド１４に接続される。さらに例示すれば、導電部材３０として抵抗などの他の電子素子を採用することもできる。この導電部材３０は例えば図１４に示すように第１アイランド１３のみに接続される。 (Modification 4)
In the present embodiment, the conductive member 30 is a wire, one end 30 a is connected to the first island 13, and the other end 30 b is connected to the IGBT 60. However, the conductive member 30 is not limited to the above example, and is appropriately adopted as long as the difference in linear expansion coefficient between the conductive member 30 and the resin portion 40 is smaller than the difference in linear expansion coefficient between the electronic element 20 and the resin portion 40. be able to. For example, a capacitor can be employed as the conductive member 30. In this case, for example, as shown in FIG. 13, one end 30 a of the conductive member 30 is connected to the first island 13 and the other end 30 b is connected to the second island 14. For example, another electronic element such as a resistor may be employed as the conductive member 30. The conductive member 30 is connected only to the first island 13, for example, as shown in FIG.

本実施形態では溝５１のｙ−ｚ平面における形状が凸形状を成している例を示した。しかしながら溝５１のｙ−ｚ平面における形状としては上記例に限定されず、例えば図１５に示すように三角形状を採用することもできる。   In this embodiment, the example in which the shape in the yz plane of the groove | channel 51 has comprised convex shape was shown. However, the shape of the groove 51 in the yz plane is not limited to the above example, and for example, a triangular shape can be adopted as shown in FIG.

（変形例５）
本実施形態では抑制部５０が１つの貫通孔５２と２つの溝５３，５４を有する例を示した。しかしながらこれとは異なり、図１６〜図１９に示すように抑制部５０が２つの貫通孔５５，５６と１つの溝５１を有する構成を採用することもできる。図１６に示す抑制部５０は図３に示す抑制部５０に対して貫通孔と溝とを交換した構成であり、図１７に示す抑制部５０は図９に示す抑制部５０に対して貫通孔と溝とを交換した構成である。そして図１８に示す抑制部５０は図１１に示す抑制部５０に対して貫通孔と溝とを交換した構成であり、図１９に示す抑制部５０は図１２に示す抑制部５０に対して貫通孔と溝とを交換した構成である。このような対応関係にあるためにその構成の説明は簡略化するが、図１６〜図１９に示す抑制部５０は以下の構成となっている。 (Modification 5)
In this embodiment, the suppression part 50 showed the example which has the one through-hole 52 and the two groove | channels 53,54. However, unlike this, as shown in FIGS. 16 to 19, a configuration in which the suppressing portion 50 includes two through holes 55 and 56 and one groove 51 can be adopted. 16 has a configuration in which a through hole and a groove are exchanged with respect to the suppression unit 50 shown in FIG. 3, and the suppression unit 50 shown in FIG. 17 has a through hole with respect to the suppression unit 50 shown in FIG. And the groove are exchanged. 18 has a configuration in which through holes and grooves are exchanged with respect to the suppression unit 50 illustrated in FIG. 11, and the suppression unit 50 illustrated in FIG. 19 penetrates the suppression unit 50 illustrated in FIG. In this configuration, the hole and the groove are exchanged. Although the description of the configuration is simplified because of such correspondence, the suppression unit 50 shown in FIGS. 16 to 19 has the following configuration.

図１６および図１７に示す抑制部５０において、溝５１はｙ方向に延びた形状を成し、貫通孔５５，５６はそれぞれｘ方向に沿って溝５１から第２領域の方へと延びた形状を成している。図１６に示す抑制部５０では、第１貫通孔５５がｘ方向に沿って溝５１の一端から第２領域へと延び、第２貫通孔５６がｘ方向に沿って溝５１の他端から第２領域へと延びている。そして図１７に示す抑制部５０では、第１貫通孔５５と第２貫通孔５６とが溝５１の中央部から延びている。   16 and 17, the groove 51 has a shape extending in the y direction, and the through holes 55 and 56 each have a shape extending from the groove 51 toward the second region along the x direction. Is made. 16, the first through hole 55 extends from one end of the groove 51 to the second region along the x direction, and the second through hole 56 extends from the other end of the groove 51 along the x direction. It extends into two areas. And in the suppression part 50 shown in FIG. 17, the 1st through-hole 55 and the 2nd through-hole 56 are extended from the center part of the groove | channel 51. FIG.

図１８および図１９に示す抑制部５０において、貫通孔５５，５６それぞれが溝５１から一面１３ａの縁部１３ｄ，１３ｅまで延びている。そして第１貫通孔５５が溝５１の一端から第２縁部１３ｄまで延びた形状を成し、第２貫通孔５６は溝５１の他端から第３縁部１３ｅまで延びた形状を成している。図１８に示す抑制部５０では、貫通孔５５，５６それぞれがｙ方向に沿った形状を成している。そして図１９に示す抑制部５０では、貫通孔５５，５６それぞれがｘ方向に対して傾斜した形状を成している。なお図示しないが、貫通孔５５，５６それぞれがｘ方向に沿う場合、第１貫通孔５５が溝５１の一端から第１縁部１３ｃまで延びた形状を成し、第２貫通孔５６が溝５１の他端から第１縁部１３ｃまで延びた形状を成しても良い。   18 and 19, the through holes 55 and 56 extend from the groove 51 to the edges 13d and 13e of the one surface 13a. The first through hole 55 has a shape extending from one end of the groove 51 to the second edge portion 13d, and the second through hole 56 has a shape extending from the other end of the groove 51 to the third edge portion 13e. Yes. In the suppression part 50 shown in FIG. 18, each of the through holes 55 and 56 has a shape along the y direction. And in the suppression part 50 shown in FIG. 19, each of the through-holes 55 and 56 has comprised the shape inclined with respect to the x direction. Although not shown, when each of the through holes 55 and 56 is along the x direction, the first through hole 55 has a shape extending from one end of the groove 51 to the first edge portion 13c, and the second through hole 56 is the groove 51. You may comprise the shape extended from the other end of this to the 1st edge part 13c.

なお、図２０に白抜き矢印で示すようにｘ方向に沿って電子素子２０から接続領域１５へと樹脂部４０の剥離が進行するが、図１６〜図１９に示す構成の場合、溝５１はｙ方向に沿った形状を成している。したがって一面１３ａに沿って進む樹脂部４０の剥離の際に生じるせん断応力が溝５１によって分散される。このために接続領域１５へと進むせん断応力が弱まり、溝５１を越えて接続領域１５へと樹脂部４０の剥離が進むことが抑制される。なお、図２０では溝５１として図１５に示す断面形状を有するものを図示している。   In addition, although the peeling of the resin part 40 progresses from the electronic element 20 to the connection region 15 along the x direction as shown by a white arrow in FIG. 20, in the case of the configuration shown in FIGS. It has a shape along the y direction. Therefore, the shearing stress generated when the resin portion 40 is peeled along the one surface 13 a is dispersed by the grooves 51. For this reason, the shear stress that proceeds to the connection region 15 is weakened, and the peeling of the resin portion 40 to the connection region 15 beyond the groove 51 is suppressed. In FIG. 20, the groove 51 having the cross-sectional shape shown in FIG. 15 is illustrated.

本実施形態ではリード部１０がＣｕから成る例を示した。しかしながらリード部１０の形成材料としては金属プレートであれば適宜採用することができる。   In the present embodiment, an example in which the lead portion 10 is made of Cu is shown. However, as a material for forming the lead portion 10, any metal plate can be adopted as appropriate.

本実施形態ではアイランド１１として第１アイランド１３と第２アイランド１４を有する例を示した。しかしながらアイランド１１が第１アイランド１３のみを有する構成を採用することもできる。   In this embodiment, the example which has the 1st island 13 and the 2nd island 14 as the island 11 was shown. However, a configuration in which the island 11 includes only the first island 13 may be employed.

本実施形態では電子素子２０がＩＧＢＴ６０を制御する制御回路が半導体基板に形成されたものである例を示した。しかしながら電子素子２０としては上記例に限定されず、シリコンなどの半導体材料から成るものであればよく、そこに如何様な回路が形成されてもよい。   In the present embodiment, an example is shown in which a control circuit for controlling the IGBT 60 by the electronic element 20 is formed on a semiconductor substrate. However, the electronic element 20 is not limited to the above example, and may be any semiconductor material such as silicon, and any circuit may be formed there.

本実施形態では抑制部５０がｘ−ｙ平面における幾何学的中心をｘ方向に貫く中心線を介して対称な形状を成している例を示した。しかしながら抑制部５０は中心線を介して対称な形状を成していなくとも良い。   In the present embodiment, an example is shown in which the suppressing unit 50 has a symmetric shape through a center line penetrating the geometric center in the xy plane in the x direction. However, the suppressing part 50 does not need to have a symmetrical shape with respect to the center line.

本実施形態では抑制部５０の中心線上に接続領域１５が位置する例を示した。しかしながら接続領域１５は中心線上に位置していなくとも良い。例えば図３で示す構成の場合、接続領域１５の位置としては、ｘ方向における位置が貫通孔５２よりも第２領域側であり、且つ、ｙ方向における位置が２つの溝５３，５４の間であれば良い。   In the present embodiment, an example in which the connection region 15 is located on the center line of the suppressing unit 50 is shown. However, the connection region 15 may not be located on the center line. For example, in the case of the configuration shown in FIG. 3, as the position of the connection region 15, the position in the x direction is closer to the second region than the through hole 52, and the position in the y direction is between the two grooves 53 and 54. I just need it.

本実施形態では貫通孔５２を構成する壁面がｚ方向に沿っている例を示した。しかしながら貫通孔５２の貫通方向としては上記例に限定されず、貫通孔５２を構成する壁面がｚ方向に対して傾斜していても良い。   In this embodiment, the example which the wall surface which comprises the through-hole 52 followed the z direction was shown. However, the penetration direction of the through hole 52 is not limited to the above example, and the wall surface constituting the through hole 52 may be inclined with respect to the z direction.

本実施形態では第１アイランド１３に電子素子２０と導電部材３０の２つが設けられる例を示した。しかしながら第１アイランド１３にはこれらの他に、例えばチップ抵抗が搭載されていても良い。   In the present embodiment, an example in which the electronic element 20 and the conductive member 30 are provided on the first island 13 is shown. However, in addition to these, for example, a chip resistor may be mounted on the first island 13.

本実施形態では特に半導体装置１００の用途について言及していなかった。しかしながら上記したように周りの環境の温度変化に対して樹脂部４０の剥離が接続領域１５へと及ぶことが抑制される、という顕著な作用効果を半導体装置１００は奏する。そのため、半導体装置１００を例えば車両のエンジンなどに直付けされるイグナイタなどに適用することができる。   In this embodiment, the application of the semiconductor device 100 is not particularly mentioned. However, as described above, the semiconductor device 100 has a remarkable effect that the peeling of the resin part 40 is prevented from reaching the connection region 15 with respect to the temperature change of the surrounding environment. Therefore, the semiconductor device 100 can be applied to, for example, an igniter that is directly attached to a vehicle engine or the like.

（変形例６）
本実施形態では１つの電子素子２０が一面１３ａに搭載（固定）された例を示した。しかしながら図２１に示すように一面１３ａに搭載される電子素子２０の数としては複数であってもよい。そして例えば図２２〜図３０に示すように２つの電子素子２０の間に接続領域１５が位置する場合、抑制部５０としてはこれら２つの電子素子２０からの樹脂部４０との剥離が接続領域１５に迫るのを抑制するべく、接続領域１５を囲む形状が好ましい。すなわち、抑制部５０は接続領域１５の四方の全てを囲む形状が好ましい。これによれば抑制部５０によって第１領域と第２領域とが分けられる。 (Modification 6)
In the present embodiment, an example in which one electronic element 20 is mounted (fixed) on one surface 13a is shown. However, as shown in FIG. 21, the number of electronic elements 20 mounted on one surface 13a may be plural. For example, when the connection region 15 is located between the two electronic elements 20 as shown in FIGS. 22 to 30, the restraining part 50 is separated from the resin part 40 from the two electronic elements 20. The shape surrounding the connection region 15 is preferable in order to suppress the approach. That is, the suppressing part 50 preferably has a shape surrounding all four sides of the connection region 15. According to this, the first region and the second region are separated by the suppressing unit 50.

図２２〜図３０に示す抑制部５０はそれぞれ、第１貫通孔５５と第２貫通孔５６を有し、第１溝５３と第２溝５４を有している。図２２では第１溝５３が２つの溝５３ａ，５３ｂに分けられ、第２溝５４は２つの溝５４ａ，５４ｂに分けられている。そして第１貫通孔５５の一端に溝５３ａが連結され、他端に溝５４ａが連結されている。同様にして第２貫通孔５６の一端に溝５３ｂが連結され、他端に溝５４ｂが連結されている。   Each of the suppressing portions 50 illustrated in FIGS. 22 to 30 includes a first through hole 55 and a second through hole 56, and includes a first groove 53 and a second groove 54. In FIG. 22, the first groove 53 is divided into two grooves 53a and 53b, and the second groove 54 is divided into two grooves 54a and 54b. A groove 53a is connected to one end of the first through hole 55, and a groove 54a is connected to the other end. Similarly, the groove 53b is connected to one end of the second through hole 56, and the groove 54b is connected to the other end.

そして図２３〜図３０では抑制部５０によって第１領域と第２領域とが完全に分断されている。図２３〜図２５では環状を成して第１領域と第２領域とを完全に分断するように、第１貫通孔５５の一端から第２貫通孔５６の一端へと第１溝５３が延び、第１貫通孔５５の他端から第２貫通孔５６の他端へと第２溝５４が延びている。図２３では貫通孔５５，５６それぞれがｙ方向に沿って延び、図２４では第１貫通孔５５がｙ方向に対して傾斜して延び第２貫通孔５６がｙ方向に沿って延びている。また図２５では貫通孔５５，５６それぞれがｙ方向に対して傾斜して延び、抑制部５０が平行四辺形を成している。これに対して図２６では、第１貫通孔５５は第２縁部１３ｄから第３縁部１３ｅの手前までｙ方向に沿って延びた形状を成し、第２貫通孔５６は第３縁部１３ｅから第２縁部１３ｄの手前までｙ方向に沿って延びた形状を成している。そして第２領域を囲むように、第２貫通孔５６の第２縁部１３ｄ側の端部から第１貫通孔５５へと第１溝５３がｘ方向に沿って延び、第１貫通孔５５の第３縁部１３ｅ側の端部から第２貫通孔５６へと第２溝５４がｘ方向に沿って延びている。以上示したように図２３〜図２６では貫通孔５５，５６それぞれが電子素子２０から接続領域１５へと向かうｘ方向に対して横断するようにアイランド１３に形成されている。特に図２３，２４，２６では貫通孔５５，５６の少なくとも一方がｙ方向に沿って延びた形状を成している。   In FIG. 23 to FIG. 30, the first region and the second region are completely divided by the suppressing unit 50. 23 to 25, the first groove 53 extends from one end of the first through hole 55 to one end of the second through hole 56 so as to form a ring and completely divide the first region and the second region. The second groove 54 extends from the other end of the first through hole 55 to the other end of the second through hole 56. In FIG. 23, each of the through holes 55 and 56 extends along the y direction, and in FIG. 24, the first through hole 55 extends while being inclined with respect to the y direction, and the second through hole 56 extends along the y direction. In FIG. 25, each of the through holes 55 and 56 extends while being inclined with respect to the y direction, and the suppressing portion 50 forms a parallelogram. On the other hand, in FIG. 26, the first through hole 55 has a shape extending in the y direction from the second edge 13d to the front of the third edge 13e, and the second through hole 56 is a third edge. It has a shape extending in the y direction from 13e to the front of the second edge 13d. The first groove 53 extends along the x direction from the end of the second through hole 56 on the second edge 13d side to the first through hole 55 so as to surround the second region. A second groove 54 extends from the end portion on the third edge portion 13e side to the second through hole 56 along the x direction. As described above, in FIGS. 23 to 26, the through holes 55 and 56 are formed on the island 13 so as to cross the x direction from the electronic element 20 toward the connection region 15. In particular, in FIGS. 23, 24 and 26, at least one of the through holes 55 and 56 has a shape extending along the y direction.

なお図２７〜図３０に示す抑制部５０は図２３〜図２６に示す抑制部５０に対して貫通孔と溝とを交換した構成である。このような対応関係にあるために図２７〜図３０の構成の説明を省略するが、これらの構成では溝５３，５４それぞれが電子素子２０から接続領域１５へと向かうｘ方向に対して横断するように、アイランド１３に形成されている。特に図２７，２８，３０では溝５３，５４の少なくとも一方がｙ方向に沿って延びた形状を成している。   In addition, the suppression part 50 shown in FIGS. 27-30 is the structure which replaced the through-hole and the groove | channel with respect to the suppression part 50 shown in FIGS. The description of the configurations of FIGS. 27 to 30 is omitted because of such a correspondence relationship, but in these configurations, the grooves 53 and 54 each cross the x direction from the electronic element 20 toward the connection region 15. Thus, it is formed on the island 13. 27, 28 and 30, in particular, at least one of the grooves 53 and 54 has a shape extending along the y direction.

最後に図３１に示すように、抑制部５０としては溝５１との連結端から貫通孔５５，５６それぞれが第２縁部１３ｄまで延びた形状を採用することもできる。   Finally, as shown in FIG. 31, a shape in which the through holes 55 and 56 each extend from the connecting end with the groove 51 to the second edge portion 13 d can be adopted as the suppressing portion 50.

１３・・・アイランド、１３ａ・・・一面、１３ｂ・・・裏面、１５・・・接続領域、２０・・・電子素子、３０・・・導電部材、４０・・・樹脂部、５０・・・抑制部、５１・・・溝、５２・・・貫通孔、１００・・・半導体装置 DESCRIPTION OF SYMBOLS 13 ... Island, 13a ... One side, 13b ... Back surface, 15 ... Connection area | region, 20 ... Electronic element, 30 ... Conductive member, 40 ... Resin part, 50 ... Suppressing part, 51 ... groove, 52 ... through hole, 100 ... semiconductor device

Claims (16)

導電プレート（１３）と、
前記導電プレートの一面（１３ａ）に搭載される電子素子（２０）と、
前記導電プレートの一面に接続される導電部材（３０）と、
前記導電プレート、前記電子素子、および、前記導電部材それぞれを一体的に被覆する樹脂部（４０）と、を有する半導体装置であって、
前記電子素子と前記樹脂部との線膨張係数差が前記導電部材と前記樹脂部との線膨張係数差よりも大きく、
前記導電プレートには、前記電子素子と前記樹脂部との線膨張係数差に起因する応力による前記樹脂部の剥離が前記導電プレートにおける前記導電部材との接続領域（１５）にまで及ぶことを抑制する抑制部（５０）が形成されており、
前記抑制部は、前記一面に形成された溝（５１）、および、前記一面からその裏面（１３ｂ）まで貫通する貫通孔（５２）を有し、
前記溝と前記貫通孔とが前記一面で連結されることで、前記溝によって構成される空間と前記貫通孔によって構成される空間とが連続的に連なっていることを特徴とする半導体装置。 A conductive plate (13);
An electronic element (20) mounted on one surface (13a) of the conductive plate;
A conductive member (30) connected to one surface of the conductive plate;
A semiconductor device having a resin portion (40) integrally covering each of the conductive plate, the electronic element, and the conductive member,
The linear expansion coefficient difference between the electronic element and the resin portion is larger than the linear expansion coefficient difference between the conductive member and the resin portion,
In the conductive plate, the peeling of the resin portion due to the stress caused by the difference in linear expansion coefficient between the electronic element and the resin portion is prevented from reaching the connection region (15) of the conductive plate with the conductive member. A restraining part (50) is formed,
The suppressing portion has a groove (51) formed on the one surface, and a through hole (52) penetrating from the one surface to the back surface (13b),
The semiconductor device according to claim 1, wherein the groove and the through hole are connected on the one surface, so that the space formed by the groove and the space formed by the through hole are continuously connected. 前記貫通孔は、前記電子素子から前記接続領域へと向かう進行方向に対して横断するように、前記導電プレートに形成されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the through-hole is formed in the conductive plate so as to cross a traveling direction from the electronic element toward the connection region. 前記一面は前記貫通孔によって前記電子素子が搭載される第１領域と前記導電部材が接続される第２領域とに分けられており、
前記溝は、前記進行方向に沿って前記貫通孔から前記第２領域の方へと延びた形状を成していることを特徴とする請求項２に記載の半導体装置。 The one surface is divided by the through hole into a first region where the electronic element is mounted and a second region where the conductive member is connected,
The semiconductor device according to claim 2, wherein the groove has a shape extending from the through hole toward the second region along the traveling direction. 前記抑制部は、前記溝として第１溝（５３）と第２溝（５４）を有しており、
前記第１溝は、前記進行方向に沿って前記貫通孔の一端から前記第２領域の方へと延びた形状を成し、
前記第２溝は、前記進行方向に沿って前記貫通孔の他端から前記第２領域の方へと延びた形状を成しており、
前記接続領域は前記第１溝と前記第２溝との間に位置していることを特徴とする請求項３に記載の半導体装置。 The suppression part has a first groove (53) and a second groove (54) as the groove,
The first groove has a shape extending from one end of the through hole toward the second region along the traveling direction,
The second groove has a shape extending from the other end of the through hole toward the second region along the traveling direction,
The semiconductor device according to claim 3, wherein the connection region is located between the first groove and the second groove. 前記溝は前記貫通孔から前記一面の縁部（１３ｄ，１３ｅ）まで延びた形状を成していることを特徴とする請求項２に記載の半導体装置。   3. The semiconductor device according to claim 2, wherein the groove has a shape extending from the through hole to an edge (13d, 13e) of the one surface. 前記抑制部は、前記溝として第１溝（５３）と第２溝（５４）を有しており、
前記第１溝は、前記貫通孔の一端から前記一面における前記進行方向に沿う第１縁部（１３ｄ）まで延びた形状を成し、
前記第２溝は、前記貫通孔の他端から前記一面における前記第１縁部と対向する第２縁部（１３ｅ）まで延びた形状を成しており、
前記一面は前記抑制部によって前記電子素子が搭載される第１領域と前記導電部材が接続される第２領域とに分断されていることを特徴とする請求項５に記載の半導体装置。 The suppression part has a first groove (53) and a second groove (54) as the groove,
The first groove has a shape extending from one end of the through hole to a first edge (13d) along the traveling direction on the one surface,
The second groove has a shape extending from the other end of the through hole to a second edge (13e) facing the first edge on the one surface,
6. The semiconductor device according to claim 5, wherein the one surface is divided into a first region where the electronic element is mounted and a second region where the conductive member is connected by the suppressing portion. 前記溝（５１）は、前記電子素子から前記接続領域へと向かう進行方向に対して横断するように、前記導電プレートに形成されていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the groove is formed in the conductive plate so as to cross a traveling direction from the electronic element toward the connection region. 前記一面は前記溝によって前記電子素子が搭載される第１領域と前記導電部材が接続される第２領域とに分けられており、
前記貫通孔（５２）は、前記進行方向に沿って前記溝から前記第２領域の方へと延びた形状を成していることを特徴とする請求項７に記載の半導体装置。 The one surface is divided by the groove into a first region where the electronic element is mounted and a second region where the conductive member is connected,
The semiconductor device according to claim 7, wherein the through hole (52) has a shape extending from the groove toward the second region along the traveling direction. 前記抑制部は、前記貫通孔として第１貫通孔（５５）と第２貫通孔（５６）を有しており、
前記第１貫通孔は、前記進行方向に沿って前記溝の一端から前記第２領域の方へと延びた形状を成し、
前記第２貫通孔は、前記進行方向に沿って前記溝の他端から前記第２領域の方へと延びた形状を成しており、
前記接続領域は前記第１貫通孔と前記第２貫通孔との間に位置していることを特徴とする請求項８に記載の半導体装置。 The suppression portion has a first through hole (55) and a second through hole (56) as the through hole,
The first through hole has a shape extending from one end of the groove toward the second region along the traveling direction,
The second through hole has a shape extending from the other end of the groove along the traveling direction toward the second region,
The semiconductor device according to claim 8, wherein the connection region is located between the first through hole and the second through hole. 前記貫通孔は前記溝から前記一面の縁部（１３ｄ，１３ｅ）まで延びた形状を成していることを特徴とする請求項７に記載の半導体装置。   The semiconductor device according to claim 7, wherein the through hole has a shape extending from the groove to the edge (13d, 13e) of the one surface. 前記抑制部は、前記貫通孔として第１貫通孔（５５）と第２貫通孔（５６）を有しており、
前記第１貫通孔は、前記溝の一端から前記一面における前記進行方向に沿う第１縁部（１３ｄ）まで延びた形状を成し、
前記第２貫通孔は、前記溝の他端から前記一面における前記第１縁部と対向する第２縁部（１３ｅ）まで延びた形状を成しており、
前記一面は前記抑制部によって前記電子素子が搭載される第１領域と前記導電部材が接続される第２領域とに分断されていることを特徴とする請求項１０に記載の半導体装置。 The suppression portion has a first through hole (55) and a second through hole (56) as the through hole,
The first through hole has a shape extending from one end of the groove to a first edge (13d) along the traveling direction on the one surface,
The second through hole has a shape extending from the other end of the groove to a second edge (13e) facing the first edge on the one surface,
11. The semiconductor device according to claim 10, wherein the one surface is divided into a first region where the electronic element is mounted and a second region where the conductive member is connected by the suppressing portion. 前記一面は前記貫通孔と前記溝とによって前記電子素子が搭載される第１領域と前記導電部材が接続される第２領域とに分けられており、
前記第２領域は前記貫通孔と前記溝とによって囲まれていることを特徴とする請求項１に記載の半導体装置。 The one surface is divided by the through hole and the groove into a first region where the electronic element is mounted and a second region where the conductive member is connected,
The semiconductor device according to claim 1, wherein the second region is surrounded by the through hole and the groove. 前記抑制部は、前記貫通孔として第１貫通孔（５５）と第２貫通孔（５６）を有し、前記溝として第１溝（５３）と第２溝（５４）を有しており、
環状を成して前記第１領域と前記第２領域とを分断するように、前記第１貫通孔の一端から前記第２貫通孔の一端へと前記第１溝が延び、前記第１貫通孔の他端から前記第２貫通孔の他端へと前記第２溝が延びていることを特徴とする請求項１２に記載の半導体装置。 The suppression portion has a first through hole (55) and a second through hole (56) as the through hole, and has a first groove (53) and a second groove (54) as the groove,
The first groove extends from one end of the first through hole to one end of the second through hole so as to divide the first region and the second region by forming an annular shape. The semiconductor device according to claim 12, wherein the second groove extends from the other end to the other end of the second through hole. 前記第１貫通孔および前記第２貫通孔の少なくとも一方、若しくは、前記第１溝および前記第２溝の少なくとも一方は、前記電子素子から前記接続領域へと向かう進行方向に対して横断するように、前記導電プレートに形成されていることを特徴とする請求項１３に記載の半導体装置。   At least one of the first through hole and the second through hole, or at least one of the first groove and the second groove crosses the traveling direction from the electronic element toward the connection region. The semiconductor device according to claim 13, wherein the semiconductor device is formed on the conductive plate. 前記抑制部は、前記貫通孔として第１貫通孔（５５）と第２貫通孔（５６）を有し、前記溝として第１溝（５３）と第２溝（５４）を有しており、
前記第１貫通孔は、前記一面における前記電子素子から前記接続領域へと向かう進行方向に沿う第１縁部（１３ｄ）から、前記一面における前記第１縁部と対向する第２縁部（１３ｅ）の手前まで延びた形状を成し、前記第２貫通孔は、前記第２縁部から前記第１縁部の手前まで延びた形状を成しており、
前記第２領域を囲むように、前記第２貫通孔の前記第１縁部側の端部から前記第１貫通孔へと前記第１溝が延び、前記第１貫通孔の前記第２縁部側の端部から前記第２貫通孔へと前記第２溝が延びていることを特徴とする請求項１２に記載の半導体装置。 The suppression portion has a first through hole (55) and a second through hole (56) as the through hole, and has a first groove (53) and a second groove (54) as the groove,
The first through hole extends from a first edge (13d) along a traveling direction from the electronic element to the connection region on the one surface, and a second edge (13e) facing the first edge on the one surface. ), And the second through hole has a shape extending from the second edge to the front of the first edge,
The first groove extends from the end of the second through hole on the first edge side to the first through hole so as to surround the second region, and the second edge of the first through hole The semiconductor device according to claim 12, wherein the second groove extends from a side end portion to the second through hole. 前記抑制部は、前記貫通孔として第１貫通孔（５５）と第２貫通孔（５６）を有し、前記溝として第１溝（５３）と第２溝（５４）を有しており、
前記第１溝は、前記一面における前記電子素子から前記接続領域へと向かう進行方向に沿う第１縁部（１３ｄ）から、前記一面における前記第１縁部と対向する第２縁部（１３ｅ）の手前まで延びた形状を成し、前記第２溝は、前記第２縁部から前記第１縁部の手前まで延びた形状を成しており、
前記第２領域を囲むように、前記第２溝の前記第１縁部側の端部から前記第１溝へと前記第１貫通孔が延び、前記第１溝の前記第２縁部側の端部から前記第２溝へと前記第２貫通孔が延びていることを特徴とする請求項１２に記載の半導体装置。 The suppression portion has a first through hole (55) and a second through hole (56) as the through hole, and has a first groove (53) and a second groove (54) as the groove,
The first groove extends from a first edge (13d) along a traveling direction from the electronic device to the connection region on the one surface, and a second edge (13e) facing the first edge on the one surface. The second groove has a shape extending from the second edge to the front of the first edge,
The first through hole extends from an end of the second groove on the first edge side to the first groove so as to surround the second region, and on the second edge side of the first groove. The semiconductor device according to claim 12, wherein the second through hole extends from an end portion to the second groove.
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