JP2015220765A - Control method for five-level power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control method for five-level power converter, capable of preventing two-level skipping during a dead time while controlling a voltage of a flying capacitor to be a desired value.SOLUTION: A Mode 1' in which a first, a second, a third and a fifth semiconductor elements S1, S2, S3, S5 are turned on is applied in place of a Mode 1 in which the first, the second, the third and the fifth semiconductor elements S1, S3, S5 are turned on. Similarly, a Mode 8' in which a sixth, an eighth, a ninth and a tenth semiconductor elements S6, S8, S9, S10 are turned on is applied in place of Mode 8 in which the sixth, the eighth and the tenth semiconductor elements S6, S8, S10 are turned on.

Description

  The present invention relates to a multi-phase power converter, and more particularly, to a switching pattern of a multi-level power converter characterized in that a common capacitor divided by four is used for each phase power converter.

  The power converter includes a main circuit switching element that is a semiconductor element. As a means for increasing the pressure of the power converter, a method of connecting a plurality of semiconductor elements in series can be mentioned. There has been proposed a power converter that outputs a voltage of five levels in the circuit configuration connected in series as described above.

  As one of the five-level power converters, a circuit configuration shown in Patent Document 1 has been proposed. The circuit of Patent Document 1 is obtained by reducing the number of flying capacitors to be used by reducing the number of flying capacitors to be used by making the flying capacitors to be used in common with an arbitrary number of phases.

  A representative circuit configuration of Patent Document 1 is shown in FIG. FIG. 7 shows a circuit configuration proposed in Embodiment 2 of Patent Document 1. (A) is the structure of a single phase inverter, (b) is the structure of a three-phase inverter. Phase U, Phase V, and Phase W in (a) and (b) have the same configuration.

  FIG. 8 shows each switching pattern in a phase shown in FIGS. 7 (a) and 7 (b). The voltage between the neutral point NP and the output terminal U is 2E in Mode1, E in Mode2 and Mode3, 0 in Mode4 and Mode5, -E in Mode6 and 7, -2E in Mode8, and can output a voltage of 5 levels. Is possible.

Here, as shown in FIG. 8, in the case of I> 0, the first flying capacitor C ₁ in Mode2 is charged, first flying capacitor C ₁ in Mode3 is discharged. In the case of I> 0, the second flying capacitor C ₂ in Mode6 is charged, the second flying capacitor C ₂ in Mode7 is discharged. Thus, E, Mode2 in accordance with the polarity of the period to the current I which outputs a voltage of -E, first flying capacitor by selecting Mode3 C _1, Mode 6, a second flying capacitor C by selecting the Mode7 ₂ charging and discharging can be selected. As a result, the first and second flying capacitors C ₁ and C ₂ can be controlled to set voltage values.

The circuit of FIG. 7 can charge and discharge the first and second flying capacitors C ₁ and C ₂ without looking at the polarity of the current. Therefore, since control can be performed without using a current sensor, and control can be performed without using the polarity of current, control can be performed without being affected by carrier ripple or noise.

  There is Non-Patent Document 1 as a paper examining the current flowing into the flying capacitor of the five-level power converter. The circuit studied in Non-Patent Document 1 is different from the configuration proposed in the present invention, but the concept can be applied.

  In Non-Patent Document 1, attention is paid to a phase module for one leg among the six phase modules, and the time average value of the current during the period E, −E is examined as the current flowing through the flying capacitor. This concept can also be applied to the circuit of FIG.

  In the circuit of FIG. 7, attention is paid to the current flowing during the period of E and −E, as in Non-Patent Document 1. When the output voltage of the five-level power converter is expressed by equation (1), the current flowing during the period of E and −E can be expressed by equation (2) when unitized. M represents the modulation rate of the 5-level power converter. When the equation (2) is used and the horizontal axis represents the modulation factor, the average current amount is as shown in FIG. At this time, the switching frequency of the switching element is sufficiently high.

  As can be seen from FIG. 9, the average value of the current flowing during the period E (Mode 2 and Mode 3 in FIG. 8) varies depending on the modulation rate, but the polarity of the current I is always the same. The same applies to the period -E (Modes 6 and 7 in FIG. 8).

Therefore, the first flying capacitor C ₁ can be charged if the period T 2 of Mode 2 is longer than the period T 3 of Mode 3, and the first flying capacitor C ₁ can be discharged if the period T 3 of Mode 3 is longer than the period T 2 of Mode 2. Similarly, the period T6 for Mode 6 The longer than the period T7 of Mode7 charging a second flying capacitor C _2, can be discharged a second flying capacitor C ₂ if the period T7 of Mode7 longer than the period T6 of the Mode 6.

Therefore, since the charging / discharging of the first and second flying capacitors C ₁ and C ₂ can be selected without detecting the instantaneous current polarity, the voltage can be controlled to be constant. In particular, the voltage of the first and second flying capacitors C ₁ and C ₂ can be maintained at a constant value by satisfying the following equations (3) and (4) during the output period of E or −E.

  This control method has an advantage that a current detector is unnecessary in the voltage control of the flying capacitor.

Japanese Patent Application No. 2013-132261

"A Sinousoid PWM Method With Voltage Balancing Capability for Diode-Clumped Five-Level Converters" IEEE TRANSACTIONS ON INDUSTRY APPLICATION. 45, NO. 3, MAY / JUNE 2009

  However, in the case of only the switching pattern of Patent Document 1, there arises a problem that two-level skip occurs due to the influence of dead time. Here, the dead time is a time lag provided to prevent a short-circuit state of the semiconductor element that may be caused by a turn-off delay time of the semiconductor element when the semiconductor element changes state from off to on. This is shown in FIG. In FIG. 10, ◯ represents a conducting semiconductor element, and a broken line ◯ represents a conducting diode.

  In FIG. 10, when the current I is flowing in the direction of the arrow, when the mode changes from 2E to E, the output voltage changes to 0 during the dead time period, so that a two-level skip from 2E to 0 occurs. Yes. This occurs to turn off the third semiconductor element S3. Since a voltage is applied in the direction in which the diode connected in parallel to the semiconductor element is conducted due to the influence of the reactor of the load, a phenomenon as shown in FIG. 10 occurs. At this time, as shown in FIG. 10B, a current of a dotted line flows and a voltage of 0 is output. That is, a two-level skip of 2E → 0 occurs during the transition from (a) to (b). When the two-level skip occurs, it causes a breakdown of the load, and it is necessary to suppress this.

  As described above, in the control method of the five-level power converter, it is a problem that the two-level skip is not generated even in the dead time while the voltage of the flying capacitor is controlled to a desired value.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is that each of the two DC voltage sources connected in series has one end connected to the negative electrode end of the upper DC voltage source. A first common switch common to each phase, a second common switch common to each phase, one end of which is connected to the positive terminal of the lower DC voltage source among the two DC voltage sources connected in series, and a first common switch A common first flying capacitor having one end connected to the other end, a second flying capacitor common to each phase having one end connected to the other end of the second common switch, and a positive terminal of the upper DC voltage source The first semiconductor element, the third semiconductor element, and the fourth semiconductor element of each phase sequentially connected in series between the first common switch and the other end of the first common switch, and a common connection point of the first semiconductor element and the third semiconductor element Each phase inserted between the other end of the first flying capacitor A seventh semiconductor element, an eighth semiconductor element, and a tenth semiconductor element of each phase sequentially connected in series between the other end of the second semiconductor element and the other end of the second common switch and the negative end of the lower DC voltage source; A ninth semiconductor element of each phase interposed between a common connection point of the eighth semiconductor element and the tenth semiconductor element and the other end of the second flying capacitor, and a common connection of the third semiconductor element and the fourth semiconductor element A fifth semiconductor element of each phase having one end connected to the point, and a sixth semiconductor element of each phase having one end connected to a common connection point of the seventh semiconductor element and the eighth semiconductor element. A single-phase five-level power converter comprising a common connection point where the other end of the fifth semiconductor element and the other end of the sixth semiconductor element are connected as an output terminal, and two each of the first to tenth semiconductor elements. A control method, which is shown in Table 3, Mode 1 ′, Mode 2, Mode 3, It has a switching pattern of mode 4, Mode 5, Mode 6, Mode 7 and Mode 8 ′, and Mode 1 ′ to Mode 2 or Mode 3, Mode 2 to Mode 1 ′ or Mode 3 or Mode 4 or Mode 5, Mode 3 to Mode 1 ′ or Mode 2 or Mode 4, and Mode 4 to Mode 2 or Mode 3 or Mode 5 or Mode 6, Mode 5 to Mode 2 or Mode 4 or Mode 6 or Mode 7, Mode 6 to Mode 4 or Mode 5 or Mode 7 or Mode 8 ′, Mode 7 to Mode 5 or Mode 6 or Mode 8 ′, Mode 8 ′ to Mode 6 or Mode 7 And

  Further, as another aspect, among the two DC voltage sources connected in series, the first common switch common to each phase whose one end is connected to the negative electrode end of the upper DC voltage source, and two connected in series A second common switch common to each phase with one end connected to the positive terminal of the lower DC voltage source among the DC voltage sources, and a first flying capacitor common to each phase with one end connected to the other end of the first common switch And a second flying capacitor common to each phase, one end of which is connected to the other end of the second common switch, and a positive terminal of the upper DC voltage source and the other end of the first common switch. The first semiconductor element, the third semiconductor element, and the fourth semiconductor element of each phase, and each of the first semiconductor element and the third semiconductor element interposed between the common connection point and the other end of the first flying capacitor. Phase second semiconductor element and the other end of the second common switch The seventh semiconductor element, the eighth semiconductor element, the tenth semiconductor element of each phase sequentially connected in series between the negative electrode terminal of the lower DC voltage source, and the common connection point of the eighth semiconductor element and the tenth semiconductor element A ninth semiconductor element of each phase interposed between the other end of the second flying capacitor and a fifth semiconductor element of each phase having one end connected to a common connection point of the third semiconductor element and the fourth semiconductor element And a sixth semiconductor element of each phase whose one end is connected to a common connection point of the seventh semiconductor element and the eighth semiconductor element, and the other end of the fifth semiconductor element of each phase and the other of the sixth semiconductor element A method for controlling a three-phase or more five-level power converter including three or more of the first to tenth semiconductor elements, the common connection point having an end connected as an output terminal, Mode1 ', Mode2, Mode3, Mode4, Mode5 Mode 1 to Mode 1 'or Mode 3, Mode 1' to Mode 1 or Mode 2 or Mode 3, Mode 2 to Mode 1 'or Mode 3 or Mode 4 or Mode 5, Mode 3 to Mode 1 or Mode 1' or Mode 2 having switching patterns of Mode 6, Mode 7, Mode 8, and Mode 8 '. Or Mode4, Mode4 to Mode2 or Mode3 or Mode5 or Mode6, Mode5 to Mode2 or Mode4 or Mode6 or Mode7, Mode6 to Mode4 or Mode5 or Mode7 or Mode8 ′, Mode7 to Mode5 or Mode6 or Mode8 or Mode8′Mode8 to Mode7 or Mode The switching pattern is transited from de8 ', Mode8' to Mode6, Mode7 or Mode8.

  Further, as one aspect thereof, the voltage of the first and second flying capacitors is controlled based on the time of the switching pattern without detecting the current polarities of the first and second flying capacitors.

  According to the present invention, in the control method of the five-level power converter, it is possible to prevent the two-level skip from occurring even during the dead time while controlling the voltage of the flying capacitor to a desired value.

Schematic which shows the influence of the dead time at the time of Mode1 'application. FIG. 3 is an explanatory diagram showing state transition of a switching pattern in the first embodiment. Schematic which shows a simultaneous selection prohibition pattern. Explanatory drawing which shows the state transition of the switching pattern in Embodiment 2. FIG. Explanatory drawing which shows the state transition of the switching pattern in consideration of dead time. Explanatory drawing which shows the state transition of the switching pattern in consideration of dead time. Explanatory drawing which shows the state transition of the switching pattern in consideration of dead time. The time chart which shows the phase voltage waveform at the time of application / non-application of the state transition of the switching pattern in Embodiment 2. The circuit diagram which shows the conventional 5 level power converter. The circuit diagram which shows each switching pattern. The graph which shows the relationship between the average current which flows during the period of output voltage E and -E, and a modulation factor. The circuit diagram which shows the example which 2 level skip generate | occur | produces during dead time.

An object of the present invention is to prevent the two-level skip from occurring even during the dead time period while controlling the voltages of the first and second flying capacitors C ₁ and C ₂ to desired values.

  Hereinafter, Embodiments 1 and 2 in a control method for a five-level power converter according to the present invention will be described in detail with reference to FIGS.

[Embodiment 1]
In the first embodiment, a switching pattern in which a two-level skip is not generated even in the dead time period in the single-phase five-level power converter having the configuration of FIG. 7A will be described.

  Here, the configuration of the single-phase five-level power converter shown in FIG.

A first common switch S _C1 common to two phases, one end of which is connected to the negative terminal of the upper DC voltage source C _DC1 among the two DC voltage sources C _DC1 and C _DC2 connected in series, and the first common switch S first and flying capacitor C ₁ which is one end to the other end of _C1 is connected, 2 phases which are sequentially connected in series between the positive terminal and the other end of the first common switch S _C1 of the upper DC voltage source C _DC1 First semiconductor elements S _1U , S _1V , third semiconductor elements S _3U , S _3V , fourth semiconductor elements S _4U , S _4V , first semiconductor elements S _1U , S _1V , third semiconductor elements S _3U , S Second semiconductor elements S _2U and S _2V interposed between the common connection point of _3V and the other end of the first flying capacitor C ₁ .

A second common switch S _C2 common to two phases, one end of which is connected to the positive terminal of the lower DC voltage source C _DC2 among the two DC voltage sources C _DC1 and C _DC2 connected in series, and a second common switch The second flying capacitor C ₂ having one end connected to the other end of the switch S _{C2 and} the other end of the second common switch S _C2 and the negative end of the lower DC voltage source C _DC2 are sequentially connected in series 2 Phase seventh semiconductor elements S _7U , S _7V , eighth semiconductor elements S _8U , S _8V , tenth semiconductor elements S _10U , S _10V , eighth semiconductor elements S _8U , S _8V , and tenth semiconductor element S _10U , S _10V and ninth semiconductor elements S _9U , S _9V interposed between the common connection point of S _10V and the other end of the second flying capacitor C ₂ .

Also, one end of the fifth semiconductor elements S _5U and S _5V is connected to a common connection point of the third semiconductor elements S _3U and S _3V and the fourth semiconductor elements S _4U and S _4V . One _{ends of} the sixth semiconductor elements S _6U and S _6V are connected to a common connection point of the seventh semiconductor elements S _7U and S _7V and the eighth semiconductor elements S _8U and S _8V . The other _{ends of} the fifth semiconductor elements S _5U and S _5V are connected to the other _{ends of} the sixth semiconductor elements S _6U and S _6V , and the connection points become the output terminals U and V.

Here, the first to tenth semiconductor elements S _{1U to} S _10U are U-phase modules, the first to tenth semiconductor elements S _{1V to} S _10V are V-phase modules, and the first to tenth semiconductor elements S _1W. A phase module of W phase is configured with ~ ₁₀ W.

For switching pattern of Figure 10, if turned on a second semiconductor element S ₂ during Mode1 selection, it is possible to output a phase voltage of E in the dead time even when the transition from Mode1 to Mode2. Therefore, 2 level skip does not occur. Therefore, when transitioning from Mode 1 to Mode 2, it is necessary to use a new pattern for selecting the second semiconductor element S ₂ . In the first embodiment, this new Mode is defined as Mode 1 ′. Similarly, in the case of Mode 8, it is necessary to turn on the ninth semiconductor element S ₉ when transitioning from Mode 8 to Mode 6.

FIG. 1 shows a specific example when Mode 1 ′ is applied. As shown in FIG. 1, when the second semiconductor element S ₂ is turned on in advance, the applied voltage between the collector and the emitter of the first common switch S _c1 becomes 2E−E = E in the period of FIG. The antiparallel diode in one common switch S _c1 is not conducting. Therefore, a current in a dotted line path flows. Therefore, switching can be performed without skipping two levels from 2E to 0 as shown in FIG. Even when the MODE8 transition Mode 6, a state to turn on the ninth semiconductor device S ₉ similarly defined as MODE8 '.

  FIG. 2 shows a detailed state transition diagram of the switching pattern based on the commutation phenomenon as shown in FIG. FIG. 2A shows a conventional state transition pattern, and FIG. 2B shows a state transition pattern according to the first embodiment.

  The arrow in FIG. 2 represents the direction of transition, and indicates that the state of both bidirectional arrows can be transitioned. In principle, transitions are performed one level at a time, such as 2E to E and E to 0, and basically any state can be transitioned to. However, patterns from Mode 3 to Mode 5 and Mode 4 to Mode 7 are prohibited because level skip occurs due to commutation during the dead time period.

  As described above, according to the first embodiment, the level skip can be suppressed even during the dead time period in the control method of the five-level power converter having two or more phases. Thereby, the dielectric breakdown of a load can be reduced.

  In the first embodiment, as described above, the current detector is not required by controlling the voltage of the flying capacitor based on the time of the switching pattern.

[Embodiment 2]
In the second embodiment, the state transition of the switching pattern in the three-phase five-level power converter configured as shown in FIG. 7B will be described. The circuit configuration of FIG. 7B is the same as the circuit configuration of FIG.

When the number of phases is 3 or more, since the first common switch S _C1 and the second common switch S _C2 exist, the charge / discharge control of the first and second flying capacitors C ₁ and C ₂ is restricted. An example is shown in FIG.

As shown in FIGS. 3A and 3B, when two phases select Mode1 ′ and Mode8 ′, if the remaining one phase tries to output a phase voltage level of 0, the remaining one phase Needs to select Mode4 or Mode5. In Mode 4 and Mode 5, since it is necessary to turn on the first common switch S _C1 or the second common switch S _C2 , the upper DC voltage source C _DC1 (or the lower DC voltage source C _DC2 ) and the first flying capacitor C ₁ (or the second flying capacitor C ₂ ) is short-circuited by the first common switch S _C1 or the second common switch S _C2 . In order to avoid this short-circuit state, Mode 1 ′ cannot be selected simultaneously with Mode 4 (Mode 8 ′ is Mode 5). Similarly, as shown in FIGS. 3C and 3D, Mode2 cannot be selected simultaneously with Mode4, and Mode6 cannot be selected simultaneously with Mode5. On the other hand, when Mode 4 or Mode 5 cannot be selected, the phase voltage level of 0 cannot be output, so that the output voltage distortion is greatly increased.

  Therefore, when Mode 4 is selected in a certain phase, Mode 1 is selected instead of Mode 1 'in the other phase. Similarly, when Mode 5 is selected in a certain phase, Mode 8 is selected instead of Mode 8 'in the other phase. If these combinations are used, the above short-circuit state can be avoided.

  Table 1 shows selectable switching pattern combinations (◯) and switching pattern combinations (x) that cannot be selected because the above-described short circuit occurs in the three-phase five-level power converter of FIG.

  FIG. 4B shows a transition pattern that satisfies the combinations of the switching patterns in Table 1 and that does not cause a level skip in the state transition of the switching patterns.

  In the transition pattern of FIG. 4B, all three-phase switching patterns are selected from group A, or all three-phase switching patterns are selected from group B. Therefore, the pattern combinations in Table 1 are satisfied.

  Moreover, the arrow in FIG. 4 represents the direction of transition, and indicates that the state of either of the bidirectional arrows can be transitioned. In principle, transitions are performed one level at a time, such as 2E to E and E to 0, and can basically transition to any state. However, patterns from Mode 1 to Mode 2, Mode 3 to Mode 5, Mode 4 to Mode 7, and Mode 6 to Mode 8 are prohibited because level skip occurs due to commutation during the dead time period.

  5A to 5C and Table 2 show all switching patterns. 5A to 5C, the fourth to seventh semiconductor elements S4 to S7 are configured by connecting two semiconductor elements in series. Table 2 summarizes all switching patterns. Further, FIG. 6 shows simulation results when the switching pattern of the second embodiment is applied and when it is not applied. FIG. 6A shows a case where the switching pattern of the second embodiment is applied, and FIG. 6B shows a case where the switching pattern of the second embodiment is not applied. FIG. 6C is an enlarged view of FIG.

  As can be seen from FIG. 6, when the switching pattern state transition of the second embodiment is not applied (FIGS. 6B and 6C), a two-level skip from 0 to 2E occurs. However, in the case where the switching pattern state transition of the second embodiment is applied (FIG. 6A), it can be seen that the two-level skip can be avoided.

  The invention of the second embodiment can be applied not only to a three-phase five-level power converter but also to a five-level power converter having four or more phases.

  As described above, according to the second embodiment, the same operational effects as those of the first embodiment can be obtained. Further, in a five-level power converter having three or more phases, level skip can be prevented even during a dead time period without increasing output voltage distortion.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

S1 to S10 ... 1st to 10th semiconductor elements C _DC1 and C _DC2 ... (upper and lower stages) DC voltage sources C ₁ and C ₂ ... first and second flying capacitors S _C1 and S _C2 ... common switches

Claims (3)

A first common switch common to each phase, one end of which is connected to the negative end of the upper DC voltage source among the two DC voltage sources connected in series;
A second common switch common to each phase, one end of which is connected to the positive terminal of the lower DC voltage source among the two DC voltage sources connected in series;
A first flying capacitor common to each phase with one end connected to the other end of the first common switch;
A second flying capacitor common to each phase with one end connected to the other end of the second common switch;
A first semiconductor element, a third semiconductor element, and a fourth semiconductor element of each phase sequentially connected in series between the positive terminal of the upper DC voltage source and the other end of the first common switch;
A second semiconductor element of each phase interposed between a common connection point of the first semiconductor element and the third semiconductor element and the other end of the first flying capacitor;
A seventh semiconductor element, an eighth semiconductor element, and a tenth semiconductor element of each phase sequentially connected in series between the other end of the second common switch and the negative electrode end of the lower DC voltage source;
A ninth semiconductor element of each phase interposed between a common connection point of the eighth semiconductor element and the tenth semiconductor element and the other end of the second flying capacitor;
A fifth semiconductor element of each phase having one end connected to a common connection point of the third semiconductor element and the fourth semiconductor element;
A sixth semiconductor element of each phase having one end connected to a common connection point of the seventh semiconductor element and the eighth semiconductor element;
A single-phase five-level power having two first to tenth semiconductor elements each having a common connection point where the other end of the fifth semiconductor element and the other end of the sixth semiconductor element are connected to each other as an output terminal A method for controlling a converter,
It has a switching pattern of Mode1 ′, Mode2, Mode3, Mode4, Mode5, Mode6, Mode7, Mode8 ′ shown in Table 3,
Mode1 'to Mode2 or Mode3, Mode2 to Mode1' or Mode3 or Mode4 or Mode5, Mode3 to Mode1 'or Mode2 or Mode4, Mode4 to Mode2 or Mode3 or Mode5 or Mode6, Mode5 to Mode2 or Mode4 or Mode6 or Mode7, Mode4 to Mode7 Alternatively, the control method of the five-level power converter is characterized in that the switching pattern is transitioned from Mode 5 to Mode 7 or Mode 8 ′, from Mode 7 to Mode 5 or Mode 6 or Mode 8 ′, and from Mode 8 ′ to Mode 6 or Mode 7.

A first common switch common to each phase, one end of which is connected to the negative end of the upper DC voltage source among the two DC voltage sources connected in series;
A second common switch common to each phase, one end of which is connected to the positive terminal of the lower DC voltage source among the two DC voltage sources connected in series;
A first flying capacitor common to each phase with one end connected to the other end of the first common switch;
A second flying capacitor common to each phase with one end connected to the other end of the second common switch;
A first semiconductor element, a third semiconductor element, and a fourth semiconductor element of each phase sequentially connected in series between the positive terminal of the upper DC voltage source and the other end of the first common switch;
A second semiconductor element of each phase interposed between a common connection point of the first semiconductor element and the third semiconductor element and the other end of the first flying capacitor;
A seventh semiconductor element, an eighth semiconductor element, and a tenth semiconductor element of each phase sequentially connected in series between the other end of the second common switch and the negative electrode end of the lower DC voltage source;
A ninth semiconductor element of each phase interposed between a common connection point of the eighth semiconductor element and the tenth semiconductor element and the other end of the second flying capacitor;
A fifth semiconductor element of each phase having one end connected to a common connection point of the third semiconductor element and the fourth semiconductor element;
A sixth semiconductor element of each phase having one end connected to a common connection point of the seventh semiconductor element and the eighth semiconductor element;
The common connection point where the other end of the fifth semiconductor element of each phase and the other end of the sixth semiconductor element are connected is used as an output terminal, and three or more phases of 5 having three or more of the first to tenth semiconductor elements. A level power converter control method comprising:
It has switching patterns of Mode1, Mode1 ′, Mode2, Mode3, Mode4, Mode5, Mode6, Mode7, Mode8, Mode8 ′ shown in Table 3,
Mode1 to Mode1 'or Mode3, Mode1' to Mode1 or Mode2 or Mode3, Mode2 to Mode1 'or Mode3 or Mode4 or Mode5, Mode3 to Mode1 or Mode1' or Mode2 or Mode4, Mode4 to Mode2 or Mode3 or Mode5 or Mode6, Mode5 Mode 2 or Mode 4 or Mode 6 or Mode 7, Mode 6 to Mode 4 or Mode 5 or Mode 7 or Mode 8 ', Mode 7 to Mode 5 or Mode 6 or Mode 8 or Mode 8' Mode 8 to Mode 7 or Mode 8 ', Mode 8' to Mode 6 or Mode 7 or Mode 8 or switching pattern 5 level control method of the power converter, characterized in that to make a transition to.

  3. The five-level power conversion according to claim 1, wherein the voltage of the first and second flying capacitors is controlled based on the time of the switching pattern without detecting the current polarity of the first and second flying capacitors. Control method.

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