JP2015211059A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2015211059A
JP2015211059A JP2014089850A JP2014089850A JP2015211059A JP 2015211059 A JP2015211059 A JP 2015211059A JP 2014089850 A JP2014089850 A JP 2014089850A JP 2014089850 A JP2014089850 A JP 2014089850A JP 2015211059 A JP2015211059 A JP 2015211059A
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semiconductor chip
film portion
thick film
semiconductor device
wiring board
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英宏 竹嶋
Hidehiro Takeshima
英宏 竹嶋
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Micron Technology Inc
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Micron Technology Inc
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method of the same, which can reduce labor hour and increase an integration degree.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming a first insulation film on one side of a first substrate; a process of forming at least one first opening and a plurality of second openings; a process of mounting a first semiconductor chip on one surface of the first substrate and in the first opening; a process of supplying a plurality of first solder balls in the plurality of second openings; a process of fusing the plurality of first solder balls to form a plurality of first conductor parts in the plurality of second openings; and a process of mounting a plurality of second solder balls connected with the plurality of first conductor parts on the first insulation film to form a plurality of first external electrodes.

Description

本発明は、半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

複数のパッケージを積み重ねて搭載したPoP(Package on Package)タイプの半導体装置を携帯機器等の小型電子装置に搭載するため、このタイプの半導体装置に対する小型化および薄型化の要求がある。そこで、薄型化を実現するため、半導体装置を構成する配線基板の厚さを薄くしたり、封止樹脂層の厚さを薄くしたりしている。しかしながら、薄型化によって、半導体装置の反りが生じやすくなるという問題が発生している。   Since a PoP (Package on Package) type semiconductor device in which a plurality of packages are stacked and mounted is mounted on a small electronic device such as a portable device, there is a demand for downsizing and thinning of this type of semiconductor device. Therefore, in order to reduce the thickness, the thickness of the wiring board constituting the semiconductor device is reduced, and the thickness of the sealing resin layer is reduced. However, there is a problem that the semiconductor device is likely to warp due to the reduction in thickness.

特許文献１には、薄型化した配線基板自体の反りを軽減するため、配線基板の一面を被覆する一方のソルダーレジスト層の厚さと、配線基板の他面を被覆する他方のソルダーレジスト層の厚さを異なる厚さに形成する技術の開示がある。   In Patent Document 1, in order to reduce the warpage of the thinned wiring board itself, the thickness of one solder resist layer covering one side of the wiring board and the thickness of the other solder resist layer covering the other side of the wiring board are disclosed. There is a disclosure of a technique for forming the thicknesses at different thicknesses.

特許文献２には、プリント配線板の表面に搭載する電子部品によるプリント配線板の反りを相殺するために、プリント配線板表面のレジストと同裏面のレジストの厚さとを変える開示がある。   Japanese Patent Application Laid-Open No. 2005-228561 discloses that the resist on the surface of the printed wiring board and the resist on the back surface are changed in order to cancel the warpage of the printed wiring board due to electronic components mounted on the surface of the printed wiring board.

特許文献３には、半導体装置の反りを低減するために、配線基板の表面上において、半導体チップ搭載領域上に形成されたソルダーレジストを除去する開示がある。   Japanese Patent Application Laid-Open No. 2004-228688 discloses that a solder resist formed on a semiconductor chip mounting region is removed on the surface of a wiring board in order to reduce warpage of the semiconductor device.

特許文献４には、半導体装置の反りを低減するために、配線基板と封止樹脂の間に低弾性樹脂を配置する開示がある。   Patent Document 4 discloses that a low-elasticity resin is disposed between a wiring board and a sealing resin in order to reduce warpage of a semiconductor device.

特開平９−１７２１０４号公報JP-A-9-172104 特開２００７−２４２６７４号公報JP 2007-242673 A 特開２０１１−２３３６１０号公報JP 2011-233610 A 特開２０１４−０１３８３６号公報JP, 2014-013836, A

以下の分析は、本願発明者により与えられる。   The following analysis is given by the inventor.

配線基板単独では反りが低減されていても、完成品である半導体装置においては反りが生じるおそれがある。その理由を以下に説明する。   Even if the warping is reduced by the wiring board alone, the warping may occur in the semiconductor device as a finished product. The reason will be described below.

配線基板の一面に半導体チップが搭載された後、この一面上に、半導体チップを覆うよう封止樹脂が供給される。配線基板の一面上、中央領域には、半導体チップが配置され、周辺領域には半導体チップが配置されていない。したがって、中央領域と周辺領域とは、封止樹脂の供給量が大きく異なり、すなわち、配線基板の一面上で封止樹脂の容積差が発生する。この容積差に起因して、封止樹脂が硬化する際、中央領域と周辺領域とでは、封止樹脂収縮量の差が大きくなり、完成品である半導体装置において反りが大きくなるおそれがある。特にPoP(Package on Package)タイプのような、配線基板のサイズよりも半導体チップのサイズが大幅に小さく、半導体チップ上の封止樹脂層の厚さが薄い半導体装置では、配線基板の隅部で反りが大きくなるおそれがある。この結果、下段の半導体装置や実装基板への実装性が低下し、信頼性が低下する。また半導体装置の反りが大きくなることで、半導体装置の全高が高くなり、携帯機器への搭載が困難になるおそれがある。   After the semiconductor chip is mounted on one surface of the wiring board, a sealing resin is supplied on the one surface so as to cover the semiconductor chip. On one surface of the wiring board, a semiconductor chip is disposed in the central region, and no semiconductor chip is disposed in the peripheral region. Therefore, the supply amount of the sealing resin differs greatly between the central region and the peripheral region, that is, a volume difference of the sealing resin occurs on one surface of the wiring board. Due to this volume difference, when the sealing resin is cured, the difference in the amount of shrinkage of the sealing resin between the central region and the peripheral region becomes large, and there is a possibility that warpage is increased in the finished semiconductor device. Especially in semiconductor devices such as the PoP (Package on Package) type, where the size of the semiconductor chip is significantly smaller than the size of the wiring board and the sealing resin layer on the semiconductor chip is thin, There is a risk of warping becoming large. As a result, the mounting property to the lower semiconductor device or the mounting substrate is lowered, and the reliability is lowered. Further, since the warpage of the semiconductor device is increased, the overall height of the semiconductor device is increased, which may make it difficult to mount it on a portable device.

かくして、半導体装置の反りを抑制することができる構造を有する半導体装置およびその製造方法が求められている。   Thus, there is a need for a semiconductor device having a structure capable of suppressing warpage of the semiconductor device and a method for manufacturing the same.

第１の視点において、半導体装置は、配線基板と、前記配線基板の一面上に搭載される半導体チップと、前記配線基板の一面上に、前記半導体チップの高さと同等の高さを有するよう形成される厚膜部と、前記配線基板の一面上に前記半導体チップおよび前記厚膜部を覆うよう形成され、前記半導体チップ上と前記厚膜部上で同等の厚さを有する封止層と、を備えている。なお、上記「高さ」とは、基準面となる配線基板の一面からの高さを意味している。半導体チップと厚膜部の高さは、所定の効果が得られる程度に同等であればよい。半導体チップ上と厚膜部上における封止層（封止材）の厚さは、所定の効果が得られる程度に同等であればよい。   In a first aspect, the semiconductor device is formed to have a wiring board, a semiconductor chip mounted on one surface of the wiring board, and a height equivalent to the height of the semiconductor chip on the one surface of the wiring board. And a sealing layer formed on one surface of the wiring substrate so as to cover the semiconductor chip and the thick film portion, and having an equivalent thickness on the semiconductor chip and the thick film portion, It has. The “height” refers to the height from one surface of the wiring board that serves as a reference surface. The heights of the semiconductor chip and the thick film portion may be equal to the extent that a predetermined effect can be obtained. The thickness of the sealing layer (sealing material) on the semiconductor chip and the thick film portion may be equal to the extent that a predetermined effect can be obtained.

第２の視点において、半導体装置の製造方法は、配線基板の一面上の周辺領域に、厚膜部を、搭載する半導体チップと同等の高さを有するよう形成する工程と、前記配線基板の一面上の中央領域に、前記半導体チップを搭載する工程と、前記配線基板の一面上に、前記半導体チップおよび前記厚膜部を覆い、前記半導体チップ上と前記厚膜部上で同等の厚さを有する封止層を形成する工程と、を備えている。   In a second aspect, a method for manufacturing a semiconductor device includes a step of forming a thick film portion in a peripheral region on one surface of a wiring substrate so as to have a height equivalent to a semiconductor chip to be mounted, and one surface of the wiring substrate. A step of mounting the semiconductor chip in the upper central region; and covering the semiconductor chip and the thick film portion on one surface of the wiring substrate, and providing an equivalent thickness on the semiconductor chip and the thick film portion. Forming a sealing layer.

本開示によれば、半導体装置の反りを抑制することができる構造を有する半導体装置およびその製造方法が提供される。   According to the present disclosure, a semiconductor device having a structure capable of suppressing warpage of the semiconductor device and a manufacturing method thereof are provided.

（Ａ）および（Ｂ）は、実施形態１の半導体装置の概略構成を模式的に示す図であって、（Ａ）は平面図、（Ｂ）は（Ａ）のＢ−Ｂ断面図である。FIGS. 2A and 2B are diagrams schematically illustrating a schematic configuration of the semiconductor device according to the first embodiment, where FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along line BB in FIG. . （Ａ）〜（Ｆ）は、図１に示した半導体装置の製造方法を説明するための工程図である。(A)-(F) are process drawings for demonstrating the manufacturing method of the semiconductor device shown in FIG. 実施形態２の半導体装置の概略構成を模式的に示す平面図である。FIG. 6 is a plan view schematically showing a schematic configuration of a semiconductor device according to a second embodiment. 実施形態３の半導体装置の概略構成を模式的に示す平面図である。FIG. 6 is a plan view schematically showing a schematic configuration of a semiconductor device according to a third embodiment. 実施形態４の半導体装置の概略構成を模式的に示す平面図である。FIG. 6 is a plan view schematically showing a schematic configuration of a semiconductor device according to a fourth embodiment. （Ａ）および（Ｂ）は、実施形態５の半導体装置の概略構成を模式的に示す図であって、（Ａ）は平面図、（Ｂ）は（Ａ）のＢ−Ｂ断面図である。(A) And (B) is a figure which shows typically schematic structure of the semiconductor device of Embodiment 5, Comprising: (A) is a top view, (B) is BB sectional drawing of (A). . （Ａ）および（Ｂ）は、実施形態６の半導体装置の概略構成を模式的に示す図であって、（Ａ）は、平面図、（Ｂ）は（Ａ）のＢ−Ｂ断面図である。(A) And (B) is a figure which shows the schematic structure of the semiconductor device of Embodiment 6 typically, (A) is a top view, (B) is BB sectional drawing of (A). is there. 実施形態７の半導体装置の概略構成を模式的に示す断面図である。FIG. 10 is a cross-sectional view schematically showing a schematic configuration of a semiconductor device of Embodiment 7.

以下、図面を参照しながら実施形態等を説明する。なお、本開示において図面参照符号を付している場合は、それらは、専ら理解を助けるためのものであり、図示の態様に限定することを意図するものではない。   Hereinafter, embodiments and the like will be described with reference to the drawings. Note that, in the present disclosure, where reference numerals are attached to the drawings, these are only for the purpose of assisting understanding, and are not intended to be limited to the illustrated embodiments.

［実施形態１］
図１（Ａ）および（Ｂ）を参照すると、実施形態１の半導体装置１は、一面側（図１（Ｂ）中の上側）に下記の構成を備えている。
配線基板１１；
配線基板１１の一面上に搭載される半導体チップ３１；
配線基板１１の一面上、半導体チップ３１の高さと同等の高さを有するよう形成される厚膜部２１ａ；
配線基板１１の一面上、半導体チップ３１および厚膜部２１ａを覆うよう形成され、半導体チップ３１上と厚膜部２１ａ上で同等の厚さを有する封止層（封止材）７２。 [Embodiment 1]
Referring to FIGS. 1A and 1B, the semiconductor device 1 of Embodiment 1 has the following configuration on one side (the upper side in FIG. 1B).
Wiring board 11;
A semiconductor chip 31 mounted on one surface of the wiring substrate 11;
A thick film portion 21a formed on one surface of the wiring substrate 11 to have a height equivalent to the height of the semiconductor chip 31;
A sealing layer (sealing material) 72 formed on one surface of the wiring substrate 11 so as to cover the semiconductor chip 31 and the thick film portion 21a and having the same thickness on the semiconductor chip 31 and the thick film portion 21a.

半導体チップ３１は、半導体装置１の一面上に、フェースアップ（回路面ないし電極パッド３１ａが表側にある）で搭載されている。厚膜部２１ａは、半導体チップ３１の外周側に、連続して形成されている。換言すると、厚膜部２１ａは、半導体チップ３１の外周全周を囲むよう環状（枠状）に形成されている。   The semiconductor chip 31 is mounted on one surface of the semiconductor device 1 face up (the circuit surface or the electrode pad 31a is on the front side). The thick film portion 21 a is continuously formed on the outer peripheral side of the semiconductor chip 31. In other words, the thick film portion 21 a is formed in an annular shape (frame shape) so as to surround the entire outer periphery of the semiconductor chip 31.

さらに、半導体装置１は、配線基板１１の一面上で厚膜部２１ａと異なる位置に配置され、厚膜部２１ａよりも薄い薄膜部２１ｂを備えている。薄膜部２１ｂは、厚膜部２１ａの内周側と半導体チップ３１の外周側との間に形成されている。詳細には、薄膜部２１ｂは、配線基板１１の一面上の中央領域（配線基板１１の一面と半導体チップ３１の裏面間）に形成され、さらに、厚膜部２１ａの内周面から段状に形成されている。   Further, the semiconductor device 1 includes a thin film portion 21b that is disposed on a surface of the wiring substrate 11 at a position different from the thick film portion 21a and is thinner than the thick film portion 21a. The thin film portion 21 b is formed between the inner peripheral side of the thick film portion 21 a and the outer peripheral side of the semiconductor chip 31. Specifically, the thin film portion 21b is formed in a central region on one surface of the wiring substrate 11 (between one surface of the wiring substrate 11 and the back surface of the semiconductor chip 31), and further stepped from the inner peripheral surface of the thick film portion 21a. Is formed.

厚膜部２１ａおよび薄膜部２１ｂは、第１の絶縁膜２１を構成している。配線基板１１の構成部品である絶縁基材１１ａと、厚膜部２１ａとは、異なる材料から形成されている。厚膜部２１ａは、配線基板１１の端面と半導体チップ３１の端面との間に配置されている。   The thick film portion 21 a and the thin film portion 21 b constitute the first insulating film 21. The insulating base material 11a, which is a component of the wiring board 11, and the thick film portion 21a are formed from different materials. The thick film portion 21 a is disposed between the end surface of the wiring substrate 11 and the end surface of the semiconductor chip 31.

半導体チップ３１は、第１の絶縁膜２１の中央領域に形成された第１の開口部４１内に収容されている。配線基板１１の一面上に配置された複数の接続パッド１１ｂが、第１の開口部４１を通じて露出可能である。半導体チップ３１の複数の電極パッド３１ａと、複数の接続パッド１１ｂとは、ボンディングワイヤ６１を介して電気的に接続されている。   The semiconductor chip 31 is accommodated in a first opening 41 formed in the central region of the first insulating film 21. A plurality of connection pads 11 b arranged on one surface of the wiring substrate 11 can be exposed through the first opening 41. The plurality of electrode pads 31 a of the semiconductor chip 31 and the plurality of connection pads 11 b are electrically connected via bonding wires 61.

配線基板１１の他面側（図１（Ｂ）中下側）には、下記の要素が設けられている：
配線基板１１の他面上に形成される第２の絶縁膜２２；
第２の絶縁膜２２に形成される複数の第２の開口部４２；
配線基板１１の他面上に設けられ、複数の第２の開口部４２を通じて露出可能な複数のランド１１ｃ；
複数のランド１１ｃ上に搭載される複数のはんだボール（外部電極）５１； The following elements are provided on the other side of the wiring board 11 (the lower side in FIG. 1B):
A second insulating film 22 formed on the other surface of the wiring substrate 11;
A plurality of second openings 42 formed in the second insulating film 22;
A plurality of lands 11 c provided on the other surface of the wiring substrate 11 and exposed through the plurality of second openings 42;
A plurality of solder balls (external electrodes) 51 mounted on the plurality of lands 11c;

複数のはんだボール５１ないし外部電極５１は、配線基板１１の一面側に配置された複数の接続パッド１１ｂ等と、配線基板１１層内の導電部を介して、電気的に接続している。   The plurality of solder balls 51 or the external electrodes 51 are electrically connected to a plurality of connection pads 11b and the like disposed on one surface side of the wiring board 11 through conductive portions in the wiring board 11 layer.

以下、半導体装置１の構成要素について詳細に説明する。   Hereinafter, the components of the semiconductor device 1 will be described in detail.

配線基板１１においては、ガラスエポキシ基板等の絶縁基材１１ａの両面に所定の配線パターンが形成されている。配線基板１１は、略矩形状であり、例えば、９０μｍ程度の厚さを有する。   In the wiring board 11, predetermined wiring patterns are formed on both surfaces of an insulating base material 11a such as a glass epoxy board. The wiring substrate 11 has a substantially rectangular shape, and has a thickness of about 90 μm, for example.

配線基板１１の一面には第１の絶縁膜２１が形成され、配線基板１１の他面には第２の絶縁膜２２が形成されている。第１および第２の絶縁膜２１，２２は、例えば、ソルダーレジスト層から形成される。配線基板１１両面上の配線パターンは、一部を除いて、第１および第２の絶縁膜２１，２２で覆われている。配線基板１１を主として構成する絶縁基材１１ａは、例えば、ガラス繊維製の布にエポキシ樹脂を含侵させて板状にしたものである。第１および第２の絶縁膜２１，２２は、例えば、エポキシ樹脂から形成される。よって、配線基板１１の構成材料と、第１および第２の絶縁膜２１，２２の構成材料は、相違している。   A first insulating film 21 is formed on one surface of the wiring substrate 11, and a second insulating film 22 is formed on the other surface of the wiring substrate 11. The first and second insulating films 21 and 22 are formed from, for example, a solder resist layer. The wiring patterns on both surfaces of the wiring substrate 11 are covered with the first and second insulating films 21 and 22 except for a part. The insulating base material 11a mainly constituting the wiring substrate 11 is formed by impregnating a glass fiber cloth with an epoxy resin to form a plate. The first and second insulating films 21 and 22 are made of, for example, an epoxy resin. Therefore, the constituent material of the wiring board 11 and the constituent materials of the first and second insulating films 21 and 22 are different.

第１の開口部４１内、特に、厚膜部２１ａと半導体チップ３１の間で、露出可能な上記配線パターン上には、複数の接続パッド１１ｂが形成されている。複数の接続パッド１１ｂは、半導体チップ３１の四つの側面ないし配線基板１１の四辺に沿って、配列されている。複数の電極パッド３１ａは、対応する複数の接続パッド１１ｂに、複数のボンディングワイヤ６１を介して、電気的に接続されている。ボンディングワイヤ６１は、例えば、Ａｕ、Ｃｕ等から形成される。複数のランド１１ｃは、半導体チップ３１配置領域の外側に、配線基板１１の四辺に沿って二列で配置されている。   A plurality of connection pads 11 b are formed in the first opening 41, particularly between the thick film portion 21 a and the semiconductor chip 31, on the wiring pattern that can be exposed. The plurality of connection pads 11 b are arranged along the four side surfaces of the semiconductor chip 31 or the four sides of the wiring substrate 11. The plurality of electrode pads 31 a are electrically connected to the corresponding plurality of connection pads 11 b through the plurality of bonding wires 61. The bonding wire 61 is made of, for example, Au or Cu. The plurality of lands 11 c are arranged in two rows along the four sides of the wiring substrate 11 outside the semiconductor chip 31 arrangement region.

厚膜部２１ａは、配線基板１１と反対側に位置する厚膜部２１ａの一面（表面）が、半導体チップ３１の一面（フェースアップ搭載の場合は回路面）と、略同じ高さとなるよう形成されている。   The thick film portion 21a is formed so that one surface (front surface) of the thick film portion 21a located on the side opposite to the wiring substrate 11 is substantially the same height as one surface (circuit surface in the case of face-up mounting) of the semiconductor chip 31. Has been.

配線基板１１の一面上、中央領域には、接着部材７１、例えば、DAF（Die Attached Film）を介して、半導体チップ３１がフェースアップ状態で搭載されている。厚膜部２１ａの厚みと、半導体チップ３１の厚みと接着部材７１の厚みとの和とが、同等にされている。半導体チップ３１は、略正方形の板状であり、表面側に所定の回路、例えばメモリ回路と、メモリ回路に内部接続される複数の電極パッド３１ａが形成されている。複数の電極パッド３１ａは、半導体チップ３１の一面上、四辺に沿って配置されている。   On one surface of the wiring substrate 11, the semiconductor chip 31 is mounted face-up on the central region via an adhesive member 71, for example, a DAF (Die Attached Film). The thickness of the thick film portion 21a is equal to the sum of the thickness of the semiconductor chip 31 and the thickness of the adhesive member 71. The semiconductor chip 31 has a substantially square plate shape, and a predetermined circuit, for example, a memory circuit, and a plurality of electrode pads 31a internally connected to the memory circuit are formed on the surface side. The plurality of electrode pads 31 a are arranged on one surface of the semiconductor chip 31 along the four sides.

配線基板１１の一面上には、封止材７２、例えば、熱硬化性のエポキシ樹脂等のような封止樹脂が硬化した封止層７２が形成されている。封止層７２は、半導体チップ３１、複数のボンディングワイヤＷおよび第１の絶縁膜２１を覆っている。上述したように、封止層７２は、半導体チップ３１上（配線基板１１の中央領域）と厚膜部２２上（配線基板１１の周辺領域）で同等の厚さを有している。封止層７２は、配線基板１１と平行に形成され、封止層７２の表面は平坦である。   On one surface of the wiring substrate 11, a sealing layer 72, for example, a sealing layer 72 in which a sealing resin such as a thermosetting epoxy resin is cured is formed. The sealing layer 72 covers the semiconductor chip 31, the plurality of bonding wires W, and the first insulating film 21. As described above, the sealing layer 72 has the same thickness on the semiconductor chip 31 (the central region of the wiring substrate 11) and on the thick film portion 22 (the peripheral region of the wiring substrate 11). The sealing layer 72 is formed in parallel with the wiring substrate 11, and the surface of the sealing layer 72 is flat.

半導体装置１の効果を説明する。   The effect of the semiconductor device 1 will be described.

（１）配線基板１１の一面上、周辺領域に配置された厚膜部２１ａの表面は、半導体チップ３１の表面と略同じ高さを有している。
（２）これによって、中央領域（半導体チップ３１）上と周辺領域上で、封止層７２の厚さを均一化することができる。
（３）すなわち、配線基板１１の一面上、中央領域（半導体チップ３１の搭載領域）と、周辺領域とにおいて、封止層７２の容積差が可及的に小さくなる。換言すると、厚膜部２１ａの存在によって、配線基板１１の周辺領域（半導体チップ３１の外周側）における封止材（封止層）７２の容積が低減される。
（４）これによって、配線基板１１全体で、封止材７２の硬化収縮時に発生する応力が均一化される（応力アンバランスの解消）。
（５）この結果、製品となる半導体装置１の反りが低減される。特に、配線基板１１の周辺領域又はコーナ部の反り又は跳ね上がりが低減される。
（６）半導体装置１の反りの低減によって、半導体装置１の二次実装性が向上される。
（７）半導体装置１の例えば下段に、別の半導体装置又は実装基板を接続する場合、信頼性の高い接続が構築できる。
（８）半導体装置１の反りの低減によって、半導体装置１の全高を低くすることができる。
（９）全高が低い半導体装置１は、小型および薄型の携帯機器等への組み込みが容易である。 (1) The surface of the thick film portion 21 a disposed on the one surface of the wiring substrate 11 in the peripheral region has substantially the same height as the surface of the semiconductor chip 31.
(2) Thereby, the thickness of the sealing layer 72 can be made uniform over the central region (semiconductor chip 31) and the peripheral region.
(3) That is, the volume difference of the sealing layer 72 becomes as small as possible on the one surface of the wiring board 11 in the central region (the mounting region of the semiconductor chip 31) and the peripheral region. In other words, the presence of the thick film portion 21a reduces the volume of the sealing material (sealing layer) 72 in the peripheral region of the wiring board 11 (the outer peripheral side of the semiconductor chip 31).
(4) Thereby, the stress generated when the sealing material 72 is cured and contracted is made uniform in the entire wiring board 11 (resolving the stress imbalance).
(5) As a result, warpage of the semiconductor device 1 as a product is reduced. In particular, warping or jumping of the peripheral area or corner portion of the wiring board 11 is reduced.
(6) The secondary mountability of the semiconductor device 1 is improved by reducing the warpage of the semiconductor device 1.
(7) When another semiconductor device or a mounting substrate is connected to the lower stage of the semiconductor device 1, for example, a highly reliable connection can be established.
(8) The overall height of the semiconductor device 1 can be reduced by reducing the warpage of the semiconductor device 1.
(9) The semiconductor device 1 having a low overall height can be easily incorporated into a small and thin portable device or the like.

次に、図２（Ａ）〜（Ｆ）を順番に参照しながら、図１（Ａ）および（Ｂ）に示した半導体装置１の製造方法の一例を説明する。なお、場合によっては、各工程は、順番を入れ替えて実行したり、同時に実行したりすることができる。   Next, an example of a method for manufacturing the semiconductor device 1 shown in FIGS. 1A and 1B will be described with reference to FIGS. 2A to 2F in order. In some cases, the steps can be executed by changing the order, or can be executed simultaneously.

図２（Ａ）に示すような配線基板１１を準備する。配線基板１１には、複数の製品領域ＰＡが配置されている。複数の製品領域ＰＡは、ダイシングエリアＤＡによって区画されている。複数の製品領域ＰＡは、ダイシングエリアＤＡに沿った切断後、複数の半導体装置１を構成する複数の配線基板１１となる。配線基板１１の両面には、複数の接続パッド１１ｂおよび複数のランド１１ｃを含む所定の配線パターンがそれぞれ形成されている。   A wiring board 11 as shown in FIG. 2A is prepared. A plurality of product areas PA are arranged on the wiring board 11. The plurality of product areas PA are partitioned by a dicing area DA. The plurality of product areas PA become the plurality of wiring boards 11 constituting the plurality of semiconductor devices 1 after cutting along the dicing area DA. On both surfaces of the wiring board 11, predetermined wiring patterns including a plurality of connection pads 11b and a plurality of lands 11c are formed.

配線基板１１の一面上にソルダーレジストを供給して第１の絶縁膜２１を形成し、同他面上にもソルダーレジストを供給して第２の絶縁膜２２を形成する。   A solder resist is supplied onto one surface of the wiring substrate 11 to form a first insulating film 21, and a solder resist is also supplied onto the other surface to form a second insulating film 22.

第１の絶縁膜２１を、フォトリソグラフィ法などを用いてパターン形成し、厚膜部２１ａ、薄膜部２１ｂおよび第１の開口部４１を形成する。第２の絶縁膜２２を、フォトリソグラフィ法などを用いてパターン形成し、複数の第２の開口部４２を形成する。厚膜部２１ａは配線基板１１の周辺領域に形成される。薄膜部２１ｂは、配線基板１１の中央領域、すなわち、半導体チップ３１の下となる領域と、厚膜部２１ａの内周面上とに形成される。特に、厚膜部２１ａは、搭載する半導体チップ３１と同等の高さを有するよう形成される。   The first insulating film 21 is patterned using a photolithography method or the like, and the thick film portion 21a, the thin film portion 21b, and the first opening 41 are formed. The second insulating film 22 is patterned using a photolithography method or the like to form a plurality of second openings 42. The thick film portion 21 a is formed in the peripheral region of the wiring board 11. The thin film portion 21b is formed in the central region of the wiring substrate 11, that is, the region below the semiconductor chip 31, and the inner peripheral surface of the thick film portion 21a. In particular, the thick film portion 21a is formed to have the same height as the semiconductor chip 31 to be mounted.

図２（Ｂ）を参照すると、ダイボンディング工程では、配線基板１１をダイボンディング装置ＤＴのステージにセットする。ダイボンディング装置ＤＴは、半導体チップ３１の図中上面を吸着保持する。半導体チップ３１の図中下面に接着部材（充填材）７１を供給する。なお、半導体チップ３１の実装後に接着部材７１を供給したり、配線基板１１の一面上に接着部材７１を供給したりしてもよい。このダイボンディング工程は、複数の製品領域ＰＡに対して同様に実行される。   Referring to FIG. 2B, in the die bonding process, the wiring board 11 is set on the stage of the die bonding apparatus DT. The die bonding apparatus DT sucks and holds the upper surface of the semiconductor chip 31 in the drawing. An adhesive member (filler) 71 is supplied to the lower surface of the semiconductor chip 31 in the drawing. The adhesive member 71 may be supplied after the semiconductor chip 31 is mounted, or the adhesive member 71 may be supplied on one surface of the wiring board 11. This die bonding process is performed similarly for a plurality of product areas PA.

接着部材７１を加熱して溶融させ、配線基板１１と半導体チップ３１間の隙間を充填する。接着部材７１を所定の温度でキュアして、接着部材７１を硬化させて、接着層（充填層）７１を形成する。   The adhesive member 71 is heated and melted to fill the gap between the wiring board 11 and the semiconductor chip 31. The adhesive member 71 is cured at a predetermined temperature, and the adhesive member 71 is cured to form an adhesive layer (filling layer) 71.

図２（Ｃ）を参照すると、ワイヤボンディング工程では、複数のボンディングワイヤ６１を用いて、熱圧着又は超音波熱圧着等により、複数の電極パッド３１ａと複数の接続パッド１１ｂとを電気的に接続する。   Referring to FIG. 2C, in the wire bonding step, the plurality of electrode pads 31a and the plurality of connection pads 11b are electrically connected by thermocompression bonding or ultrasonic thermocompression bonding using a plurality of bonding wires 61. To do.

図２（Ｄ）を参照すると、モールド工程では、モールド金型（上型Ｍ１，下型Ｍ２）を用いて、配線基板１１を上下から型締めする。上型Ｍ１にはキャビティが形成されている。このキャビティは、中央領域（半導体チップ３１）上と周辺領域上で、封止層７２の厚さが均一となるよう形成されている。上型Ｍ１が、複数の製品領域ＰＡを一括して覆うよう、配線基板１１がセットされる。上型Ｍ１にはゲート部が形成されている。このゲート部からキャビティ内に、加熱溶融された封止材７２を注入する。封止材７２には、例えばエポキシ樹脂等の熱硬化性樹脂が用いられる。配線基板１１ないし半導体装置１において、中央領域（半導体チップ３１上）に対する封止材７２の供給量と、周辺領域に対する封止材７２の供給量の差は、可及的に小さくされている。封止材７２の充填後、封止材７２を所定の温度でキュアして、封止層７２を形成する。封止層７２は、配線基板１１の他面上、複数の製品領域ＰＡを一括して覆っている。   Referring to FIG. 2D, in the molding process, the wiring substrate 11 is clamped from above and below using a mold (upper mold M1, lower mold M2). A cavity is formed in the upper mold M1. The cavity is formed so that the thickness of the sealing layer 72 is uniform over the central region (semiconductor chip 31) and the peripheral region. The wiring substrate 11 is set so that the upper mold M1 covers a plurality of product areas PA at a time. A gate portion is formed on the upper mold M1. The sealing material 72 heated and melted is injected into the cavity from the gate portion. For the sealing material 72, for example, a thermosetting resin such as an epoxy resin is used. In the wiring substrate 11 or the semiconductor device 1, the difference between the supply amount of the sealing material 72 to the central region (on the semiconductor chip 31) and the supply amount of the sealing material 72 to the peripheral region is made as small as possible. After filling with the sealing material 72, the sealing material 72 is cured at a predetermined temperature to form the sealing layer 72. The sealing layer 72 collectively covers the plurality of product areas PA on the other surface of the wiring substrate 11.

上述したように、半導体チップ３１の高さと、厚膜部２１ａの高さとは同等にされている。これによって、配線基板１１の中央領域（半導体チップ３１）上の封止層７２の厚さと、配線基板１１の周辺領域（厚膜部２１ａ）上の封止層７２の厚さとを、通常のモールド工程を経て、同等にすることが容易化されている。換言すると、厚膜部２１ａの存在によって、配線基板１１の周辺領域（半導体チップの外周側）における封止材（封止層）７２の容積が低減される。   As described above, the height of the semiconductor chip 31 is made equal to the height of the thick film portion 21a. As a result, the thickness of the sealing layer 72 on the central region (semiconductor chip 31) of the wiring substrate 11 and the thickness of the sealing layer 72 on the peripheral region (thick film portion 21a) of the wiring substrate 11 are set to a normal mold. It is easy to equalize through the process. In other words, the presence of the thick film portion 21a reduces the volume of the sealing material (sealing layer) 72 in the peripheral region of the wiring substrate 11 (the outer peripheral side of the semiconductor chip).

図２（Ｅ）を参照すると、配線基板１１の他面側において、ボールマウント装置ＢＴを用いて、複数の第２の開口部４２内を通じて露出している複数のランド１１ｃ上に、フラックスを介して、複数のはんだボール５１を搭載する。複数のはんだボール５１は、電気的導体製のボールであって、例えば、金属製のボールである。配線基板１１をリフローして、複数のはんだボール５１を溶融させ、複数のランド１１ｃと接続させる。   Referring to FIG. 2E, on the other surface side of the wiring board 11, a ball mount device BT is used to place a flux on the plurality of lands 11c exposed through the plurality of second openings 42 through the flux. Then, a plurality of solder balls 51 are mounted. The plurality of solder balls 51 are balls made of an electrical conductor, for example, metal balls. The wiring board 11 is reflowed to melt the plurality of solder balls 51 and connect to the plurality of lands 11c.

図２（Ｆ）を参照すると、基板ダイシング工程では、封止層７２上にダイシングテープＤＴａを接着し、ダイシングテープＤＴａによって配線基板１１を支持する。ダイシングブレードＤＢにより、ダイシングエリアＤＡに沿って、配線基板１１を縦横に切断して、製品領域ＰＡ毎に切断分離する。次に、ダイシングテープＤＴａからのピックアップにより、図１（Ａ）および（Ｂ）に示したような半導体装置１が複数個得られる。さらに、複数のはんだボール（外部電極）５１上に、下段パッケージを接続することによって、積層型半導体装置が得られる。   Referring to FIG. 2F, in the substrate dicing step, the dicing tape DTa is bonded onto the sealing layer 72, and the wiring substrate 11 is supported by the dicing tape DTa. The wiring board 11 is cut vertically and horizontally along the dicing area DA by the dicing blade DB, and cut and separated for each product area PA. Next, a plurality of semiconductor devices 1 as shown in FIGS. 1A and 1B are obtained by pickup from the dicing tape DTa. Furthermore, a stacked semiconductor device can be obtained by connecting a lower package onto a plurality of solder balls (external electrodes) 51.

実施形態１の製造方法によれば、半導体チップ３１の高さと、厚膜部２１ａの高さとを予め同等にすることにより、通常のモールド工程を用いて、配線基板１１の中央領域（半導体チップ３１）上の封止層７２の厚さと、配線基板１１の周辺領域（厚膜部２１ａ）上の封止層７２の厚さを同等に形成すること（封止層７２容積分布の均一化）が容易化されている。   According to the manufacturing method of the first embodiment, the height of the semiconductor chip 31 and the height of the thick film portion 21a are made equal to each other in advance, so that the central region (semiconductor chip 31) of the wiring substrate 11 is obtained using a normal molding process. ) The thickness of the upper sealing layer 72 and the thickness of the sealing layer 72 on the peripheral region (thick film portion 21a) of the wiring substrate 11 are formed to be equal (uniformization of the volume distribution of the sealing layer 72). It has been made easier.

［実施形態２］
実施形態２では、主として、実施形態１との相違点について説明し、共通点については、実施形態１の記載を適宜参照するものとする。 [Embodiment 2]
In the second embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for common points.

図３を参照すると、実施形態２の半導体装置２において、厚膜部２１ａは、配線基板１１上に、半導体装置３１を囲むよう環状に形成されている。厚膜部２１ａの内壁において、四隅（コーナ部）には、すなわち、半導体チップ３１の四隅と対向する四隅には、テーパ部２１ｃがそれぞれ形成されている。換言すると、厚膜部２１ａの四隅が斜めに面取りされている。複数のテーパ部２１ｃは、半導体装置３１に向かって徐々に低く形成されている。   Referring to FIG. 3, in the semiconductor device 2 of the second embodiment, the thick film portion 21 a is formed on the wiring substrate 11 in an annular shape so as to surround the semiconductor device 31. On the inner wall of the thick film portion 21a, taper portions 21c are formed at the four corners (corner portions), that is, at the four corners facing the four corners of the semiconductor chip 31, respectively. In other words, the four corners of the thick film portion 21a are chamfered obliquely. The plurality of tapered portions 21 c are formed so as to be gradually lower toward the semiconductor device 31.

実施形態２の半導体装置２によれば、実施形態１の半導体装置１と同様の効果が得られると共に、厚膜部２１ａの内壁のコーナ部をテーパ状に形成することにより、封止層７２を形成するモールド工程（図２（Ｄ）参照）において、コーナ部におけるボイドの発生を抑制することができる。   According to the semiconductor device 2 of the second embodiment, the same effect as that of the semiconductor device 1 of the first embodiment is obtained, and the sealing layer 72 is formed by forming the corner portion of the inner wall of the thick film portion 21a in a tapered shape. In the molding process to be formed (see FIG. 2D), generation of voids in the corner portion can be suppressed.

［実施形態３］
実施形態３では、主として、実施形態１との相違点について説明し、共通点については、実施形態１の記載を適宜参照するものとする。 [Embodiment 3]
In the third embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for common points.

図１（Ａ）を参照すると、実施形態１の半導体装置１では、厚膜部２１ａを半導体チップ３１の周りに、すなわち、配線基板１１の周辺部に、環状ないし枠状に配置した。   Referring to FIG. 1A, in the semiconductor device 1 according to the first embodiment, the thick film portion 21a is arranged in a ring shape or a frame shape around the semiconductor chip 31, that is, around the periphery of the wiring substrate 11.

図４を参照すると、実施形態３に係る半導体装置３では、厚膜部２１ａが、半導体チップ３１の四隅と対向する位置に分割して形成されている。すなわち、厚膜部２１ａは、配線基板１１の４隅にそれぞれ配置されている。   Referring to FIG. 4, in the semiconductor device 3 according to the third embodiment, the thick film portion 21 a is divided and formed at positions facing the four corners of the semiconductor chip 31. That is, the thick film portions 21 a are disposed at the four corners of the wiring board 11, respectively.

実施形態３の半導体装置３によれば、実施形態１の半導体装置１と同様の効果が得られると共に、封止材７２の硬化収縮時、大きな応力が加わりやすい配線基板１１の四隅にのみ、厚膜部２１ａを形成することによって、モールド工程（図２（Ｄ）参照）における封止材７２の流動性を向上できる。封止材７２の流動性向上によって、ボイドの発生も低減できる。ボイドの発生を低減することによって、リフロー時等の半導体装置１の温度上昇時、ボイド膨張に起因する封止層７２中のクラック発生を低減でき、半導体装置１の信頼性を向上できる。   According to the semiconductor device 3 of the third embodiment, the same effect as that of the semiconductor device 1 of the first embodiment can be obtained. By forming the film part 21a, the fluidity of the sealing material 72 in the molding process (see FIG. 2D) can be improved. By improving the fluidity of the sealing material 72, generation of voids can be reduced. By reducing the generation of voids, it is possible to reduce the occurrence of cracks in the sealing layer 72 due to void expansion when the temperature of the semiconductor device 1 rises during reflow or the like, and the reliability of the semiconductor device 1 can be improved.

［実施形態４］
実施形態４では、主として、実施形態１との相違点について説明し、共通点については、実施形態１の記載を適宜参照するものとする。 [Embodiment 4]
In the fourth embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be appropriately referred to for common points.

図１（Ａ）を参照すると、実施形態１の半導体装置１では、略正方形の板状な半導体チップ３１を用い、又半導体チップ３１の全周を囲むよう環状に厚膜部２１ａを形成している。   Referring to FIG. 1A, in the semiconductor device 1 of the first embodiment, a substantially square plate-shaped semiconductor chip 31 is used, and a thick film portion 21a is formed in an annular shape so as to surround the entire circumference of the semiconductor chip 31. Yes.

図５を参照すると、実施形態４の半導体装置４では、略長方形の板状な半導体チップ３１を用いている。複数の電極パッド３１ａは、半導体チップ３１一面の短辺３１ｘに沿って配置されている。厚膜部２１ａは、半導体チップ３１の一対の長辺３１ｙに沿って延在するよう、分割形成されている。したがって、第１の絶縁膜２１は、一対の長辺３１ｙに沿って厚く形成され、一対の短辺３１ｘに沿って、薄く形成されている。   Referring to FIG. 5, the semiconductor device 4 of the fourth embodiment uses a substantially rectangular plate-shaped semiconductor chip 31. The plurality of electrode pads 31 a are arranged along the short side 31 x of the entire surface of the semiconductor chip 31. The thick film part 21 a is divided and formed so as to extend along the pair of long sides 31 y of the semiconductor chip 31. Therefore, the first insulating film 21 is formed thick along the pair of long sides 31y and thinly formed along the pair of short sides 31x.

実施形態４の半導体装置４によれば、実施形態１の半導体装置１による効果に加えて、下記の効果を得ることができる。   According to the semiconductor device 4 of the fourth embodiment, in addition to the effects of the semiconductor device 1 of the first embodiment, the following effects can be obtained.

半導体チップ３１が長方形状の場合であって厚膜部２１ａを設けない場合、半導体チップ３１の全周を囲むよう封止材７２を供給すると、半導体チップ３１の長辺３１ｙと、配線基板１１の端部の間の封止材７２の容積が、半導体チップ３１の短辺３１ｘと配線基板１１の端部の間の封止材の容積よりも多くなる。これによって、半導体チップ３１の長辺３１ｙ側の封止材７２の硬化収縮による応力が、短辺側のそれよりも大きくなり、半導体装置４は反って鞍状になりやすい。   When the semiconductor chip 31 is rectangular and the thick film portion 21 a is not provided, when the sealing material 72 is supplied so as to surround the entire circumference of the semiconductor chip 31, the long side 31 y of the semiconductor chip 31 and the wiring substrate 11 The volume of the sealing material 72 between the end portions is larger than the volume of the sealing material between the short side 31 x of the semiconductor chip 31 and the end portion of the wiring substrate 11. As a result, the stress due to curing shrinkage of the sealing material 72 on the long side 31y side of the semiconductor chip 31 becomes larger than that on the short side, and the semiconductor device 4 tends to be warped.

実施形態４の半導体装置４によれば、硬化収縮に伴って大きな応力が加わる半導体チップの一対の長辺３１ｙと配線基板１１の端面との間に、第１の絶縁膜２１の厚膜部２１ａを配置し、一対の短辺３１ｘ側には厚膜部２１ａを配置していない。これによって、上記応力は可及的に均一に配線基板１１に印加され、反りの発生が抑制される。加えて、モールド工程（図２（Ｄ）参照）では、厚膜部２１ａ，２１ａの間に、封止材７２を流動させることによって、封止材７２の流動性が向上し、ボイドの発生が低減できる。   According to the semiconductor device 4 of the fourth embodiment, the thick film portion 21a of the first insulating film 21 is located between the pair of long sides 31y of the semiconductor chip to which a large stress is applied as the resin shrinks and the end surface of the wiring substrate 11. The thick film portion 21a is not disposed on the pair of short sides 31x side. Thereby, the stress is applied to the wiring board 11 as uniformly as possible, and the occurrence of warpage is suppressed. In addition, in the molding process (see FIG. 2D), by causing the sealing material 72 to flow between the thick film portions 21a and 21a, the fluidity of the sealing material 72 is improved, and voids are generated. Can be reduced.

［実施形態５］
実施形態５では、主として、実施形態１との相違点について説明し、共通点については、実施形態１の記載を適宜参照するものとする。 [Embodiment 5]
In the fifth embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for common points.

図１（Ｂ）を参照すると、実施形態１の半導体装置１では、第１の絶縁膜２１は、厚膜部２１ａと、薄膜部２１ｂと、を有している。薄膜部２１ｂは、少なくとも、半導体チップ３１の一面（配線基板１１側を向いている面、搭載面）と配線基板１１の一面の間に形成されている。厚膜部２１ａは、半導体チップ３１下の接着層７１乃至薄膜部２１ｂなどの厚さ分、半導体チップ３１よりも厚く形成されている。   Referring to FIG. 1B, in the semiconductor device 1 according to the first embodiment, the first insulating film 21 includes a thick film portion 21a and a thin film portion 21b. The thin film portion 21 b is formed at least between one surface of the semiconductor chip 31 (a surface facing the wiring substrate 11 side, a mounting surface) and one surface of the wiring substrate 11. The thick film portion 21 a is formed thicker than the semiconductor chip 31 by the thickness of the adhesive layer 71 to the thin film portion 21 b below the semiconductor chip 31.

図６を参照すると、実施形態５の半導体装置５では、少なくとも、厚膜部２１ａの内側の領域、特に、半導体チップ３１下に薄膜部が形成されていない。これによって、厚膜部２１ａを、薄膜部の厚さ分、薄く形成することができる（図１（Ｂ）中、半導体チップ３１下の薄膜部２１ｂの厚さ参照）。薄膜部がないことによって、封止層７２の形成前は配線基板１１の一面上の配線パターンが露出されるが、半導体チップ３１は、絶縁性の接着部材７１を介して配線基板１１の一面に実装されるため、配線ショートの問題はない。   Referring to FIG. 6, in the semiconductor device 5 of the fifth embodiment, at least a region inside the thick film portion 21 a, particularly, a thin film portion is not formed under the semiconductor chip 31. Thus, the thick film portion 21a can be formed as thin as the thin film portion (refer to the thickness of the thin film portion 21b below the semiconductor chip 31 in FIG. 1B). Due to the absence of the thin film portion, the wiring pattern on one surface of the wiring substrate 11 is exposed before the sealing layer 72 is formed, but the semiconductor chip 31 is formed on one surface of the wiring substrate 11 via the insulating adhesive member 71. Since it is mounted, there is no problem of wiring short circuit.

実施形態５の半導体装置５によれば、実施形態１の半導体装置１と同様の効果が得られると共に、薄膜部を有していないことによって、半導体チップ３１を配線基板１１に低く搭載できる。よって、厚膜部２１ａを低く形成することができる。かくして、半導体装置５を薄型化できる。   According to the semiconductor device 5 of the fifth embodiment, the same effect as that of the semiconductor device 1 of the first embodiment can be obtained, and the semiconductor chip 31 can be mounted on the wiring substrate 11 at a low level by not having the thin film portion. Therefore, the thick film portion 21a can be formed low. Thus, the semiconductor device 5 can be thinned.

［実施形態６］
実施形態６では、主として、実施形態１との相違点について説明し、共通点については、実施形態１の記載を適宜参照するものとする。 [Embodiment 6]
In the sixth embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be appropriately referred to for the common points.

図１（Ａ）を参照すると、実施形態１の半導体装置１では、一つの半導体チップ３１を用いている。   Referring to FIG. 1A, the semiconductor device 1 of the first embodiment uses one semiconductor chip 31.

図７を参照すると、実施形態６の半導体装置６では、第１および第２の半導体チップ３１，３２を積層して用いている。第１および第２の半導体チップ３１，３２は、同一構成の半導体チップであり（例えば、長方形状）、短辺に沿って複数の電極パッド３１ａ，３２ａが配置されている。第１および第２の半導体チップ３１，３２は、他方の複数の電極パッド３１ａ，３２ａが露出するよう、クロス積載されている。すなわち、第１および第２の半導体チップ３１，３２は、第１の半導体チップ３１の長辺と、第２の半導体チップ３２の短辺が平行となるよう（第１の半導体チップ３１の短辺と、第２の半導体チップ３２の長辺が平行となるよう）、積層されている。第１および第２の半導体チップ３１，３２の周囲に配置される厚膜部２１ａの表面は、上段に積層される第２の半導体チップ３２の表面と略同じ位置になるように形成されている。   Referring to FIG. 7, in the semiconductor device 6 of the sixth embodiment, the first and second semiconductor chips 31 and 32 are stacked and used. The first and second semiconductor chips 31 and 32 are semiconductor chips having the same configuration (for example, rectangular shape), and a plurality of electrode pads 31a and 32a are arranged along the short side. The first and second semiconductor chips 31 and 32 are cross-stacked so that the other plurality of electrode pads 31a and 32a are exposed. That is, in the first and second semiconductor chips 31 and 32, the long side of the first semiconductor chip 31 and the short side of the second semiconductor chip 32 are parallel (the short side of the first semiconductor chip 31). The long sides of the second semiconductor chip 32 are parallel to each other). The surface of the thick film portion 21a disposed around the first and second semiconductor chips 31, 32 is formed so as to be substantially at the same position as the surface of the second semiconductor chip 32 stacked on the upper stage. .

実施形態６の半導体装置６においても、実施形態１の半導体装置１と同様な効果が得られると共に、配線基板１１上に複数の半導体チップを積層したことによって、半導体装置６の大容量化或いは高機能化を図ることができる。   Also in the semiconductor device 6 of the sixth embodiment, the same effect as that of the semiconductor device 1 of the first embodiment can be obtained, and a plurality of semiconductor chips are stacked on the wiring substrate 11, thereby increasing the capacity or the semiconductor device 6. Functionalization can be achieved.

［実施形態７］
実施形態７では、主として、実施形態１との相違点について説明し、共通点については、実施形態１の記載を適宜参照するものとする。 [Embodiment 7]
In the seventh embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for common points.

図１（Ａ）を参照すると、実施形態１の半導体装置１では、配線基板１１に、半導体チップ３１をフェースアップで搭載し、ワイヤボンディング接続（図２（Ｃ）参照）している。   Referring to FIG. 1A, in the semiconductor device 1 of the first embodiment, a semiconductor chip 31 is mounted face-up on a wiring board 11 and wire-bonding connection is made (see FIG. 2C).

図８を参照すると、実施形態７の半導体装置７では、配線基板１１に、半導体チップ３１をフェースダウンで搭載し、複数の電極パッド３１ａを複数のバンプ電極３１ｂを介して複数の接続パッド１１ｂにフリップチップ接続している。フリップチップ接続を採用することによって、半導体チップ３１上と厚膜部２１ａ上とに形成する封止層７２をさらに薄く形成することができ、もって半導体装置７の薄型化が達成できる。すなわち、フェースアップ搭載（ワイヤボンディング接続）の場合も、フェースダウン搭載（フリップチップ接続）の場合も、実施形態１で説明した効果が達成されると共に、後者の場合には、半導体装置７をさらに薄型化することができる。   Referring to FIG. 8, in the semiconductor device 7 of the seventh embodiment, the semiconductor chip 31 is mounted face-down on the wiring board 11, and the plurality of electrode pads 31a are connected to the plurality of connection pads 11b via the plurality of bump electrodes 31b. Flip chip connection. By adopting the flip chip connection, the sealing layer 72 formed on the semiconductor chip 31 and the thick film portion 21a can be formed even thinner, so that the semiconductor device 7 can be made thinner. That is, in the case of face-up mounting (wire bonding connection) and face-down mounting (flip chip connection), the effect described in the first embodiment is achieved. In the latter case, the semiconductor device 7 is further provided. Thinning can be achieved.

以上、本発明者によってなされた発明を実施形態等に基づき説明したが、本発明は上記実施形態等に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。例えば、基板として、ガラスエポキシ基板等のリジットな配線基板、ポリイミド基板等を用いたフレキシブルな配線基板、両者の中間的性質を有する配線基板などを適宜選択して用いることができる。半導体チップとしては、メモリチップ、ロジックチップ、およびその他のチップを適宜選択して採用することができる。搭載する複数の半導体チップは、構成が同じものでもよく、異なるものでもよい。例えば、DRAMおよびFlashメモリチップ等を搭載することができる。   As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment etc., it cannot be overemphasized that this invention is not limited to the said embodiment etc., and can be variously changed in the range which does not deviate from the summary. . For example, a rigid wiring board such as a glass epoxy board, a flexible wiring board using a polyimide board or the like, or a wiring board having an intermediate property between the two can be appropriately selected and used as the board. As the semiconductor chip, a memory chip, a logic chip, and other chips can be appropriately selected and employed. The plurality of semiconductor chips to be mounted may have the same configuration or different configurations. For example, DRAM and Flash memory chips can be mounted.

（付記）
［付記１、第３の視点］
絶縁基板と、
前記絶縁基板の一面上に搭載した半導体チップと、
前記半導体チップよりも厚さが厚く、前記絶縁基板のエッジと前記半導体チップの間に配置されるよう前記絶縁基板上に形成された厚膜部を有する第１の絶縁膜と、
前記第１の絶縁膜の厚膜部と前記半導体チップを覆うように、前記絶縁基板上に形成した封止材（封止樹脂等）と、
を備える、半導体装置。
好ましくは、前記厚膜部は、前記半導体チップの一面（前記配線基板側を向いている面）と前記配線基板の一面の間に形成される、接着層又は絶縁膜などの厚さ分、前記半導体チップよりも厚く形成される。 (Appendix)
[Appendix 1, Third Viewpoint]
An insulating substrate;
A semiconductor chip mounted on one surface of the insulating substrate;
A first insulating film having a thickness greater than that of the semiconductor chip and having a thick film portion formed on the insulating substrate so as to be disposed between an edge of the insulating substrate and the semiconductor chip;
A sealing material (such as a sealing resin) formed on the insulating substrate so as to cover the thick film portion of the first insulating film and the semiconductor chip;
A semiconductor device comprising:
Preferably, the thick film portion is formed between the one surface of the semiconductor chip (the surface facing the wiring substrate side) and the one surface of the wiring substrate by a thickness of an adhesive layer or an insulating film, It is formed thicker than the semiconductor chip.

［付記２、第４の視点］
配線基板（絶縁基板、或いは、絶縁基材に配線パターンが形成された基板）と、
前記配線基板の一面上に搭載される半導体チップと、
前記絶縁基板の一面上、前記絶縁基板の端部と前記半導体チップの間に配置され、前記半導体チップよりも厚さが厚い厚膜部を少なくとも有する第１の絶縁膜と、
前記半導体チップおよび前記第１の絶縁膜（前記厚膜部）を少なくとも覆うよう、前記絶縁基板の一面上に形成される封止層と、
を備える、半導体装置。
好ましくは、前記厚膜部は、前記半導体チップの一面（前記配線基板側を向いている面）と前記配線基板の一面の間に形成される、接着層又は絶縁膜などの厚さ分、前記半導体チップよりも厚く形成される。 [Appendix 2, Fourth Viewpoint]
A wiring substrate (an insulating substrate or a substrate having a wiring pattern formed on an insulating substrate);
A semiconductor chip mounted on one surface of the wiring board;
A first insulating film disposed on one surface of the insulating substrate between the end of the insulating substrate and the semiconductor chip and having at least a thick film portion thicker than the semiconductor chip;
A sealing layer formed on one surface of the insulating substrate so as to cover at least the semiconductor chip and the first insulating film (the thick film portion);
A semiconductor device comprising:
Preferably, the thick film portion is formed between the one surface of the semiconductor chip (the surface facing the wiring substrate side) and the one surface of the wiring substrate by a thickness of an adhesive layer or an insulating film, It is formed thicker than the semiconductor chip.

第１〜第４の各視点において好ましい構成を以下に例示する。   Preferred configurations in the first to fourth viewpoints are exemplified below.

［付記３］
前記配線基板の一面上に、前記半導体チップおよび前記厚膜部を覆うよう形成され、前記半導体チップ上と前記厚膜部上で同等の厚さを有する封止層。
［付記４］
前記配線基板の一面上で前記厚膜部と異なる位置に配置され、前記厚膜部よりも薄い薄膜部。前記厚膜部および前記薄膜部は、第１の絶縁膜を構成する。
［付記５］
前記配線基板の構成部材である絶縁基材と、前記厚膜部（第１の絶縁膜）とは、異なる材料から形成される。
［付記６］
前記厚膜部（第１の絶縁膜）は、前記配線基板の端面と前記半導体チップの端面（エッジ）との間に配置される。
［付記７］
前記厚膜部（第１の絶縁膜）は、前記半導体チップの外周側に、分割形成され又は連続して形成される。
［付記８］
前記厚膜部（第１の絶縁膜）は、前記半導体チップの外周全周を囲むよう環状に形成され、前記薄膜部は、前記厚膜部の内周側と前記半導体チップの外周側との間に形成される。
［付記９］
前記厚膜部（第１の絶縁膜）の内壁において、前記半導体チップの複数の隅と対向する位置に複数のテーパ部が形成される。
［付記１０］
前記厚膜部は、前記半導体チップの複数の隅と対向する位置ないし前記配線基板の複数の隅に分割形成される。
［付記１１］
前記厚膜部は、前記半導体チップの一対の長辺に沿って延在するよう、分割形成される。
［付記１２］
分割形成される一対の前記厚膜部の間に、前記薄膜部が形成される。
［付記１３］
前記配線基板の一面上に、前記半導体チップが直接的に搭載される。
［付記１４］
前記配線基板の一面上に、複数の前記半導体チップが積層され、前記厚膜部（第１の絶縁膜の所定部分）は、前記複数の半導体チップのうち上段の前記半導体チップの高さと同等の高さを有するよう形成される。
［付記１５］
前記半導体チップは、前記配線基板にフェースアップで実装されると共にワイヤボンディング接続され、前記半導体チップと前記厚膜部の間の空間が、前記ワイヤボンディング接続に利用される。
［付記１６］
前記半導体チップは、前記配線基板にフェースダウンで実装されると共にフリップチップ接続される。
［付記１７］
前記配線基板の一面と前記半導体チップとの間に形成される接着層を備え、前記厚膜部の厚みと、前記半導体チップの厚みと前記接着層の厚みとの和とが、同等である。
［付記１８］
前記厚膜部ないし前記第１の絶縁膜の形成時、前記配線基板の一面上、少なくとも前記半導体チップの下となる部分に、薄膜部が形成される。 [Appendix 3]
A sealing layer formed on one surface of the wiring substrate so as to cover the semiconductor chip and the thick film portion and having an equivalent thickness on the semiconductor chip and the thick film portion.
[Appendix 4]
A thin film portion disposed on a surface of the wiring board at a position different from the thick film portion and thinner than the thick film portion. The thick film portion and the thin film portion constitute a first insulating film.
[Appendix 5]
The insulating base material, which is a constituent member of the wiring board, and the thick film portion (first insulating film) are formed from different materials.
[Appendix 6]
The thick film portion (first insulating film) is disposed between an end face of the wiring board and an end face (edge) of the semiconductor chip.
[Appendix 7]
The thick film portion (first insulating film) is formed separately or continuously on the outer peripheral side of the semiconductor chip.
[Appendix 8]
The thick film portion (first insulating film) is formed in an annular shape so as to surround the entire outer periphery of the semiconductor chip, and the thin film portion is formed between an inner peripheral side of the thick film portion and an outer peripheral side of the semiconductor chip. Formed between.
[Appendix 9]
On the inner wall of the thick film portion (first insulating film), a plurality of taper portions are formed at positions facing the plurality of corners of the semiconductor chip.
[Appendix 10]
The thick film portion is divided and formed at positions facing a plurality of corners of the semiconductor chip or at a plurality of corners of the wiring board.
[Appendix 11]
The thick film portion is divided and formed so as to extend along a pair of long sides of the semiconductor chip.
[Appendix 12]
The thin film portion is formed between a pair of the thick film portions formed in a divided manner.
[Appendix 13]
The semiconductor chip is directly mounted on one surface of the wiring board.
[Appendix 14]
A plurality of the semiconductor chips are stacked on one surface of the wiring board, and the thick film portion (predetermined portion of the first insulating film) is equivalent to the height of the upper semiconductor chip among the plurality of semiconductor chips. It is formed to have a height.
[Appendix 15]
The semiconductor chip is mounted face-up on the wiring board and connected by wire bonding, and the space between the semiconductor chip and the thick film portion is used for the wire bonding connection.
[Appendix 16]
The semiconductor chip is mounted face-down on the wiring board and flip-chip connected.
[Appendix 17]
An adhesive layer formed between one surface of the wiring substrate and the semiconductor chip is provided, and the thickness of the thick film portion is equal to the sum of the thickness of the semiconductor chip and the thickness of the adhesive layer.
[Appendix 18]
At the time of forming the thick film part or the first insulating film, a thin film part is formed on one surface of the wiring board at least under the semiconductor chip.

なお、本発明の全開示（請求の範囲及び図面を含む）の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素（各請求項の各要素、各実施形態ないし実施例の各要素、各図面の各要素等を含む）の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲及び図面を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。また、本願に記載の数値及び数値範囲については、明記がなくともその任意の中間値、下位数値、及び、小範囲が記載されているものとみなされる。   It should be noted that the embodiments and examples may be changed and adjusted within the scope of the entire disclosure (including claims and drawings) of the present invention and based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are included within the scope of the claims of the present invention. Is possible. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. Further, regarding numerical values and numerical ranges described in the present application, it is considered that any intermediate value, lower numerical value, and small range are described even if not specified.

１，２，３，４，５，６，７ 半導体装置
１１ 配線基板
１１ａ 絶縁基材
１１ｂ 接続パッド
１１ｃ ランド
２１ 第１の絶縁膜
２１ａ 厚膜部
２１ｂ 薄膜部
２１ｃ テーパ部
２２ 第２の絶縁膜
３１ 半導体チップ、第１の半導体チップ
３１ａ 電極パッド
３１ｂ バンプ電極
３１ｘ 短辺
３１ｙ 長辺
３２ 第２の半導体チップ
３２ａ 電極パッド
４１ 第１の開口部
４２ 第２の開口部
５１ はんだボール（外部電極）
６１ ボンディングワイヤ
７１ 接着部材（充填材、樹脂充填材）、接着層（充填層）
７２ 封止材（封止樹脂）、封止層
ＢＴ ボールマウント装置
ＤＴ ダイボンディング装置
ＤＡ ダイシングエリア
ＤＢ ダイシングブレード
ＤＴａ ダイシングテープ
ＤＬ ダイボンディングライン
ＰＡ 製品領域 1, 2, 3, 4, 5, 6, 7 Semiconductor device 11 Wiring substrate 11a Insulating base material 11b Connection pad 11c Land 21 First insulating film 21a Thick film portion 21b Thin film portion 21c Tapered portion 22 Second insulating film 31 Semiconductor chip, first semiconductor chip 31a Electrode pad 31b Bump electrode 31x Short side 31y Long side 32 Second semiconductor chip 32a Electrode pad 41 First opening 42 Second opening 51 Solder ball (external electrode)
61 Bonding wire 71 Adhesive member (filler, resin filler), adhesive layer (filler layer)
72 Sealing material (sealing resin), sealing layer BT Ball mount device DT Die bonding device DA Dicing area DB Dicing blade DTa Dicing tape DL Die bonding line PA Product area

Claims (18)

配線基板と、
前記配線基板の一面上に搭載される半導体チップと、
前記配線基板の一面上に、前記半導体チップの高さと同等の高さを有するよう形成される厚膜部と、
前記配線基板の一面上に、前記半導体チップおよび前記厚膜部を覆うよう形成され、前記半導体チップ上と前記厚膜部上で同等の厚さを有する封止層と、
を備える、半導体装置。 A wiring board;
A semiconductor chip mounted on one surface of the wiring board;
A thick film portion formed on one surface of the wiring board to have a height equivalent to the height of the semiconductor chip;
A sealing layer formed on one surface of the wiring substrate so as to cover the semiconductor chip and the thick film portion, and having an equivalent thickness on the semiconductor chip and the thick film portion;
A semiconductor device comprising: 前記配線基板の一面上で前記厚膜部と異なる位置に配置され、前記厚膜部よりも薄い薄膜部を備え、
前記厚膜部および前記薄膜部は、第１の絶縁膜を構成する、
請求項１記載の半導体装置。 Arranged on the one surface of the wiring board at a position different from the thick film part, comprising a thin film part thinner than the thick film part,
The thick film portion and the thin film portion constitute a first insulating film,
The semiconductor device according to claim 1. 前記配線基板の構成部材である絶縁基材と、前記厚膜部とは、異なる材料から形成される請求項１又は２記載の半導体装置。   The semiconductor device according to claim 1, wherein the insulating base material that is a constituent member of the wiring board and the thick film portion are formed of different materials. 前記厚膜部は、前記配線基板の端面と前記半導体チップの端面との間に配置される請求項１〜３のいずれか一記載の半導体装置。   The semiconductor device according to claim 1, wherein the thick film portion is disposed between an end surface of the wiring board and an end surface of the semiconductor chip. 前記厚膜部は、前記半導体チップの外周側に、分割形成され又は連続して形成される請求項１〜４のいずれか一記載の半導体装置。   5. The semiconductor device according to claim 1, wherein the thick film portion is divided or continuously formed on an outer peripheral side of the semiconductor chip. 前記厚膜部は、前記半導体チップの外周全周を囲むよう環状に形成され、
前記薄膜部は、前記厚膜部の内周側と前記半導体チップの外周側との間に形成される請求項１〜５のいずれか一記載の半導体装置。 The thick film portion is formed in an annular shape so as to surround the entire outer periphery of the semiconductor chip,
The semiconductor device according to claim 1, wherein the thin film portion is formed between an inner peripheral side of the thick film portion and an outer peripheral side of the semiconductor chip. 前記厚膜部の内壁において、前記半導体チップの複数の隅と対向する位置に複数のテーパ部が形成される請求項６記載の半導体装置。   The semiconductor device according to claim 6, wherein a plurality of taper portions are formed at positions facing the plurality of corners of the semiconductor chip on the inner wall of the thick film portion. 前記厚膜部は、前記半導体チップの複数の隅と対向する位置ないし前記配線基板の複数の隅に分割形成される請求項５記載の半導体装置。   The semiconductor device according to claim 5, wherein the thick film portion is divided and formed at positions facing a plurality of corners of the semiconductor chip or at a plurality of corners of the wiring board. 前記厚膜部は、前記半導体チップの一対の長辺に沿って延在するよう、分割形成される請求項５記載の半導体装置。   The semiconductor device according to claim 5, wherein the thick film portion is divided and formed so as to extend along a pair of long sides of the semiconductor chip. 分割形成される一対の前記厚膜部の間に、前記薄膜部が形成される、請求項９記載の半導体装置。   The semiconductor device according to claim 9, wherein the thin film portion is formed between a pair of the thick film portions formed in a divided manner. 前記配線基板の一面上に、前記半導体チップが直接的に搭載される、請求項１〜１０のいずれか一記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip is directly mounted on one surface of the wiring board. 前記配線基板の一面上に、複数の前記半導体チップが積層され、
前記厚膜部は、前記複数の半導体チップのうち上段の前記半導体チップの高さと同等の高さを有するよう形成される請求項１〜１１のいずれか一記載の半導体装置。 A plurality of the semiconductor chips are stacked on one surface of the wiring board,
The semiconductor device according to claim 1, wherein the thick film portion is formed to have a height equivalent to a height of the upper semiconductor chip among the plurality of semiconductor chips. 前記半導体チップは、前記配線基板にフェースアップで実装されると共にワイヤボンディング接続され、
前記半導体チップと前記厚膜部の間の空間が、前記ワイヤボンディング接続に利用される、
請求項１〜１２のいずれか一記載の半導体装置。 The semiconductor chip is mounted face up on the wiring board and connected by wire bonding,
A space between the semiconductor chip and the thick film part is used for the wire bonding connection.
The semiconductor device as described in any one of Claims 1-12. 前記半導体チップは、前記配線基板にフェースダウンで実装されると共にフリップチップ接続される、
請求項１〜１２のいずれか一記載の半導体装置。 The semiconductor chip is mounted face down on the wiring board and flip chip connected.
The semiconductor device as described in any one of Claims 1-12. 前記配線基板の一面と前記半導体チップとの間に形成される充填層を備え、
前記厚膜部の厚みと、前記半導体チップの厚みと前記充填層の厚みとの和とが、同等である請求項１４記載の半導体装置。 A filling layer formed between one surface of the wiring board and the semiconductor chip;
The semiconductor device according to claim 14, wherein a thickness of the thick film portion is equal to a sum of a thickness of the semiconductor chip and a thickness of the filling layer. 配線基板の一面上の周辺領域に、厚膜部を、搭載する半導体チップと同等の高さを有するよう形成する工程と、
前記配線基板の一面上の中央領域に、前記半導体チップを搭載する工程と、
前記配線基板の一面上に、前記半導体チップおよび前記厚膜部を覆い、前記半導体チップ上と前記厚膜部上で同等の厚さを有する封止層を形成する工程と、
を備える、半導体装置の製造方法。 Forming a thick film portion in a peripheral region on one surface of the wiring board so as to have a height equivalent to a semiconductor chip to be mounted;
Mounting the semiconductor chip in a central region on one surface of the wiring board;
Forming a sealing layer on one surface of the wiring board, covering the semiconductor chip and the thick film portion, and having an equivalent thickness on the semiconductor chip and the thick film portion;
A method for manufacturing a semiconductor device. 前記厚膜部の形成時、前記配線基板の一面上、少なくとも前記半導体チップの下となる部分に、薄膜部を形成する、
請求項１６記載の半導体装置の製造方法。 When forming the thick film portion, a thin film portion is formed on one surface of the wiring substrate, at least under the semiconductor chip.
The method for manufacturing a semiconductor device according to claim 16. 前記半導体チップを、前記配線基板の一面上に直接的に搭載する、
請求項１６記載の半導体装置の製造方法。 The semiconductor chip is directly mounted on one surface of the wiring board.
The method for manufacturing a semiconductor device according to claim 16.
JP2014089850A 2014-04-24 2014-04-24 Semiconductor device Pending JP2015211059A (en)

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