JP2015216219A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the time and labor required for manufacturing and increasing an integration degree, and a method for manufacturing the same.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming a first insulating layer on one side of a first substrate; forming at least one first opening and a plurality of second openings in the first insulating layer; mounting a first semiconductor chip on the one surface of the first substrate and in the first opening; supplying a plurality of first solder balls into the plurality of second openings; forming a plurality of first conductor parts in the plurality of second openings by melting the plurality of first solder balls; and forming a plurality of first external electrodes on the first insulating layer by mounting a plurality of second solder balls connected to the plurality of first conductor parts.

Description

  The present invention relates to a semiconductor device.

  In order to increase the density and functionality of semiconductor devices, there is a PoP (Package on Package) type stacked semiconductor device in which a plurality of packages are stacked and mounted. For example, in Patent Document 1 (JP 2013-125765 A), an upper package in which two memory chips are stacked and mounted on a wiring board is stacked on a lower package in which a logic chip is flip-chip mounted on a wiring board. A PoP type stacked semiconductor device is disclosed.

  When the wiring board of the upper package and the memory chip are connected by wire as in Patent Document 1, the electrical characteristics of the memory chip of the upper package becomes severe and the demand for high speed cannot be satisfied. A structure in which memory chips are flip-chip mounted on both sides of a substrate has been studied. For example, Patent Document 2 (Japanese Patent Laid-Open No. 2006-210566) discloses a configuration in which a semiconductor chip is flip-chip mounted on both surfaces of a wiring board.

  In Patent Document 3 (Japanese Patent Laid-Open No. 2006-19433), a semiconductor element is flip-chip mounted on a wiring body on which a conductor post is formed, and the wiring body is covered with an insulating resin so as to cover the semiconductor element and the conductor post. There is a disclosure in which an insulating resin is ground to expose a back surface of a semiconductor chip and a conductor post from the insulating resin, and a solder bump is formed on the exposed conductor post.

  Patent Document 4 (Japanese Patent Application Laid-Open No. 2010-103348) discloses that a wiring board on which a conductor layer is formed is covered with a sealing resin so that the conductor layer is exposed, and solder balls are mounted on the exposed conductor layer. A conductor layer is formed by mounting a solder ball on the substrate, a sealing resin is formed on the wiring substrate so as to cover the conductor layer (solder ball), and the conductor layer is exposed by grinding the sealing resin. There is a disclosure of mounting a solder ball on an exposed conductor layer.

JP 2013-125765 A JP 2006-210566 A JP 2006-19433 A JP 2010-103348 A

  The following analysis is given by the inventor.

  However, when the upper package is configured as in Patent Document 2, a semiconductor chip is mounted on the back surface side of the wiring board, so that there is a problem that sufficient standoff cannot be ensured. If the standoff of the upper package cannot be secured, it is difficult to electrically connect the upper package and the lower package.

  In other words, in the semiconductor device of Patent Document 2, the mounting surface of the upper semiconductor chip surface-mounted on the substrate and the mounting surface of the plurality of solder balls arranged around it are the same, so the upper semiconductor chip The difference in height between the surface and the apexes of the plurality of solder balls is reduced. For this reason, the space between the lower substrate connected to the plurality of solder balls and the upper semiconductor chip is reduced. Therefore, it is difficult to dispose the lower semiconductor chip mounted on the lower substrate so as to face the upper semiconductor chip.

  According to the method for manufacturing a semiconductor device of Patent Documents 3 and 4, a step of forming a conductor portion on a substrate in advance, a step of covering the conductor portion on the substrate with an underfill resin, and a sealing layer (underfill resin layer) And a step of grinding the sealing layer to expose the conductor portion buried therein. Such a method requires time and effort to expose the conductor portion.

  Thus, there is a need for a semiconductor device and a method for manufacturing the semiconductor device that can reduce the labor required for manufacturing and increase the degree of integration.

  In a first aspect, a method for manufacturing a semiconductor device includes a step of forming a first insulating layer on one side of a first substrate, and at least one first opening in the first insulating layer. A plurality of second openings, a step of mounting a first semiconductor chip on one surface of the first substrate in the first opening, and the plurality of second openings. Supplying a plurality of first solder balls in the openings, and melting the plurality of first solder balls to form a plurality of first conductor parts in the plurality of second openings. And mounting a plurality of second solder balls connected to the plurality of first conductor portions on the first insulating layer to form a plurality of first external electrodes. Yes.

  In a second aspect, a method for manufacturing a semiconductor device includes a step of forming an insulating layer on one side of a substrate, a step of forming a plurality of openings in the insulating layer, and a plurality of openings in the plurality of openings. Supplying the first solder balls, melting the plurality of solder balls to form the conductor portions in the plurality of openings, and connecting the plurality of conductor portions on the insulating layer Mounting a plurality of second solder balls.

In a third aspect, the semiconductor device is provided on a first substrate, a first insulating layer formed on one side of the first substrate, formed of a solder resist, and the first insulating layer. At least one first opening, and a plurality of second openings provided in the first insulating layer;
A first semiconductor chip mounted in the first opening, a plurality of first conductors provided in the plurality of second openings, and provided on the first insulating layer; And a plurality of external electrodes connected to the plurality of first conductor portions.

  According to the present disclosure, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce manufacturing labor and increase the degree of integration.

It is a figure which shows typically the structure of the semiconductor device (upper package) of Embodiment 1 seen from the other surface side. It is the figure which looked at the semiconductor device shown in FIG. 1 from the one surface side. It is AA step sectional drawing of FIG. FIG. 2 is a cross-sectional view schematically showing a stacked semiconductor device in which a lower package is stacked on the semiconductor device shown in FIG. 1. (A)-(D) are process drawings for demonstrating the manufacturing method of the semiconductor device of Embodiment 1. FIG. (E)-(F) are process drawings following FIG.5 (D). (A)-(D) are process drawings explaining the preferable process of FIG.6 (E), and have shown the process of forming a conductor part in an opening part with a solder ball especially. It is a figure which shows typically the cross-section of the semiconductor device of Embodiment 2. FIG. FIG. 2 is a diagram schematically illustrating a stacked semiconductor device in which a plurality of other-stage packages are stacked on the semiconductor device illustrated in FIG. 1. (A)-(D) are process drawings for demonstrating the manufacturing method of the semiconductor device of Embodiment 2. FIG. (E)-(G) are process drawings following FIG.10 (D). FIG. 6 is a cross-sectional view schematically showing a stacked semiconductor device according to a third embodiment. FIG. 6 is a cross-sectional view schematically showing a semiconductor device of Embodiment 4. (A) And (B) is process drawing for demonstrating the manufacturing method of the semiconductor device of Embodiment 4. FIG.

  Hereinafter, embodiments and the like will be described with reference to the drawings. Note that, in the present disclosure, where reference numerals are attached to the drawings, these are only for the purpose of assisting understanding, and are not intended to be limited to the illustrated embodiments.

[Embodiment 1]
The semiconductor device according to the first embodiment is an upper package including a substrate on which both sides of a semiconductor chip are mounted. A lower package can be stacked on the upper package. As the semiconductor chip, various chips such as a memory chip and a logic chip can be appropriately employed depending on the purpose.

1 to 3, on one side of the first substrate 11 provided in the semiconductor device 1 (upper package 1a) of the first embodiment (the back side in FIG. 1, the front side in FIG. 2, the lower side in FIG. 3). The following elements are provided:
First substrate 11;
A first insulating layer 21 provided on one side of the first substrate 11 and formed of a solder resist;
At least one first opening 41 provided in the first insulating layer 21;
A plurality of second openings 42 provided in the first insulating layer 21;
A first semiconductor chip 31 mounted in the first opening 41, in particular, mounted on the one surface of the first substrate 11 and in the first opening 41;
A plurality of first conductor portions 61 provided in the plurality of second openings 42;
A plurality of first external electrodes 52 formed from a plurality of second solder balls 52 provided on the first insulating layer 21 and connected to the plurality of first conductor portions 61.

  In particular, referring to FIGS. 7A to 7D, preferably, the plurality of first conductor portions 61 are inserted into the plurality of second openings 42 and melted therein. It is formed from a solder ball 51.

On the other side of the first substrate 11 (the front side in FIG. 1, the back side in FIG. 2, the upper side in FIG. 3), the following elements are provided:
A second insulating layer (insulating thin film) 22 provided on the other side of the first substrate 11;
A third opening 43 provided in the second insulating layer 22;
A second semiconductor chip 32 mounted on the other side of the first substrate 11, in particular, mounted on the other surface of the first substrate 11 and in the third opening 43;
A second insulating layer (insulating thin film) 22 provided on the other side of the first substrate 11;

  The components of the semiconductor device 1 will be described in detail with reference to FIGS.

  The first substrate 11 is a wiring substrate in which a predetermined wiring pattern is formed on both surfaces of an insulating base material such as a glass epoxy substrate. The first substrate 11 has a substantially rectangular shape.

  First and second insulating layers 21 and 22 are formed on both surfaces of the first substrate 11, respectively. Similar to the first insulating layer 21, the second insulating layer 22 can also be formed from a solder resist. The first insulating layer 21 is thicker than the second insulating layer 22. For example, the first insulating layer 21 is formed with a thickness of 80 μm, and the second insulating layer 22 is formed with a thickness of 20 μm.

  Referring to the lower side of the first substrate 11 in FIG. 3, the first insulating layer 21 includes a first opening 41 disposed in a substantially central region of the first insulating layer 21 and a first insulating layer 21. A plurality of second openings 42 disposed in the peripheral region of the layer 21. The plurality of second openings 42 are arranged in two rows along four sides on one surface of the first insulating layer 21.

  The first semiconductor chip 31 is accommodated in the first opening 41 and mounted on one surface of the first substrate 11 by flip chip mounting. The first semiconductor chip 31 can be formed from, for example, a substantially rectangular plate-shaped silicon substrate. When the first semiconductor chip 31 is, for example, a memory chip, a memory circuit is internally connected to a plurality of first electrode pads 31a described later.

  The first semiconductor chip 31 has a chip thickness of 60 μm, for example, and has a plurality of first bump electrodes 31 b having a thickness of 20 μm. Since the back surface (circuit surface, main surface) of the first semiconductor chip 31 is flip-chip mounted on the bottom surface of the first opening 41, the surface of the first semiconductor chip 31 is the first insulating layer. 21 is almost the same height as the surface.

  Before mounting the first semiconductor chip 31, the plurality of first connection pads 11 a are exposed through the first opening 41. Before the formation of the first conductor portion 61, the plurality of lands 11 c are exposed through the plurality of second openings 42. The plurality of first connection pads 11 a and the like form a wiring pattern on one surface of the first substrate 11. One side of the plurality of first connection pads 11a is electrically connected to the corresponding plurality of first conductor portions 61 via the plurality of lands 11c, and further includes a plurality of second solder balls (a plurality of solder balls). The first external electrode) 52 is electrically connected.

  The plurality of first electrode pads 31 a are disposed on one surface of the first semiconductor chip 31 along two opposing short sides. A plurality of first bump electrodes 31 b are formed on the plurality of first electrode pads 31 a so as to protrude from one surface of the first semiconductor chip 31. The plurality of first bump electrodes 31b can be composed of, for example, a pillar portion made of Cu and a solder layer 31c formed on the surface of the pillar portion.

  The plurality of first bump electrodes 31 b included in the first semiconductor chip 31 are electrically connected to the other side of the corresponding plurality of first connection pads 11 a arranged on the first substrate 11.

  A gap between the first semiconductor chip 31 and the first substrate 11 is filled with a resin filler 71 such as UF (underfill), NCF (non-conductive film), or NCP (non-conductive paste). ) Is filled, and a filling layer 71 is formed.

  On the other side of the first substrate 11, the second semiconductor chip 32 disposed in the third opening 43 also has the same configuration as the first semiconductor chip, and basically has the same connection configuration. Have. Therefore, the second semiconductor chip 32 will be described with respect to differences from the first semiconductor chip 31, and the above description regarding the first semiconductor chip 31 will be referred to as appropriate for the common points.

  The second insulating layer 22 has a third opening 43 disposed in a substantially central region of the second insulating layer 22. The second semiconductor chip 32 is mounted in the third opening 43 on the other surface of the first substrate 11.

  Before mounting the second semiconductor chip 32, the plurality of second connection pads 11 b are exposed through the third opening 43. One side of the plurality of second connection pads 11b is electrically connected to the corresponding plurality of second electrode pads 32a via the plurality of second bump electrodes 32b, and the other side is connected to the corresponding plurality of second electrode pads 32b. The land 11c is electrically connected via a plurality of conductors in the first substrate 11.

  A gap between the second semiconductor chip 32 and the other surface of the first substrate 11 is filled with a resin filler 71, for example, UF, NCF, or NCP, and a filling layer 71 is formed. .

  On the other surface of the first substrate 11, for example, a resin sealing layer 72 whose main component is a curable epoxy resin or the like is formed. The second semiconductor chip 32 is covered with a sealing layer 72.

  The first and second semiconductor chips 31 and 32 are rectangular. A plurality of first and second electrode pads 31a and 31b are arranged on two short sides on one surface of the first and second semiconductor chips 31 and 32, respectively. The first and second semiconductor chips 31 and 32 are flip-chip mounted on both surfaces of the first substrate 11 so as to cross each other (in a crossed state). In other words, the two short sides of the first semiconductor chip 31 protrude from the two long sides of the second semiconductor chip 32 when viewed in plan or from the thickness direction of the first substrate 11. Similarly, the two short sides of the second semiconductor chip 32 protrude from the two long sides of the first semiconductor chip 31. Accordingly, the plurality of first electrode pads 31 a included in the first semiconductor chip 31 and the plurality of second electrode pads 32 a included in the second semiconductor chip 32 are not in a plan view and are not formed in the first substrate 11. They do not overlap when viewed from the thickness direction.

The semiconductor device 1 (upper package 1a) of the first embodiment described above has the following configuration:
(1) A first opening 41 and a plurality of second openings 42 are provided in the first insulating layer 21 made of solder resist on the first substrate 11;
(2) The first semiconductor chip 31 is flip-chip mounted in the first opening 41;
(3) A plurality of first conductor portions 61 are provided in the plurality of second openings 42. Preferably, the first conductor portion 61 is formed using the first solder ball 51;
(4) A plurality of second solder balls 52 are mounted on the plurality of first conductor portions 61, and a plurality of first external electrodes 52 are formed.
(5) The surface of the first insulating layer 21 serving as a mounting surface for the plurality of second solder balls 52 can be formed at the same height as or higher than the surface of the first semiconductor chip 31.
(6) A second substrate (see the substrate 12 in FIG. 4) connected to the plurality of second solder balls 52 or the plurality of first external electrodes 52, and the first substrate 11 (particularly the first substrate). A sufficient space having a height corresponding to the diameter of the plurality of second solder balls 52 or the thickness of the plurality of first external electrodes 52 can be formed between the semiconductor chip 31).
(7) Thus, a sufficient stand-off SO (see FIG. 4) can be secured on the first semiconductor chip 31 mounting surface of the first substrate 11, in particular, directly on the first semiconductor chip 31.

  Further effects of the semiconductor device 1 of the first embodiment will be described.

  The mounting surfaces of the plurality of second solder balls 52 to the plurality of first external electrodes 52 are raised by the thickness of the first insulating layer 21, so that the plurality of second solder balls 52 to The first external electrode 52 can be formed small. As a result, a narrow pitch and a high degree of integration can be achieved.

  By mounting the first and second semiconductor chips 31 and 32 on both surfaces of the first substrate 11 by flip chip mounting, the wiring length can be shortened compared to the case of wire bonding mounting, and the semiconductor chip, for example, It is possible to improve the electrical characteristics of a memory chip such as a DRAM and increase the speed of the semiconductor device 1.

  By mounting the first and second semiconductor chips 31 and 32 on both surfaces of the first substrate 11 by flip chip mounting, the semiconductor device 1 can be thinned.

  The first and second semiconductor chips 31 and 32 are flip-chip mounted on the upper and lower surfaces of the first substrate 11 while being rotated 90 degrees relative to each other. As a result, a plurality of first electrode pads 31a (bump electrodes 31b) arranged on two opposing short sides of the first semiconductor chip 31 and two opposing short sides of the second semiconductor chip 32 are arranged. The plurality of second electrode pads 32 a (bump electrodes 32 b) arranged are arranged at positions that do not overlap in the thickness direction of the first substrate 11. For this reason, a plurality of lands 11c for the first semiconductor chip 31 are arranged on two sides of the four sides on the first substrate 11, and for the second semiconductor chip 32 on the remaining two sides. The plurality of lands 11c can be arranged in a distributed manner. As a result, wiring concentration is avoided and the first and second semiconductor chips 31 and 32 can be made to have equal length wiring. Furthermore, in the first substrate 11, the density of wiring can be avoided, so that the manufacturing yield of the substrate can be improved and the manufacturing cost of the semiconductor device 1 can be reduced.

  Next, an example in which the stacked semiconductor device 1 shown in FIG. 4 is configured by stacking the lower package 1b shown in FIG. 4 on the semiconductor device 1 (upper package 1a) shown in FIG.

  Referring to FIG. 4, the lower package 1 b has a second substrate 12. Similar to the first substrate 11, the second substrate 12 can be formed using an insulating base material. A predetermined wiring pattern is formed on both surfaces of the second substrate 12. A third insulating layer 23 is formed on the surface of the second substrate 12 on the first substrate 11 side, and a fourth insulating layer 24 is formed on the opposite surface. The third and fourth insulating layers 23 and 24 can be formed of a solder resist. The third and fourth insulating layers 23 and 24 have a thickness of 20 μm, for example.

  The third insulating layer 23 includes a fourth opening 44 disposed in the substantially central region and a plurality of fifth openings 45 disposed in the peripheral region. The plurality of third connection pads 12 a can be exposed through the fourth opening 44, and the plurality of lands 12 c can be exposed through the plurality of fifth openings 45.

  The fourth insulating layer 24 has a plurality of sixth openings 46. The plurality of lands 12 c of the wiring pattern can be exposed from the plurality of sixth openings 46. A plurality of third solder balls 53 are mounted on the plurality of lands 12c. Another package can be connected to the lower package 1b via the plurality of third solder balls 53.

  A third semiconductor chip 33 is flip-chip mounted in the fourth opening 44 on the surface of the second substrate 12 on the first substrate 11 side. As the third semiconductor chip 33, for example, a logic chip can be used. The plurality of third electrode pads 33a arranged on one surface of the third semiconductor chip 33 is connected to the plurality of third connection pads 12a on the second substrate 12 via the plurality of third bump electrodes 33b. Is electrically connected. A gap between the third semiconductor chip 33 and the second substrate 12 is filled with a resin filler 71 such as UF, NCF, or NCP.

  The plurality of second solder balls (external electrodes) 52 of the upper package 1a are arranged in the peripheral region on the first insulating layer 21 so as not to interfere with the third semiconductor chip 33 included in the lower package 1b. Bonded to a plurality of lands 12 c on the substrate 12.

  In the upper package 1 a, the first insulating layer 21 is formed thick so that the surface of the first insulating layer 21 is the same height as one surface of the first semiconductor chip 31. Thus, a large space corresponding to the diameter of the plurality of second solder balls 52 or the thickness of the plurality of external electrodes 52 between the first semiconductor chip 31 and the second substrate 12, that is, sufficient standoff. SO is formed. The second substrate 12 is connected to the first substrate 31 via a plurality of second solder balls 52 or external electrodes 52 so that the third semiconductor chip 33 is disposed in this space.

  By securing a sufficient standoff SO in this way, the first and the compact can be made compact while preventing interference between the first semiconductor chip 31 of the upper package 1a and the third semiconductor chip 33 of the lower package 1b. By stacking the second substrates 11 and 12, the degree of integration of the plurality of semiconductor chips 31, 32 and 33 can be increased. In addition, since the mounting surface of the plurality of second solder balls (external electrodes) 52 is raised by the first insulating layer 21, even if a plurality of second solder balls 52 having a relatively small diameter are used, it is sufficient. A stand-off SO can be secured. Accordingly, the upper and lower packages 1a and 1b can be configured compactly in the plane direction, and the reliability of mechanical and electrical connection between the upper and lower packages 1a and 1b is improved.

  Next, an example of a method for manufacturing the semiconductor device 1 shown in FIG. 4 will be described with reference to FIGS. 5A to 5D and FIGS. 6E and 6F in order. In some cases, the steps can be executed by changing the order, or can be executed simultaneously.

  As shown in FIG. 5A, a first substrate 11 is prepared. A plurality of product areas PA are arranged on the first substrate 11. The plurality of product areas PA are partitioned by dicing lines DL. The plurality of product areas PA become a plurality of wiring boards of a plurality of upper packages 1a (see FIG. 4) after cutting along the dicing lines DL.

  A solder resist is supplied to one surface of the first substrate 11 to form a first insulating layer 21, and a solder resist is supplied to the other surface to form a second insulating layer 22. The first insulating layer 21 is formed thicker than the second insulating layer 22.

  A predetermined pattern is formed on the first and second insulating layers 21 and 22 by using, for example, a photolithography method. As a result, a first opening 41 and a plurality of second openings 42 are formed in the first insulating layer 21, and a third opening 43 is formed in the second insulating layer 22. . In some cases, pattern formation may be performed simultaneously with the formation of the first and second insulating layers 21 and 22. In addition, it is preferable to use the method which can be formed in the state which exposed the 1st conductor part 61 grade | etc., Without shaving the 1st conductor part 61 from the 1st insulating layer 21, for the said pattern formation.

  Referring to FIG. 5B, in the die bonding process, the first substrate 11 is set on the stage of the die bonding apparatus DT. The die bonding apparatus DT sucks and holds the back surface of the second semiconductor chip (for example, memory chip) 32. A plurality of second bump electrodes 32 b are arranged on the plurality of second electrode pads 32 a included in the second semiconductor chip 32. A filler 71 made of NCF is supplied to one surface of the second semiconductor chip 32 so as to cover the plurality of second bump electrodes 32b.

  In this embodiment, the case where NCF is used as a filler will be described. However, after flip chip mounting, a method of filling UF, or after supplying NCP to the first substrate 11 side, flip chip mounting, A method of filling NCP may be used.

  The second semiconductor chip 32 is flip-chip mounted or mounted in the third opening 43 on the other surface of the first substrate 11 by using the die bonding apparatus DT. This process is performed similarly for a plurality of product areas PA.

  The plurality of second electrode pads 32a on the second semiconductor chip 32 are transferred to the second surface of the first substrate 11 via the plurality of second bump electrodes 32b by thermocompression bonding or ultrasonic thermocompression bonding. Bonded to the second connection pad 11b.

  The filler 71 is melted by heating at the time of bonding, and is filled in a gap between the other surface of the first substrate 11 and the main surface of the second semiconductor chip 32. The filler 71 is cured at a predetermined temperature, and the filler 71 is cured to form the filler layer 71.

  Referring to FIG. 5C, in the molding process, the first substrate 11 is clamped from above and below using a molding die of a transfer mold apparatus (not shown). A cavity is formed in the upper mold of the molding die. The first substrate 11 is set so that the upper mold covers a plurality of product areas PA at a time. A gate portion is formed on the upper mold. The sealing material 72 heated and melted is injected into the cavity from the gate portion. For the sealing material 72, for example, a thermosetting resin such as an epoxy resin is used. After filling with the sealing material 72, the sealing material is cured at a predetermined temperature to form the sealing layer 72. The sealing layer 72 collectively covers the plurality of product areas PA on the other surface of the first substrate 11. The sealing layer 72 covers the plurality of second semiconductor chips 32 mounted on the plurality of product areas PA.

  Referring to FIG. 5D, the first semiconductor chip 31 is flip-chip mounted in the first opening 41 on one surface of the first substrate 11. As described above, the first and second semiconductor chips 31 and 32 are preferably arranged in an intersecting state. Since the die bonding process of the first semiconductor chip 31 is the same as the die bonding process of the second semiconductor chip 32 described above, the above description should be referred to.

  However, the first insulating layer 21 is formed thicker than the second insulating layer 22, and the first opening 41 is formed deeper than the third opening 43. Therefore, the second semiconductor chip 32 protrudes from the third opening 43, whereas the first semiconductor chip 31 is accommodated in the second opening 42. That is, since the first insulating layer 21 is formed thick, the surface of the first insulating layer 21 is positioned at substantially the same height as the back surface of the first semiconductor chip 31.

  Referring to FIG. 6E, in the in-layer conductor portion forming step, the first conductor portion 61 is formed in the second opening 42 of the first insulating layer 21. A preferable method for forming the first conductor portion 61 and the like will be described later with reference to FIGS.

  Still referring to FIG. 6E, on one surface of the first insulating layer 21, a plurality of second openings 42 in which a plurality of first conductor portions 61 are formed are provided via a flux. A plurality of second solder balls 52 are mounted. The plurality of second solder balls 52 are balls made of an electrical conductor, for example, metal balls. A plurality of first external parts that reflow the first substrate 11 to melt the plurality of second solder balls 52 and connect to the plurality of first conductor portions 61 in the plurality of second openings 42. An electrode 52 is formed.

  Referring to FIG. 6F, in the substrate dicing step, the dicing tape DTa is bonded onto the sealing layer 72, and the first substrate 11 and the like are supported by the dicing tape DTa. The first substrate 11 and the like are cut vertically and horizontally along the dicing line DL by the dicing blade DB and cut and separated for each product area PA. Next, the upper package 1a as shown in FIG. 3 is obtained by pickup from the dicing tape DTa. Then, by connecting the lower package 1b onto the plurality of second solder balls (external electrodes) 52 included in the upper package 1a, the stacked semiconductor device 1 as shown in FIG. 4 is obtained.

  Next, a preferable method for forming the plurality of first conductor portions 61 and the plurality of first external electrodes 52 will be described in detail.

  Referring to FIG. 7A, in the in-layer conductor portion forming step, the first substrate 11 on which both the first and second semiconductor chips 31 and 32 are mounted is set on the stage of the ball mount device BT. Hold by adsorption.

  The plurality of first solder balls (small balls) 51 sucked and held in the plurality of suction holes of the ball mount device BT are supplied to the plurality of second openings 42 via the flux, and the plurality of lands 11c A plurality of first solder balls 51 are mounted on the board. The number of the first solder balls 51 supplied to one second opening 42 is set by the thickness of the second insulating layer 22 (depth of the second opening 42). For example, the two first solder balls 51 are supplied to the respective second openings 42, and the two first solder balls 51 are stacked on the land 11c. The plurality of first solder balls 51 are balls made of an electrical conductor, for example, metal balls.

  Referring to FIG. 7B, the first substrate 11 on which the plurality of first solder balls 51 are mounted is reflowed at a predetermined temperature.

  Referring to FIG. 7C, the plurality of first solder balls 51 are melted by the reflow, and a plurality of first conductor portions 61 are formed in the plurality of second openings 42.

  Referring to FIG. 7D, after the formation of the first conductor portion 61, in the external electrode formation step (mounting step of the second solder ball 52), a plurality of suction holes of the ball mount device BT are provided in the plurality of suction holes. The second solder ball (large ball) 52 is sucked and held. The plurality of second solder balls 52 are preferably larger in diameter than the plurality of first solder balls 51 and the plurality of second openings 42. The plurality of second solder balls 52 are mounted on the plurality of second openings 42 on one surface of the first insulating layer 21 through the plurality of adsorption holes via the flux. When the plurality of first conductor portions 61 are formed by reflow, the surfaces of the plurality of first conductor portions 61 tend to be concave. Accordingly, some of the plurality of second solder balls 52 are fitted into the plurality of second openings 42. A plurality of first external electrodes 52 are formed on the plurality of first conductor portions 61 by reflowing the first substrate 11 on which the plurality of second solder balls 52 are mounted.

  Next, dicing as described above can be performed to obtain a plurality of semiconductor devices 1, in particular, a plurality of upper packages 1a. Then, by connecting the lower package 1b on the plurality of second solder balls (external electrodes) 52, the stacked semiconductor device 1 as shown in FIG. 4 is obtained.

The manufacturing method of Embodiment 1 demonstrated above includes the following processes:
Preparing a first substrate 11 having a first insulating layer 21 having a first opening 41 and a plurality of second openings 42;
Mounting the first semiconductor chip 31 in the first opening 41 on the first substrate 11;
Supplying a plurality of first solder balls 51 into the second opening 42;
Heating the first substrate 11 to melt the plurality of first solder balls 51 to form the plurality of first conductor portions 61 in the plurality of second openings 42;
A plurality of second solder balls 52 having a diameter larger than that of the plurality of first solder balls 51 are placed on the plurality of second openings 42 to the plurality of first conductor portions 61 on one surface of the first substrate. The process of mounting.

  According to the manufacturing method of the first embodiment, it is possible to easily provide a stacked semiconductor device 1 with sufficient standoff and high integration. The further effect of the manufacturing method of Embodiment 1 is illustrated below.

(1) Since the plurality of first conductor portions 61 can be formed in an exposed state, the labor of cutting the first insulating layer 21 can be saved.
(2) Since the first insulating layer 21 can be formed from a solder resist, pattern formation including the first and second openings 41 and 42 can be easily performed using various methods such as photolithography. Can be formed.

[Embodiment 2]
In the second embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for common points.

  FIG. 8 schematically shows the configuration of the first upper package 2a of the stacked semiconductor device 2 shown in FIG.

  Referring to FIG. 9, in the stacked semiconductor device 2 according to the second embodiment, the lower package 2b is connected to the lower side of the first upper package 2a, and the second upper stage is further connected to the upper side of the first upper package 2a. The package 2c is stacked. The first and second upper packages 2a and 2c have the same structure. Therefore, the following mainly describes one of the first and second upper packages 2a and 2c.

  The first and second upper packages 2a and 2c of the second embodiment are the same as the upper package 1a of the first embodiment (see FIG. 3), the plurality of seventh openings 47 and the plurality of the plurality of seventh openings 47 formed in the sealing layer 72. This is mainly different in that it has a second conductor portion 62 formed in the seventh opening 47.

  With reference to FIGS. 8 and 9, in the upper package 2 a of the second embodiment, a plurality of seventh openings 47 are formed in the sealing layer 72 on the other surface of the first substrate 11. A plurality of second conductor portions 62 are formed in the plurality of seventh openings 47. A plurality of lands 11 c are formed in the peripheral regions on the front surface (other surface) and the back surface (one surface) of the first substrate 11. A part of the plurality of second conductor parts 62 is electrically connected to the second connection pad 11b, and the other part of the plurality of second conductor parts 62 is a plurality of parts on the surface of the first substrate 11. The plurality of lands 11 c on the back surface of the first substrate 11 are electrically connected via the lands 11 c and vias.

  The second upper package 2c having the third substrate 13 has the same configuration as the first upper package 2a described above.

The semiconductor device 2 of the second embodiment also includes the following configuration:
A first opening 41 and a plurality of second openings 42 are provided in the first insulating layer 21;
The first semiconductor chip 31 is flip-chip mounted in the first opening 41;
A plurality of first conductor portions 61 are provided in the plurality of second openings 42 (preferably, a plurality of first solder balls 51 are used);
A plurality of second solder balls 52 are mounted on the plurality of first conductor portions 61.

  Therefore, the semiconductor device 2 according to the second embodiment can obtain the same effects as those of the first embodiment. Furthermore, according to the second embodiment, the plurality of seventh openings 47 are formed in the sealing layer 72, and the plurality of second conductor parts 62 are formed in the plurality of seventh openings 47. As a result, as shown in FIG. 9, the second upper package 2c can be further stacked on the basic first upper package 2a, so that the stacked semiconductor device 2 has a large capacity or high functionality. Can be achieved.

  With reference to FIGS. 10A to 10D and FIGS. 11E to 11G, a method for manufacturing the semiconductor device 2 of the second embodiment will be described. Regarding the common points of the manufacturing method of the second embodiment and the manufacturing method of the first embodiment, the description of the first embodiment will be referred to as appropriate, and the differences between the two will be mainly described below.

  In the manufacturing method of the second embodiment, first, the steps of the first embodiment shown in FIGS. 5A to 5C are executed, and the sealing step shown in FIG. ) The following steps are executed.

  Referring to FIG. 10A, the first substrate 11 supplied with the sealing material 72 is transferred to the laser drilling process. A plurality of lands 11 c are arranged on the other surface of the first substrate 11 and in the peripheral region. A position corresponding to the plurality of lands 11c on the sealing material 72 is irradiated with laser light using a laser oscillator LO, and the sealing material 72 is partially removed. As a result, the seventh opening 47 is formed in the sealing material 72, and the plurality of lands 11 c are exposed through the seventh opening 47.

  Referring to FIG. 10B, the first solder ball 51 is held by suction using a ball mount device BT having a plurality of suction holes. The solder balls used here may be equivalent to those for forming the first conductor portion 61. The first solder ball 51 preferably has a smaller diameter than the diameter of the seventh opening 47. The first solder balls 51 attracted and held are collectively mounted on the plurality of lands 11c in the plurality of seventh openings 47 (bottom) via the flux. The number of the first solder balls 51 supplied to one seventh opening 47 is set by the thickness of the sealing material 72 (depth of the seventh opening 47). For example, the two first solder balls 51 are supplied to the respective seventh openings 47, and the two first solder balls 51 are stacked on one land 11c. The plurality of first solder balls 51 are balls made of an electrical conductor, for example, metal balls.

  Referring to FIG. 10C, the first substrate 11 supplied with the plurality of first solder balls 51 is reflowed at a predetermined temperature. Referring to FIG. 10D, the plurality of first solder balls 51 supplied into the plurality of seventh openings 47 are melted by the reflow, and a plurality of second solder balls 51 are sealed in the sealing layer 72. A conductor 62 is formed.

  The mounting process of the first semiconductor chip 31 shown in FIG. 11 (E), the forming process of the plurality of first conductor portions 61 and the plurality of external electrodes 52 shown in FIG. 11 (F), the dicing shown in FIG. 11 (G). In the first embodiment, the process is performed in the same manner as the process described with reference to FIG. 5D, FIG. 6E, or FIGS. 7A to 7D and FIG.

  According to the manufacturing method of the second embodiment, the same effects as those of the manufacturing method of the first embodiment can be obtained, and the capacity or function of the stacked semiconductor device 2 can be increased.

[Embodiment 3]
In the third embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be referred to as appropriate for common points.

  Referring to FIG. 12, the stacked semiconductor device 3 according to the third embodiment has a stacked structure in which a lower package 3b is connected to an upper package 3a. The upper package 3a of the third embodiment has the same structure as the upper package 1a of the first embodiment (see FIG. 3). The lower package 3b of the third embodiment differs from the lower package 1b of the first embodiment (see FIG. 4) in the following points:

The fifth insulating layer 25 is formed thicker than the third insulating layer 23 shown in FIG. 9;
The fifth insulating layer 25 has a plurality of eighth openings 48 for forming a conductor portion;
A plurality of third conductor portions 63 are formed in the plurality of eighth openings 48;
A plurality of first external electrodes (a plurality of second solder balls) 52 of the upper package 3a are connected to a plurality of third conductor portions 63 in a plurality of eighth openings 48 (the embodiment). 1 is connected to a plurality of lands 12c with reference to FIG.

  In the third embodiment, the same effect as in the first embodiment can be obtained. Further, the plurality of second solder balls 52 are connected to the conductor portions 61 and 63 in the openings 42 and 48 on both sides. According to such a connection method, a plurality of small second solder balls 52 can be used as compared with the case of the one-side land connection method of the first embodiment. As a result, the plurality of first external electrodes 52 included in the upper package 3a can be formed small, and the pitch of the external electrodes can be reduced.

[Embodiment 4]
In the fourth embodiment, differences from the first embodiment will be mainly described, and the description of the first embodiment will be appropriately referred to for common points.

  Comparing FIG. 14A and FIGS. 7A to 7C, the fourth embodiment is the same as that of the first embodiment and the first insulating layer 21 formed on one surface of the first substrate 11. The formation method of the 1 conductor part 61 is different. Except for the first conductor portion 61, the semiconductor device 4 of the fourth embodiment (upper package 4a shown in FIG. 13) and the semiconductor device 1 of the first embodiment (upper package 1a shown in FIG. 3) have the same structure. have. Therefore, hereinafter, the first conductor portion 61 forming step in the fourth embodiment will be described with respect to differences from the forming step of the first conductor portion 61 shown in FIGS. 7A to 7C. 14 (B) and FIG. 7 (D) are compared, and the difference in the effect due to the difference in the formation process will be described.

  With reference to FIGS. 7A to 7C, in the first embodiment, a plurality of first conductor portions 61 are provided in a plurality of second openings 42 using a plurality of first solder balls 51. Forming. For this reason, the surfaces (interfaces) of the plurality of first conductor portions 61 are below the opening surfaces of the plurality of second opening portions 42 (the surface of the first insulating layer 21).

  Referring to FIG. 14A, in the fourth embodiment, the plurality of first conductor portions 61 are formed in the plurality of second openings 42 by plating with Cu or the like. Therefore, the surfaces (interfaces) of the plurality of first conductor portions 61 are substantially flush with the opening surfaces of the plurality of second opening portions 42 (surfaces of the first insulating layer 21).

  Referring to FIG. 14B, the surfaces of the plurality of first conductor portions 61 are mounting surfaces for the plurality of second solder balls 52. Since the surface of the plurality of first conductor portions 61 is at a high position, the mounting surface of the plurality of second solder balls 52 is also at a high position, and the standoff (SO) larger than that shown in FIG. Is secured. In addition, Embodiment 4 can also show the effect of Embodiment 1 similarly.

  In the fourth embodiment, the method of forming the plurality of first conductor portions 61 by plating after the mounting of the first semiconductor chip 31 has been described. However, before the mounting of the first semiconductor chip 31, the plurality of first conductor chips 61 are formed. The conductor part 61 may be formed.

  As mentioned above, although the invention made | formed by this inventor was demonstrated based on embodiment etc., it cannot be overemphasized that this invention is not limited to the said embodiment etc., and can be variously changed in the range which does not deviate from the summary. . For example, a rigid wiring board such as a glass epoxy board, a flexible wiring board using a polyimide board or the like, or a wiring board having an intermediate property between the two can be appropriately selected and used as the board. As the semiconductor chip, a memory chip, a logic chip, and other chips can be appropriately selected and employed. The plurality of semiconductor chips mounted on both sides of the substrate may have the same configuration or different configurations. For example, a DRAM can be mounted on one surface of the substrate and a Flash memory chip or the like can be mounted on the other surface. In the embodiments and the like, the example in which the two semiconductor chips mounted on both surfaces of the substrate are arranged so as to intersect with each other has been described.

(Appendix)
[See Appendix 1, Fourth Viewpoint, Embodiment 4]
Forming a first insulating layer on one side of the first substrate;
Forming at least one first opening and a plurality of second openings in the first insulating layer;
Mounting a first semiconductor chip on one surface of the first substrate and in the first opening;
Forming a plurality of first conductor portions by plating in the plurality of second openings;
Mounting a solder ball for forming an external electrode connected to the plurality of first conductor portions on the first insulating layer to form a plurality of first external electrodes;
A method of manufacturing a semiconductor device including:

[See Appendix 2, Fifth Viewpoint, Embodiment 4]
A first substrate;
A first insulating layer provided on one side of the first substrate;
At least one first opening provided in the first insulating layer;
A plurality of second openings provided in the first insulating layer;
A first semiconductor chip mounted in the first opening;
A plurality of first conductor portions provided in the plurality of second openings and formed by plating;
A plurality of external electrodes provided on the first insulating layer and connected to the plurality of first conductor portions;
A semiconductor device comprising:

  Preferred configurations from the first to fifth viewpoints are exemplified below.

[Appendix 3, saving and labor saving]
One surface of each of the plurality of first conductor portions is formed in an exposed state, and the plurality of external electrode forming (second solder balls) are mounted on the one surface in the exposed state. Thereby, a plurality of external electrodes can be connected without cutting out the plurality of first conductor portions.

[Appendix 4, saving and labor saving]
The plurality of first conductor portions are in a state where the plurality of lands or the plurality of pads are exposed through the plurality of second openings on a plurality of lands or connection pads to be connected. It is formed,

[Appendix 5, Ease of pattern formation]
The first insulating layer is formed of a solder resist, and after forming the first insulating layer and the plurality of second openings, the plurality of first conductor portions are formed.

[Appendix 6, securing standoffs]
The surface of the first insulating layer to be a mounting surface for forming the plurality of external electrodes (second solder balls) is formed at the same height as or higher than the surface of the first semiconductor chip.

[Appendix 7, Double-sided mounting board]
A second insulating layer that is thinner than the first insulating layer is formed on the other side of the first substrate, a third opening is formed in the second insulating layer, and the third opening is formed in the third opening. Including a step of mounting a second semiconductor chip.

[Appendix 8, securing standoff, connecting lower package]
A step of connecting a second substrate on which a third semiconductor chip is mounted on the plurality of external electrode forming (second solder balls) or the plurality of first external electrodes; A space between one semiconductor chip and the second substrate having a height corresponding to the diameter of the plurality of external electrode forming (second) solder balls or the thickness of the plurality of first external electrodes. And the third semiconductor chip is disposed in the space on the first semiconductor chip.

[Appendix 9, securing standoff, connecting lower package]
Forming a third insulating layer having at least one fourth opening and a plurality of fifth openings on one surface of the second substrate; and another surface on the second substrate. A step of forming a fourth insulating layer having a plurality of sixth openings, a step of mounting the third semiconductor chip in the fourth openings, and the one surface of the second substrate. Connecting the plurality of external electrode forming (second) solder balls or the plurality of first external electrodes onto the plurality of lands exposed through the plurality of fifth openings. A plurality of second solder balls connected to a plurality of lands on the other surface of the second substrate and exposed through the plurality of sixth openings. Forming an electrode.

[Supplementary Note 10, Seventh Opening in Sealant]
A step of supplying a sealing material covering the second semiconductor chip to the other side of the first substrate; and a plurality of seventh layers in the sealing material or a sealing layer formed by the sealing material. And forming a plurality of second conductor portions electrically connected to the second semiconductor chip or the first conductor portion in the plurality of seventh openings. And including.

[Appendix 11, upper package added]
The method includes a step of connecting a third substrate having a plurality of semiconductor chips mounted on both sides on the plurality of second conductor portions.

[Appendix 12, Solder Ball Both Sides Connect to Conductor in Opening]
Forming a fifth insulating layer on one side of the second substrate; forming a plurality of eighth openings in the fifth insulating layer; and within the plurality of eighth openings. A plurality of third conductor portions, a plurality of third conductor portions, and a plurality of (second) solder balls for forming external electrodes or a plurality of first external electrodes. And a step of performing.

[Appendix 13, chip crossing arrangement]
The first semiconductor chip mounted on one side of the first substrate and the second semiconductor chip mounted on the other side of the first substrate include a plurality of the first semiconductor chip. The first electrode pads and the plurality of second electrode pads of the second semiconductor chip are arranged in an intersecting state so as not to be seen in a plan view and do not overlap in the thickness direction of the first substrate. .

[Appendix 14]
The semiconductor device of appendix 14 has a structure formed by the manufacturing method of any one of appendices 1 and 3-13.

  It should be noted that the embodiments and examples may be changed and adjusted within the scope of the entire disclosure (including claims and drawings) of the present invention and based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are included within the scope of the claims of the present invention. Is possible. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. Further, regarding numerical values and numerical ranges described in the present application, it is considered that any intermediate value, lower numerical value, and small range are described even if not specified.

1, 2, 3, 4 Semiconductor device, stacked semiconductor device 1a Upper package, first upper package 1b Lower package 2a First upper package 2b Lower package 2c Second upper package 3a Upper package 3b Lower package 4a Upper package 11 First board (wiring board, double-sided mounting board)
11a 1st connection pad 11b 2nd connection pad 11c Land 12 2nd board | substrate (FIG. 4, board | substrate of the lower package 1b)
12a Third connection pad 12c Land 13 Third substrate (embodiment 2, FIG. 9, substrate of second upper package 2c)
13c land (Embodiment 2, FIG. 9)
21 1st insulating layer (on one surface of the 1st board | substrate 11)
22 2nd insulating layer (on the other surface of the 1st board | substrate 11)
23 Third insulating layer (on one surface of the second substrate 12)
24 Fourth insulating layer (on the other surface of the second substrate 12)
25 Fifth insulating layer (on one surface of the second substrate 12)
26 Sixth insulating layer (on the other surface of the second substrate 12)
31 First semiconductor chip (lower side in FIG. 3)
31a First electrode pad 31b First bump electrode 31c Solder layer 32 Second semiconductor chip (upper side in FIG. 3)
32a Second electrode pad 32b Second bump electrode 32c Solder layer 33 Third semiconductor chip (Embodiment 2, FIG. 9)
33a Third electrode pad 33b Third bump electrode 41 First opening (embodiment 1, FIG. 4, in the first insulating layer 21 on the one surface of the first substrate 11, and within the first semiconductor chip 31) )
42 Second opening (Embodiment 1, FIG. 4, in the first insulating layer 21 on the one surface of the first substrate 11, for forming the first conductor 61)
43 3rd opening (Embodiment 1, FIG. 4, in the 2nd insulating layer 22 on the other surface of the 1st board | substrate 11, 2nd semiconductor chip 32 accommodation)
44 Fourth opening (embodiment 1, FIG. 4, in the third insulating layer 23 on the one surface of the second substrate 12, accommodating the third semiconductor chip 33)
45 Fifth opening (Embodiment 1, FIG. 4, in the third insulating layer 23 on one surface of the second substrate 12)
46 Sixth opening (Embodiment 1, FIG. 4, in the fourth insulating layer 24 on the other surface of the second substrate 12)
47 7th opening (Embodiment 2, FIG. 8, in the sealing layer 72, for forming the 2nd conductor part 62)
48 Eighth opening (Embodiment 3, FIG. 12, in the fifth insulating layer 25, for forming the third conductor 63)
51 First solder ball (small ball, for forming the first conductor 61)
52 Second solder ball, first external electrode (Embodiments 1 and 3, FIGS. 4 and 9, for lower connection)
53 Third solder ball, second external electrode (Embodiment 1, FIG. 4, and further for lower connection)
61 1st conductor part (Embodiment 1, FIG. 3)
62 2nd conductor part (Embodiment 2, FIG. 8, 7th opening part 47 of the sealing layer 72)
63 3rd conductor part (Embodiment 3, FIG. 12, in the 8th opening part 48 in the 5th insulating layer 25 on the 2nd board | substrate 12)
71 Filler (Resin Filler), Filling Layer 72 Sealing Material (Sealing Resin), Sealing Layer BT Ball Mount Device DT Die Bonding Device DB Dicing Blade DTa Dicing Tape DL Dicing Line LO Laser Oscillator PA Product Area SO Standoff

Claims (20)

Forming a first insulating layer on one side of the first substrate;
Forming at least one first opening and a plurality of second openings in the first insulating layer;
Mounting a first semiconductor chip on one surface of the first substrate and in the first opening;
Supplying a plurality of first solder balls into the plurality of second openings;
Melting the plurality of first solder balls to form a plurality of first conductor portions in the plurality of second openings;
Mounting a plurality of second solder balls connected to the plurality of first conductor portions on the first insulating layer to form a plurality of first external electrodes;
A method of manufacturing a semiconductor device including: One surface of the plurality of first conductor portions is formed in an exposed state,
The plurality of second solder balls are mounted on the exposed surface.
A method for manufacturing a semiconductor device according to claim 1. The plurality of first conductor portions are in a state where the plurality of lands or the plurality of pads are exposed through the plurality of second openings on a plurality of lands or connection pads to be connected. It is formed,
A method for manufacturing a semiconductor device according to claim 1. The first insulating layer is formed of a solder resist,
After forming the first insulating layer and the plurality of second openings, the plurality of first conductor portions are formed.
The manufacturing method of the semiconductor device as described in any one of Claims 1-3.   The surface of the said 1st insulating layer used as the mounting surface of these 2nd solder balls is formed in the same height as the surface of the said 1st semiconductor chip, or higher than it. A method for manufacturing a semiconductor device according to claim 1.   A second insulating layer that is thinner than the first insulating layer is formed on the other side of the first substrate, a third opening is formed in the second insulating layer, and the third opening is formed in the third opening. The manufacturing method of the semiconductor device as described in any one of Claims 1-5 including the process of mounting a 2nd semiconductor chip. Connecting a second substrate on which a third semiconductor chip is mounted on the plurality of second solder balls or the plurality of first external electrodes,
A space having a height corresponding to a diameter of the plurality of second solder balls or a thickness of the plurality of first external electrodes between the first semiconductor chip and the second substrate by the connection. Formed,
The method for manufacturing a semiconductor device according to claim 1, wherein the third semiconductor chip is disposed in the space on the first semiconductor chip. Forming a third insulating layer having at least one fourth opening and a plurality of fifth openings on one surface of the second substrate;
Forming a fourth insulating layer having a plurality of sixth openings on the other surface of the second substrate;
Mounting the third semiconductor chip in the fourth opening;
The plurality of second solder balls or the plurality of first external electrodes are connected to the plurality of lands exposed through the plurality of fifth openings on the one surface of the second substrate. Process,
A plurality of second external electrodes are formed by connecting a plurality of third solder balls on the plurality of lands that are exposed through the plurality of sixth openings on the other surface of the second substrate. Forming a step;
A method for manufacturing a semiconductor device according to claim 7. Supplying a sealing material covering the second semiconductor chip to the other side of the first substrate;
Forming a plurality of seventh openings in the sealing material or the sealing layer formed by the sealing material;
Forming a plurality of second conductor portions electrically connected to the second semiconductor chip or the first conductor portion in the plurality of seventh openings;
The manufacturing method of the semiconductor device as described in any one of Claims 1-8 containing these.   The method for manufacturing a semiconductor device according to claim 9, further comprising a step of connecting a third substrate having a plurality of semiconductor chips mounted on both sides on the plurality of second conductor portions. Forming a fifth insulating layer on one side of the second substrate;
Forming a plurality of eighth openings in the fifth insulating layer;
Forming a plurality of third conductor portions in the plurality of eighth openings;
Connecting the plurality of third conductor portions and the plurality of second solder balls or the plurality of first external electrodes;
A method for manufacturing a semiconductor device according to claim 7, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the plurality of second solder balls are larger in diameter than the first solder balls and the plurality of second openings.   The first semiconductor chip mounted on one side of the first substrate and the second semiconductor chip mounted on the other side of the first substrate include a plurality of the first semiconductor chip. The first electrode pads and the plurality of second electrode pads of the second semiconductor chip are arranged in an intersecting state so as not to be seen in a plan view and do not overlap in the thickness direction of the first substrate. The manufacturing method of the semiconductor device as described in any one of Claims 6-12. Forming an insulating layer on one side of the substrate;
Forming a plurality of openings in the insulating layer;
Supplying a plurality of first solder balls into the plurality of openings;
Melting the plurality of solder balls to form the conductor portion in the plurality of openings; and
Mounting a plurality of second solder balls connected to the plurality of conductor portions on the insulating layer;
A method of manufacturing a semiconductor device including: A first substrate;
A first insulating layer provided on one side of the first substrate and formed from a solder resist;
At least one first opening provided in the first insulating layer;
A plurality of second openings provided in the first insulating layer;
A first semiconductor chip mounted in the first opening;
A plurality of first conductor portions provided in the plurality of second openings;
A plurality of external electrodes provided on the first insulating layer and connected to the plurality of first conductor portions;
A semiconductor device comprising:   16. The semiconductor device according to claim 15, wherein the surface of the first insulating layer is at the same height as or higher than the surface of the first semiconductor chip. A second insulating layer provided on the other side of the first substrate and thinner than the first insulating layer;
A third opening provided in the second insulating layer;
A second semiconductor chip mounted in the third opening on the other surface of the first substrate;
A semiconductor device according to claim 15 or 16. A sealing layer provided on the other side of the first substrate and covering the second semiconductor chip; and a plurality of seventh openings provided in the sealing layer;
A plurality of second conductor portions provided in the plurality of seventh openings and electrically connected to the second semiconductor chip or the first conductor layer;
A plurality of second external electrodes provided on the sealing material or the sealing layer so as to be electrically connected to the plurality of second conductor portions;
A semiconductor device according to claim 17. A second substrate connected on the plurality of first external electrodes;
A space formed between the first semiconductor chip and the second substrate and having a height corresponding to the thickness of the plurality of first external electrodes;
A third semiconductor chip mounted on the second substrate and disposed in the space on the first semiconductor chip;
The semiconductor device as described in any one of Claims 15-18 provided with these. A fifth insulating layer provided on one side of the second substrate;
A plurality of eighth openings provided in the fifth insulating layer;
A plurality of third conductor portions provided in the plurality of eighth openings and connected to the plurality of first external electrodes;
The semiconductor device according to claim 19.

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