JP2015204388A - switching element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching element in which problems of hot carriers are less likely to occur.SOLUTION: A switching element has a first-conductivity-type drain region, a first-conductivity-type drift region in contact with the drain region, a second-conductivity-type body region in contact with the drift region, a first-conductivity-type source region in contact with the body region, a first insulating film formed on the upper surface of the body region, a gate electrode formed on the first insulating film, a second insulating film formed on the upper surface of the drift region, and a second-conductivity-type floating region formed on the underside of the drain region, and separated from the drain region by the drift region.

Description

  The present invention relates to a switching element.

  Cited Document 1 discloses a lateral MOSFET. In this MOSFET, a LOCOS oxide film is formed on the surface of the n-type epitaxial layer near the drain region.

JP 2005-093809 A

  In the MOSFET of the cited document 1, a high electric field is generated in the epitaxial layer below the LOCOS oxide film near the drain region. For this reason, carriers accelerated by a high electric field (so-called hot carriers) are injected into the gate oxide film, and the characteristics of the switching element deteriorate. Therefore, the present specification provides a switching element in which the problem of hot carriers hardly occurs.

  The switching element of the present invention includes a drain region of a first conductivity type exposed on an upper surface of a semiconductor layer, an exposed surface of the upper surface, is in contact with the drain region, and has a first conductivity type higher than the drain region. A first conductivity type drift region having a low impurity concentration; a second conductivity type body region exposed on the upper surface; in contact with the drift region; and separated from the drain region by the drift region; A source region of a first conductivity type that is exposed on the upper surface, is in contact with the body region, and is separated from the drift region by the body region, and is formed on the upper surface where the body region is exposed. A first insulating film, a gate electrode formed on the first insulating film, a second insulating film formed on the upper surface from which the drift region is exposed, Serial is formed on the lower side of the drain region, having a floating region of a second conductivity type which is separated from the drain region by the drift region.

  In this switching element, a floating region is formed below the drain region. For this reason, a depletion layer spreads from the floating region to the drift region during the operation of the switching element. As a result, the potential is distributed so that equipotential lines extend along the region between the drain region and the floating region. When the potential is thus distributed, the electric field in the drift region under the second insulating film is relaxed, and the generation of hot carriers is suppressed. Furthermore, since the direction of the electric field in the drift region under the second insulating film is directed away from the upper surface of the semiconductor layer, hot carriers are not easily injected into the insulating film. For this reason, the characteristics of this switching element are unlikely to deteriorate.

The longitudinal cross-sectional view of MOSFET10 which concerns on embodiment. The longitudinal cross-sectional view of the conventional MOSFET. The graph which shows the relationship between the position Y and angle (theta). The longitudinal cross-sectional view of MOSFET of a modification.

  A MOSFET 10 shown in FIG. 1 has an SOI substrate 12. The SOI substrate 12 has a substrate layer 14, a buried insulating film 16, and an active layer 18. The substrate layer 14 and the active layer 18 are made of Si. The substrate layer 14 and the active layer 18 are separated from each other by the buried insulating film 16. In the active layer 18, a drain region 20, a drift region 22, a floating region 24, a body region 26, a source region 28, and a body contact region 30 are formed.

  The drain region 20 is n-type and exposed on the upper surface 18 a of the active layer 18. The n-type impurity concentration of the drain region 20 is high. The drain region 20 is connected to the drain electrode 40 formed on the upper surface 18 a of the active layer 18 by ohmic connection.

  The drift region 22 is n-type and is formed in a well shape around the drain region 20. The drift region 22 is in contact with the drain region 20. The n-type impurity concentration of the drift region 22 is lower than the n-type impurity concentration of the drain region 20. The drift region 22 is exposed on the upper surface 18 a in a range in contact with the drain region 20 among the upper surface 18 a located between the drain region 20 and the source region 28.

  The floating region 24 is p-type and is formed below the drain region 20. The floating region 24 is formed at a position overlapping the drain region 20 when the SOI substrate 12 is viewed in plan. The floating region 24 is in contact with the drift region 22. A drift region 22 is interposed between the floating region 24 and the drain region 20. The floating region 24 is separated from the drain region 20 by the drift region 22. The entire periphery of the floating region 24 is surrounded by the drift region 22. For this reason, the floating region 24 is in contact only with the drift region 22 and is not in contact with other semiconductor regions.

  The body contact region 30 is p-type and exposed on the upper surface 18 a of the active layer 18. The body contact region 30 has a high p-type impurity concentration. The body contact region 30 is connected to the source electrode 44 formed on the upper surface 18a of the active layer 18 by ohmic connection.

  The source region 28 is n-type and is exposed on the upper surface 18 a of the active layer 18. The source region 28 is formed at a position on the drain region 20 side with respect to the body contact region 30. Source region 28 is in contact with body contact region 30. The n-type impurity concentration of the source region 28 is as high as the n-type impurity concentration of the drain region 20. The source region 28 is connected to the source electrode 44 by ohmic connection.

  The body region 26 is p-type and is formed in a well shape around the source region 28 and the body contact region 30. The body region 26 is in contact with the source region 28 and the body contact region 30. The body region 26 is in contact with the drift region 22. The p-type impurity concentration in the body region 26 is lower than the p-type impurity concentration in the body contact region 30. Body region 26 is exposed at upper surface 18 a located between source region 28 and drift region 22.

  A gate insulating film 46, a LOCOS insulating film 48, and a gate electrode 42 are formed on the upper surface 18 a of the active layer 18.

  The gate insulating film 46 covers the entire upper surface 18 a located between the source region 28 and the drift region 22. The gate insulating film 46 also covers a part of the upper surface 18a in the range where the drift region 22 is exposed.

  The LOCOS insulating film 48 is formed thicker than the gate insulating film 46. The LOCOS insulating film 48 covers the entire upper surface 18 a located between the gate insulating film 46 and the drain region 20. That is, the LOCOS insulating film 48 is formed on the upper surface 18a in the range where the drift region 22 is exposed. The gate insulating film 46 and the LOCOS insulating film 48 are connected. The entire upper surface 18 a between the source region 28 and the drain region 20 is covered with the gate insulating film 46 and the LOCOS insulating film 48.

  The gate electrode 42 is formed on the gate insulating film 46 and is insulated from the active layer 18. A part of the gate electrode 42 is also formed on the LOCOS insulating film 48. The gate electrode 42 extends from the upper part of the source region 28 to the upper part of the drift region 22, and faces the body region 26 through the gate insulating film 46.

  The MOSFET 10 is applied with a positive voltage between the source electrode 44 and the drain electrode 40 on the drain electrode 40 side. When a voltage equal to or higher than the threshold value is applied to the gate electrode 42, the region facing the gate electrode 42 (that is, the region in the vicinity of the upper surface 18a of the body region 26 between the source region 28 and the drift region 22) is inverted to n-type and Is formed. Therefore, a current flows from the drain electrode 40 to the source electrode 44 through the drain region 20, the drift region 22, the channel and the source region 28. That is, the MOSFET 10 is turned on. When the voltage of the gate electrode 42 is lowered below the threshold value, the channel disappears and the MOSFET is turned off.

  Next, the potential distribution in the drift region during the operation of the MOSFET will be described by comparing the conventional MOSFET with the MOSFET 10 of the present embodiment. FIG. 2 shows a longitudinal sectional view of a conventional MOSFET corresponding to FIG. For the sake of explanation, in FIG. 2, the same reference numerals as those in FIG. The MOSFET of FIG. 2 differs from MOSFET 10 of FIG. 1 only in that it does not have a floating region 24. The other configuration of the MOSFET of FIG. 2 is the same as that of the MOSFET of FIG.

  During the operation of the conventional MOSFET, a high electric field is generated in the drift region 22 below the LOCOS insulating film 48 in the vicinity of the drain region 20 due to the potential difference between the gate electrode 42 and the drain electrode 40. That is, in the conventional MOSFET, as shown by the dotted line in FIG. For this reason, carriers are accelerated in the lateral direction as indicated by an arrow 90 by the electric field in the drift region 22. Therefore, carriers flow toward the channel through the vicinity of the LOCOS insulating film 48. Carriers (hot carriers) that are excessively accelerated in the drift region 22 are injected into the gate insulating film 46 as indicated by an arrow 90, thereby degrading the characteristics of the MOSFET.

  On the other hand, in the MOSFET 10 of the present embodiment, a p-type floating region 24 is formed below the drain region 20 as shown in FIG. A depletion layer extends from the floating region 24 to the drift region 22 around the floating region 24. As a result, the potential is distributed in the vicinity of the drain region 20 so that the equipotential line extends along the drift region 22 between the drain region 20 and the floating region 24 as shown by the dotted line in FIG. As a result, in the region 50 (see FIG. 1) near the drain region 20 in the drift region 22, the equipotential lines are widened and the electric field is relaxed. For this reason, hot carriers are unlikely to occur in the MOSFET of the present embodiment. In the region 50, the direction of the electric field is obliquely downward. For this reason, in the drift region 22, as indicated by an arrow 92, carriers flow deeper than the conventional MOSFET (see arrow 90 in FIG. 2). Therefore, even when hot carriers are generated, the hot carriers are not easily trapped in the gate insulating film 46. Therefore, in the MOSFET 10 of this embodiment, the deterioration of the MOSFET characteristics due to hot carrier injection into the gate insulating film 46 hardly occurs.

  FIG. 3 shows a result of measuring the relationship between the position Y in the depth direction of the floating region 24 (see FIG. 1) and the angle θ (see FIG. 1) in the traveling direction of the hot carrier by simulation. As shown in FIG. 3, when the position Y is 0.4 μm or more, it can be seen that the angle θ is more remarkably increased and the hot carriers flow through deeper positions. Therefore, when the position Y is 0.4 μm or more, the deterioration of the MOSFET characteristics due to hot carriers can be more effectively suppressed.

  In the above embodiment, one floating region 24 is formed below the drain region 20. However, as shown in FIG. 4, a plurality of floating regions 24 may be formed below the drain region 20. In FIG. 4, the floating regions 24 are separated from each other by the drift region 22. According to such a configuration, as shown in FIG. 4, the equipotential lines are more likely to extend in the lateral direction, so that deterioration of the MOSFET characteristics due to hot carriers can be more effectively suppressed.

  In the above-described embodiment, the n-channel type switching element has been described. However, the above-described technique may be employed for the p-channel type switching element.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: MOSFET
12: SOI substrate 14: substrate layer 16: buried insulating film 18: active layer 18a: upper surface 20: drain region 22: drift region 24: floating region 26: body region 28: source region 30: body contact region 40: drain electrode 42 : Gate electrode 44: Source electrode 46: Gate insulating film 48: LOCOS insulating film

Claims (1)

A drain region of a first conductivity type exposed on the upper surface of the semiconductor layer;
A first conductivity type drift region exposed on the top surface, in contact with the drain region, and having a first conductivity type impurity concentration lower than that of the drain region;
A body region of a second conductivity type exposed on the upper surface, in contact with the drift region, and separated from the drain region by the drift region;
A source region of a first conductivity type exposed on the upper surface, in contact with the body region, and separated from the drift region by the body region;
A first insulating film formed on the upper surface where the body region is exposed;
A gate electrode formed on the first insulating film;
A second insulating film formed on the upper surface where the drift region is exposed;
A floating region of a second conductivity type formed below the drain region and separated from the drain region by the drift region;
A switching element.

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