JP2015193164A - Non-discharge nozzle detection apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a simplified circuit configuration for quickly detecting information about discharge or non-discharge of liquid droplets from each of plural nozzles in a period from a reference time.SOLUTION: A quaternary data receiving unit 60 generates quaternary data from a waveform selection signal sin for each clock, and a non-discharge determination unit 61 determines whether or not an ink droplet is discharged from a corresponding nozzle 8, on the basis of the quaternary data. An SRAM 63 stores, for each of all the nozzles, 1 for an ink droplet not being discharged and 0 for an ink droplet being discharged in the past discharge periods. An AND circuit 65 ANDs, for each nozzle 8, the SRAM 63 content with the non-discharge determination unit 61 output result for each discharge period, and if an ink droplet is discharged, outputs 0. The SRAM 63 is updated with the new output result.

Description

  The present invention relates to a non-ejection nozzle detection device capable of detecting information related to the presence or absence of droplet ejection for a plurality of nozzles.

  In an inkjet printer, if there are nozzles that have not ejected ink droplets for a long time, the ink in the nozzles will thicken, and the ejection characteristics may change and print image quality may deteriorate. For this reason, a technique is described in which information on whether or not ink droplets have been ejected is stored in a D-type flip-flop provided for each nozzle, and flushing is performed on nozzles that have not ejected ink droplets for a predetermined time or longer (for example, , See Patent Document 1).

JP-A-1-127362

  According to the above-described technology, every time a CPU (Central Processing Unit) determines the presence or absence of nozzles that are not discharging droplets, the output of each D-type flip-flop corresponding to all nozzles is output. It is necessary to confirm, and the process becomes complicated.

An object of the present invention is to provide a non-ejection nozzle detection device that can quickly detect information relating to the presence or absence of droplet ejection for a plurality of nozzles with a simple circuit configuration.

  A non-ejection nozzle detection device according to the present invention includes a storage circuit that stores information indicating whether or not droplets are ejected from a reference time to an n-th ejection cycle (n is a natural number) for each of a plurality of nozzles that eject droplets. A determination circuit for determining the presence or absence of droplet ejection in the (n + 1) th ejection cycle based on dot data indicating a droplet ejection amount in each of the (n + 1) th ejection cycle from each of the plurality of nozzles; and each of the plurality of nozzles And an update circuit that updates information stored in the storage circuit for each ejection cycle based on information from the storage circuit and information from the determination circuit.

  According to the present invention, it is possible to quickly detect information regarding the presence or absence of droplet discharge from the reference time for a plurality of nozzles with a simple circuit configuration. In the present invention, the “information about whether ink is ejected” includes not only information indicating whether ink droplets are ejected itself, but also whether there are more than a predetermined number of ink ejected and count number information.

1 is a schematic side view showing the inside of an ink jet printer according to a first embodiment of the present invention. It is a top view of the inkjet head shown in FIG. FIG. 2 is a functional block diagram of the printer shown in FIG. 1. FIG. 4 is a functional block diagram of the image processing circuit shown in FIG. 3. FIG. 4 is a functional block diagram of a non-ejection nozzle detection circuit shown in FIG. 3. FIG. 4 is a timing chart of the non-ejection nozzle detection circuit shown in FIG. 3, which is a functional block diagram of the non-ejection nozzle detection circuit according to the second embodiment of the present invention. 4 is a timing chart of the non-ejection nozzle detection circuit shown in FIG. 3. It is a functional block diagram of the non-ejection nozzle detection circuit concerning the modification of a 2nd embodiment of the present invention. It is a functional block diagram of a non-ejection nozzle detection circuit according to a third embodiment of the present invention.

<First Embodiment>
A schematic configuration of an ink jet printer 1 according to a preferred embodiment of the present invention will be described.

  As shown in FIG. 1, the printer 1 has an upper casing 11 and a lower casing 12 both having a rectangular parallelepiped shape. In addition, the left side surface in FIG. In addition, the right side surface in FIG. The upper housing 11 has an open bottom surface, and the lower housing 12 has an open top surface. The upper housing 11 is connected to the lower housing 12 so as to be rotatable about a rotation shaft 13. A paper discharge unit 15 is provided on the upper surface of the upper housing 11. The paper P that has been printed is sequentially discharged to the paper discharge unit 15. Inside the upper housing 11, a control unit 1p that controls the operation of the printer 1 is disposed.

  Further, an inkjet head 2, a paper tray 20, a paper transport mechanism 30, and a platen 9 are disposed in the internal space of the printer 1.

  As shown in FIGS. 1 and 2, the inkjet head 2 has a substantially rectangular parallelepiped shape, and has a discharge surface 2 a formed with a plurality of nozzles 8 for discharging ink droplets on the lower surface thereof. . Ink is supplied from an ink tank (not shown). The ink supplied to the inkjet head 2 reaches the nozzle 8 via a common ink chamber and a plurality of pressure chambers communicating with the common ink chamber. By driving an actuator (described later) included in the actuator unit 80a (see FIG. 3), a pressure is applied to the ink stored in the pressure chamber, and an ink droplet is ejected from the nozzle 8. FIG. 2 is a top view of the inkjet head 2, but the nozzle 8 is shown by a solid line for convenience of explanation.

  As shown in FIG. 2, the plurality of nozzles 8 form the same four nozzle units 80 (u1 to u4 in order from left to right in FIG. 1). The nozzle unit 80 has a trapezoidal section, and in the section, a plurality of nozzles 8 are arranged in a matrix and at different positions (shifted by L) in the main scanning direction. In each nozzle unit 80, a plurality of nozzles 8 arranged in the main scanning direction form one nozzle row 8a, and 16 nozzle rows 8a are arranged in parallel and in the sub-scanning direction ( FIG. 2 schematically shows only 8 columns). The four nozzle units 80 are arranged in a staggered manner along the main scanning direction so that the long side and the short side are sequentially reversed with respect to the sub-scanning direction. Specifically, the nozzle unit u1 and the nozzle unit u3 are arranged in the same position in the sub scanning direction and different in the main scanning direction, and the nozzle unit u2 and the nozzle unit u4 are arranged in the same position in the sub scanning direction and different in the main scanning direction. Has been placed. One actuator unit 80a is used for each nozzle unit 80. The actuator unit 80a includes as many actuators as the number of nozzles 8 arranged in the nozzle unit 80. In addition, a driver IC 80b (see FIG. 3) for controlling the actuator unit 80a is provided for each actuator unit 80a. The nozzle unit 80 and the corresponding actuator unit 80a and driver IC 80b form one head unit.

  The sheet tray 20 can hold a plurality of stacked sheets P and is detachably disposed on the bottom surface of the lower housing 12.

  The platen 9 is a plate member for supporting paper, and is fixed to the lower housing 12 so as to face the ejection surface 2a of the inkjet head 2 in a state where the upper housing 11 is in the closed position.

  The paper transport mechanism 30 constitutes a transport path for the paper P that passes from the paper tray 20 between the inkjet head 2 and the platen 9 to the paper discharge unit 15. The paper transport mechanism 30 includes a pickup roller 31, nip rollers 32a to 32e, and guides 33a to 33d. The pickup roller 31 sends out the sheets P stacked on the sheet tray 20 one by one from above. The nip rollers 32 a to 32 e are arranged along the conveyance path and apply a conveyance force to the paper P. The guides 33a to 33d are respectively disposed between the pickup roller 31 and the nip rollers 32a to 32e in the conveyance path, and the sheet P to which conveyance force is applied by the nip rollers 32a to 32e reaches the next nip rollers 32a to 32e. The paper P is guided. When the paper P transported by the paper transport mechanism 30 passes between the ink jet head 2 and the platen 9, an image is printed by ink droplets ejected from the nozzles 8 that open on the ejection surface 2 a of the ink jet head 2. The The paper P on which the image is printed is further transported by the paper transport mechanism 30 and discharged to the paper discharge unit 15.

  As shown in FIG. 3, the control unit 1p includes a CPU (Central Processing Unit) 41, a ROM (Read Only Memory) 42, a RAM (Random Access Memory) 43, an I / O control circuit 44, and an image processing circuit. 45, a print control circuit 46, a non-ejection nozzle detection circuit 47, and a preliminary ejection change circuit 48. The I / O control circuit 44 is electrically connected to the paper transport mechanism 30. The print control circuit 46 is electrically connected to one inkjet head 2, the image processing circuit 45, and the non-ejection nozzle detection circuit 47.

  The ROM 42 stores a control program 42a (firmware) for controlling the printer 1, various settings, initial values, and the like. The RAM 43 is used as a work area from which the control program 42a is read or as a storage area (main memory) for temporarily storing data.

  The CPU 41 causes the printer 1 to execute print processing while storing the processing results in the RAM 43 in accordance with signals sent from the control program 42a read from the ROM 42 and various sensors (not shown). When the printing process is executed, the CPU 41 functions as a RIP (Raster image processor) by the control program 42a. The RIP stores image data (which may be stored in an internal memory or main memory (not shown) or may be received from a host computer) represented in a page description language indicating an image to be printed. Is converted into raster data having the resolution indicated by the data, developed as RIP data on the main memory, and output to the image processing circuit 45. The RIP data includes gradation values (multi-valued data) indicated by 256 gradations from 0 to 255 for each of the pixels arranged in a matrix in the main scanning direction and the sub-scanning direction.

  The image processing circuit 45 quantizes the RIP data output from the CPU 41 into four values (00, 01, 10, 11) while performing error diffusion from 256 gradation values. Further, the image processing circuit 45 sequentially converts the quantized gradation value generated by the four-value quantization into a serial signal, and further converts the serial signal into a differential signal by LVDS (Low voltage differential signaling) to perform printing control. Transmit to circuit 46.

  The print control circuit 46 will be described in detail with reference to FIG. As shown in FIG. 4, the print control circuit 46 includes an LVDS reception unit 71, an LVDS transmission unit 72, a nozzle array map 73, a selection signal generation circuit 74, an ejection waveform setting register 77, and an ejection waveform generation circuit 78. And a CPU interface 79. The LVDS receiver 71 is an LVDS receiver that receives the differential signal transmitted from the image processing circuit 45. The LVDS receiver 71 converts the received differential signal into a quantized gradation value and outputs it.

  The nozzle row map 73 stores the positional relationship of the nozzles 8. The selection signal generation circuit 74 refers to the nozzle row map 73, rearranges the quantized gradation values input from the LVDS receiving unit 71 according to the positional relationship of the corresponding nozzles 8, and conforms to the arrangement of the nozzle rows. A waveform selection signal sin (four-value data) is generated.

  The waveform selection signal sin is one of four types of drive signals for driving the actuator unit 2b (corresponding to no discharge “00”, small droplet “01”, medium droplet “10”, and large droplet “11”). This is a 2-bit signal for selection. The generated waveform selection signal sin is output to the driver IC 80b in synchronization with a clock (not shown) as a differential signal via the LVDS transmitter 72 in serial form. Further, the selection signal generation circuit 74 outputs the waveform selection signal sin to the non-ejection nozzle detection circuit 47.

  The ejection waveform setting register 77 can store waveform patterns for generating four types of drive signal waveforms. When receiving the drive waveform pattern from the CPU 41 via the CPU IF 79, the waveform setting register 77 stores the received waveform pattern.

  The discharge waveform generation circuit 78 refers to the discharge waveform setting register 77 and generates waveform data signals of four types of drive signals. The generated waveform data signal of the drive signal is output to the driver IC 80b in synchronization with a clock (not shown) as a differential signal via the LVDS transmitter 72 in a serial format.

  The driver IC 80b converts the received differential signal into a waveform selection signal sin and drive waveform data. Furthermore, the driver IC 80b outputs the waveform selection signal sin to the actuator unit 80a, generates four types of drive signals from the drive waveform data, and outputs them to the actuator unit 80a. The actuator unit 80a selects the four types of input drive signals according to the waveform selection signal sin, thereby driving each actuator and ejecting ink droplets from the nozzles 8.

  The non-ejection nozzle detection circuit 47 is a nozzle 8 that has not ejected ink droplets once from the reference time (for example, when the previous maintenance process is performed) to the most recent ejection cycle (nth ejection cycle: n is a natural number). In this description, it is detected whether or not at least one nozzle (referred to as “non-ejection nozzle”) exists. The preliminary ejection change circuit 48 performs a flushing (preliminary ejection) process according to the detection result of the non-ejection nozzle detection circuit 47. When the preliminary ejection change circuit 48 detects the presence of a non-ejection nozzle, the non-ejection nozzle is used as a maintenance process in order to prevent the ink in the non-ejection nozzle from thickening and the ink ejection characteristics from deteriorating. Alternatively, a flushing process for discharging a predetermined amount of ink from all the nozzles 8 is executed. Thereby, it can suppress that an ink discharge characteristic falls. On the other hand, when the non-ejection nozzle is not detected, the preliminary ejection change circuit 48 delays the timing for executing the flushing process. Thereby, it is possible to suppress wasteful consumption of ink. A nozzle that ejects ink droplets at least once from the reference time to the most recent ejection cycle (nth ejection cycle) may be referred to as “ejection nozzle” in the following description.

  As shown in FIG. 5, the non-ejection nozzle detection circuit 47 includes a quaternary data reception unit 60, a non-ejection determination unit 61, an RD / WR address generation state machine 62, and an SRAM (memory circuit: Static Random Access Memory). 63, 64-bit DFF (D Flip Flop) 64 (first latch circuit: DFF1), AND circuit 65 (ejection history calculation circuit: AND1), DFF66 (second latch circuit: DFF2), and DFF67 (third Latch circuit: DFF 3), OR circuit 68 (aggregation circuit), OR circuit 69, and DFF 70. A clock (CLK) signal is input to the RD / WR address generation state machine 62, the SRAM 63, the DFF 64, the DFF 66, and the DFF 67 and 70, and they are synchronized with each other based on the clock. Since this clock is the same as the operation clock of the print control circuit 46, the quaternary data reception unit 60 and the non-ejection determination unit 61 that receive a signal from the print control circuit 46 are the RD / WR address generation state machine 62 and SRAM 63. , DFF64, DFF66, and DFF67, 68.

  The quaternary data receiving unit 60 is a waveform selection signal that is quaternary data (no ejection “00”, small droplet “01”, medium droplet “10”, large droplet “11”) output from the selection signal generation circuit 74. Sin is received sequentially. The non-ejection determining unit 61 determines whether or not each nozzle 8 does not eject ink droplets in the (n + 1) th ejection cycle from the quaternary data received by the quaternary data receiving unit 60. That is, the non-ejection determination unit 61 generates a non-ejection signal 1 indicating that the nozzle 8 does not eject an ink droplet in the (n + 1) th ejection cycle if the quaternary data is “00” indicating no ejection. If any one of “01”, medium droplet “10”, and large droplet “11”, an ejection signal 0 indicating that an ink droplet is ejected is output. The quaternary data quantized by the image processing circuit 45 may be supplied to the quaternary data receiving unit 60 or the non-ejection determining unit 61 as it is without using LVDS.

  The SRAM 63 is a 64 bit × 83 word storage circuit, and stores information indicating the presence or absence of ink ejection up to the nth ejection cycle for each nozzle 8. Each bit of the SRAM 63 corresponds to a different nozzle 8, and each bit stores a non-discharge signal 1 if the corresponding nozzle 8 is a non-discharge nozzle, and stores a discharge signal 0 if the corresponding nozzle 8 is a discharge nozzle. The RD / WR address generation state machine 62 outputs an address signal designating each bit of the SRAM 63 and a read or write command signal according to an instruction from the CPU 41. Thereby, each bit of the SRAM 63 can be read out or rewritten in each discharge cycle.

  The DFF 64 latches the storage contents of the SRAM 63, that is, whether or not each nozzle 8 is a non-ejection nozzle (non-ejection signal or ejection signal) in order of 64 bits. The AND circuit 65 has two input units and one output unit. The output of the non-ejection determination unit 61 relating to the (n + 1) th ejection cycle (information regarding the presence or absence of droplet ejection in the (n + 1) th ejection cycle) is sequentially input to one of the two input units for the plurality of nozzles 8. The other one of the input units sequentially inputs the 1-bit stored contents (information indicating whether or not droplets are discharged up to the n-th discharge period) latched by the DFF 64 for the plurality of nozzles 8. The AND circuit 65 outputs the non-ejection signal 1 (information indicating that there is no liquid droplet ejection by the (n + 1) th ejection cycle) from the output section when the non-ejection signal 1 is input to the two input sections. In other cases, a non-ejection signal 0 (information indicating that droplet ejection is present by the (n + 1) th ejection cycle) is output from the output unit. The DFF 66 latches the output result from the output unit of the AND circuit 65 by 64 bits. The latch result of the DFF 66 is input to the SRAM 63, and the stored contents of the SRAM 63 are updated every discharge cycle. As described above, in this embodiment, the two DFFs 64 and 66 and the AND circuit 65 constitute an update circuit.

  The AND circuit 65 switches the input source in order from the lower bit of the DFF 64 to the upper bit so that the signal output from the non-ejection determination unit 61 is switched, and the output destination of the output unit is also changed from the lower bit of the DFF 66. Switch in order toward the upper bits. When the output is completed for all 64 bits of the DFF 64, the DFF 64 repeats latching in units of 64 bits until all the stored contents of the SRAM 63 are latched.

  The DFF 67 latches the storage content of the SRAM 63 in units of 64 bits so as to be synchronized with the DFF 64. The OR circuit 68 includes 64 input units to which signals are input from the DFF 67 in units of 64 bits and one output unit. When at least one of the 64-bit units input to the input unit is a non-ejection signal 1 (indicating that there is no liquid droplet ejection), the OR circuit 68 applies to the 64 nozzles 8 corresponding to the 64-bit. A non-ejection signal 1 (indicating that at least one of the 64 nozzles 8 has no ink droplet ejection by the n-th ejection cycle) is output from the output unit, and in other cases (that is, 64 nozzles 8) In the case where all of these signals are ejection signals 0), the ejection signal 0 (indicating that droplet ejection has occurred by the nth ejection cycle for 64 nozzles 8) is output from the output unit. The DFF 70 latches the output result of the OR circuit 69. The OR circuit 69 has two input units to which the output result of the OR circuit 68 and the output result of the DFF 70 are input, and one output unit. The OR circuit 69 outputs the non-ejection signal 1 from the output section when at least one of the inputs input to the two input sections is the non-ejection signal 1, and otherwise outputs the ejection signal 0 from the output section. Output. Accordingly, the OR circuit 69 outputs the non-ejection signal 1 if there is at least one non-ejection nozzle 8 that has not ejected ink droplets by the n-th ejection cycle, and the ejection signal 0 if all nozzles 8 are ejection nozzles. Is output from the output unit.

  As described above, according to the printer 1 of the present embodiment, it is possible to quickly detect whether or not there are at least one non-ejection nozzle for the plurality of nozzles 8 with a simple circuit configuration.

  Further, when both the output of the non-ejection determination unit 61 related to the (n + 1) th ejection cycle and the 1-bit storage content from the DFF 64 to the nth ejection cycle are the non-ejection signal 1, the AND circuit 65 is the non-ejection signal 1. Since 1 is output from the output unit, and in other cases, the discharge signal 0 is output from the output unit, the processing in the update circuit can be performed efficiently.

  Further, since the contents stored in the SRAM 63 can be divided and processed by the DFFs 64 and 66, the circuit can be reduced in size.

  Further, when the DFF 67 latches the storage contents of the SRAM 63 in units of 64 bits and at least one of the inputs in units of 64 bits input to the input unit by the OR circuit 68 is the non-ejection signal 1, the non-ejection nozzle is detected. Therefore, the non-ejection nozzle from the reference time can be detected with a simple circuit configuration.

Second Embodiment
A second embodiment of the present invention will be described with reference to FIG. In addition, about the substantially same member and process procedure as 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The non-ejection nozzle detection circuit 247 includes a quaternary data reception unit 60, a non-ejection determination unit 61, an RD / WR address generation state machine 62, an SRAM 63, a 64-bit DFF 64, an AND circuit 65, a DFF 66, A page last line detection unit (total trigger signal output circuit) 267, an AND circuit (extraction circuit: AND2) 268, an OR circuit 69, and a DFF 70 are included. The last page last line detection unit 267 is a total trigger signal when printing the last page and the last line (for example, the last line of the 500th page from the previous maintenance process) in a period longer than a predetermined discharge cycle from the reference time. 1 is output, otherwise 0 is output. The AND circuit 268 includes two input units to which the output result of the AND circuit 65 and the output from the final page last line detection unit 267 are input, and one output unit. The AND circuit 268 outputs a non-ejection signal 1 (information indicating that there is no liquid droplet ejection by the (n + 1) th ejection cycle) from the output section when 1 is input to both input sections, and otherwise. Outputs an ejection signal 0 (information indicating that there is droplet ejection before the (n + 1) th ejection cycle) from the output unit. The output result when the non-ejection nozzle is detected is latched in the DFF 70. In the present embodiment, the OR circuit 69 and the DFF 70 constitute a non-ejection nozzle presence / absence detection circuit. Further, the final page final line detection unit 267, the AND circuit 268, and the non-ejection nozzle presence / absence detection circuit constitute a totaling circuit.

  The operation of the non-ejection nozzle detection circuit 247 will be described with reference to FIG. In order to simplify the description, the total number of nozzles in the head is assumed to be 4 in FIG. Therefore, the four clock cycles coincide with one ejection cycle (processing for one line). As shown in FIG. 7, the quaternary data receiving unit 60 receives the waveform selection signal sin output from the selection signal generation circuit 74 every clock. Further, the non-ejection determining unit 61 determines whether or not an ink droplet is ejected from the corresponding nozzle 8 based on the quaternary data received by the quaternary data receiving unit 60. That is, the non-ejection determining unit 61 outputs a non-ejection signal 1 when the nozzle 8 does not eject ink droplets in the ejection cycle, and outputs a ejection signal 0 when ejecting. The SRAM 63 stores the non-ejection signal 1 when no ink droplet has been ejected in the past ejection cycle, and the ejection signal 0 when the ink droplet has been ejected (therefore, all the initial values are the non-ejection signal 1). ). The AND circuit 65 takes the logical product (AND) of the storage contents of the SRAM 63 and the output result of the non-ejection determination unit 61 for each nozzle 8 and outputs an ejection signal 0 if there is ejection of an ink droplet. The output result is stored in the SRAM 63. Hereinafter, it demonstrates along a specific example.

(A) Regarding the processing of the first line,
In the first discharge cycle, since the four-value data of the second nozzle in the first line is “10” (medium droplet), the non-discharge determination of the second nozzle is “discharge (0)”, and the DFF 64 is an initial value. Becomes “non-ejection (1)”. For this reason, the output waveform of the second nozzle of the AND circuit 65 (AND1) becomes “discharge (0)”. This becomes the output waveform of the DFF 64 of the second line as it is.

(B) Regarding the processing of the second line,
In the second ejection cycle, the quaternary data of the fourth nozzle in the second line is “01” (small droplet), so the non-ejection determination of the fourth nozzle is “ejection (0)”, and the DFF 64 is the second Only the value of the nozzle is “discharge (0)”. For this reason, the output waveform of the second and fourth nozzles of the AND circuit 65 is “discharge (0)”. This becomes the output waveform of the DFF 64 in the third line as it is.

(C) Regarding the processing of the third line,
In the third ejection cycle, the quaternary data of the first and second nozzles in the third line is “10” (medium droplet), so the non-ejection determination of the first and second nozzles is “ejection (0)”. In the DFF 64, only the values of the second and fourth nozzles are “discharge (0)”. For this reason, the output waveform of the first, second, and fourth nozzles of the AND circuit 65 is “discharge (0)”. This becomes the output waveform of the DFF 64 in the fourth line as it is.

(D) Regarding the processing of the fourth line,
In the fourth ejection cycle, when the quaternary data of the second, third, and fourth nozzles in the fourth line are “10” (medium droplet), “01” (small droplet), and “11” (large droplet), The non-ejection determination of the second, third, and fourth nozzles is “ejection (0)”, and in DFF64, only the values of the first, second, and fourth nozzles are “ejection (0)”. For this reason, the output waveforms of all (1, 2, 3, and 4) nozzles of the AND circuit 65 are “ejection (0)”. Since the fourth line is the final line of the final page, 1 is output from the final page final line detection unit 267. At this time, since the output of the AND circuit 65 is “discharge (0)”, the output of the AND circuit 268 (AND2) is “discharge (0)”. Accordingly, the outputs of the OR circuit 69 and the DFF 70 are also “discharge (0)”, and the non-discharge nozzles are not detected.

(E) Regarding the processing of the 4 ′ line,
On the other hand, in the fourth ejection cycle, when the quaternary data of the 2nd and 4th nozzles in the 4 ′ line is “10” (medium droplet) and “11” (large droplet), the non-existence of the 2nd and 4th nozzles The ejection determination is “ejection (0)”, and in the DFF 64, only the values of the first, second, and fourth nozzles are “ejection (0)”. Therefore, the output waveform of the first, second, and fourth nozzles of the AND circuit 65 is “discharge (0)”, and the output waveform of the third nozzle is “non-discharge (1)”. Since the 4′-th line is the final line of the final page, 1 is output from the final page final line detection unit 267. At this time, since the third output waveform of the AND circuit 65 is “non-ejection (1)”, the output of the AND circuit 268 (AND2) is “non-ejection (1)”. Accordingly, the outputs of the OR circuit 69 and the DFF 70 are also “non-ejection (1)”, and the non-ejection nozzle is detected. Thus, the OR circuit 69 and the DFF 70 function as a non-ejection nozzle presence / absence detection circuit.

  As described above in detail, according to the printer of this embodiment, it is possible to quickly detect whether or not there is at least one non-ejection nozzle for the plurality of nozzles 8 with a simple circuit configuration.

  Further, it is possible to more quickly detect whether or not there is at least one non-ejection nozzle for the plurality of nozzles 8 without referring to the SRAM 63.

  Further, the non-ejection nozzle presence / absence detection circuit can know whether or not there is at least one non-ejection nozzle by the ejection cycle when the total trigger signal is output.

  The final page final line detection unit 267 outputs 1 as the total trigger signal on the final line of the final page, but the total trigger signal may be output at an arbitrary timing.

<Modification>
A modification of the second embodiment of the present invention will be described with reference to FIG. In this embodiment, the OR circuit 69 and the DFF 70 which are non-ejection nozzle presence / absence detection circuits are configured such that the output result when the non-ejection nozzle of the AND circuit 65 is detected is latched in the DFF 70. Other configurations may be used as long as they are detected. For example, as shown in FIG. 8, instead of the OR circuit 69 and the DFF 70, an up counter (non-ejection nozzle number detection circuit) 370 that counts the output result when the non-ejection nozzle of the AND circuit 65 is detected is arranged. May be.

  According to this, it is possible to know the number of non-ejection nozzles by the ejection cycle when the total trigger signal is output.

<Third Embodiment>
A third embodiment of the present invention will be described with reference to FIG. In addition, about the substantially same member and process procedure as 1st and 2nd embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted. In the second embodiment described above, one totalizing circuit is provided for all the nozzles 8. However, in this embodiment, all the nozzles 8 are grouped into four blocks for each nozzle unit 80. In addition, one summing circuit is provided for each block.

  The non-ejection nozzle detection circuit 447 includes a quaternary data reception unit 60, a non-ejection determination unit 61, an RD / WR address generation state machine 62, an SRAM 63, a 64-bit DFF 64, an AND circuit 65, and a DFF 66. Four summing circuits B1 to B4 corresponding to different nozzle units 80 are provided.

  The aggregation circuits B1 to B4 include a final page final line detection unit (aggregation trigger signal output circuit) 267, block 1 to 4 detection units 467a to 467d, an AND circuit 468, an OR circuit 69, and a DFF 70. Yes. The last page last line detection unit 267 outputs 1 as a total trigger signal when printing the last page and the last line in a period longer than a predetermined discharge cycle from the reference time, and outputs 0 otherwise. . The block 1 to 4 detection units 467a correspond to different nozzle units 80, and output 1 when performing processing related to the nozzles 8 belonging to the corresponding nozzle unit 80, and output 0 otherwise. Accordingly, the functioning summing circuits B1 to B4 are switched according to the output results of the block 1 to 4 detection units 467a to 467d.

  The AND circuit 468 includes three input units to which the output result of the AND circuit 65, the output from the final page last line detection unit 267, and the outputs from the block 1-4 detection units 467a to 467d are input, and one output. Part. The AND circuit 468 outputs the non-ejection signal 1 from the output unit when 1 is input to all three input units, and outputs the ejection signal 0 from the output unit otherwise. That is, the AND circuit 468 outputs the output result of the AND circuit 65 only when detecting the presence / absence of a non-ejection nozzle for the corresponding nozzle unit 80. The output result when the non-ejection nozzle is detected is latched in the DFF 70.

  As described above in detail, according to the printer of the present embodiment, whether or not there is at least one non-ejecting nozzle for each block composed of a plurality of nozzles 8 is quickly detected with a simple circuit configuration. can do.

  Further, it is possible to know for each block whether or not there is at least one non-ejection nozzle by the ejection cycle when the total trigger signal is output.

  In addition, this embodiment is only a mere illustration and does not limit this invention at all. Therefore, the present invention can be variously improved and modified without departing from the scope of the invention. For example, in the above-described embodiment, each circuit is described as an independent configuration for convenience of explanation. However, these circuits do not need to be independent from each other, and these circuits have substantially equivalent functions. At least two or more circuits may be configured as one circuit.

  Furthermore, in the above-described embodiment, the same flushing process is performed when a non-ejection nozzle is detected. However, the flushing process is performed depending on the aggregation result by the aggregation circuit, for example, the number of non-ejection nozzles and the occurrence frequency. The contents of may be changed. For example, the preliminary ejection change circuit 48 has no non-ejecting nozzles (embodiments 1 and 2), the number of non-ejecting nozzles is a predetermined number or less (modified example), and the blocks without non-ejecting nozzles are only specific blocks When this is detected (Embodiment 3), the total amount of ink discharged by the flushing process may be lowered. According to this, the efficiency of flushing can be improved.

  In the above-described embodiment, the non-ejection nozzle detection circuit has a configuration that includes a circuit that detects non-ejection nozzles and a circuit that counts the presence / absence of non-ejection nozzles. There may be. In this case, the presence or number of non-ejection nozzles can be detected by directly searching the stored contents of the SRAM 63.

  Further, in the third embodiment, the configuration in which the plurality of nozzles 8 are grouped so as to correspond to the nozzle unit 80 has been described. However, the nozzle group 80 may be grouped in an arbitrary relationship regardless of the nozzle unit 80.

  In the first embodiment, only one configuration of the summing circuit has been described. However, as in the third embodiment, a summing circuit may be provided for each block in which a plurality of nozzles 8 are grouped.

  Furthermore, although an example in which the present invention is applied to an ink jet printer has been described, the present invention can be applied to any apparatus that records an image by discharging droplets onto a recording medium, such as a copying machine or a facsimile.

DESCRIPTION OF SYMBOLS 1 ... Inkjet printer 1p ... Control part 2 ... Inkjet head 2a ... Ejection surface 2b ... Actuator unit 8 ... Nozzle 60 ... Four-value data receiving part 61 ... Non-ejection determination part 62 ... RD / WR address generation state machine 63 ... SRAM
64, 66, 67, 70 ... DFF
65 ... AND circuit 67 ... DFF
68, 69 ... OR circuit

Claims (9)

For each of the plurality of nozzles that discharge droplets, a storage circuit that stores information indicating the presence or absence of droplet discharge from the reference time to the nth discharge cycle (n is a natural number);
A determination circuit for determining the presence / absence of liquid droplet ejection in the (n + 1) th ejection cycle based on dot data indicating the ejection amount of liquid droplets in the (n + 1) th ejection cycle from each of the plurality of nozzles;
An update circuit that updates information stored in the storage circuit for each of the plurality of nozzles for each ejection cycle based on information from the storage circuit and information from the determination circuit. A non-ejection nozzle detection device. The update circuit includes:
For each of the plurality of nozzles, there is information relating to the presence or absence of droplet ejection related to the (n + 1) th ejection cycle from the determination circuit and information indicating whether or not droplet ejection has occurred up to the nth ejection cycle from the storage circuit. When the two input information indicates that there is no liquid droplet ejection, information indicating that there is no liquid droplet ejection is output by the (n + 1) th ejection cycle. The non-ejection nozzle detection device according to claim 1, further comprising an ejection history calculation circuit that outputs information indicating that there is droplet ejection by the (n + 1) th ejection cycle. The update circuit further includes a first latch circuit and a second latch circuit,
Information indicating the presence / absence of liquid droplet ejection related to the plurality of nozzles up to the nth ejection cycle stored in the memory circuit is read from the memory circuit by a predetermined number of a plurality that is smaller than the number of nozzles. The predetermined number of pieces of information latched in the first latch circuit and latched in the first latch circuit are input to the ejection history calculation circuit,
Information output from the ejection history calculation circuit is latched in the second latch circuit by the predetermined number of times, and the information stored in the storage circuit is updated according to the information latched in the second latch circuit. The non-ejection nozzle detection device according to claim 2. A third latch circuit for latching information indicating the presence or absence of droplet ejection related to the plurality of nozzles stored in the storage circuit until the n-th ejection cycle, for each of the predetermined number of times;
When the predetermined number of pieces of information are inputted from the third latch circuit, and at least one of the inputted pieces of the predetermined number of pieces of information indicates that there is no liquid droplet ejection, the predetermined number of nozzles are changed to the second number. A summing circuit that outputs information indicating that there is no droplet discharge before the n discharge cycle, and outputs information indicating that there is droplet discharge before the nth discharge cycle for the predetermined number of nozzles in other cases The non-ejection nozzle detection device according to claim 3, further comprising: Further comprising a counting circuit for counting information on the presence or absence of droplet discharge from the reference time for the plurality of nozzles;
The aggregation circuit is
A total trigger signal output circuit that outputs a total trigger signal at a predetermined timing;
For each of the plurality of nozzles, an extraction circuit that extracts a signal corresponding to information output from the discharge history calculation circuit in a discharge cycle in which the total trigger signal is output from the total trigger signal output circuit is included. The non-ejection nozzle detection device according to claim 2 or 3.   Non-ejection nozzle presence / absence detection in which the aggregation circuit outputs information on whether at least one of the plurality of nozzles has not ejected droplets from the reference time based on a signal from the extraction circuit The non-ejection nozzle detection device according to claim 5, further comprising a circuit.   For each of a plurality of blocks obtained by grouping the plurality of nozzles, the counting circuit includes liquids from the reference time in the nozzles belonging to each block based on the signals from the extraction circuit and the extraction circuit. The non-ejection nozzle detection device according to claim 5, further comprising a non-ejection nozzle presence / absence detection circuit that outputs information regarding whether there is at least one nozzle that has not ejected droplets.   The aggregation circuit further includes a non-ejection nozzle number detection circuit that outputs information on the number of nozzles that have not ejected droplets from the reference time among the plurality of nozzles based on a signal from the extraction circuit. The non-ejection nozzle detection device according to claim 5 or 6, wherein   The preliminary discharge change circuit which changes the contents of preliminary discharge concerning the plurality of nozzles according to the total result by the total circuit is further provided. Non-discharge nozzle detection device.

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