JP4765309B2 - Liquid ejecting apparatus and driving signal applying method - Google Patents

Description

  The present invention relates to a liquid ejection apparatus that has an element capable of performing an operation for ejecting a liquid and that can apply a plurality of drive signals to the element, and a method for applying a drive signal applied to the element.

As a liquid ejecting apparatus having an element capable of performing an operation for ejecting liquid, there are various apparatuses such as a printing apparatus, a color filter manufacturing apparatus, and a dyeing apparatus. In recent years, there has been proposed an apparatus capable of applying a plurality of drive signals to one element for the purpose of expanding the change width of the amount of liquid to be discharged or discharging the liquid at a higher frequency. For example, see Patent Document 1.) In this apparatus, a switch for controlling application of a drive signal to an element is provided corresponding to each of the plurality of drive signals. In this apparatus, the drive signal includes a plurality of drive pulses, and the drive pulses can be selectively applied to the element. This is because various amounts of liquid to be discharged can be selected.
JP 2000-52570 A

  By the way, in this apparatus, a signal having a constant voltage is generated from the end of generation of a drive pulse to the start of generation of the next drive pulse. A control period is provided while the constant voltage signal is generated. In this control period, control for switching between application and non-application of the drive signal to the element is performed. However, in this apparatus, no special control is performed during the control period. For this reason, there is a possibility that a plurality of switches may be turned on at the same time when the switches are switched. For example, consider a case where the drive signal applied to the element is switched from one drive signal to the other drive signal. In this case, regarding the logic for switching on / off of the switch, the logic level corresponding to one drive signal is switched from on to off, and the logic level corresponding to the other drive signal is switched from off to on. Even if such control is performed, in practice, the logic may repeatedly turn on and off in a short time during the transition period of switching.

  If there is a difference between the voltages of the drive signals when a plurality of switches are turned on at the same time, an unscheduled current may flow and adversely affect the apparatus. For example, a current may flow from a drive circuit that generates one drive signal, and the drive circuit that generates the other drive signal may draw this current. That is, a through current may occur between a plurality of drive circuits. Since this through current causes a sudden increase in current and the like, it can cause noise. This noise may adversely affect the operation of the apparatus. In addition, since the through current distorts the shape of the drive signal, there is a possibility of adversely affecting ink ejection.

  The present invention has been proposed to solve the above-described problems, and its object is to prevent a plurality of switches from being simultaneously turned on in a control period for switching between application and non-application of a drive signal. There is.

The main invention for achieving the object is as follows:
(A) an element capable of executing an operation for discharging liquid;
(B) A drive signal generation unit that generates a first drive signal having a plurality of unit signals within a repetition period and a second drive signal having a plurality of unit signals different from the first drive signal within the repetition period. When,
(C) a first switch that controls application of each unit signal to the element in the first drive signal;
(D) a second switch for controlling application of each unit signal to the element in the second drive signal;
(E) a first switch control signal that causes the first switch to select a unit signal to be applied to the element among a plurality of unit signals of the first drive signal, and a plurality of unit signals of the second drive signal. A decoder that outputs a second switch control signal that causes the second switch to select a unit signal to be applied to the element;
(F) the first switch and the second switch based on a first timing pulse that defines the switching timing of the first switch control signal and a second timing pulse that defines the switching timing of the second switch control signal; Is switched within the repetition period, so that the unit signal of the first drive signal and the unit signal of the second drive signal are selectively applied to the element, and a liquid having a magnitude corresponding to the unit signal is discharged. And a controller to
Have
The controller is connected in parallel to a first monostable multivibrator, a first capacitor connected in parallel to the first monostable multivibrator, a second monostable multivibrator, and the second monostable multivibrator. A second capacitor,
The first monostable multivibrator turns off the first switch over a first period based on the first timing pulse, and the first period is determined by changing the capacitance of the first capacitor. And
The second monostable multivibrator turns off the second switch over a second period based on the second timing pulse, and the second period is determined by changing the capacitance of the second capacitor. A liquid ejection device.

  Other features of the present invention will become apparent from the description of this specification and the accompanying drawings.

=== Summary of disclosure ===
At least the following will be made clear by the description of the present specification and the accompanying drawings.

That is, an element capable of performing an operation for ejecting a liquid, a first drive signal having a plurality of unit signals for defining the operation of the element, and a second having another unit signal for defining the operation of the element. A drive signal generating unit that generates a drive signal; a first switch that controls application of the unit signal to the element; a second switch that controls application of the other unit signal to the element; and the unit signal And a controller that forcibly turns off the first switch for a predetermined period from the end of the generation of the unit signal to the start of the generation of the next unit signal.
According to such a liquid ejecting apparatus, the controller forcibly turns off the first switch during a predetermined period defined between the end of generation of the unit signal and the start of generation of the next unit signal. Then, by performing control for switching between application and non-application of the first drive signal during this predetermined period, it is possible to prevent the first switch and the second switch from being turned on simultaneously. Thereby, the malfunction that the electric current which is not planned flows can be prevented.

In this liquid ejection apparatus, the first switch controls application of the unit signal to the element based on a switch control signal, and the controller controls the first switch regardless of the switch control signal. 1 switch is turned off for the predetermined period.
According to such a liquid ejecting apparatus, even if the switch control signal indicates the on state in a predetermined period due to the occurrence of an undesired logic level in the transition period of switching, the controller turns off the first switch. Let it be in a state. For this reason, it is possible to prevent a problem that a plurality of switches are simultaneously turned on, and to reliably prevent a problem that an unscheduled current flows.

In this liquid ejecting apparatus, the controller turns off the first switch based on a timing pulse that defines a switching timing of the switch control signal.
According to such a liquid ejecting apparatus, the timing at which the first switch is turned off can be matched with the timing at which the first switch control signal is switched. For this reason, it is possible to reliably prevent a problem that an unscheduled current flows.

In this liquid ejection apparatus, the controller invalidates the switch control signal at the timing of the front edge of the timing pulse and validates the switch control signal at the timing of the rear edge of the timing pulse. thing.
According to such a liquid ejection apparatus, the first switch is controlled based on the timing of the front edge and the timing of the rear edge of the timing pulse. For this reason, the period during which the first switch is turned off can be reliably matched with the period during which the switch control signal is switched.

In this liquid ejection apparatus, the controller invalidates the first switch control signal based on the timing pulse, and validates the first switch control signal after the predetermined period has elapsed since the invalidation. What to do.
According to such a liquid ejecting apparatus, the off time of the first switch can be determined without being restricted by the time width of the timing pulse, and the off time can be optimized.

In this liquid ejection apparatus, the controller outputs the switch control signal to the first switch when the switch control signal and the gate control signal are input, and the gate control signal is at a predetermined level, and the gate A gate circuit that outputs an off control signal for turning off the first switch to the first switch when the control signal is at another predetermined level; and during a period in which the first switch is turned off. The gate control signal is set to the other predetermined level.
According to such a liquid ejecting apparatus, since the gate circuit is controlled by the gate control signal, it is suitable for high-speed processing.

In this liquid ejection apparatus, the drive signal generation unit generates a second drive signal having a plurality of the other unit signals, and the controller performs the next operation after the end of the generation of the other unit signals. The second switch is forcibly turned off for another predetermined period before generation of another unit signal is started.
According to such a liquid ejecting apparatus, the controller forcibly turns off the second switch in another predetermined period defined between the end of generation of another unit signal and the start of generation of the next other unit signal. Put it in a state. In addition, by performing control for switching between application and non-application of the second drive signal during another predetermined period, it is possible to prevent the first switch and the second switch from being turned on simultaneously, and an unscheduled current is generated. It is possible to prevent a problem that flows.

In this liquid ejection apparatus, the second switch controls application of the other unit signal to the element based on another switch control signal, and the controller controls the other switch control signal. Regardless of whether the second switch is turned off for the other predetermined period.
According to such a liquid ejecting apparatus, even if another switch control signal indicates an ON state in another predetermined period due to generation of an undesired logic level in the transition period of switching, the controller 2 Turn off the switch. For this reason, it is possible to prevent a problem that a plurality of switches are simultaneously turned on, and to reliably prevent a problem that an unscheduled current flows.

In this liquid ejection apparatus, the controller turns off the second switch based on another timing pulse that defines the switching timing of the other switch control signal.
According to such a liquid ejecting apparatus, the timing at which the second switch is turned off can be matched with the timing at which another switch control signal is switched. For this reason, it is possible to reliably prevent a problem that an unscheduled current flows.

In this liquid ejection apparatus, the controller invalidates the other switch control signal at the timing of the front edge of the other timing pulse, and controls the other switch at the timing of the rear edge of the other timing pulse. The signal must be valid.
According to such a liquid ejection apparatus, the second switch is controlled based on the timing of the front edge and the timing of the rear edge of the timing pulse. For this reason, the period during which the second switch is turned off can be reliably matched with the period during which the other switch control signal is switched.

In this liquid ejection apparatus, the controller invalidates the second switch control signal based on the other timing pulse, and after the other predetermined period has elapsed since the invalidation, the controller performs the second switch control. The signal must be valid.
According to such a liquid ejecting apparatus, the off time of the second switch can be determined without being restricted by the time width of the timing pulse, and the off time can be optimized.

In this liquid discharge apparatus, the controller receives the other switch control signal and the other gate control signal, and when the other gate control signal is at a predetermined level, Another gate circuit that outputs to the second switch another off control signal for turning the second switch off when the other gate control signal is at another predetermined level. And the other gate control signal is set to the other predetermined level over a period in which the second switch is turned off.
Such a liquid ejecting apparatus is suitable for high-speed processing because the other gate circuit is controlled by another gate control signal.

  In such a liquid ejecting apparatus, it is preferable that the liquid is a liquid ink for printing.

Also, an element capable of executing an operation for ejecting printing liquid ink, a first drive signal having a plurality of unit signals for defining the operation of the element, and another unit signal for defining the operation of the element A drive signal generation unit that generates a plurality of second drive signals, a first switch that controls application of the unit signal to the element based on a switch control signal, and a switch that is based on another switch control signal. A second switch for controlling application of another unit signal to the element; and when the switch control signal and the gate control signal are input and the gate control signal is at a predetermined level, the switch control signal is transmitted to the first switch. A gate circuit for outputting to the first switch an off control signal for turning off the first switch when the gate control signal is at another predetermined level; When another switch control signal and another gate control signal are input and the other gate control signal is at a predetermined level, the other switch control signal is output to the second switch, and the other gate control signal is output. And another gate circuit that outputs another off control signal for turning off the second switch to the second switch when the second switch is at a predetermined level. Before the start of the generation of the unit signal, the gate control signal at the timing of the front edge of the timing pulse based on the timing pulse that defines the switching timing of the switch control signal regardless of the switch control signal. The other predetermined level is set to invalidate the switch control signal, and the gate control is performed at the timing of the rear edge of the timing pulse. The signal is set to the predetermined level to enable the switch control signal, or based on the timing pulse, the gate control signal is set to the other predetermined level to disable the first switch control signal, and the invalid After the elapse of a predetermined period, the gate control signal is set to the predetermined level and the first switch control signal is enabled to forcibly turn off the first switch for the predetermined period. And the switching timing of the other switch control signal is defined regardless of the other switch control signal between the end of generation of the other unit signal and the start of generation of the next other unit signal. Based on the other timing pulse, at the timing of the front edge of the other timing pulse, the other gate control signal is set to the other predetermined level to The other switch control signal is invalidated, the other gate control signal is set to the predetermined level at the timing of the rear edge of the other timing pulse, the other switch control signal is validated, or the other Based on the timing pulse, the other gate control signal is set to the other predetermined level, the second switch control signal is disabled, and the other gate control is performed after the predetermined period has elapsed since the disablement. A controller for forcing the second switch to the off state for the other predetermined period by setting the signal to the predetermined level and enabling the second switch control signal. A liquid ejection device can also be realized.
According to such a liquid ejecting apparatus, almost all of the described effects can be obtained, so that the object of the present invention can be achieved most effectively.

  In addition, a first drive signal having a plurality of unit signals for defining the operation of the element capable of performing an operation for discharging the liquid and a second drive signal having another unit signal for defining the operation of the element are generated. A drive signal generation step; and a switch-off step for forcibly turning off the first switch for a predetermined period from the end of generation of the unit signal to the start of generation of the next unit signal. A driving signal applying method can also be realized.

=== Target of explanation ===
<About liquid ejection device>
There are various types of liquid ejection devices such as a printing device, a color filter manufacturing device, a display manufacturing device, a semiconductor manufacturing device, and a DNA chip manufacturing device, and it is difficult to describe all of them. Therefore, in this specification, a printer as a printing apparatus and a printing system having the printer will be described as an example. The printing system is a system having at least a printing apparatus and a printing control apparatus that controls the operation of the printing apparatus, and corresponds to one form of a liquid ejection system having a liquid ejection apparatus and an ejection control apparatus. To do.

=== Configuration of Printing System ===
<About the overall configuration>
First, the printing apparatus will be described together with a printing system. Here, FIG. 1 is a diagram illustrating the configuration of the printing system 100.
The illustrated printing system 100 includes a printer 1 as a printing apparatus and a computer 110 as a printing control apparatus. Specifically, the printing system 100 includes a printer 1, a computer 110, a display device 120, an input device 130, and a recording / reproducing device 140.

  The printer 1 prints an image on a medium such as paper, cloth, or film. In addition, regarding this medium, in the following description, a sheet S (see FIG. 3A), which is a typical medium, will be described as an example. The computer 110 is communicably connected to the printer 1. In order to cause the printer 1 to print an image, the computer 110 outputs print data corresponding to the image to the printer 1. Computer programs such as application programs and printer drivers are installed in the computer 110. The display device 120 has a display. The display device 120 is for displaying a user interface of a computer program, for example. The input device 130 is a keyboard 131 or a mouse 132, for example. The recording / reproducing device 140 is, for example, a flexible disk drive device 141 or a CD-ROM drive device 142.

=== Computer ===
<Configuration of Computer 110>
FIG. 2 is a block diagram illustrating configurations of the computer 110 and the printer 1. First, the configuration of the computer 110 will be briefly described.

  The computer 110 includes the recording / reproducing device 140 and the host-side controller 111 described above. The recording / reproducing apparatus 140 is communicably connected to the host-side controller 111, and is attached to the housing of the computer 110, for example. The host-side controller 111 performs various controls in the computer 110, and the display device 120 and the input device 130 described above are also connected to be communicable. The host-side controller 111 includes an interface unit 112, a CPU 113, and a memory 114. The interface unit 112 is interposed between the printer 1 and exchanges data. The CPU 113 is an arithmetic processing unit for performing overall control of the computer 110. The memory 114 is for securing an area for storing a computer program used by the CPU 113, a work area, and the like, and includes a RAM, an EEPROM, a ROM, a magnetic disk device, and the like. As described above, computer programs stored in the memory 114 include application programs and printer drivers. The CPU 113 performs various controls according to the computer program stored in the memory 114.

  The print data is data in a format that can be interpreted by the printer 1, and includes various command data and pixel data SI (see FIG. 6 and the like). The command data is data for instructing the printer 1 to execute a specific operation. The command data includes, for example, command data for instructing paper feed, command data for indicating the carry amount, and command data for instructing paper discharge. The pixel data SI is data related to the pixels of the image to be printed. Here, the pixel is a square grid virtually defined on the paper, and indicates a region where dots are formed. The pixel data SI in the print data is data relating to dots formed on the paper (for example, gradation values). In the present embodiment, the pixel data SI is composed of 2-bit data. That is, the pixel data SI includes data [00] corresponding to no dot, data [01] corresponding to small dots, data [10] corresponding to formation of medium dots, and data corresponding to large dots. [11]. Therefore, the printer 1 can form dots with four gradations.

=== Printer ===
<About the configuration of the printer 1>
Next, the configuration of the printer 1 will be described. Here, FIG. 3A is a diagram illustrating a configuration of the printer 1 of the present embodiment. FIG. 3B is a side view illustrating the configuration of the printer 1 of the present embodiment. In the following description, FIG. 2 is also referred to.

  As shown in FIG. 2, the printer 1 includes a paper transport mechanism 20, a carriage moving mechanism 30, a head unit 40, a detector group 50, a printer-side controller 60, and a drive signal generation circuit 70. In the present embodiment, the printer-side controller 60 and the drive signal generation circuit 70 are provided on a common controller board CTR. The head unit 40 includes a head control unit HC and a head 41.

  In the printer 1, the control target unit, that is, the paper transport mechanism 20, the carriage moving mechanism 30, the head unit 40 (head controller HC, head 41), and the drive signal generation circuit 70 are controlled by the printer-side controller 60. As a result, the printer-side controller 60 prints an image on the paper S based on the print data received from the computer 110. Each detector in the detector group 50 monitors the status in the printer 1. Each detector outputs the detection result to the printer-side controller 60. Upon receiving the detection results from each detector, the printer-side controller 60 controls the control target unit based on the detection results.

<Regarding the paper transport mechanism 20>
The paper transport mechanism 20 corresponds to a medium transport unit that transports a medium. The paper transport mechanism 20 feeds the paper S to a printable position, or transports the paper S by a predetermined transport amount in the transport direction. This transport direction is a direction that intersects the carriage movement direction described below. 3A and 3B, the paper transport mechanism 20 includes a paper feed roller 21, a transport motor 22, a transport roller 23, a platen 24, and a paper discharge roller 25. The paper feed roller 21 is a roller for automatically feeding the paper S inserted into the paper insertion opening into the printer 1 and has a D-shaped cross section in this example. The transport motor 22 is a motor for transporting the paper S in the transport direction, and its operation is controlled by the printer-side controller 60. The transport roller 23 is a roller for transporting the paper S sent by the paper feed roller 21 to a printable area. The operation of the transport roller 23 is also controlled by the transport motor 22. The platen 24 is a member that supports the paper S being printed from the back side of the paper S. The paper discharge roller 25 is a roller for carrying the paper S that has been printed.

<About the carriage moving mechanism 30>
The carriage moving mechanism 30 is for moving the carriage CR to which the head unit 40 is attached in the carriage moving direction. The carriage movement direction includes a movement direction from one side to the other side and a movement direction from the other side to the one side. Since the head unit 40 includes the head 41, the carriage movement direction corresponds to the movement direction of the head 41, and the carriage movement mechanism 30 corresponds to a head moving unit that moves the head 41 in the movement direction. The carriage moving mechanism 30 includes a carriage motor 31, a guide shaft 32, a timing belt 33, a driving pulley 34, and a driven pulley 35. The carriage motor 31 corresponds to a drive source for moving the carriage CR. The operation of the carriage motor 31 is controlled by the printer-side controller 60. A drive pulley 34 is attached to the rotation shaft of the carriage motor 31. The drive pulley 34 is disposed on one end side in the carriage movement direction. A driven pulley 35 is disposed on the other end side in the carriage movement direction on the opposite side to the drive pulley 34. The timing belt 33 is connected to the carriage CR and is spanned between a driving pulley 34 and a driven pulley 35. The guide shaft 32 supports the carriage CR in a movable state. The guide shaft 32 is attached along the carriage movement direction. Accordingly, when the carriage motor 31 operates, the carriage CR moves along the guide shaft 32 in the carriage movement direction.

<About the head unit 40>
The head unit 40 is for ejecting ink toward the paper S. The head unit 40 is attached to the carriage CR. The head 41 included in the head unit 40 is provided on the lower surface of the head case 42. The head control unit HC included in the head unit 40 is provided inside the head case 42. The head controller HC will be described in detail later.

  Next, the structure of the head 41 will be described. Here, FIG. 4 is a cross-sectional view for explaining the structure of the head 41. The illustrated head 41 includes a flow path unit 41A and an actuator unit 41B. The flow path unit 41A includes a nozzle plate 411 provided with a nozzle Nz, a storage chamber forming substrate 412 in which an opening serving as an ink storage chamber 412a is formed, and a supply port forming substrate 413 in which an ink supply port 413a is formed. Have The actuator unit 41B has a pressure chamber forming substrate 414 in which an opening to be a pressure chamber 414a is formed, a vibration plate 415 that partitions a part of the pressure chamber 414a, and an opening to be a supply side communication port 416a. It has a lid member 416 and a piezo element 417 formed on the surface of the diaphragm 415. In the head 41, a series of flow paths from the ink storage chamber 412a to the nozzle Nz through the pressure chamber 414a is formed. In use, this flow path is filled with ink, and by deforming the piezo element 417, ink can be ejected from the corresponding nozzle Nz. Accordingly, in the head 41, the piezo element 417 corresponds to an element capable of executing an operation for ejecting ink.

  In the printer 1, as described above, there is no dot corresponding to the data [00] of the pixel data SI, formation of a small dot corresponding to the data [01], formation of a medium dot corresponding to the data [10], In addition, four types of control of forming large dots corresponding to data [11] can be performed. For this reason, a plurality of types of ink having different amounts can be ejected from each nozzle Nz. For example, from each nozzle Nz, there are three types of ink consisting of large ink droplets capable of forming large dots, medium ink droplets capable of forming medium dots, and small ink droplets capable of forming small dots. Can be discharged.

<Regarding the detector group 50>
The detector group 50 is for monitoring the status of the printer 1. As shown in FIGS. 3A and 3B, the detector group 50 includes a linear encoder 51, a rotary encoder 52, a paper detector 53, a paper width detector 54, and the like. The linear encoder 51 is for detecting the position of the carriage CR (head 41, nozzle Nz) in the carriage movement direction. The rotary encoder 52 is for detecting the rotation amount of the transport roller 23. The paper detector 53 is for detecting the leading end position of the paper S to be printed. The paper width detector 54 is for detecting the width of the paper S to be printed.

<About the printer-side controller 60>
The printer-side controller 60 controls the printer 1. As shown in FIG. 2, the printer-side controller 60 includes an interface unit 61, a CPU 62, a memory 63, and a control unit 64. The interface unit 61 exchanges data with the computer 110 which is an external device. The CPU 62 is an arithmetic processing unit for performing overall control of the printer 1. The memory 63 is for securing an area for storing a program of the CPU 62, a work area, and the like, and is configured by a storage element such as a RAM, an EEPROM, or a ROM. Then, the CPU 62 controls each control target unit according to the computer program stored in the memory 63. For example, the CPU 62 controls the paper transport mechanism 20 and the carriage moving mechanism 30 via the control unit 64.

  Further, the CPU 62 outputs a head control signal for controlling the operation of the head 41 to the head controller HC, and outputs a control signal for generating the drive signal COM to the drive signal generation circuit 70. For example, as shown in FIG. 6, the head control signal includes a transfer clock CLK, pixel data SI, a latch signal LAT, a first change signal CH_A, and a second change signal CH_B. The control signal for generating the drive signal COM is, for example, a DAC value. This DAC value is information for instructing the voltage to be output from the first drive signal generation unit 70A and the second drive signal generation unit 70B, and is updated every extremely short update cycle. The DAC value is a kind of generation information for generating the drive signal COM.

<About the drive signal generation circuit 70>
The drive signal generation circuit 70 generates a commonly used drive signal COM and corresponds to a drive signal generation unit. The drive signal COM of this embodiment is used in common for all the piezo elements 417 corresponding to one nozzle row. Here, FIG. 5 is a block diagram illustrating the configuration of the drive signal generation circuit 70.

  The drive signal generation circuit 70 can simultaneously generate a plurality of types of drive signals COM. The drive signal generation circuit 70 of the present embodiment includes a first drive signal generation unit 70A that generates the first drive signal COM_A and a second drive signal generation unit 70B that generates the second drive signal COM_B. Then, the first drive signal generation unit 70A amplifies the first waveform generation circuit 71A that outputs a signal of a voltage corresponding to the DAC value (generation information) and the current of the signal generated by the first waveform generation circuit 71A. A first current amplification circuit 72A is provided. The second drive signal generation unit 70B includes a second waveform generation circuit 71B and a second current amplification circuit 72B. The first waveform generation circuit 71A and the second waveform generation circuit 71B have the same configuration, and the first current amplification circuit 72A and the second current amplification circuit 72B have the same configuration.

<About the generated drive signal COM>
Next, the drive signal generated by the drive signal generation circuit 70 will be described. The exemplified drive signal generation circuit 70 generates the first drive signal COM_A and the second drive signal COM_B shown in FIG. That is, the first drive signal generation unit 70A generates the first drive signal COM_A based on the first DAC value (corresponding to the first generation information). In addition, the second drive signal generation unit 70B generates the second drive signal COM_B based on the second DAC value (corresponding to the second generation information).

  The first drive signal COM_A includes a first waveform section SS11 generated in the period T11 in the repetition period T, a second waveform section SS12 generated in the period T12, and a third waveform section SS13 generated in the period T13. Have. Here, the first waveform section SS11 has a drive pulse PS1. The second waveform section SS12 has a drive pulse PS2, and the third waveform section SS13 has a drive pulse PS3. The drive pulse PS1 and the drive pulse PS2 are applied to the piezo element 417 when a large dot is formed, and have the same waveform. That is, the drive pulse PS1 and the drive pulse PS2 define from the start to the end of the operation for ejecting ink when forming a large dot. The drive pulse PS3 is applied to the piezo element 417 when the medium dot is formed. The drive pulse PS3 defines from the start to the end of the operation for ejecting ink when forming a medium dot. By applying this drive pulse PS3 to the piezo element 417, a medium ink droplet is ejected from the head 41 (corresponding nozzle Nz).

  The second drive signal COM_B has a first waveform section SS21 generated in the period T21 and a second waveform section SS22 generated in the period T22. In the second drive signal COM_B, the first waveform section SS21 has a drive pulse PS4, and the second waveform section SS22 has a drive pulse PS5. Here, the drive pulse PS4 is applied to the piezo element 417 when forming small dots. By applying this drive pulse PS4 to the piezo element 417, a small ink droplet is ejected from the head 41. Therefore, this drive pulse PS4 defines from the start to the end of the operation for ejecting ink when forming small dots. The drive pulse PS5 is applied to the piezo element 417 when a large dot is formed. That is, this drive pulse PS5 also defines from the start to the end of the operation for ejecting ink when forming a large dot. In the present embodiment, the period T22 has the same start timing and length as the period T13 in the first drive signal COM_A. That is, the total length of the period T11 and the period T12 of the first drive signal COM_A is the same as the length of the period T21 of the second drive signal COM_B.

  These drive pulses PS1 to PS5 all define the operation of the piezo element 417 when ink is ejected. Of the drive pulses PS1 to PS5, the drive pulses PS1 to PS3 included in the first drive signal COM_A correspond to unit signals. The drive pulses PS4 and PS5 included in the second drive signal COM_B correspond to other unit signals.

  The first drive signal COM_A and the second drive signal COM_B can be applied to the piezo element 417 for each waveform portion. That is, a part of the first drive signal COM_A and the second drive signal COM_B can be selectively applied to the piezo element 417. Further, a part of the first drive signal COM_A and a part of the second drive signal COM_B can be combined and applied to the piezo element 417. In this example, the first waveform portion SS11 of the first drive signal COM_A and the first waveform portion SS21 of the second drive signal COM_B are transferred to the piezo element 417 at the start timing of the repetition period T (the latch pulse timing of the latch signal LAT). It can be selected whether or not to apply. In addition, at the timing of the first change pulse of the first change signal CH_A, it is possible to select whether or not to apply the second waveform portion SS12 of the first drive signal COM_A to the piezo element 417. Note that control for applying each waveform portion to the piezo element 417 will be described in detail later.

<About the head controller HC>
Next, the head controller HC will be described. Here, FIG. 6 is a block diagram illustrating the configuration of the head controller HC. FIG. 7 is an explanatory diagram of the control logic 84. FIG. 8 is an explanatory diagram of the decoder 83.

  As shown in FIG. 6, the head controller HC includes a first shift register 81A, a second shift register 81B, a first latch circuit 82A, a second latch circuit 82B, a decoder 83, a control logic 84, A prevention circuit 85, a first switch 86A, and a second switch 86B are provided. Each part excluding the control logic 84 (that is, the first shift register 81A, the second shift register 81B, the first latch circuit 82A, the second latch circuit 82B, the decoder 83, the prevention circuit 85, the first switch 86A, and the first switch 86A) Two switches 86B) are provided for each piezo element 417. Since the piezo element 417 is provided for each nozzle Nz from which ink is ejected, these parts are also provided for each nozzle Nz.

  The head controller HC performs control for ejecting ink based on the pixel data SI from the printer-side controller 60. That is, the head controller HC controls the first switch 86A and the second switch 86B based on the print data, and selectively applies the necessary portions of the first drive signal COM_A and the second drive signal COM_B to the piezo element 417. I am letting. In the present embodiment, the pixel data SI is composed of 2 bits, and the pixel data SI is sent to the recording head 41 in synchronization with the clock signal CLK. Then, the upper bit group of the pixel data SI is set in each first shift register 81A, and the lower bit group is set in each second shift register 81B. A first latch circuit 82A is electrically connected to the first shift register 81A, and a second latch circuit 82B is electrically connected to the second shift register 81B. When the latch signal LAT from the printer-side controller 60 becomes H level, each first latch circuit 82A latches the upper bits of the corresponding pixel data SI, and each second latch circuit 82B receives the lower bits of the pixel data SI. Latch. Pixel data SI (a set of upper bits and lower bits) latched by the first latch circuit 82A and the second latch circuit 82B is input to the decoder 83, respectively.

  The decoder 83 performs decoding based on the upper and lower bits of the pixel data SI, and controls a switch control signal SW (first switch control signal SW_A, second switch control) for controlling the first switch 86A and the second switch 86B. Signal SW_B, see FIG. 8). The switch control signal SW is output based on a combination of the selection data stored in the control logic 84 and the pixel data SI latched by the first latch circuit 82A and the second latch circuit 82B.

  Here, the control logic 84 and selection data stored in the control logic 84 will be described. As shown in FIG. 7, the control logic includes a plurality of registers RG that can store 1-bit data. Each register RG is configured by, for example, a D-FF (delay flip flop) circuit. Each register RG stores predetermined selection data.

  For convenience of explanation, in FIG. 7, each register RG is arranged in a matrix of four in the column direction (vertical direction) and eight in the row direction (horizontal direction). Then, four registers RG belonging to the same column are grouped, and are shown with reference numerals Q0 to Q7 in order from the left group. Each register RG is divided into a register group (groups Q0 to Q3) located on the left side in the row direction and a register group (groups Q4 to Q7) located on the right side in the row direction. For the register group located on the left side, four registers RG belonging to the same row are grouped, and symbols G11 to G14 are given in order from the group located on the upper side. Similarly, the registers located on the right side are indicated by reference numerals G21 to G24 in order from the group located on the upper side.

  The above grouping is performed based on the role of each register RG. First, the registers RG belonging to the groups Q0 to Q3 located on the left side in the row direction can store the first selection data for the first drive signal COM_A. Each register RG belonging to the four groups Q4 to Q7 located on the right side in the row direction can store the second selection data for the second drive signal COM_B. Further, the registers RG belonging to the same column can store selection data used with the same gradation value. More specifically, each of the registers RG belonging to the group Q0 and the group Q4 can store selection data corresponding to pixel data SI (data [00]) without dots. Each register RG belonging to group Q1 and group Q5 can store selection data corresponding to pixel data SI (data [01]) of small dots. Similarly, the registers RG belonging to the groups Q2 and Q6 receive selection data corresponding to the medium dot pixel data SI (data [10]), and the registers RG belonging to the groups Q3 and Q7 store the large dot pixel data SI. Selection data corresponding to (data [11]) can be stored.

  Each register RG belonging to the same row can store selection data of the same waveform portion. More specifically, each register RG belonging to the group G11 can store selection data for the first waveform section SS11 generated in the period T11. Each register RG belonging to the group G12 can store selection data for the second waveform section SS12 generated in the period T12. Further, each register RG belonging to the group G13 can store selection data for the third waveform section SS13 generated in the period T13.

  Note that the registers RG belonging to the group G14 are not used in the present embodiment. Each register RG belonging to this group G14 stores selection data for the fourth waveform section when the first drive signal COM_A is composed of four waveform sections.

  The selection data for the first waveform section SS21 generated in the period T21 is stored in each register RG belonging to the group G21, and the second waveform section SS22 generated in the period T22 is stored in each register RG belonging to the group G22. Selection data for each is stored. In the present embodiment, the registers RG belonging to the group G23 and the registers RG belonging to the group G23 are not used.

  Summarizing the above, each register RG included in the control logic 84 includes the corresponding drive signal type (first drive signal COM_A, second drive signal COM_B) and corresponding pixel data SI (data [00] to data [11]. It can be said that selection data determined by each factor of the corresponding waveform portion (the first waveform portion SS11, the second waveform portion SS22, etc.) is stored. For example, in the registers RG (Q0, G11) belonging to both the group Q0 and the group G11, the selection corresponding to the first waveform portion SS11 of the first drive signal COM_A in the pixel data SI (data [00]) without dots. Data is stored. Further, in the registers RG (Q3, G13) belonging to both the group Q3 and the group G13, the selection corresponding to the third waveform portion SS13 of the first drive signal COM_A in the large dot pixel data SI (data [11]). Data is stored. Similarly, the registers RG (Q7, G22) belonging to both the group Q7 and the group G22 correspond to the second waveform portion SS22 of the second drive signal COM_A in the large dot pixel data SI (data [11]). Selection data is stored.

  The selection data stored in these registers RG is defined by the multiplexer MX0 to multiplexer MX7 as a latch pulse included in the latch signal LAT, a change pulse included in the first change signal CH_A, and a change pulse included in the second change signal CH_B. Are selected sequentially at the timings. That is, the timing defined by these pulses corresponds to the selection data switching timing. The selection data selected by the multiplexer MX0 to the multiplexer MX7 is the first drive as the first selection data q0 to q3 for the first drive signal COM_A and the second selection data q4 to q7 for the second drive signal COM_B. The signal is output through the control signal line group CTL_A for the signal COM_A and the control signal line group CTL_B for the second drive signal COM_B.

  Here, the first selection data q0 is selection data corresponding to a tone value without dots. The first selection data q1 is selection data corresponding to the gradation value of small dots. Similarly, the first selection data q2 is selection data corresponding to the gradation value of the medium dot, and the first selection data q3 is selection data corresponding to the gradation value of the large dot. On the other hand, the second selection data q4 is selection data corresponding to the gradation value without dots, and the second selection data q5 is selection data corresponding to the gradation value of small dots. The second selection data q6 is selection data corresponding to the gradation value of medium dots, and the second selection data q7 is selection data corresponding to the gradation value of large dots.

  Note that the value of each register RG is set by serial transfer using the program data and clock SCLK of FIG. Incidentally, in this setting, the first selection data q0 and the second selection data q4 that control the same gradation are not both set to the data [1]. This is because the first drive signal generation unit 70A and the second drive signal generation unit 70B are short-circuited.

  Next, the decoder 83 will be described. The decoder 83 selects the data corresponding to the latched pixel data SI from the first selection data q0 to q3 and the second selection data q4 to q7, and outputs it as the switch control signal SW. The decoder 83 includes a first decoding unit 83A that outputs a first switch control signal SW_A and a second decoding unit 83B that outputs a second switch control signal SW_B.

  The first decoding unit 83A has four AND gates 831A to 834A and one OR gate 835A. Each of the AND gates 831A to 834A has three input terminals and one output terminal. One selection data among the first selection data q0 to q3, upper bit data of the pixel data SI, and pixel data Data of lower bits of SI is input. Each of the AND gates 831A to 834A is different in the way of inputting the upper bit data and the lower bit data of the pixel data SI.

  In other words, the first selection data q0 without dots, the inverted data of the upper bits of the pixel data SI, and the inverted data of the lower bits are input to the AND gate 831A. Therefore, when the pixel data SI is data [00], the output from the AND gate 831A has contents according to the first selection data q0 without dots. The AND gate 832A receives the first selection data q1 of small dots, the inverted data of the upper bits of the pixel data SI, and the lower bit data. Therefore, when the pixel data SI is data [01], the output from the AND gate 832A has contents according to the first selection data q1 of small dots. The AND gate 833A receives medium dot first selection data q2, upper bit data of pixel data SI, and inverted data of lower bits. Therefore, when the pixel data SI is data [10], the output from the AND gate 832A has contents according to the medium dot first selection data q2. The AND gate 834A receives the large dot first selection data q3, the upper bit data of the pixel data SI, and the lower bit data. For this reason, when the pixel data SI is data [11], the output from the AND gate 832A has contents according to the first selection data q3 of large dots.

  The OR gate 835A has four input terminals and one output terminal. The outputs from the AND gates 831A to 834A are input to each of the four input terminals. A first switch control signal SW_A is output from the OR gate 835A. That is, among the first selection data q0 to q3, the data corresponding to the latched pixel data SI is output as the first switch control signal SW_A.

  The second decoding unit 83B also includes four AND gates 831B to 834B and one OR gate 835B. The configuration of the second decoding unit 83B is the same as that of the first decoding unit 83A. That is, the second selection data q4 without dots, the inverted data of the upper bits of the pixel data SI, and the inverted data of the lower bits are input to the AND gate 831B. The AND gate 832B receives small dot second selection data q5, inverted data of upper bits of pixel data SI, and lower bit data. The AND gate 833B receives the second selection data q6 for medium dots, the upper bit data of the pixel data SI, and the inverted data of the lower bits. The AND gate 834B receives the first selection data q7 of large dots, the upper bit data of the pixel data SI, and the lower bit data. The outputs from the four AND gates 831B to 834B are input to the OR gate 835B. The OR gate 835B outputs the second selection data q4 to q7 corresponding to the latched pixel data SI as the second switch control signal SW_B.

  The first switch control signal SW_A and the second switch control signal SW_B output from the decoder 83 are input to the first switch 86A and the second switch 86B. The first switch 86A and the second switch 86B switch between an on state and an off state by changing a resistance value. For example, the resistance value is about 100Ω in the on state, and the resistance value is several tens of MΩ or more in the off state. When such first switch 86A and second switch 86B are used, switching noise hardly occurs when the states of the first switch 86A and the second switch 86B are switched. For this reason, it is possible to reliably prevent a problem that a through current flows when the drive signal COM is switched.

  The first drive signal COM_A from the drive signal generation circuit 70 is applied to the input side of the first switch 86A, and the second drive signal COM_B is applied to the input side of the second switch 86B. A piezo element 417 is electrically connected to the common output side of the first switch 86A and the second switch 86B. The first switch 86A and the second switch 86B are provided for each generated drive signal COM, and form the second drive signal COM_B and the waveform sections SS11 to SS13 constituting the first drive signal COM_A. The waveform portions SS21 and SS22 are selectively applied to the piezo element 417.

  The first switch control signal SW_A controls the operation of the first switch 86A, and the second switch control signal SW_B controls the operation of the second switch 86B. That is, the first switch control signal SW_A corresponds to the switch control signal for the first switch 86A. The second switch control signal SW_B corresponds to another switch control signal for the second switch 86B. Specifically, when the first switch control signal SW_A is data [1], the first switch 86A is turned on, and the first drive signal COM_A is applied to the piezo element 417. Further, when the first switch control signal SW_A is data [0], the first switch 86A is turned off, so that the first drive signal COM_A is not applied to the piezo element 417. Similarly, when the second switch control signal SW_B is data [1], the second switch 86B is turned on and the second drive signal COM_B is applied to the piezo element 417. When the second switch control signal SW_B is data [0], the second switch 86B is turned off, so that the second drive signal COM_B is not applied to the piezo element 417.

  The piezo element 417 behaves like a capacitor. For this reason, when the application of the drive signal COM is stopped, the piezo element 417 maintains the potential immediately before the stop. Accordingly, during the period in which the application of the drive signal COM is stopped, the piezo element 417 maintains the deformed state immediately before the application of the drive signal COM is stopped.

  In the present embodiment, a prevention circuit 85 is disposed between the decoder 83 and the first switch 86A and the second switch 86B. The prevention circuit 85 corresponds to a controller for preventing the first drive signal COM_A and the second drive signal COM_B from being simultaneously applied to one piezo element 417. That is, the prevention circuit 85 forcibly turns off the first switch 86A at the timing when the content of the first switch control signal SW_A is switched. The prevention circuit 85 forcibly turns off the second switch 86B at the timing when the content of the second switch control signal SW_B is switched. The prevention circuit 85 will be described later in detail.

<About gradation control>
Next, gradation control in the printer 1 will be described. Here, FIG. 9 is a diagram illustrating the first drive signal COM_A, the second drive signal COM_B, and necessary control signals. FIG. 10 is a diagram illustrating a waveform portion applied to the piezo element 417 when a large dot is formed, a medium dot is formed, and a small dot is formed. In this gradation control, the operations of the first switch 86A and the second switch 86B are controlled based on the first switch control signal SW_A and the second switch control signal SW_B as described above.

  First, a case where large dots are formed (pixel data SI is data [11]) will be described. In this case, the decoder 83 selects the first selection data q3 and the second selection data q7 based on the pixel data SI indicating the formation of large dots. Then, the first selection data q3 is output as the first switch control signal SW_A, and the second selection data q7 is output as the second switch control signal SW_B. In the present embodiment, the first switch control signal SW_A is set to data [110] according to the time series of T11, T12, and T13, and the second switch control signal SW_B is set to data [01] according to the time series of T21 and T22. The Accordingly, as shown in the uppermost stage of FIG. 10, the first drive signal COM_A is applied to the piezo element 417 in the periods T11 and T12, and the second drive signal COM_B is applied to the piezo element 417 in the period T22. That is, the drive signal COM applied to the piezo element 417 is switched between the period T12 and the period T22. As a result, the drive pulse PS1 included in the first waveform section SS11 of the first drive signal COM_A, the drive pulse PS2 included in the second waveform section SS12 of the first drive signal COM_A, and the second waveform section SS22 of the second drive signal COM_B. Are sequentially applied to the piezo element 417, and an amount of ink corresponding to a large dot is ejected from the nozzle Nz.

  Next, a case where medium dots are formed (pixel data SI is data [10]) will be described. In this case, the decoder 83 selects the first selection data q2 and the second selection data q6 based on the pixel data SI indicating the formation of medium dots, and outputs them as the first switch control signal SW_A and the second switch control signal SW_B. . In the present embodiment, the first switch control signal SW_A is data [001], and the second switch control signal SW_B is data [00]. As a result, as shown in the upper part of FIG. 10, the first drive signal COM_A is applied to the piezo element 417 in the period T13, and the second drive signal COM_B is not applied to the piezo element 417. Accordingly, the drive pulse PS3 included in the third waveform portion SS13 of the first drive signal COM_A is applied to the piezo element 417, and an amount of ink corresponding to the medium dot is ejected from the nozzle Nz.

  Next, a case where small dots are formed (pixel data SI is data [01]) will be described. In this case, the decoder 83 selects the first selection data q1 and the second selection data q5 based on the pixel data SI indicating the formation of small dots, and outputs them as the first switch control signal SW_A and the second switch control signal SW_B. . In the present embodiment, the first switch control signal SW_A is data [001], and the second switch control signal SW_B is data [00]. Accordingly, as shown in the lower middle part of FIG. 10, the second drive signal COM_B is applied to the piezo element 417 in the period T21, and the first drive signal COM_A is not applied to the piezo element 417. Accordingly, the drive pulse PS4 included in the first waveform portion SS21 of the second drive signal COM_B is applied to the piezo element 417, and an amount of ink corresponding to a small dot is ejected from the nozzle Nz.

  In the case of no dot formation (pixel data SI is data [00]), the decoder 83 selects the first selection data q0 and the second selection data q4 based on the pixel data SI indicating the formation of small dots, The first switch control signal SW_A and the second switch control signal SW_B are output. In the present embodiment, the first switch control signal SW_A is data [000], and the second switch control signal SW_B is data [00]. As a result, as shown in the lowermost stage of FIG. 10, neither the first drive signal COM_A nor the second drive signal COM_B is applied to the piezo element 417.

<About printing operation>
In the printer 1 having the above-described configuration, the printer-side controller 60 controls the control target units (the paper transport mechanism 20, the carriage moving mechanism 30, the head unit 40, and the drive signal generation circuit 70) according to the computer program stored in the memory 63. Control. Therefore, this computer program has a code for executing this control. Then, the printing operation on the paper S is performed by controlling the control target portion.

  Here, FIG. 11 is a flowchart for explaining the printing operation. The illustrated printing operation includes a print command receiving operation (S10), a paper feeding operation (S20), a dot forming operation (S30), a conveying operation (S40), a paper discharge determination (S50), a paper discharge process (S60), and It has a print end determination (S70). Hereinafter, each operation will be briefly described.

The print command receiving operation (S10) is an operation of receiving a print command from the computer 110. In this operation, the printer-side controller 60 receives a print command via the interface unit 61.
The paper feeding operation (S20) is an operation for moving the paper S to be printed and positioning it at a printing start position (so-called cueing position). In this operation, the printer-side controller 60 rotates the paper feed roller 21 and the transport roller 23 by driving the transport motor 22 and the like.
The dot forming operation (S30) is an operation for forming dots on the paper S. In this operation, the printer-side controller 60 drives the carriage motor 31 and outputs a control signal to the drive signal generation circuit 70 and the head 41. Thus, ink is ejected from the nozzles Nz while the head 41 is moving, and dots are formed on the paper S.
The transport operation (S40) is an operation for moving the paper S in the transport direction. In this operation, the printer-side controller 60 drives the carry motor 22 to rotate the carry roller 23. By this transport operation, dots can be formed at positions different from the dots formed by the previous dot formation operation.
The paper discharge determination (S50) is an operation for determining whether or not it is necessary to discharge the paper S to be printed. This determination is made by the printer-side controller 60 based on the presence or absence of print data, for example.
The paper discharge process (S60) is a process of discharging the paper S, and is performed on the condition that “discharge” is determined in the previous paper discharge determination. In this case, the printer-side controller 60 rotates the paper discharge roller 25 to discharge the printed paper S to the outside.
The print end determination (S70) is a determination as to whether or not to continue printing. This determination is also made by the printer-side controller 60.

=== Outline of the Embodiment ===
<Regarding the switch control signal SW>
By the way, the above description is made on the assumption of an ideal state for the purpose of explaining the configuration of the printer 1. For this reason, the first switch control signal SW_A and the second switch control signal SW_B do not simultaneously indicate an on level (for example, data [1]). However, when the printer 1 is actually operated, the first switch control signal SW_A and the second switch control signal SW_B may be simultaneously turned on in a transitional state at the time of switching. Here, FIG. 12A is a schematic diagram for explaining the voltage change of the switch control signal SW at the switching timing. FIG. 12B is a diagram schematically illustrating a state in which the first switch 86A and the second switch 86B are turned on at the same time.

  As shown in FIG. 12A, the switch control signal SW (first switch control signal SW_A, second switch control signal SW_B) includes a latch pulse of the latch signal LAT, a change pulse of the first change signal CH_A, and a second change signal CH_B. The content is updated in response to a change pulse. At the time of this update, an undesired logic level in the switching transition period may occur in the switch control signal SW. There are various causes for the occurrence of an undesired logic level, and one of the causes is the operation of the logic circuit. As described above, the decoder 83 and the control logic 84 include many gates (AND gates 831A to 834A, 831A to 834A, OR gates 835A and 835B), a register RG, and multiplexers MX0 to MX7. When these components operate, the delay time of each component is usually different. For this reason, an undesired logic level may occur before the state is finally determined.

  An undesired logic level can occur not only when the content of the switch control signal SW changes before and after the switching timing, but also when it is the same before and after the switching timing. As described above, each register RG of the control logic 84 stores selection data for each waveform section. For this reason, even if the content of the switch control signal SW is the same before and after the switching timing, the selection data that is the source is stored in different registers RG. For example, in each period T11, T12, T13 of the repetition period T, the selection data q0 is all data [0]. However, what is used in the period T11 is in the register RG (Q0, G11), what is used in the period T12 is in the register RG (Q0, G12), and what is used in the period T13 is in the register RG (Q0, G13). It is remembered. Therefore, the multiplexer MX0 needs to switch the register RG from which the selection data q0 is read in response to the change pulse of the first change signal CH_A. Due to this switching operation, an undesired logic level at the time of switching is set. It can happen.

  If an undesired logic level occurs in the switch control signal SW, the switch corresponding to the switch control signal SW may be turned on. For example, when an undesired logic level is generated in the first switch control signal SW_A, the first switch 86A is turned on. Further, when an undesired logic level is generated in the second switch control signal SW_B, the second switch 86B is turned on. Here, when one switch is turned on and the other switch is turned on, each switch 86A, 86B has a resistance value of about 100Ω as schematically shown in FIG. 12B. To fall. As a result, the first drive signal generator 70A and the second drive signal generator 70B are electrically connected through the first switch 86A and the second switch 86B. This phenomenon may occur simultaneously with other nozzles. In the worst case, the drive signal generation unit 70A and the drive signal generation unit 70B are short-circuited with a resistance value of 100Ω / number of nozzles.

  At this time, if the first drive signal COM_A and the second drive signal COM_B are different voltages, an unscheduled current I may flow due to the voltage difference. For example, in the case of pixel data SI of small dots, the timing at which the content of the first switch control signal SW_A is switched during the period T21 during which the first waveform portion SS21 of the second drive signal COM_B is applied to the piezo element 417. To come. That is, the first change pulse in the first change signal CH_A is generated at the boundary between the period T11 and the period 12. At this switching timing, as described above, there is a possibility that the first switch 86A is turned on due to an undesired logic level. When the first switch 86A is turned on, the voltage of the second drive signal COM_B (in this example, a voltage within the range of the lowest voltage to the intermediate voltage) and the voltage of the first drive signal COM_A (in this example, the intermediate voltage) An unscheduled current I (hereinafter also referred to as a through current I) flows due to the difference from the voltage. This through current I may adversely affect the drive signal generators 70A and 70B. Further, when the signals are simultaneously turned on, the waveform of the small dots may be disturbed, and proper ink ejection may not be performed.

  Therefore, in the present embodiment, in order to prevent such adverse effects, the first switch 86A for controlling the application of the first drive signal COM_A to the piezo element 417 and the application of the second drive signal COM_B to the piezo element 417 are applied. The operation of the second switch 86B to be controlled is controlled by a prevention circuit 85 as a controller.

  The prevention circuit 85 starts from the generation of the drive pulse (for example, the drive pulse PS1) in one drive signal COM (for example, the first drive signal COM_A) until the generation of the next drive pulse (for example, the drive pulse PS2) In the meantime, one switch (for example, the first switch 86A) is forcibly turned off for a predetermined period (for example, the generation period of the first change pulse of the first change signal CH_A).

  In addition, the prevention circuit 85 generates another drive pulse (for example, drive pulse PS5) from the end of generation of another drive pulse (for example, drive pulse PS4) in the other drive signal COM (for example, the second drive signal COM_B). ) Until the start of generation of the other switch (for example, the second switch 86B) forcibly for another predetermined period (for example, the generation period of the first change pulse of the second change signal CH_B). Turn off.

  By providing such a prevention circuit 85, one switch is forcibly turned off in a predetermined period, and the other switch is forcibly turned off in another predetermined period. As a result, it is possible to prevent these switches from being turned on at the same time, and to prevent a problem that the through current I flows.

=== Prevention circuit ===
<Regarding Configuration of Prevention Circuit 85>
Next, the configuration of the prevention circuit 85 will be described. Here, FIG. 13 is a diagram illustrating a configuration of the prevention circuit. FIG. 14A is a diagram for explaining the relationship between the first switch control signal SW_A and the output of the first AND gate 852. FIG. 14B is a diagram for explaining the relationship between the second switch control signal SW_B and the output of the second AND gate 853.

  The prevention circuit 85 includes a gate control signal output unit 851, a first AND gate 852, and a second AND gate 853. The gate control signal output unit 851 outputs a gate control signal GS based on the latch signal LAT, the first change signal CH_A, and the second change signal CH_B. Here, the gate control signal GS is a signal for determining whether or not to output the first switch control signal SW_A and the second switch control signal SW_B to the first switch 86A and the second switch 86B. In other words, the gate control signal GS is a signal for determining whether to enable or disable the first switch control signal SW_A and the second switch control signal SW_B.

  The gate control signal output unit 851 has a first OR gate 851a and a second OR gate 851b.

  The first OR gate 851a outputs a first gate control signal GS_A (corresponding to a first switch gate control signal) for the first switch 86A. The first OR gate 851a has two input terminals and one output terminal. The latch signal LAT is input to one of the input terminals, and the first change signal CH_A is input to the other input terminal. The first gate control signal GS_A output from the first OR gate 851a is at the H level when the latch signal LAT is at the H level (data [1] level). Further, when the first change signal CH_A is at H level, it is also at H level. In other cases, the first gate control signal GS_A is at the L level. That is, as shown in FIG. 14A, the first gate control signal GS_A is at the H level over a period in which either the latch pulse of the latch signal LAT or the change pulse of the first change signal CH_A is generated. Therefore, it can be said that the first gate control signal GS_A has a first timing pulse (corresponding to a timing pulse for the first switch control signal) based on the latch pulse and the change pulse.

  The first timing pulse defines the selection data switching periods t11, t12, and t13 (see FIG. 9) in the first drive signal COM_A. That is, it becomes H level over these periods t11, t12, and t13. Here, each waveform part SS11-SS13 which comprises 1st drive signal COM_A has the drive pulse PS, respectively. That is, the first waveform section SS11 has a drive pulse PS1, the second waveform section SS12 has a drive pulse PS2, and the third waveform section SS13 has a drive pulse PS3. Therefore, it can be said that the first timing pulse is generated over a predetermined period from the end of generation of a certain drive pulse PS to the start of generation of the next drive pulse PS.

  The second OR gate 851b outputs a second gate control signal GS_B (corresponding to another gate control signal for the second switch) for the second switch 86B. The second OR gate 851b also has two input terminals and one output terminal. The latch signal LAT is input to one of the input terminals, and the second change signal CH_B is input to the other input terminal. The second gate control signal GS_B becomes H level when one of the latch signal LAT and the second change signal CH_B is H level. That is, as shown in FIG. 14B, the second gate control signal GS_B includes a second timing pulse (another timing pulse for the second switch control signal based on the latch pulse of the latch signal LAT and the change pulse of the second change signal CH_B). It corresponds to.)

  The second timing pulse becomes H level over the selection data switching periods t21 and t22 in the second drive signal COM_B (see FIG. 9). Accordingly, the second timing pulse is generated over another predetermined period from the end of generation of a certain drive pulse PS to the start of generation of the next drive pulse PS in the second drive signal COM_B.

  The first AND gate 852 corresponds to a gate circuit in the controller. The first AND gate 852 has two input terminals and one output terminal. The first switch control signal SW_A is input to one of the input terminals, and the inverted first gate control signal GS_A is input to the other input terminal. The first AND gate 852 outputs a first switch control signal SW_A when the first gate control signal GS_A is at L level (corresponding to a predetermined level). That is, the first switch control signal SW_A becomes valid. On the other hand, when the first gate control signal GS_A is at the H level (corresponding to another predetermined level), that is, during the period in which the first timing pulse is generated, the first gate control signal GS_A is not related to the first switch control signal SW_A. The output of the 1 AND gate 852 becomes L level. As a result, the first AND gate 852 outputs a first off control signal (corresponding to an off control signal for the first switch) for turning off the first switch 86A.

  The second AND gate 853 corresponds to another gate circuit in the controller. The second AND gate 853 also has two input terminals and one output terminal. The second switch control signal SW_B is input to one of the input terminals, and the inverted second gate control signal GS_B is input to the other input terminal. The second AND gate 853 outputs a second switch control signal SW_B when the second gate control signal GS_B is at L level (corresponding to a predetermined level). That is, the second switch control signal SW_B becomes valid. On the other hand, when the second gate control signal GS_B is at the H level (corresponding to another predetermined level), that is, during the period when the second timing pulse is generated, the second gate control signal GS_B is not related to the second switch control signal SW_B. The output of the 2 AND gate 853 becomes L level. As a result, the second AND gate 853 outputs a second off control signal (corresponding to another off control signal for the second switch) for turning off the second switch 86B.

  The first switch 86A is forcibly turned off by the first off control signal. That is, it is turned off regardless of the content of the first switch control signal SW_A. Therefore, even if the first switch control signal SW_A becomes H level due to generation of an undesired logic level, it is possible to prevent the first switch 86A from being turned on by this logic level. For example, even if the first switch control signal SW_A is turned on during the period t12, the first switch 86A is turned off. Here, in the case of the pixel data SI of small dots, the second switch 86B is in the on state during the period t12, but the first switch 86A is forcibly turned off, so the first switch It is possible to prevent the 86A and the second switch 86B from being turned on at the same time, and to prevent a problem that the through current I flows. Further, the drive signal can be prevented from being distorted.

  In the present embodiment, the first AND gate 852 is controlled by the first gate control signal GS_A. The first timing pulse included in the first gate control signal GS_A is generated in synchronization with the latch pulse of the latch signal LAT and the change pulse of the first change signal CH_A. The contents of the first switch control signal SW_A are switched in response to these latch pulses and change pulses. Therefore, by controlling the first AND gate 852 with the first gate control signal GS_A, the timing at which the first switch 86A is turned off can be matched with the timing at which the first switch control signal SW_A is switched. Specifically, at the timing of the rising edge of the first timing pulse, the first switch control signal SW_A can be disabled and the first switch 86A can be turned off, and the first switch control signal SW_A is enabled at the timing of the falling edge. Can be. As a result, it is possible to reliably prevent a problem that the through current I flows. In addition, waveform distortion can be suppressed.

  The same applies to the second switch 86B. That is, the second switch 86B is forcibly turned off by the second off control signal regardless of the content of the second switch control signal SW_B. Therefore, even if the second switch control signal SW_B becomes H level due to noise, the second switch 86B can be prevented from being turned on. For example, in the period t21 or the period t22, the second switch 86B is turned off. Here, in the present embodiment, the period t21 is aligned with the period t11 in the first drive signal COM_A. The period t22 is aligned with the period t13 in the first drive signal COM_A.

  In this case, ideally, the voltage of the first drive signal COM_A and the voltage of the second drive signal COM_B should be equal to the intermediate voltage that is the start voltage of the drive pulse PS. If the intermediate voltage of the first drive signal COM_A and the intermediate voltage of the second drive signal COM_B are the same, even if the first switch 86A and the second switch 86B are simultaneously turned on, the unscheduled current I is Not flowing. However, in reality, there is a possibility that the intermediate voltage of the first drive signal COM_A and the intermediate voltage of the second drive signal COM_B may be shifted due to variations in the first drive signal generator 70A and the second drive signal generator 70B. is there. And when these intermediate voltages have shifted | deviated, the through-current I will flow according to the voltage difference. And in this embodiment, even if it is such a case, the malfunction that the through-current I flows can be prevented reliably.

  In the present embodiment, the switching timing of the second switch control signal SW_B is synchronized with the switching timing of the first switch control signal SW_A. However, even when the switching timing is asynchronous, it is the same as the case described with the first drive signal COM_A. Has the effect of.

  In the present embodiment, the prevention circuit 85 is configured by a logic circuit such as an AND gate or an OR gate. The operations of the first AND gate 852 and the second AND gate 853 are controlled by the gate control signal GS. This simplifies the configuration and is suitable for high-speed processing.

  In the present embodiment, the gate control signal output unit 851 is provided for each nozzle, but the present invention is not limited to this configuration. For example, a single gate control signal output unit 851 may be provided, and the output gate control signal GS may be shared by circuits corresponding to all nozzles.

=== Other Embodiments ===
The above-described embodiment is mainly described with respect to the printing system 100 including the printer 1, and includes disclosure of a driving signal application method, a liquid ejection system, and the like. The above-described embodiments are for facilitating understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed and improved without departing from the gist thereof, and it is needless to say that the present invention includes equivalents thereof. In particular, the embodiments described below are also included in the present invention.

<Regarding the prevention circuit 85>
The prevention circuit 85 of the first embodiment described above defines a period during which the first switch 86A and the second switch 86B are turned off using the rising edge and the falling edge of the timing pulse. For this reason, there was no freedom of setting about the period made into an OFF state. If the off-state period can be determined irrespective of the timing pulse, it is preferable to optimize the off-time. Hereinafter, a modified example configured as described above will be described. Here, FIG. 15 is a diagram for explaining a main part of a modified prevention circuit 85 ′.

  This modification is different from the first embodiment described above in that monostable multivibrators 854A and 854B are provided between the gate control signal output unit 851 and the first AND gate 852. That is, the first monostable multivibrator 854A outputs an H level signal over a predetermined period based on the timing pulse of the first timing signal. The second monostable multivibrator 854B outputs an H level signal for another predetermined period based on the timing pulse of the second timing signal.

  These monostable multivibrators 854A and 854B function as timers. That is, the first monostable multivibrator 854A functions as a first timer for the first switch 86A. The second monostable multivibrator 854B functions as a first timer for the second switch 86B. Regarding the signal output from the first monostable multivibrator 854A, the H level time ETA corresponds to a period during which the first switch 86A is turned off. Regarding the signal output from the second monostable multivibrator 854B, the H level time ETB corresponds to a period during which the second switch 86B is turned off. The period during which the first switch 86A and the second switch 86B are turned off can be adjusted, for example, by changing the capacitance of the connected capacitors 855A and 855B. Therefore, in this embodiment, the period during which the first switch 86A and the second switch 86B are turned off can be optimized. In addition, the period for turning off can be determined with high accuracy.

<About drive elements>
In the above-described embodiment, ink is ejected using the piezo element 417. However, the element for ejecting ink is not limited to the piezo element 417. For example, any element that can execute an operation for ejecting ink, such as a heating element or a magnetostrictive element, can be used.

<About the drive signal COM>
In the above-described embodiment, the printer 1 that outputs two types of drive signals COM including the first drive signal COM_A and the second drive signal COM_B has been described as an example. However, the present invention is not limited to this configuration. That is, the printer 1 that can simultaneously generate three or more types of drive signals COM may be used.

<About ink>
Since the above embodiment is an embodiment of the printer 1, liquid dye ink or pigment ink is ejected from the nozzle Nz. However, the ink ejected from the nozzles Nz is not limited to such ink as long as it is liquid.

<About other application examples>
In the above-described embodiment, the printer 1 has been described. However, the present invention is not limited to this. For example, color filter manufacturing apparatus, dyeing apparatus, fine processing apparatus, semiconductor manufacturing apparatus, surface processing apparatus, three-dimensional modeling machine, liquid vaporizer, organic EL manufacturing apparatus (particularly polymer EL manufacturing apparatus), display manufacturing apparatus, film formation The same technology as that of the present embodiment may be applied to various liquid ejection devices to which inkjet technology such as a device and a DNA chip manufacturing device is applied. These methods and manufacturing methods are also within the scope of application.

1 is a diagram illustrating a configuration of a printing system. It is a block diagram explaining the structure of a computer and a printer. FIG. 3A is a diagram illustrating the configuration of the printer. FIG. 3B is a side view illustrating the configuration of the printer. It is sectional drawing for demonstrating the structure of a head. It is a block diagram explaining the structure of a drive signal generation circuit. It is a block diagram explaining the structure of a head control part. It is explanatory drawing of a control logic. It is explanatory drawing of a decoder. It is a figure explaining a 1st drive signal, a 2nd drive signal, and a required control signal. It is a figure explaining the waveform part applied to a piezo element at the time of formation of a large dot, the formation of a medium dot, and the formation of a small dot. It is a flowchart explaining printing operation. FIG. 12A is a schematic diagram illustrating a voltage change of the switch control signal at the switching timing. FIG. 12B is a diagram schematically illustrating a state in which the first switch and the second switch are simultaneously turned on. It is a figure which shows the structure of a prevention circuit. FIG. 14A is a diagram illustrating the relationship between the first switch control signal and the output of the first AND gate. FIG. 14B is a diagram illustrating the relationship between the second switch control signal and the output of the second AND gate. It is a figure explaining the principal part in the prevention circuit of a modification.

Explanation of symbols

1 printer, 20 paper transport mechanism, 21 paper feed roller, 22 transport motor,
23 transport roller, 24 platen, 25 paper discharge roller,
30 Carriage moving mechanism, 31 Carriage motor, 32 Guide shaft,
33 Timing belt, 34 Drive pulley, 35 Drive pulley,
40 head units, 41 heads, 41A flow path unit,
411 nozzle plate, 412 storage chamber forming substrate, 412a ink storage chamber,
413 supply port forming substrate, 413a ink supply port,
41B actuator unit,
414 pressure chamber forming substrate, 414a pressure chamber,
415 diaphragm, 416 lid member, 416a supply side communication port, 417 piezo element,
42 head case, 50 detector groups, 51 linear encoder,
52 Rotary encoder, 53 Paper detector, 54 Paper width detector,
60 printer-side controller, 61 interface section,
62 CPU, 63 memory, 64 control unit,
70 drive signal generation circuit, 70A first drive signal generation unit,
71A first waveform generation circuit, 72A first current amplification circuit,
70B second drive signal generation unit, 71B second waveform generation circuit,
72B second current amplification circuit,
81A first shift register, 81B second shift register,
82A first latch circuit, 82B second latch circuit,
83 decoder, 83A first decoding unit,
831A to 834A and gate, 835A or gate,
83B 2nd decoding part, 831B-834B AND gate,
835B OR gate, 84 control logic,
85, 85 ′ prevention circuit, 851 gate control signal output unit,
851a first OR gate, 851b second OR gate,
852 first AND gate, 853 second AND gate,
854A, 854B monostable multivibrator,
855A, 855B capacitors,
86A first switch, 86B second switch,
100 printing system, 110 computer, 111 host side controller,
112 interface unit, 113 CPU, 114 memory,
120 display device, 130 input device, 131 keyboard, 132 mouse,
140 recording / reproducing apparatus, 141 flexible disk drive apparatus,
142 CD-ROM drive device,
S paper, CTR controller board, HC head controller, CR carriage,
Nz nozzle, COM_A first drive signal, COM_B second drive signal,
SI pixel data, LAT latch signal,
CH_A first change signal, CH_B second change signal,
SW switch control signal,
SW_A first switch control signal, SW_B second switch control signal,
RG register, MX multiplexer,
q0 to q3 first selection data, q4 to q7 second selection data,
CTL_A control signal line group, CTL_B control signal line group, PS drive pulse,
GS gate control signal, GS_A first gate control signal, GS_B second gate control signal

Claims (5)

(A) an element capable of executing an operation for discharging liquid;
(B) A drive signal generation unit that generates a first drive signal having a plurality of unit signals within a repetition period and a second drive signal having a plurality of unit signals different from the first drive signal within the repetition period. When,
(C) a first switch that controls application of each unit signal to the element in the first drive signal;
(D) a second switch for controlling application of each unit signal to the element in the second drive signal;
(E) a first switch control signal that causes the first switch to select a unit signal to be applied to the element among a plurality of unit signals of the first drive signal, and a plurality of unit signals of the second drive signal. A decoder that outputs a second switch control signal that causes the second switch to select a unit signal to be applied to the element;
(F) the first switch and the second switch based on a first timing pulse that defines the switching timing of the first switch control signal and a second timing pulse that defines the switching timing of the second switch control signal; Is switched within the repetition period, so that the unit signal of the first drive signal and the unit signal of the second drive signal are selectively applied to the element, and a liquid having a magnitude corresponding to the unit signal is discharged. And a controller to
Have
The controller is connected in parallel to a first monostable multivibrator, a first capacitor connected in parallel to the first monostable multivibrator, a second monostable multivibrator, and the second monostable multivibrator. A second capacitor,
The first monostable multivibrator turns off the first switch over a first period based on the first timing pulse, and the first period is determined by changing the capacitance of the first capacitor. And
The second monostable multivibrator turns off the second switch over a second period based on the second timing pulse, and the second period is determined by changing the capacitance of the second capacitor. A liquid ejection device. The liquid ejection device according to claim 1,
The controller is
Based on the first timing pulse, the first switch control signal is invalidated,
A liquid ejecting apparatus, wherein the first switch control signal is validated after the first period has elapsed since the invalidation. The liquid ejection device according to claim 1 or 2,
The controller is
Based on the second timing pulse, the second switch control signal is invalidated,
A liquid ejecting apparatus that validates the second switch control signal after the second period has elapsed since the invalidation. The liquid ejection device according to any one of claims 1 to 3,
A liquid ejection apparatus, wherein the liquid is a liquid ink for printing. (A) an element capable of executing an operation for discharging liquid;
(B) A drive signal generation unit that generates a first drive signal having a plurality of unit signals within a repetition period and a second drive signal having a plurality of unit signals different from the first drive signal within the repetition period. When,
(C) a first switch that controls application of each unit signal to the element in the first drive signal;
(D) a second switch for controlling application of each unit signal to the element in the second drive signal;
(E) a first switch control signal that causes the first switch to select a unit signal to be applied to the element among a plurality of unit signals of the first drive signal, and a plurality of unit signals of the second drive signal. A decoder that outputs a second switch control signal that causes the second switch to select a unit signal to be applied to the element;
(F) the first switch and the second switch based on a first timing pulse that defines the switching timing of the first switch control signal and a second timing pulse that defines the switching timing of the second switch control signal; Is switched within the repetition period, so that the unit signal of the first drive signal and the unit signal of the second drive signal are selectively applied to the element, and a liquid having a magnitude corresponding to the unit signal is discharged. And a controller to
Have
The controller is connected in parallel to a first monostable multivibrator, a first capacitor connected in parallel to the first monostable multivibrator, a second monostable multivibrator, and the second monostable multivibrator. A second capacitor,
The first monostable multivibrator turns off the first switch over a first period based on the first timing pulse, and the first period is determined by changing the capacitance of the first capacitor. And
The second monostable multivibrator turns off the second switch over a second period based on the second timing pulse, and the second period is determined by changing the capacitance of the second capacitor. A method for applying a drive signal in a liquid ejection device,
Turning off the first switch for the first period based on the first timing pulse and turning off the second switch for the second period based on the second timing pulse;
By switching the first switch within the repetition period after the first period and switching the second switch within the repetition period after the second period, each drive pulse in the first drive signal and the second drive are switched. Selectively applying each drive pulse in the signal to the element;
A driving signal applying method including:

Images