JP2015186438A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce inductance of a positive electrode conductor and a negative electrode conductor and increase heat dissipation performance in a semiconductor device including six semiconductor chips which constitute three pairs of upper and lower arms of a three-phase inverter, and the paired positive electrode conductor and negative electrode conductor as conductors connected to a DC power supply.SOLUTION: A semiconductor device comprises two paired power supply terminals, each pair including a positive electrode terminal (31) and a negative electrode terminal (41) which are arranged adjacent to each other in an X direction. A positive electrode conductor (30) has a positive electrode connection part (33) which electrically connects a positive electrode heat sink (32) and the positive electrode terminal and electrically connecting the positive electrode terminals with each other. A negative electrode conductor (40) has a negative electrode connection part (43) which electrically connects a negative electrode heat sink (42) and the negative electrode terminal and electrically connects the negative electrode terminals with each other. At least one of the positive electrode connection part and the negative electrode connection part forms a layered structure with the other conductor via a mold resin part (100) and a plate thickness direction of the connection part which forms the layered structure is assumed to be a thickness direction.

Description

  The present invention relates to a semiconductor device including six semiconductor chips constituting three upper and lower arms of a three-phase inverter and a positive conductor and a negative conductor as a pair of conductors connected to a DC power source.

  Conventionally, as a semiconductor device including six semiconductor chips constituting three upper and lower arms of a three-phase inverter and a positive conductor and a negative conductor as a pair of conductors connected to a DC power source, it is described in Patent Document 1. Things are known.

  In the semiconductor device described in Patent Document 1, the positive electrode conductor connects two positive terminals (positive DC terminals), the positive terminals, and the substrate on which the upper arm side semiconductor chip is mounted and the positive terminal. And a connecting part (positive electrode side plate-like conductor). On the other hand, the negative electrode conductor is a negative electrode connecting portion (negative electrode plate conductor) that connects two negative terminals (negative DC terminals), the negative terminals, and the substrate on which the lower arm side semiconductor chip is mounted and the negative terminal. And have.

  Thus, the semiconductor device has two power supply terminal pairs including a positive electrode terminal and a negative electrode terminal, and these terminals are in the first direction orthogonal to the thickness direction of the semiconductor chip, the negative electrode terminal, the positive electrode terminal, and the negative electrode terminal. The positive terminals are arranged in this order.

Japanese Patent No. 3633432

  As described above, since the semiconductor device described in Patent Document 1 has two power supply terminal pairs, the inductance of the positive electrode conductor and the negative electrode conductor can be reduced as compared with the configuration having only one power supply terminal pair. .

  Moreover, in patent document 1, the positive electrode connection part and the negative electrode connection part form the laminated structure part via the insulating sheet. Thereby, the inductance can be further reduced.

  However, the positive electrode connecting portion and the negative electrode connecting portion are arranged with the plate thickness direction as a second direction orthogonal to both the thickness direction of the semiconductor chip and the first direction. The positive electrode connecting portion and the negative electrode connecting portion are portions through which a large current flows, and the width thereof is sufficiently long with respect to the plate thickness. That is, in the thickness direction, the positive electrode connecting portion and the negative electrode connecting portion are sufficiently longer than the semiconductor chip.

  As described above, since the positive electrode connecting portion and the negative electrode connecting portion are long in the thickness direction, the six semiconductor chips are sealed by the mold resin portion, and the heat sinks are disposed on both sides of each semiconductor chip, When applying to a semiconductor device having a double-sided heat dissipation structure in which the heat dissipation surface of the heat sink is exposed from the mold resin portion, the distance from the semiconductor chip to the heat dissipation surface becomes long. Thereby, there exists a possibility that thermal resistance may increase and heat dissipation may fall.

  In view of the above problems, the present invention is a semiconductor comprising six semiconductor chips constituting the three upper and lower arms of a three-phase inverter, and a positive conductor and a negative conductor as a pair of conductors connected to a DC power source. An object of the device is to reduce the inductance of the positive electrode conductor and the negative electrode conductor and to improve heat dissipation.

  The invention disclosed herein employs the following technical means to achieve the above object. Note that the reference numerals in parentheses described in the claims and in this section indicate a corresponding relationship with specific means described in the embodiments described later as one aspect, and limit the technical scope of the invention. Not what you want.

  One of the disclosed inventions is arranged with the same thickness direction as each other, has a main electrode on both sides in the thickness direction and a control electrode on one of both sides, and constitutes three upper and lower arms of a three-phase inverter. A mold resin portion (100) having one semiconductor chip (20 to 25), one surface (100a) in the thickness direction and a back surface (100b) opposite to the one surface, and integrally sealing each semiconductor chip; A positive electrode conductor (30) and a negative electrode conductor (40) as a pair of conductors connected to a power source are electrically connected to the main electrode on the negative electrode side of each semiconductor chip on the upper arm side, and are connected to the main electrode. The first heat sink (52a, 62a, 72a) of each phase where the heat radiation surface opposite to the surface is exposed from the back surface of the mold resin portion, and the main electrode on the positive electrode side of each semiconductor chip on the lower arm side, respectively. Are electrically connected, comprising the phases of the second output heat sink radiating surface opposite to the connection surface of the main electrode is exposed from one surface of the mold resin portion (52 b, 62b, 72b), the. In the positive electrode conductor, each semiconductor chip on the upper arm side is arranged on the same surface and the main electrode on the positive electrode side of the semiconductor chip is electrically connected, and the heat radiation surface opposite to the semiconductor chip mounting surface is the mold resin portion. A positive heat sink (32) exposed from one surface and a positive electrode terminal (31) connected to the positive electrode side of the DC power supply and projecting from the side surface (100c) of the mold resin portion. In the negative electrode conductor, each semiconductor chip on the lower arm side is arranged on the same surface, and the main electrode on the negative electrode side of the semiconductor chip is electrically connected, and the heat radiation surface opposite to the semiconductor chip mounting surface is the mold resin portion. The negative electrode heat sink (42) exposed from the back surface and the negative electrode terminal (41) connected to the negative electrode side of the DC power supply and projecting from the same side surface as the positive electrode terminal are included.

  The positive electrode terminal and the negative electrode terminal are arranged adjacent to each other in a first direction orthogonal to the thickness direction to form a power supply terminal pair, and the power supply terminal pair has two. The positive electrode conductor has a positive electrode connection part (33) that electrically connects the positive electrode heat sink and the positive electrode terminal and electrically connects the positive electrode terminals to each other, and the negative electrode conductor electrically connects the negative electrode heat sink and the negative electrode terminal. It has a negative electrode connection part (43) which connects and electrically connects negative electrode terminals. Then, at least one of the positive electrode connecting portion and the negative electrode connecting portion forms a laminated structure with a mold resin portion between the other conductor, and the thickness direction is the thickness direction of the connecting portion forming the laminated structure. It is characterized by that.

  According to this, there are two power supply terminal pairs in which the positive electrode terminal and the negative electrode terminal are arranged adjacent to each other. In other words, it has two current paths from the DC power supply to the semiconductor chip. Therefore, the inductance of the positive electrode conductor and the negative electrode conductor can be reduced. Further, since at least one of the positive electrode connecting portion and the negative electrode connecting portion forms a laminated structure with the other conductor through the mold resin portion, this also reduces the inductance of the positive electrode conductor and the negative electrode conductor. it can.

  Moreover, in the laminated structure formed through the molding resin part between at least one connection part of a positive electrode conductor and a negative electrode conductor, and another conductor, the plate | board thickness direction of a connection part is made into the thickness direction. Thereby, compared with the structure by which the width direction of a connection part is made into the thickness direction, the distance from a semiconductor chip to a thermal radiation surface can be shortened. Therefore, thermal resistance can be reduced and heat dissipation can be improved.

  In another disclosed invention, two power supply terminal pairs are arranged apart from each other in the first direction, and the positive electrode heat sink and the negative electrode heat sink each have a first direction as a longitudinal direction, a thickness direction, and a first direction. Are arranged side by side in a second direction orthogonal to the two directions. In the second direction, the power supply terminal pair protrudes from the side surface of the mold resin portion, and one of the positive electrode heat sink and the negative electrode heat sink that is close to the side surface in the second direction (30) has the semiconductor chips aligned in the first direction. And the extended region (35) extended in the first direction from the central region on both ends of the central region. And as a connection part which connects the heat sink (40) on the side far from the side and the corresponding terminal, the first connection part (43a) connected to one of the two terminals across the extended region on one end side, A second connecting portion (43b) connected to the other of the two terminals across the extension region on the other end side, and between the first connecting portion and the second connecting portion and the heat sink near the side surface The laminated structure is formed respectively.

  According to this, the heat sink on the side close to the pair of power supply terminals extends in the first direction, and the first connecting portion and the second connecting portion that connect the other heat sink and the corresponding two terminals are respectively extended regions. It is arranged to straddle. According to this, a laminated structure is formed by the heat sink and the connecting portion straddling the heat sink. Therefore, in the configuration in which the semiconductor chips are arranged in two rows on the upper arm side and the lower arm side, the inductance of the positive electrode connecting portion and the negative electrode connecting portion can be reduced.

  In addition, since the first connecting portion and the second connecting portion straddle the extended region of the heat sink, the first output heat sink and the second output heat sink of each phase are connected while connecting the heat sink far from the side surface and the corresponding terminal. The heat radiating surface can be easily exposed from the mold resin portion. Thus, since it does not straddle the central region, in other words, it straddles the dead space, so that heat dissipation can be improved while reducing inductance.

  One of the other inventions disclosed is that, in the first direction, two power supply terminal pairs are arranged apart from each other, and in the second direction orthogonal to both the thickness direction and the first direction, the power supply terminal pair is molded resin. It protrudes from one side of the part. The positive heat sink and the negative heat sink are each divided into a plurality of parts in the first direction and arranged side by side, and opposed to the first output heat sink and the second output heat sink in the first direction (36, 44). And extending regions (37, 45) extending from the facing region to the power supply terminal pair side. The positive electrode connecting portion has a first positive electrode connecting portion (33c) that extends in the first direction and connects the divided positive heat sinks in the extending region, and the negative electrode connecting portion extends in the first direction. And having a first negative electrode connecting portion (43c) for connecting the divided negative heat sinks in the extending region. And the laminated structure is formed by the 1st positive electrode connection part and the 1st negative electrode connection part, It is characterized by the above-mentioned.

  According to this, each heat sink is divided into a plurality in the first direction, and extends toward the electrode electron pair side in the second direction. The divided positive heat sink is connected in the extended region by the first positive electrode connecting portion, and the negative heat sink divided in plural is connected in the extended region by the first negative electrode connecting portion. A laminated structure is formed by the first positive electrode connecting portion and the first negative electrode connecting portion. Therefore, in the configuration in which the semiconductor chips are arranged in a row, the inductance of the positive electrode connecting portion and the negative electrode connecting portion can be reduced.

  In addition, the first positive electrode connection portion connects the positive heat sinks divided into a plurality in the extension region, and the first negative electrode connection portion connects the negative heat sinks divided in a plurality in the extension region. Therefore, the heat radiating surfaces of the first output heat sink and the second output heat sink of each phase can be easily exposed from the mold resin portion while connecting each heat sink to the corresponding terminal by the connecting portion. Thus, since it connects not in an opposing area | region but in other words in a dead space, heat dissipation can be improved, reducing an inductance.

  One of the other disclosed inventions is an arrangement relationship in which the positive terminal and the negative terminal in one of the two power terminal pairs and the positive terminal and the negative terminal in the other of the power terminal pair are mirror-reversed in the first direction. It is characterized by being.

  A semiconductor device having a double-sided heat dissipation structure can perform double-sided heat dissipation by a multistage cooler. In this case, semiconductor devices are respectively arranged on both sides of the cooler. According to the present invention, the positive terminals and the negative terminals overlap each other even when the semiconductor devices arranged on both sides are in the same direction or in the opposite directions. Therefore, when a semiconductor device constitutes an inverter assembly together with a cooler, a capacitor, etc., the degree of freedom of arrangement can be improved.

1 is a circuit diagram of a semiconductor device according to a first embodiment. FIG. 2 is a perspective view illustrating a schematic configuration of the semiconductor device illustrated in FIG. 1. In FIG. 2, it is the figure which abbreviate | omitted the insulating sheet. In FIG. 3, it is the figure which abbreviate | omitted the mold resin part. In FIG. 4, it is the figure which abbreviate | omitted a part of negative electrode conductor and a part of output conductor. FIG. 3 is a perspective view showing a state in which FIG. 2 is inverted about the Y axis. In FIG. 6, it is the figure which abbreviate | omitted the insulating sheet. In FIG. 7, it is the figure which abbreviate | omitted the mold resin part. It is a perspective view which shows schematic structure of an inverter assembly. It is a figure which shows the effect which divided | segmented the electric current path | route. FIG. 5 is a perspective view showing the position of a power supply terminal pair in a semiconductor device that is in a reversal positional relationship with each other. It is the side view which looked at FIG. 11 from the power supply terminal opposite side. It is a perspective view which shows schematic structure of the semiconductor device which concerns on 2nd Embodiment. In FIG. 13, it is the figure which abbreviate | omitted the insulating sheet. In FIG. 14, it is the figure which abbreviate | omitted the mold resin part. In FIG. 15, it is the figure which abbreviate | omitted a part of negative electrode conductor and a part of output conductor. FIG. 15 is a perspective view showing a state in which FIG. 14 is inverted about the Y axis. In FIG. 17, it is the figure which abbreviate | omitted the mold resin part. It is a perspective view which shows a part of connection part of a positive electrode conductor. It is a perspective view which shows schematic structure of an inverter assembly. FIG. 5 is a perspective view showing the position of a power supply terminal pair in a semiconductor device that is in a reversal positional relationship with each other. It is the side view which looked at FIG. 21 from the power supply terminal pair side.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is provided to the part which is mutually the same or equivalent in each figure below. Further, the thickness direction of the semiconductor chip is indicated as the Z direction. Moreover, it is orthogonal to a Z direction and the extending direction of a control terminal is shown as a Y direction. A direction orthogonal to both the Y direction and the Z direction is referred to as an X direction. Further, the planar shape indicates a shape along a plane defined by the X direction and the Y direction unless otherwise specified. The X direction corresponds to the first direction described in the claims, and the Y direction corresponds to the second direction.

(First embodiment)
First, the circuit configuration of the semiconductor device 10 according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 1, the semiconductor device 10 includes upper and lower arms connected between a positive electrode (high potential side) and a negative electrode (low potential side) of a DC power supply 201 in order to drive a motor 200 as a load. Has three phases. As described above, the semiconductor device 10 is configured as a three-phase inverter, and converts DC power into three-phase AC and outputs it to the motor 200. Such a semiconductor device 10 is mounted on, for example, an electric vehicle or a hybrid vehicle. Reference numeral 202 shown in FIG. 1 is a smoothing capacitor.

  The semiconductor chip constituting each arm has a power switching element such as an IGBT or a MOSFET and an FWD element connected in antiparallel to the switching element. Note that the power system switching element and the FWD element may be formed as separate chips. In the present embodiment, the semiconductor device 10 includes six semiconductor chips 20 to 25 that employ n-channel IGBT elements as switching elements. The U-phase upper and lower arms are configured with the semiconductor chip 20 as the upper arm side and the semiconductor chip 21 as the lower arm side. Similarly, the upper and lower arms of the V phase are configured with the semiconductor chip 22 as the upper arm side and the semiconductor chip 23 as the lower arm side. The upper and lower arms of the W phase are configured with the semiconductor chip 24 as the upper arm side and the semiconductor chip 25 as the lower arm side.

  The semiconductor device 10 includes a positive conductor 30 and a negative conductor 40 as a pair of conductors (wiring portions) connected to the DC power supply 201. In addition, the semiconductor device 10 includes output conductors 50, 60, and 70 as output lines (output wirings) to the motor 200. The positive conductor 30 has a positive terminal 31 for external connection, and is connected to the positive side of the DC power supply 201 via the positive terminal 31. Further, the positive electrode conductor 30 is electrically connected to the collector electrode of the IGBT element formed on the semiconductor chips 20, 22, 24 on the upper arm side. On the other hand, the negative electrode conductor 40 has a negative electrode terminal 41 as a terminal for external connection, and is connected to the negative electrode side of the DC power supply 201 via the negative electrode terminal 41. Further, the negative electrode conductor 40 is electrically connected to the emitter electrode of the IGBT element formed in the semiconductor chips 21, 23, 25 on the lower arm side.

  The output conductor 50 is electrically connected to the emitter electrode of the IGBT element formed on the semiconductor chip 20 and the collector electrode of the IGBT element formed on the semiconductor chip 21. Then, it is connected to the U-phase line of the motor 200 via the output terminal 51 for external connection. Similarly, the output conductor 60 is electrically connected to the emitter electrode of the IGBT element formed on the semiconductor chip 22 and the collector electrode of the IGBT element formed on the semiconductor chip 23. Then, it is connected to the V-phase line of the motor 200 via the output terminal 61 for external connection. The output conductor 70 is electrically connected to the emitter electrode of the IGBT element formed on the semiconductor chip 24 and the collector electrode of the IGBT element formed on the semiconductor chip 25. Then, it is connected to the W-phase line of the motor 200 via the output terminal 71 for external connection. The collector electrodes and emitter electrodes of the semiconductor chips 20 to 25 correspond to the main electrodes described in the claims.

  Furthermore, the semiconductor device 10 includes control terminals 80 to 85 and driver ICs 90 to 95. The control terminals 80 to 85 transmit digital signals from a microcomputer (not shown) to the corresponding driver ICs 80 to 85. Further, the digital signals processed by the driver ICs 80 to 85 are output to the microcomputer or the like. The control terminal 80 is connected to the driver IC 90, and the control terminal 81 is connected to the driver IC 91. Similarly, the control terminal 82 is connected to the driver IC 92, and the control terminal 83 is connected to the driver IC 93. The control terminal 84 is connected to the driver IC 94, and the control terminal 85 is connected to the driver IC 95.

  The driver ICs 90 to 95 are formed by forming drive circuits for controlling driving of elements formed in the corresponding semiconductor chips 20 to 25 on the semiconductor chips. The driver ICs 90 to 95 generate an analog signal such as a gate drive signal based on a control signal (digital signal) input from a microcomputer (not shown) and output the analog signal to the semiconductor chips 20 to 25, for example. The driver IC 90 corresponds to the semiconductor chip 20, and the driver IC 91 corresponds to the semiconductor chip 21. Similarly, the driver IC 92 corresponds to the semiconductor chip 22, and the driver IC 93 corresponds to the semiconductor chip 23. The driver IC 94 corresponds to the semiconductor chip 24, and the driver IC 95 corresponds to the semiconductor chip 25.

  Next, the structure of the semiconductor device 10 will be described with reference to FIGS.

  As shown in FIGS. 2, 3, 6, and 7, the semiconductor device 10 includes a mold resin portion 100 that integrally seals the semiconductor chips 20 to 25. In this way, the six semiconductor chips 20 to 25 constituting the three-phase inverter are a 6 in 1 package sealed with the mold resin portion 100.

  The mold resin portion 100 is formed by, for example, a transfer mold method using an epoxy resin. The mold resin portion 100 has a substantially rectangular plane shape, and one surface 100a in the Z direction and a back surface 100b opposite to the one surface 100a are substantially flat. And from these surfaces 100a and 100b, the heat dissipation surfaces of heat sinks 32, 42, 52a, 52b, 62a, 62b, 72a and 72b described later are exposed.

  The insulating sheet 101 is affixed on the one surface 100a and the back surface 100b so as to cover the heat dissipation surface described above. The insulating sheet 101 electrically separates the semiconductor device 10 and the cooler from each other in a configuration in which coolers are disposed on both sides of the semiconductor device 10 in the Z direction and heat radiation from both sides is performed from the semiconductor device 10.

  In the mold resin part 100, the positive electrode conductor 30 and the negative electrode conductor 40 described above protrude from the side surface 100c connecting the one surface 100a and the back surface 100b, and the positive electrode terminal 31 and the negative electrode terminal 41 are disposed on the side surface 100c side. In the present embodiment, the positive terminal 31 has two positive terminals 31 a and 31 b, and the negative terminal 41 has two negative terminals 41 a and 41 b. In the X direction, the positive electrode terminal 31a and the negative electrode terminal 41a are arranged adjacent to each other in a pair, and the positive electrode terminal 31b and the negative electrode terminal 41b are arranged adjacent to each other in a pair. That is, it has two power supply terminal pairs.

  From the side surface 100c, in addition to the positive electrode terminal 31 and the negative electrode terminal 41 described above, control terminals 80, 82, 84 corresponding to the semiconductor chips 20, 22, 24 on the upper arm side also protrude. These control terminals 80, 82, and 84 are each extended in the Y direction and arranged side by side in the X direction.

  Specifically, in the X direction, the negative terminal 41a, the positive terminal 31a, the control terminal 80, the control terminal 82, the control terminal 84, the positive terminal 31b, and the negative terminal 41b are arranged in this order. That is, the control terminals 80, 82, 84 are arranged between the two power supply terminal pairs. In the X direction, the positive electrode terminal 31a and the negative electrode terminal 41a forming one of the two power supply terminal pairs and the positive electrode terminal 31b and the negative electrode terminal 41b forming the other of the power supply terminal pair are in a mirror-inverted arrangement relationship. . In other words, when the semiconductor device 10 is folded around the center in the X-axis direction, the positive electrode terminals 31a and 31b and the negative electrode terminals 41 and 41b are in a positional relationship.

  On the other hand, the output conductors 50, 60, 70 protrude from the side surface 100d opposite to the side surface 100c, and the output terminals 51, 61, 71 are disposed on the side surface 100d side. Further, control terminals 81, 83, 85 corresponding to the semiconductor chips 21, 23, 25 on the lower arm side also protrude from the side surface 100d. These control terminals 81, 83, and 85 are each extended in the Y direction.

  In the present embodiment, in the X direction, the control terminal 81, the output conductor 50 (output terminal 51), the control terminal 83, the output conductor 60 (output terminal 61), the control terminal 85, and the output conductor 70 (output terminal 71) are arranged in this order. Is arranged in.

  The positive conductor 30 includes a heat sink 32 and a connecting portion 33 in addition to the positive terminal 31 described above. The negative conductor 40 also includes a heat sink 42 and a connecting portion 43 in addition to the negative terminal 41 described above. The output conductors 50, 60, 70 also include heat sinks 52a, 52b, 62a, 62b, 72a, 72b and connecting portions 53, 63, 73 in addition to the output terminals 51, 61, 71 described above. . The heat sink 32 corresponds to the positive heat sink described in the claims, and the heat sink 42 corresponds to the negative heat sink. The connecting portion 33 corresponds to a positive electrode connecting portion, and the connecting portion 43 corresponds to a negative electrode connecting portion. The heat sinks 52a, 62a, 72a correspond to the first output heat sink, and the heat sinks 52b, 62b, 72b correspond to the second output heat sink.

  Each of the heat sinks 32, 42, 52a, 52b, 62a, 62b, 72a, 72b performs an electrical relay function between the corresponding terminals 31, 41, 51, 61, 71 and the semiconductor chips 20 to 25, and the semiconductor chip. 20 to 25 serve to radiate the generated heat.

  As shown in FIGS. 4 and 5, the heat sink 32 is formed integrally with the positive electrode terminal 31 via the connecting portion 33. In the present embodiment, the connecting portion 33 includes a connecting portion 33 a that connects the positive electrode terminal 31 a and the heat sink 32, and a connecting portion 33 b that connects the positive electrode terminal 31 b and the heat sink 32.

  As shown in FIG. 7, in the Z direction, one surface of the heat sink 32 is exposed from the one surface 100 a of the mold resin portion 100 to become a heat radiating surface. This heat radiating surface is substantially flush with one surface 100a. On the other hand, the semiconductor chips 20, 22, 24 on the upper arm side are arranged on the surface opposite to the heat radiating surface with the collector electrode formation surface facing each other, and each collector electrode is soldered to the heat sink 32. The heat sink 32 has a planar rectangular shape whose longitudinal direction is the X direction, and the semiconductor chips 20, 22, and 24 are arranged side by side in the X direction.

  Further, as shown in FIG. 5, the heat sink 32 includes a central region 34 (a region surrounded by a broken line in the figure) that is the mounting region of the semiconductor chips 20, 22, 24, and both ends from the central region 34 in the X direction. And an extended region 35 that is extended to each side. Thus, in the present embodiment, the heat sink 32 extends outward from the central region 34.

  The connecting portions 33a and 33b are both extended in the Y direction, one end is connected to the heat sink 32, and the other end is connected to the corresponding positive terminals 31a and 31b. The width (length in the X direction) of the connecting portions 33a and 33b is sufficiently longer than the plate thickness (length in the Z direction). Similarly to the positive terminals 31a and 31b, the connecting portions 33a and 33b have an arrangement relationship in which mirrors are inverted in the X direction. In the present embodiment, the connecting portions 33 a and 33 b are connected to the heat sink 32 in the vicinity of the boundary between the central region 34 and the extended region 35. Further, a part of each of the connecting portions 33 a and 33 b protrudes from the side surface 100 c of the mold resin portion 100.

  As shown in FIG. 7, from one surface 100a of the mold resin portion 100, one surface of the heat sinks 52b, 62b, 72b is exposed in addition to the heat sink 32 described above. This heat radiating surface is substantially flush with one surface 100a. As shown in FIGS. 5 and 8, the heat sinks 52b, 62b, and 72b are integrally formed with the output terminals 51, 61, and 71 through corresponding connecting portions 53, 63, and 73, respectively. The heat sinks 52b, 62b, 72b have substantially the same thickness as the heat sink 32.

  On the surface opposite to the heat dissipation surface of the heat sinks 52b, 62b, 72b, the semiconductor chips 21, 23, 25 on the lower arm side are arranged with the collector electrode forming surfaces facing each other, and the corresponding heat sinks 52b, 62b, 72b are arranged on the corresponding heat sinks 52b, 62b, 72b. The collector electrode is soldered. In the X direction, the heat sink 52b, the heat sink 62b, and the heat sink 72b are arranged in this order, and the semiconductor chip 21 is arranged on the heat sink 52b. The semiconductor chip 23 is disposed on the heat sink 62b, and the semiconductor chip 25 is disposed on the heat sink 72b. That is, the semiconductor chips 21, 23, and 25 are arranged side by side in the X direction. The heat sinks 52b, 62b, 72b are arranged side by side with respect to the heat sink 32 in the Y direction.

  The connecting portions 53, 63, 73 are all extended in the Y direction. The connecting portion 53 has one end connected to the heat sink 52 b and the other end connected to the output terminal 51. Similarly, the connecting portion 63 has one end connected to the heat sink 62 b and the other end connected to the output terminal 61. One end of the connecting portion 73 is connected to the heat sink 72 b and the other end is connected to the output terminal 71. And the connection structure of the output terminals 51, 61, 71, the heat sinks 52b, 62b, 72b, and the connecting portions 53, 63, 73 has a substantially plane L shape as shown in FIG. Further, some of the connecting portions 53, 63, 73 protrude from the side surface 100 d of the mold resin portion 100.

  On the other hand, on the surface opposite to the heat sinks 52b, 62b, 72b in the semiconductor chips 21, 23, 25, a heat sink 42 is arranged as shown in FIG. The heat sink 42 is formed integrally with the negative electrode terminal 41 via the connecting portion 43. In the present embodiment, the connecting portion 43 includes a connecting portion 43 a that connects the negative electrode terminal 41 a and the heat sink 42, and a connecting portion 43 b that connects the negative electrode terminal 41 b and the heat sink 42. This connection part 43a is equivalent to the 1st connection part as described in a claim, and the connection part 43b is equivalent to a 2nd connection part.

  As shown in FIG. 3, in the Z direction, one surface of the heat sink 42 is exposed from the back surface 100 b of the mold resin portion 100 and serves as a heat dissipation surface. This heat radiating surface is substantially flush with one surface 100b. On the other hand, the surface opposite to the heat radiating surface is disposed opposite to the emitter electrode forming surface of the semiconductor chip 20, 22, 24 on the upper arm side, and each emitter electrode is electrically connected to the heat sink 42. In the present embodiment, terminals (metal blocks) (not shown) are individually interposed in the opposing regions, the heat sink 42 is soldered to one end of the terminal, and the emitter electrode is soldered to the other end of the terminal.

  The heat sink 42 also has a planar rectangular shape with the X direction as the longitudinal direction, and its overall length is substantially the same as that of the heat sink 32.

  Both of the connecting portions 43a and 43b extend in the Y direction, one end is connected to the heat sink 42, and the other end is connected to the corresponding negative terminals 41a and 41b. The width (length in the X direction) of the connecting portions 43a and 43b is sufficiently longer than the plate thickness (length in the Z direction). Similarly to the negative terminals 41a and 41b, the connecting portions 43a and 43b have an arrangement relationship that is mirror-reversed in the X direction. In the present embodiment, the connecting portions 43 a and 43 b are disposed so as to straddle the extended region 35 of the heat sink 32.

  Specifically, in the X direction, the connecting portion 43a is arranged on the opposite side to the control terminal 80 with respect to the connecting portion 33a, and is disposed so as to straddle the extended region 35 on the semiconductor chip 20 side in the heat sink 32. When the back surface 100b side is upward with respect to the one surface 100a, the connecting portion 43a is disposed above the extending region 35 of the heat sink 32 with the plate thickness direction as the Z direction, and the connecting portion 43a and the extending region 35 are connected to each other. A mold resin portion 100 is interposed therebetween. Similarly, in the X direction, the connecting portion 43b is arranged on the opposite side to the control terminal 84 with respect to the connecting portion 33b, and is disposed so as to straddle the extended region 35 on the semiconductor chip 24 side in the heat sink 32. The connecting portion 43b is also disposed above the extending region 35 of the heat sink 32 with the plate thickness direction as the Z direction, and the mold resin portion 100 is interposed between the connecting portion 43b and the extending region 35.

  As described above, in the semiconductor device 10 according to the present embodiment, the heat sink 32 of the positive electrode conductor 30 and the connection portion 43 (43a, 43b) of the negative electrode conductor 40 form a laminated structure including the mold resin portion 100 interposed therebetween. ing.

  In this embodiment, as shown in FIGS. 4 and 5, the connecting portions 43a and 43b are divided into a portion integrated with the terminal 41 and a portion integrated with the heat sink 42, both of which are soldered. It is attached.

  On the other hand, as shown in FIG. 4, heat sinks 52a, 62a, and 72a are disposed on the surface opposite to the heat sink 32 of the semiconductor chips 20, 22, and 24 on the upper arm side. The heat sink 52a is disposed opposite to the emitter electrode of the semiconductor chip 20, and is electrically connected to the emitter electrode. The heat sink 62a is disposed opposite to the emitter electrode of the semiconductor chip 22 and is electrically connected to the emitter electrode. The heat sink 72a is disposed to face the emitter electrode of the semiconductor chip 24 and is electrically connected to the emitter electrode. In this embodiment. Like the heat sink 42, it is connected via a terminal. For example, one end of the terminal is soldered to the emitter electrode of the semiconductor chip 20, and the other end is soldered to the heat sink 52a.

  Each heat sink 52a, 62a, 72a is electrically connected to a corresponding phase heat sink 52b, 62b, 72b. For example, a protrusion (not shown) is provided on each heat sink 52a, 62a, 72a, and this protrusion is soldered to 52b, 62b, 72b. The heat sinks 52a, 62a, 72a have substantially the same thickness as the heat sink 42 described above, and the surface opposite to the semiconductor chips 20, 22, 24 is from the back surface 100b of the mold resin portion 100 as shown in FIG. It is an exposed heat dissipation surface.

  Each of the control terminals 80 to 85 has a plurality of terminals, and an island 86 is connected to a part of them as shown in FIG. As shown in FIG. 4, driver ICs 90 to 95 are mounted on each island 86. The driver ICs 90 to 95 are electrically connected to the control electrodes of the corresponding semiconductor chips 20 to 25 through bonding wires (not shown). Moreover, it is electrically connected to the corresponding control terminals 80 to 85 via bonding wires (not shown).

  Next, an inverter assembly to which the above-described semiconductor device 10 is applied will be described with reference to FIG.

  As shown in FIG. 9, the inverter assembly 110 includes a multi-stage cooler 111, a large capacitor 112, and a bus bar 113 in addition to the semiconductor device 10 described above. Then, in a state where the plurality of semiconductor devices 10 are arranged in each stage of the multistage cooler 111, each cooler of the multistage cooler 111 is pressed by the pressing slope 114, and the semiconductor device 10 is sandwiched between the coolers.

  In addition, the bus bar 113 electrically connects the positive terminal 31 and the negative terminal 41 of each semiconductor device 10 to the corresponding terminal portion 112 a of the large capacitor 112. In the present embodiment, in order to improve the assembly property, the bus bar 113 is a structure in which the positive electrode bus bar 113a connecting the positive electrode terminal 31 and the negative electrode bus bar 113b connecting the negative electrode terminal 41 are integrated via the insulating member 113c. have.

  In the example shown in FIG. 9, the inverter assembly 110 also includes a circuit block 115 and a boost reactor 116, and the circuit block 115 and the boost reactor 116 are sandwiched by the multistage cooler 111 together with the plurality of semiconductor devices 10. To be cooled.

  Next, the effect of the semiconductor device 10 will be described.

  As described above, the semiconductor device 10 has two power supply terminal pairs in which the positive terminal 31 (31a, 31b) and the negative terminal 41 (41a, 41b) are arranged adjacent to each other. In other words, there are two current paths from the current supply sources of the DC power supply 201 and the capacitor 202 to the semiconductor chips 20 to 25.

FIG. 10 is a diagram for explaining the inductance reduction by having two current paths. The voltage is V, the current flowing through the first current path is I ₁ , the inductance is L ₁ , the current flowing through the second current path is I ₂ , the inductance is L ₂ , the combined current is I, and the combined inductance is L Then, it can be shown as the following formula.

Further, since I = I1 + I2, the relationship between the inductances can be expressed by the following equation from Equations 1 to 3.

  As shown in Formula 4, the inductance of the positive electrode conductor 30 and the negative electrode conductor 40 can be reduced by dividing the current path (energization current) from the current supply source into two parts.

  Further, the connecting portion 43 (43 a, 43 b) of the negative electrode conductor 40 forms a laminated structure with the heat sink 32 of the positive electrode conductor 30 through the mold resin portion 100. In this way, since the positive electrode conductor 30 and the negative electrode conductor 40 whose currents flow in opposite directions are run side by side, the inductance can also be reduced.

  Moreover, in the positive electrode conductor 30 and the negative electrode conductor 40, the terminals 31 and 41 are also arranged in parallel, and the connecting portions 33 and 43 are also arranged in parallel. These parallel running arrangements are made not in the Z direction, which is the thickness direction, but in the X direction. This can also reduce the inductance.

  Further, a current path from the positive electrode terminal 31 to the negative electrode terminal 41 is formed by solder bonding without using a bonding wire. Thus, since the bonding wire is not used in the current path through which a large current flows, the inductance can be reduced also by this. Further, in the Z direction, the heat sink 32 and the heat sinks 52a, 62a, and 72a are arranged to face each other, and the heat sinks 52b, 62b, and 72b and the heat sink 42 are arranged to face each other. This can also reduce the inductance.

  Furthermore, the plate thickness direction of the connecting portion 43 (43a, 43b) having the above-described laminated structure is the Z direction. In the Z direction, the connecting portion 43 (43a, 43b) and the heat sink 32 are connected to the mold resin portion 100. It is laminated through. That is, the positive electrode conductor 30 and the negative electrode conductor 40 are run in parallel in the Z direction. Therefore, the distance from the semiconductor chips 20 to 25 to the heat dissipation surface can be shortened as compared with the configuration in which the width direction of the connecting portion is the Z direction. Thereby, thermal resistance can be made small and heat dissipation can be improved.

  As described above, according to the semiconductor device 10 of the present embodiment, the inductance of the positive electrode conductor 30 and the negative electrode conductor 40 can be reduced and the heat dissipation can be improved.

  In addition, in the present embodiment, the heat sink 32 of the positive conductor 30 positioned on the power supply terminal pair side has a central region 34 that is a mounting region of the semiconductor chips 20, 22, 24, and both ends from the central region 34 in the X direction. And an extended region 35 that extends. And the connection parts 43a and 43b which connect the heat sink 42 of the negative electrode conductor 40 and the two negative electrode terminals 41 (41, 41b) are arrange | positioned so that the extension area | region 35 may be straddled, respectively. Therefore, the heat sinks 52a, 52b, 62a, 62b of the output conductors 50, 60, 70 are connected to the corresponding negative electrode terminals 41 (41a, 41b) connected to the heat sink 42 far from the side surface 100c on which the power supply terminal pair is disposed. , 72a, 72b can be easily exposed from the mold resin part 100. Thus, since it does not straddle the center region 34, in other words, it straddles a dead space, heat dissipation can be improved while reducing inductance.

  In the present embodiment, in the X direction, the positive terminal 31a and the negative terminal 41a forming one of the two power terminal pairs and the positive terminal 31b and the negative terminal 41b forming the other of the power terminal pair are mirror-inverted. It has become a relationship. In other words, when the semiconductor device 10 is folded around the center in the X-axis direction, the positive electrode terminals 31a and 31b and the negative electrode terminals 41 and 41b are in a positional relationship. Therefore, in the two semiconductor devices 10 adjacent to each other through the above-described cooler, the positional relationship in which the other is reversed 180 degrees around the Y axis (reversed positional relationship) is also shown in FIGS. As shown, the positive electrode terminal 31 b of one semiconductor device 10 overlaps the positive electrode terminal 31 b of the other semiconductor device 10. Further, the negative electrode terminal 41 b of one semiconductor device 10 overlaps the negative electrode terminal 41 b of the other semiconductor device 10. Therefore, when the double-sided heat dissipation structure using the multi-stage cooler 111 is employed, both the positional relationship in the same direction and the reversed positional relationship can be employed. Thereby, when the semiconductor device 10 constitutes the inverter assembly 110 together with the multi-stage cooler 111, the capacitor 112, and the like, the degree of freedom of arrangement of the semiconductor device 10 (degree of freedom of wiring) can be improved.

  In the present embodiment, as described above, since the heat sink 42 is connected to the negative electrode terminal 41 across the extended region 35 of the heat sink 32, two power terminal pairs are provided on the side surface 100 c of the mold resin portion 100. The control terminals 80, 82, 84 can be projected from the position between the two. Therefore, the physique of the semiconductor device 10 can be reduced in the Z direction as compared with the configuration in which the control terminals 80, 82, and 84 are protruded on the one surface 100 a side or the back surface 100 b side of the mold resin portion 100. Moreover, the double-sided heat dissipation structure by the multistage cooler 111 described above is facilitated.

  In the present embodiment, as an example, a laminated structure in which the plate thickness direction is the Z direction is formed by the heat sink 32 of the positive electrode conductor 30 and the connecting portion 43 (43a, 43b) of the negative electrode conductor 40 is shown. It was. However, when the heat sink 42 of the negative electrode conductor 40 is close to the pair of power supply terminals in the Y direction, the heat sink 42 extends in the X direction from the central region on which the semiconductor chips 21, 23, 25 are mounted. A stacked structure may be formed by extending the extended region over the connecting portion 43 (43a, 43b) of the positive electrode conductor 30. Further, the output terminals 51, 61, 71 may be connected to the heat sinks 52a, 62a, 72a on the upper arm side by connecting portions 53, 63, 73.

(Second Embodiment)
In the present embodiment, description of parts common to the semiconductor device 10 shown in the first embodiment is omitted.

  The circuit configuration of the semiconductor device 10 according to the present embodiment is the same as that of the first embodiment (see FIG. 1). The difference is that the semiconductor chips 20 to 25 are arranged in a row in the X direction, and the stacked structure described above is different from that of the first embodiment.

  First, the structure of the semiconductor device 10 will be described with reference to FIGS.

  As shown in FIGS. 13, 14, and 17, in this embodiment, the positive electrode conductor 30, the negative electrode conductor 40, and the output conductors 50, 60, 70 protrude from the side surface 100 c of the mold resin portion 100. Two power supply terminal pairs (positive terminal 31 and negative terminal 41) and output terminals 51, 61, 71 are arranged on the side surface 100c side. That is, all the main terminals (power terminals) are arranged on the side surface 100c side. On the other hand, the control terminals 80 to 85 protrude from the side surface 100d.

  As shown in FIG. 16, the six semiconductor chips 20 to 25 are arranged in a row in the X direction. Specifically, from one end, the U-phase upper arm semiconductor chip 20, the U-phase lower arm semiconductor chip 21, the V-phase lower arm semiconductor chip 23, the V-phase upper arm semiconductor chip 22, and the W-phase lower arm semiconductor chip. 25, the semiconductor chips 24 of the W-phase upper arm are arranged in this order. For this reason, the mold resin portion 100 has a substantially rectangular shape with the X direction as the longitudinal direction.

  The positive electrode conductor 30 has the positive electrode terminal 31, the heat sink 32, and the connection part 33 similarly to 1st Embodiment. In this embodiment, as shown in FIGS. 16 to 18, the positive terminal 31 has two positive terminals 31 a and 31 b. These positive terminals 31a and 31b have a mirror-inverted arrangement relationship in the X direction.

  The positive conductor 30 has heat sinks 32 a, 32 b, and 32 c as the heat sink 32. That is, in this embodiment, the heat sink 32 is divided into three in the X direction. The heat sink 32a corresponds to the semiconductor chip 20 of the U-phase upper arm, and the heat sink 32b corresponds to the semiconductor chip 22 of the V-phase upper arm. The heat sink 32c corresponds to the semiconductor chip 24 of the W-phase upper arm. As shown in FIGS. 16 and 18, each of the heat sinks 32 a, 32 b, and 32 c includes a facing region 36 (a region surrounded by a broken line in the figure) facing the heat sinks 52 b, 62 b, and 72 b in the X direction, and a facing region 36. And an extension region 37 extending in the Y direction to the power supply terminal pair side.

  The positive electrode conductor 30 has connecting portions 33 a, 33 b, and 33 c as connecting portions 33. This connection part 33c is equivalent to the 1st positive electrode connection part as described in a claim. As shown in FIGS. 16 to 19, the connecting portion 33 c extends in the X direction with the Z direction as the plate thickness direction, and connects the heat sinks 32 a, 32 b, 32 c in the extending region 37. That is, the connecting portion 33c is disposed at a position that does not overlap the heat sinks 52a, 52b, 62a, 62b, 72a, 72c in the Y direction. The width (the length in the Y direction) of the connecting portion 33c is sufficiently longer than the plate thickness (the length in the Z direction). The connecting portions 33a and 33b extend in the Y direction. The connecting portion 33a connects the positive terminal 31a and the connecting portion 33c, and the connecting portion 33b connects the positive terminal 31b and the connecting portion 33c.

  The negative electrode conductor 40 includes a negative electrode terminal 41, a heat sink 42, and a connecting portion 43, as in the first embodiment. In the present embodiment, as shown in FIGS. 14 and 15, the negative electrode terminal 41 includes two negative electrode terminals 41 a and 41 b. These negative terminals 41a and 41b are also arranged in a mirror-inverted relationship in the X direction. The negative electrode terminal 41a is arranged next to the positive electrode terminal 31a to form a power supply terminal pair, and the negative electrode terminal 41b is arranged next to the positive electrode terminal 31b to form a power supply terminal pair. The two power supply terminal pairs are also arranged in a mirror-inverted relationship in the X direction.

  The negative electrode conductor 40 has heat sinks 42 a and 42 b as the heat sink 42. That is, in the present embodiment, the heat sink 42 is divided into two in the X direction. The heat sink 42a corresponds to the semiconductor chip 21 of the U-phase lower arm and the semiconductor chip 23 of the V-phase lower arm, and the heat sink 42b corresponds to the semiconductor chip 25 of the W-phase lower arm. As shown in FIG. 15, each of the heat sinks 42 a and 42 b is also similar to the heat sinks 32 a, 32 b, and 32 c, and an opposing region 44 (region surrounded by a broken line in the figure) that faces the heat sinks 52 a, 62 a, 72 a in the X direction And an extension region 45 extending in the Y direction from the facing region 44 to the power supply terminal pair side.

  The negative electrode conductor 40 has connecting portions 43 a, 43 b, and 43 c as connecting portions 43. This connection part 43c is equivalent to the 1st negative electrode connection part as described in a claim. The connecting portion 43 c extends in the X direction with the Z direction as the plate thickness direction, and connects the heat sinks 42 a and 42 b in the extending region 37. That is, the connection part 43c is arrange | positioned in the Y direction at the position which does not overlap with the heat sinks 52a, 52b, 62a, 62b, 72a, 72c. The width (the length in the Y direction) of the connecting portion 43c is sufficiently longer than the plate thickness (the length in the Z direction). The connecting portions 43a and 43b extend in the Y direction. The connecting portion 43a connects the negative electrode terminal 41a and the heat sink 42a, and the connecting portion 43b connects the negative electrode terminal 41b and the heat sink 42b.

  And as shown in FIG.15 and FIG.16, the mold resin part 100 is interposed between the connection part 43c and the connection part 33c, and between the extension part 37 of the connection part 43c and the heat sink 32b, A laminated structure is formed in which the thickness direction is the Z direction. Further, a mold resin portion 100 is interposed between the connecting portion 33c and the heat sink 42a, and between the connecting portion 33c and the heat sink 42b, so that a laminated structure in which the plate thickness direction is the Z direction is formed.

  Similarly to the first embodiment, the output conductors 50, 60, 70 also have output terminals 51, 61, 71, heat sinks 52, 62, 72, and connecting portions 53, 63, 73. Further, as the heat sinks 52, 62, 72, there are heat sinks 52a, 62a, 72a on the upper arm side and heat sinks 52b, 62b, 72b on the lower arm side. Each connection part 53,63,73 is extended in the Y direction.

  The output terminal 51 is connected to the heat sink 52 a on the upper arm side via the connecting portion 53. The connection part 53 is divided | segmented into the output terminal 51 side and the heat sink 52a side, and is integrated by soldering. The output terminal 61 is integrally connected to the heat sink 62 b on the lower arm side via the connecting portion 63. The output terminal 71 is integrally connected to the heat sink 72b on the lower arm side via a connecting portion 73. The output terminal 51 may be connected to at least one of the heat sinks 52a and 52b by the connecting portion 53. Similarly, the output terminal 61 may be connected to at least one of the heat sinks 62 a and 62 b by the connecting portion 63. The output terminal 71 may be connected to at least one of the heat sinks 72 a and 72 b by the connecting portion 73.

  In the semiconductor device 10 configured as described above, the U-phase output terminal 51, the negative electrode terminal 41 a, the positive electrode terminal 31 a, the V-phase output terminal 61, the positive electrode terminal 31 b, the negative electrode terminal 41 b, W from one end side in the X direction. The phase output terminals 71 are arranged in this order. That is, the connection part 63 protrudes from the position between two power supply terminal pairs arrange | positioned away in the side surface 100c of the mold resin part 100 from which a power supply terminal pair protrudes. Further, the connecting portion 63 protrudes in the Z direction from a position between the positive electrode conductor 30 and the negative electrode conductor 40, specifically, a position between the connecting portion 33c and the extended region 37 of the heat sink 42a.

  Next, an inverter assembly to which the above-described semiconductor device 10 is applied will be described with reference to FIG.

  In addition to the semiconductor device 10 described above, the inverter assembly 110 illustrated in FIG. 20 also includes a multistage cooler 111, a large capacitor 112, and a bus bar 113. And the semiconductor device 10 is pinched | interposed with a cooler in the state which has arrange | positioned the several semiconductor device 10 in each step | level of the multistage cooler 111.

  In addition, the bus bar 113 electrically connects the positive terminal 31 and the negative terminal 41 of each semiconductor device 10 to the corresponding terminal portion 112 a of the large capacitor 112. In the example shown in FIG. 20, the inverter assembly 110 also includes a circuit block 115, and the circuit block 115 is sandwiched and cooled by the multistage cooler 111 together with the plurality of semiconductor devices 10. Yes.

  Next, the effect of the semiconductor device 10 will be described.

  According to the semiconductor device 10 according to the present embodiment, the same effects as those of the semiconductor device 10 according to the first embodiment can be obtained. That is, the inductance of the positive electrode conductor 30 and the negative electrode conductor 40 can be reduced by dividing the current path (energization current) from the current supply source into two.

  Further, the connecting portion 33 of the positive electrode conductor 30 forms a laminated structure with the mold resin portion 100 interposed between the heat sinks 42 a and 42 b and the connecting portion 43 c of the negative electrode conductor 40. In addition, the connecting portion 43c of the negative electrode conductor 40 forms a laminated structure with the extended region 37 of the heat sink 32b. In this way, since the positive electrode conductor 30 and the negative electrode conductor 40 whose currents flow in opposite directions are run side by side, the inductance can also be reduced.

  The terminals 31 and 41 are also arranged in parallel, and the connecting portions 33a and 43a and the connecting portions 33b and 43b are also arranged in parallel. These parallel running arrangements are made not in the Z direction, which is the thickness direction, but in the X direction. This can also reduce the inductance.

  Moreover, since the current path from the positive electrode terminal 31 to the negative electrode terminal 41 is formed by solder bonding without using a bonding wire, the inductance can be reduced also by this. Further, in the Z direction, the heat sinks 32a, 32b, 32c and the heat sinks 52a, 62a, 72a are arranged to face each other, and the heat sinks 52b, 62b, 72b and the heat sinks 42a, 42b are arranged to face each other. This can also reduce the inductance.

  Further, the thickness direction of the connecting portions 33c and 43c forming the above-described laminated structure is the Z direction. That is, the positive electrode conductor 30 and the negative electrode conductor 40 are run in parallel in the Z direction. Therefore, the distance from the semiconductor chips 20 to 25 to the heat dissipation surface can be shortened as compared with the configuration in which the width direction of the connecting portion is the Z direction. Thereby, thermal resistance can be made small and heat dissipation can be improved.

  As described above, also with the semiconductor device 10 of the present embodiment, the inductance of the positive conductor 30 and the negative conductor 40 can be reduced and the heat dissipation can be improved.

  In addition, in the present embodiment, the heat sink 32 of the positive conductor 30 and the heat sink 42 of the negative conductor 40 are each divided into a plurality in the X direction. Further, the plurality of divided heat sinks 32 (32a to 32c) have an extending region 37 extending from the facing region 36 toward the power supply terminal pair side in the Y direction. Similarly, the plurality of divided heat sinks 42 (42a, 42b) have an extension region 45 extending from the facing region 44 toward the power supply terminal pair side in the Y direction. Further, the positive electrode conductor 30 has a connection portion 33 c that connects the plurality of heat sinks 32 a to 32 c at the extended region 37 as the connection portion 33, and the negative electrode conductor 40 has the plurality of heat sinks 42 a and 42 b as the connection portion 43. It has the connection part 43c connected by the extension area | region 45. As shown in FIG. And the laminated structure which makes a plate | board thickness direction a Z direction is formed of the connection parts 33c and 43c.

  In this manner, the extension regions 37 and 45 are provided in the heat sinks 32 and 42, that is, they are connected in a dead space, instead of being connected in the opposing regions 36 and 44. Therefore, the heat radiation surfaces of the heat sinks 52a, 52b, 62a, 62b, 72a, 72b of the respective phases can be easily exposed from the mold resin portion 100. That is, heat dissipation can be improved while reducing inductance.

  Also in the present embodiment, the positive electrode terminal 31a and the negative electrode terminal 41a forming one of the two power supply terminal pairs and the positive electrode terminal 31b and the negative electrode terminal 41b forming the other of the power supply terminal pair are mirror-inverted in the X direction. It has become a relationship. Therefore, in the two semiconductor devices 10 that are adjacent to each other through the above-described cooler, the positional relationship in which the other is reversed 180 degrees around the Y axis (the positional relationship reversed to each other) is also shown in FIGS. As shown, the positive electrode terminal 31 b of one semiconductor device 10 overlaps the positive electrode terminal 31 b of the other semiconductor device 10. Further, the negative electrode terminal 41 b of one semiconductor device 10 overlaps the negative electrode terminal 41 b of the other semiconductor device 10. Therefore, when the double-sided heat dissipation structure using the multi-stage cooler 111 is employed, both the positional relationship in the same direction and the reversed positional relationship can be employed. Thereby, when the semiconductor device 10 constitutes the inverter assembly 110 together with the multi-stage cooler 111, the capacitor 112, and the like, the degree of freedom of arrangement of the semiconductor device 10 (degree of freedom of wiring) can be improved.

  In the present embodiment, since the connecting portions 33c and 43c are arranged with the plate thickness direction as the Z direction, the connecting portion 63 (output conductor 60) is arranged between the positive conductor 30 and the negative conductor 40 in the Z direction. More specifically, it can project from the position between the connecting portion 33c and the extended region 37 of the heat sink 42a. Therefore, the size of the semiconductor device 10 can be reduced in the Z direction.

  In the present embodiment, the main terminals (the positive terminal 31, the negative terminal 41, the output terminals 51, 61, 71) and the control terminals 80 to 85 are arranged separately on the opposite side surfaces 100c, 100d of the mold resin portion 100. Has been. Therefore, even if a short circuit occurs and a large current flows instantaneously between the main terminals, no noise is generated on the control terminal side due to magnetic coupling. That is, malfunction of the elements of the semiconductor chips 20 to 25 due to noise can be suppressed.

  In the present embodiment, as an example, the heat sink 32 is divided into three parts and the heat sink 42 is divided into two parts. However, in the above configuration, the heat sink 42 may be divided into three parts. Also, the arrangement of the semiconductor chips 20 to 25 is not particularly limited as long as the arrangement of the semiconductor chips 20 to 25 is in a line in the X direction and the upper and lower sides of the same phase are adjacent to each other. Therefore, depending on the arrangement, the heat sink 32 can be divided into two parts.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 20-25 ... Semiconductor chip, 30 ... Positive electrode conductor, 31, 31a, 31b ... Positive electrode terminal, 32, 32a, 32b, 32c ... Heat sink, 33, 33a, 33b, 33c ... connecting portion, 34 ... central region, 35 ... extended region, 36 ... facing region, 37 ... extended region, 40 ... negative electrode conductor, 41, 41a, 41b ... negative electrode terminal, 42, 42a, 42b ... heat sink, 43, 43a, 43b, 43c ... connection part, 44 ... opposing region, 45 ... extension region, 50, 60, 70 ... Output conductors, 51, 61, 71 ... Output terminals, 52a, 52b, 62a, 62b, 72a, 72b ... Heat sinks, 53, 63, 73 ... Connection parts, 80-85 ... Control terminal, 86 ... Island, 9 -95 ... Driver IC, 100 ... Mold resin part, 100a ... One side, 100b ... Back side, 100c, 100d ... Side, 101 ... Insulation sheet, 110 ... Inverter assembly, 111 ... Multi-stage cooler, 112 ... Large capacitor, 112a ... Terminal part, 113 ... Bus bar, 113a ... Positive electrode bus bar, 113b ... Negative electrode bus bar, 113c ... Insulating member, 114 ... Pressing plate, 115 ... Circuit block, 116 ... Boosting reactor

Claims (5)

Six semiconductor chips (20 to 20) which are arranged with the same thickness direction as each other, have a main electrode on both surfaces in the thickness direction and a control electrode on one of the both surfaces, and constitute three upper and lower arms of a three-phase inverter. 25)
A mold resin portion (100) having one surface (100a) and a back surface (100b) opposite to the one surface in the thickness direction, and integrally sealing each semiconductor chip;
As a pair of conductors connected to a DC power supply,
Each semiconductor chip on the upper arm side is disposed on the same surface and the main electrode on the positive electrode side of the semiconductor chip is electrically connected, and the heat dissipation surface opposite to the semiconductor chip mounting surface is the one surface of the mold resin portion A positive electrode conductor (30) having a positive electrode heat sink (32) exposed from a positive electrode terminal (31) connected to a positive electrode side of a DC power source and projecting from a side surface (100c) of the mold resin portion,
And each semiconductor chip on the lower arm side is disposed on the same surface, and the main electrode on the negative electrode side of the semiconductor chip is electrically connected, and the heat radiation surface opposite to the semiconductor chip mounting surface is the mold resin portion. A negative electrode conductor (40) having a negative electrode heat sink (42) exposed from the back surface and a negative electrode terminal (41) connected to the negative electrode side of a DC power source and protruding from the same side surface as the positive electrode terminal;
Each phase is electrically connected to the main electrode on the negative electrode side of each semiconductor chip on the upper arm side, and the heat radiation surface opposite to the connection surface with the main electrode is exposed from the back surface of the mold resin portion. 1 output heat sink (52a, 62a, 72a);
Each phase of each phase is electrically connected to the main electrode on the positive electrode side of each semiconductor chip on the lower arm side, and the heat radiation surface opposite to the connection surface with the main electrode is exposed from the one surface of the mold resin portion. Two output heat sinks (52b, 62b, 72b);
With
The positive electrode terminal and the negative electrode terminal are arranged adjacent to each other in a first direction orthogonal to the thickness direction to form a power supply terminal pair, and have two power supply terminal pairs,
The positive electrode conductor has a positive electrode connection part (33) for electrically connecting the positive electrode heat sink and the positive electrode terminal and electrically connecting the positive electrode terminals to each other;
The negative electrode conductor has a negative electrode connection part (43) for electrically connecting the negative electrode heat sink and the negative electrode terminal and electrically connecting the negative electrode terminals to each other,
At least one of the positive electrode connecting part and the negative electrode connecting part forms a laminated structure with the mold resin part between the other conductor and the plate thickness direction of the connecting part forming the laminated structure is A semiconductor device having a thickness direction. The two pairs of power supply terminals are spaced apart in the first direction;
The positive heat sink and the negative heat sink are arranged side by side in a second direction orthogonal to both the thickness direction and the first direction, with the first direction as a longitudinal direction,
In the second direction, the power terminal pair protrudes from the side surface of the mold resin portion,
Of the positive heat sink and the negative heat sink, one close to the side surface in the second direction (30) includes a central region (34) in which the semiconductor chips are arranged in the first direction, and the central region. An extended region (35) extending in the first direction from the central region on both ends,
As the connecting portion that connects the heat sink (40) on the side far from the side surface and the corresponding terminal, a first connecting portion (connected to one of the two terminals across the extended region on one end side) 43a) and a second connecting portion (43b) connected to the other of the two terminals across the extended region on the other end side,
2. The semiconductor device according to claim 1, wherein the stacked structure is formed between the first connecting portion and the second connecting portion and the heat sink close to the side surface. In the first direction, the two power supply terminal pairs are arranged apart from each other,
In the second direction perpendicular to both the thickness direction and the first direction, the power terminal pair protrudes from one side surface of the mold resin portion,
The positive heat sink and the negative heat sink are each divided into a plurality in the first direction and arranged side by side, and opposed to the first output heat sink and the second output heat sink in the first direction. A region (36, 44) and an extending region (37, 45) extending from the opposing region to the power terminal pair side,
The positive electrode connecting portion includes a first positive electrode connecting portion (33c) extending in the first direction and connecting the divided positive heat sink in the extending region.
The negative electrode connecting portion has a first negative electrode connecting portion (43c) extending in the first direction and connecting the divided negative heat sink in the extending region,
The semiconductor device according to claim 1, wherein the stacked structure is formed by the first positive electrode connecting portion and the first negative electrode connecting portion.   In the first direction, the positive terminal and the negative terminal in one of the two power terminal pairs and the positive terminal and the negative terminal in the other of the power terminal pair are mirror-inverted. The semiconductor device according to claim 1, wherein: An output terminal (51, 61, 71) of each phase connected to at least one of the first output heat sink and the second output heat sink;
Control terminals (80 to 85) respectively connected to the control electrodes of the semiconductor chip;
Further comprising
At least one of the output terminal and the control terminal of each phase has two power supply terminal pairs that are arranged apart from each other in the first direction on the side surface (100c) of the mold resin portion from which the power supply terminal pair protrudes. The semiconductor device according to claim 1, wherein the semiconductor device protrudes from a position between the two.

Images