JP2015185971A - amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception amplifier of low power consumption including an input signal amplitude detection function, in which restriction of circuit pattern layout is less.SOLUTION: An amplifier has an amplification unit 1 outputting an input signal while amplifying with an amplification factor depending on the control voltage (VGC), an amplitude detection circuit 14 for detecting the amplitude of a signal (SM) amplified by the amplification unit 1, and generating a detection voltage (VA) depending on the amplitude thereof, a gain control unit 2 generating a control voltage so as to reduce the difference between a detection voltage generated by the amplitude detection circuit and a reference voltage (VREF), and an adder 3 for adding the detection voltage generated by the amplitude detection circuit and the control voltage generated by the gain control unit while weighting.

Description

  The present invention relates to an amplifier, and more particularly to an amplifier mounted in a receiving apparatus such as an optical communication system or a wireless communication system.

In general, a receiving apparatus such as an optical communication system or a wireless communication system is provided with an amplifier (hereinafter also referred to as “reception amplifier”) that amplifies a received signal. For example, a receiving device in an optical communication system receives a current signal output from a photodiode in addition to a photodiode (PD: Photodiode) that performs optical-current conversion on an optical signal transmitted from a transmission line (optical fiber). A reception amplifier (transimpedance amplifier circuit (TIA)) that converts the voltage signal into a voltage amplitude that is linearly amplified to a voltage amplitude at which a subsequent circuit (for example, an analog / digital converter and a digital signal processor) can operate. )) And are provided.
Similarly, a receiving apparatus in a radio communication system amplifies a high-frequency signal received by an antenna and linearly amplifies the signal to a voltage amplitude at which a subsequent circuit can operate (low noise amplifier circuit (LNA: Low Noise)). Amplifier)) is provided.

  In addition to the above functions, a receiving amplifier mounted on a receiving apparatus has a function of detecting and outputting the amplitude of an input received signal (hereinafter referred to as “input signal amplitude detecting function”). is there. For example, Non-Patent Document 1 and Non-Patent Document 2 disclose a conventional configuration of a receiving amplifier having an input signal amplitude detection function.

  FIG. 12 shows a configuration of a reception amplifier having a conventional input signal amplitude detection function represented by Non-Patent Document 1. The receiving amplifier 500 shown in the figure includes an input stage amplifier circuit 51, an intermediate stage amplifier circuit 52, an output stage amplifier circuit 53, amplitude detection circuits 54 and 56, an adder 55, and an amplifier circuit 57 for gain control. Is provided.

  The amplifier circuit 51 in the input stage is a transimpedance core circuit, and linearly amplifies a current signal (received signal) SIN based on the optical signal supplied to the input terminal 59 with a predetermined transimpedance gain, and outputs it. The intermediate stage amplifier circuit 52 linearly amplifies the output signal of the amplifier circuit 51 with a gain corresponding to the gain control voltage supplied from the amplifier circuit 57 and outputs the amplified signal. The output stage amplifier circuit 53 linearly amplifies the output signal of the intermediate stage amplifier circuit 52 with a predetermined gain, and outputs the amplified signal to the output terminal 57. The amplitude detection circuit 54 detects the amplitude of the output signal of the amplification circuit 52 at the intermediate stage and outputs a voltage corresponding to the amplitude. The adder 55 outputs a voltage corresponding to the difference between the voltage output from the amplitude detection circuit 54 and the amplitude reference voltage VREF. The gain control amplification circuit 57 amplifies the output voltage of the adder 55 and outputs a gain control voltage for controlling the gain of the amplification circuit 52 in the intermediate stage. The amplitude detection circuit 56 detects the amplitude of the output signal of the amplifier circuit 51 in the input stage and outputs a signal corresponding to the amplitude to the input signal amplitude detection terminal 58.

  A specific circuit configuration of the amplitude detection circuit 56 is disclosed in Non-Patent Document 3, for example. A specific circuit configuration of the amplitude detection circuit 54, the adder 55, and the gain control amplification circuit 57 is disclosed in Patent Document 1, for example.

  According to the reception amplifier 500 described above, the output amplitude of the amplification circuit 52 at the intermediate stage is controlled to a constant value determined by the amplitude reference voltage VREF without depending on the amplitude of the reception signal. Further, since the amplitude detection circuit 56 generates a voltage corresponding to the amplitude of the received signal amplified with a constant gain by the amplifier circuit 51 in the input stage, it is output from the input signal amplitude detection terminal as shown in FIG. The input signal amplitude detection voltage is a voltage depending on the amplitude of the received signal.

  That is, according to the reception amplifier 500, an output signal having substantially constant amplitude regardless of the reception signal (current amount based on the optical signal) can be generated, and the magnitude of the reception signal can be detected. It becomes possible.

JP 2013-5372 A

H. Fukuyama, et al., “Two-channel InP HBT Differential Automatic-gain-controlled Transimpedance Amplifier IC for 43-Gbit / s DQPSK Photoreceiver”, IEEE “Compound Semiconductor IC Symposium 2008”, H. 2, pp. 145- 148, Oct. 2008, Fig. 4 Y. Na, et al., “A Design of 13dBm IIP3 DVB-S.2 RF Receiver with Auto Calibration Technique”, “Asia-Pacific Microwave Conference, 2008”, A1-20, Dec. 2008, Figure 2 Robert G. Meyer, “Low-Power Monolithic RF Peak Detector Analysis”, IEEE, “IEEE JOURNAL OF SOLID-STATE CIRCUITS”, VOL. 30, NO. 1, JANUARY 1995

However, the receiving amplifier 500 shown in FIG. 12 has the following drawbacks.
The first drawback is that the power consumption of the entire receiving amplifier 500 is large. For example, each of the amplitude detection circuits 54 and 56 receives a signal that changes at a high speed, and therefore requires a large input band. Therefore, it is necessary to give a large bias current to the transistors constituting the amplitude detection circuits 54 and 56 from the viewpoint of speeding up, and the power consumption of the amplitude detection circuits 54 and 56 tends to increase. As a result, there is a problem that the power consumption of the receiving amplifier 500 as a whole increases.

  The second drawback is a restriction on the circuit pattern layout of the receiving amplifier 500. For example, as described above, in order to input signals that change at high speed to the amplitude detection circuits 54 and 56, the signal line connecting the amplification circuit 52 of the intermediate stage and the amplitude detection circuit 54, and the amplification circuit 51 of the input stage A large bandwidth is required for the signal line connecting the amplitude detection circuit 56.

  In order to increase the bandwidth of the signal line, it is necessary to reduce the inductance value and capacitance value of the signal line. Therefore, it is necessary to adjust the element impedance and the characteristic impedance of the line in order to shorten the line length. Will be constrained.

  Further, according to the study by the present inventors, in order to increase the input dynamic range of the receiving amplifier, in addition to the configuration of the receiving amplifier 500, a mechanism for controlling the gain of the amplifier circuit 51 in the input stage is further provided. There is a problem that the input signal amplitude detection voltage is easily affected by fluctuations in temperature, power supply voltage, and the like.

  For example, in the configuration of the conventional receiving amplifier 500, in order to give the input signal amplitude detection voltage a characteristic that monotonously increases or decreases monotonously depending only on the amplitude of the received signal, the amplifier circuit 51 of the input stage is linearly operated, It is desirable to keep the gain constant. However, since a general amplifier circuit has an upper limit in input amplitude that can be linearly amplified, when the amplifier circuit 51 in the input stage is configured by a general amplifier circuit, the upper limit of the signal amplitude of the received signal to be input. There will be restrictions. Therefore, as described above, a mechanism for controlling not only the amplification circuit 52 in the intermediate stage but also the gain of the amplification circuit 51 in the input stage is further added, and when a reception signal having a large signal amplitude is input, the amplification circuit 51 in the input stage. If the gain is controlled to be reduced, the input dynamic range of the receiving amplifier 500 can be increased.

  However, in this configuration, since the gains of the two amplifier circuits 51 and 52 are controlled, when the characteristics of the amplifier circuits 51 and 52 change due to temperature and power supply voltage, the gain distribution of the two amplifiers also changes. Occurs. In the configuration in which the input signal amplitude is detected based on the output amplitude of the amplifier circuit 51 in the input stage as described above, the amplitude of the received signal is kept constant when the gain distribution of the two amplifier circuits 51 and 52 changes. Even if there is a state, the input signal amplitude detection voltage varies.

  That is, when a mechanism for controlling the gain of the amplifier circuit 51 in the input stage is added to the receiving amplifier 500 in order to increase the input dynamic range, the input signal amplitude detection voltage is easily affected by variations in temperature, power supply voltage, and the like. There is a problem of becoming.

  The present invention has been made in view of the above problems, and an object of the present invention is to reduce power consumption in a receiving amplifier.

  Another object of the present invention is to enable detection of an input signal amplitude while relaxing a restriction on a circuit pattern layout.

  Another object of the present invention is to expand an input dynamic range while suppressing a decrease in detection accuracy of an input signal amplitude in a receiving amplifier.

  An amplifier according to the present invention amplifies an input signal with an amplification factor corresponding to a control voltage and outputs the detected signal, detects an amplitude of the signal amplified by the amplifier, and generates a detection voltage corresponding to the amplitude An amplitude detector that generates the control voltage, and a detection that is generated by the amplitude detector so that a difference between the detection voltage generated by the amplitude detector and a reference voltage is small. And an adder that weights and adds the voltage and the control voltage generated by the gain control unit.

  In the amplifier, the amplifying unit includes: a first amplifying circuit that amplifies the input signal; and a second amplifying circuit that amplifies the signal amplified by the first amplifying circuit, and the first amplifying circuit and the The second amplification circuit may be configured such that each amplification factor is changed based on the control voltage.

  In the amplifier, the adder amplifies the detection voltage with a first amplification factor, amplifies the control voltage with a second amplification factor, adds the amplified voltages, and outputs the amplified voltage. And the second amplification factor may be set such that a rate of change of the differential signal with respect to the input signal is constant.

  In the amplifier, the adder amplifies the detection voltage with a first amplification factor, amplifies the control voltage with a second amplification factor, adds the amplified voltages, and outputs the resultant as a differential signal. And an output circuit that converts the differential signal output from the adder circuit into a single-ended signal and outputs the signal.

  In the amplifier, the adder circuit forms a differential input circuit, and includes a first transistor and a second transistor that input the control voltage to a base electrode, and a first terminal connected to the emitter electrode of the first transistor. A resistor, one end connected to the emitter electrode of the second transistor, the other end connected to the other end of the first resistor, a first fixed voltage node supplied with a first fixed voltage, A first current source connected between a connection node of the first resistor and the second resistor; a third transistor and a fourth transistor that form a differential input circuit and input the detection voltage to a base electrode; A third resistor having one end connected to the emitter electrode of the third transistor, a first resistor connected to the emitter electrode of the fourth transistor, and a second end connected to the other end of the third resistor. A second current source connected between the resistance, the first fixed voltage node, a connection node between the third resistor and the fourth resistor, a collector current of the first transistor, and a third current of the third transistor A resistor circuit that generates a first voltage signal based on a collector current and generates a second voltage signal based on a collector current of the second transistor and a collector current of the fourth transistor, and The output circuit may receive the first voltage signal and the second voltage signal and generate the single-ended signal based on a difference between the first voltage signal and the second voltage signal.

  In the amplifier, the resistor circuit has one end connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied, and the other end connected to a collector electrode of the first transistor and a third transistor A fifth resistor commonly connected to the collector electrode of the second transistor, one end connected to the second fixed voltage node, and the other end commonly connected to the collector electrode of the second transistor and the collector electrode of the fourth transistor. A voltage at the other end of the fifth resistor as the first voltage signal, and a voltage at the other end of the sixth resistor as the second voltage signal. May be.

  In the amplifier, the resistor circuit has one end connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied, and the other end connected to the collector electrode of the first transistor. A fifth resistor; one end connected to the second fixed voltage node; the other end connected to the collector electrode of the second transistor; one end connected to the other end of the fifth resistor; A seventh resistor having one end connected to the collector electrode of the third transistor, an eighth resistor having one end connected to the other end of the sixth resistor and the other end connected to the collector electrode of the fourth transistor; The output circuit may input a voltage at the other end of the seventh resistor as the first voltage signal, and input a voltage at the other end of the eighth resistor as the second voltage signal.

  In the amplifier, the resistor circuit has one end connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied, and the other end connected to a collector electrode of the third transistor. A fifth resistor; one end connected to the second fixed voltage node; the other end connected to the collector electrode of the fourth transistor; one end connected to the other end of the fifth resistor; A seventh resistor having one end connected to the collector electrode of the first transistor, an eighth resistor having one end connected to the other end of the sixth resistor and the other end connected to the collector electrode of the second transistor; The output circuit may input a voltage at the other end of the seventh resistor as the first voltage signal, and input a voltage at the other end of the eighth resistor as the second voltage signal.

  In the amplifier, the resistor circuit has one end connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied, and the other end connected to collector electrodes of the first transistor and the third transistor. A fifth resistor commonly connected to the second resistor, one end connected to the second fixed voltage node, the other resistor connected to the collector electrode of the second transistor, and one end connected to the second fixed voltage node. A second resistor connected to the collector electrode of the fourth transistor, and the output circuit inputs a voltage at the other end of the fifth resistor as the first voltage signal, and The voltage at the other end of the seventh resistor may be input as the second voltage signal.

  In the amplifier, the output circuit includes a fifth transistor that receives current from a power supply voltage node to a collector electrode, and inputs one of a pair of differential signals output from the adder circuit to a base electrode; A sixth transistor is supplied with a current from a power supply voltage node and inputs the other of the pair of differential signals to a base electrode; a ninth resistor having one end connected to the emitter electrode of the fifth transistor; A tenth resistor connected to the emitter electrode of the six transistors, a seventh transistor having a collector electrode and a base electrode connected in common to the other end of the ninth resistor, and a base electrode serving as the base electrode of the seventh transistor; An eighth transistor having a collector electrode connected to the other end of the tenth resistor, and an emitter electrode of the seventh transistor connected to the other end of the tenth resistor; An eleventh resistor connected at the other end to the first fixed voltage node, and a twelfth resistor at one end connected to the emitter electrode of the eighth transistor and connected at the other end to the first fixed voltage node. And a ninth transistor that inputs the collector voltage of the eighth transistor to the base electrode, and a load element connected between the emitter electrode of the ninth transistor and the first fixed voltage node. May be. The tenth resistor may have a resistance value corresponding to a sum of a resistance value of the ninth resistor and a resistance value of the eleventh resistor.

  According to the present invention, it is possible to provide a reception amplifier having an input signal amplitude detection function with low power consumption and less restrictions on circuit pattern layout.

  In the present invention, the amplifying unit includes the first amplifying circuit and the second amplifying circuit, and the amplification factors of the first amplifying circuit and the second amplifying circuit are changed by the control voltage. As a result, it is possible to expand the input dynamic range while suppressing a decrease in the detection accuracy of the input signal amplitude.

FIG. 1 is a diagram illustrating a configuration of a reception amplifier according to the first embodiment. FIG. 2 is a diagram illustrating characteristics of the gain of the second amplifier circuit 11, the output amplitude of the output signal SM, the detection voltage VA of the amplitude detection circuit 14, and the gain control voltage VGC with respect to the amplitude of the input signal SIN. FIG. 3 is a diagram for explaining the generation principle of the input signal amplitude detection voltage VPA. FIG. 4 is a diagram showing a circuit configuration of the amplitude detection circuit 14, the adder 15, and the gain control amplifier circuit 16. As shown in FIG. FIG. 5 is a diagram illustrating a circuit configuration of the adder 3 according to the first embodiment. FIG. 6 is a diagram illustrating the characteristics of the input signal amplitude detection voltage VPA with respect to the input signal SIN in the reception amplifier 100. FIG. 7 is a diagram illustrating another circuit configuration example of the output circuit 32. FIG. 8 is a diagram illustrating a configuration of the reception amplifier according to the second embodiment. FIG. 9 is a diagram illustrating a circuit configuration of an adder that generates an input signal amplitude detection voltage according to the third embodiment. FIG. 10 is a diagram illustrating a circuit configuration of an adder that generates an input signal amplitude detection voltage according to the fourth embodiment. FIG. 11 is a diagram illustrating a circuit configuration of an adder that generates an input signal amplitude detection voltage according to the fifth embodiment. FIG. 12 is a diagram showing a configuration of a reception amplifier 500 having a conventional input signal amplitude detection function. FIG. 13 is a diagram illustrating the characteristics of the input signal amplitude detection terminal voltage with respect to the input signal SIN in the conventional receiving amplifier 500.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< Embodiment 1 >>
FIG. 1 shows a configuration of an amplifier according to Embodiment 1 of the present invention.

  An amplifier 100 shown in the figure is a receiving amplifier mounted on a receiving apparatus such as an optical communication system or a wireless communication system. For example, in a receiving device of an optical communication system, an optical signal sent from a transmission line (optical fiber) is subjected to light-current conversion by a PD, and the converted current signal is converted to a voltage signal. The amplifier 100 (hereinafter referred to as “reception amplifier 100”) receives the current signal converted by the PD as an input signal SIN, and a circuit (for example, an analog / digital converter, a digital signal processor, or the like) at a subsequent stage inputs the current signal. Linear amplification to operable voltage amplitude.

  As shown in FIG. 1, the reception amplifier 100 includes an amplifying unit 1, an output stage amplifying circuit 13, an amplitude detecting circuit 14, a gain control unit 2, an adder 3, and a plurality of external terminals. In the figure, as the external terminals, for example, an input terminal PI and output terminals PO and PA are representatively shown.

  Although not particularly limited, the receiving amplifier 100 can be realized by a semiconductor integrated circuit formed on a semiconductor substrate by a known HBT (Heter Junction Bipolar Transistor) manufacturing process, for example. The receiving amplifier 100 may be realized as a one-chip semiconductor device or may be realized as a multi-chip semiconductor device, and is not particularly limited.

  The amplifying unit 1 amplifies and outputs the input signal SIN supplied to the input terminal PI. The amplification unit 1 can change the gain (amplification factor). Specifically, the amplification unit 1 includes a first amplification circuit 10 having a fixed gain and a second amplification circuit 11 having a variable gain. The gain of the second amplifier circuit 11 is adjusted according to the gain control voltage VGC generated by the gain control unit 2 described later.

  The output stage amplifier circuit 13 amplifies the signal SM amplified by the amplifier unit 1 with a desired amplification factor, and outputs the amplified signal SM to the output terminal PO. Although not particularly limited, the output stage amplifier circuit 13 has a constant (fixed) amplification factor.

  The amplitude detection circuit 14 detects the amplitude of the signal SM amplified by the amplification unit 1, and generates a detection voltage VA corresponding to the amplitude value. The gain control unit 2 generates a gain control voltage VGC for adjusting the gain of the second amplifier circuit 11 so that the difference between the detection voltage VA generated by the amplitude detection circuit 14 and the reference voltage VREF becomes small. Specifically, the gain controller 2 calculates the difference between the detection voltage VA and the reference voltage VREF, and the gain for generating the gain control voltage VGC so that the difference calculated by the adder 15 becomes zero. And an amplifier circuit 16 for control. By increasing the gain of the amplifier circuit 16 for gain control, the difference between the detection voltage VA and the reference voltage VREF can be made closer to zero.

  The adder 3 weights and adds the detection voltage VA generated by the amplitude detection circuit 14 and the gain control voltage VGC generated by the gain control unit 16, so that a voltage (in accordance with the amplitude of the input signal SIN ( Hereinafter, this is referred to as “input signal amplitude detection voltage.”) VPA is generated and output to the output terminal PA. Details of the adder 3 will be described later.

Here, gain control in the receiving amplifier 100 will be described.
As shown in FIG. 1, the second amplification circuit 11, the amplitude detection circuit 14, and the gain control unit 2 form one closed loop. By this closed loop (hereinafter referred to as “gain control loop”), the gain of the second amplifier circuit 11, the output amplitude of the output signal SM, the detection voltage VA of the amplitude detection circuit 14, and the gain control voltage VGC are shown in FIG. The characteristics are as shown.
FIG. 2 is a diagram illustrating characteristics of the gain of the second amplifier circuit 11, the output amplitude of the output signal SM, the detection voltage VA of the amplitude detection circuit 14, and the gain control voltage VGC with respect to the input signal SIN.

In the figure, reference numeral 205 represents the characteristic of the gain of the second amplifier circuit 11 with respect to the amplitude of the input signal SIN, and reference numeral 201 represents the amplitude of the output signal SM of the second amplifier circuit 11 with respect to the amplitude of the input signal SIN. The reference numeral 202 represents the characteristic of the gain control voltage VGC with respect to the amplitude of the input signal SIN, and the reference numeral 203 represents the characteristic of the detection voltage VA with respect to the amplitude of the input signal SIN.
In the figure, “Al” represents the amplitude value of the input signal SIN when the gain control voltage VGC reaches the upper limit value that can be output from the gain control unit 2, and “Ah” represents the gain control voltage VGC. It represents the amplitude value of the input signal SIN when the lower limit value that can be output by the gain control unit 2 is reached.

  As shown by the characteristic 201 in FIG. 2, for example, when the amplitude of the input signal SIN is in the range of Al to Ah, the amplitude of the output signal SM of the second amplifier circuit 11 is kept substantially constant. This is because the gain controller 2 makes the second amplifier circuit 11 so that the amplitude of the output signal SM of the first amplifier circuit 11 is constant (the product of the amplitude of the input signal SIN and the gain of the first amplifier circuit 11 is constant). This is realized by controlling the gain. Specifically, as shown in the characteristic 202 of FIG. 2, the gain control unit 2 generates the gain control voltage VGC so that the detection voltage VA and the reference voltage (amplitude reference voltage) VREF coincide with each other. The gain of the two amplifier circuit 11 is controlled so as to monotonously decrease (inversely proportional) with respect to the input signal SIN, as indicated by the characteristic 205 in FIG. As a result, the amplitude of the output signal SM of the second amplifier circuit 11 is kept substantially constant regardless of the amplitude of the input signal SIN.

  On the other hand, in the range where the amplitude of the input signal SIN is smaller than Al, the gain control voltage VGC reaches the upper limit value as shown by the characteristics 205 and 202 in FIG. 2, and the gain of the second amplifier circuit 11 does not change (does not increase). Therefore, the amplitude of the output signal SM of the second amplifier circuit 11 has a characteristic that decreases monotonously as the amplitude of the input signal SIN decreases. In the range where the amplitude of the input signal SIN is larger than Ah, the gain control voltage VGC reaches the lower limit as shown by the characteristics 205 and 202 in FIG. 2, and the gain of the second amplifier circuit 11 does not change (does not decrease). Therefore, the amplitude of the output signal SM of the second amplifier circuit 11 increases monotonously with the increase of the amplitude of the input signal SIN.

  Therefore, the amplitude of the output signal SM of the second amplifier circuit 11 increases in proportion to the amplitude of the input signal SIN in the range where the amplitude of the input signal SIN is smaller than Al, as shown by the characteristic 201 in FIG. In the range where the amplitude of the input signal SIN is from Al to Ah, the input signal SIN is constant regardless of the amplitude of the input signal SIN, and in the range where the amplitude of the input signal SIN is larger than Ah, the characteristic increases in proportion to the amplitude of the input signal SIN Become. The output signal SM whose amplitude is controlled in this way is amplified at a predetermined amplification factor by the subsequent amplification circuit 13 as described above, and is output to the output terminal PO.

  The detection voltage VA of the amplitude detection circuit 14 depends on the amplitude of the input signal SIN similarly to the amplitude of the output signal SM of the second amplification circuit 11. For example, when the amplitude of the input signal SIN is in the range from Al to Ah, the amplitude of the output signal SM of the second amplifier circuit 11 is kept constant, so that the detection voltage VA of the amplitude detection circuit 14 is constant. . In addition, when the amplitude of the input signal SIN is in a range smaller than Al, the gain of the second amplifier circuit 11 does not change, so that the amplitude of the signal SM decreases as the amplitude of the input signal SIN decreases, and the detection voltage VA deviates so as to be lower than the reference voltage VREF. Similarly, even when the amplitude of the input signal SIN is in a range larger than Ah, the gain of the second amplifier circuit 11 does not change, so that the amplitude of the signal SM increases as the amplitude of the input signal SIN increases and is detected. The voltage VA deviates so as to exceed the reference voltage VREF.

  Accordingly, the detection voltage VA of the amplitude detection circuit 14 increases in proportion to the amplitude of the input signal SIN in the range where the amplitude of the input signal SIN is smaller than Al, as shown by the characteristic 203 in FIG. Is constant regardless of the amplitude of the input signal SIN, and increases in proportion to the amplitude of the input signal SIN when the amplitude of the input signal SIN is larger than Ah.

  As described above, according to the gain control loop, when the amplitude of the input signal SIN is in the range from Al to Ah, the amplitude is constant regardless of the input signal SIN, and in other ranges, the amplitude is proportional to the input signal SIN. As a result, the input signal SIN can be amplified.

Next, the principle of generating the input signal amplitude detection voltage VPA by the adder 3 will be described in detail with reference to FIG.
FIG. 3 is a diagram for explaining the generation principle of the input signal amplitude detection voltage VPA. In FIG. 3, reference numeral 202X represents the characteristic of the signal obtained by inverting the gain control voltage VGC with respect to the gain control voltage VGC, and reference numeral 204 represents the characteristic of the input signal amplitude detection voltage VPA with respect to the amplitude of the input signal SIN. .

  As described above, the adder 3 generates the input signal amplitude detection voltage VPA by weighting and adding the detection voltage VA and the gain control voltage VGC. Specifically, as shown in FIG. 3, the signal (characteristic 202X) obtained by inverting the polarity of the gain control voltage VGC and the detection voltage VA (characteristic 203) of the amplitude detection circuit 14 are appropriately weighted and added. As a result, a voltage (characteristic 204) that monotonously increases as the amplitude of the input signal SIN increases can be obtained. By outputting this voltage (characteristic 204) as the input signal amplitude detection voltage VPA, the input signal amplitude detection function in the receiving amplifier 100 can be realized.

  For example, the slope of the inverted signal of the gain control voltage VGC when the amplitude of the input signal SIN is in the range of Al to Ah is “gm”, and the slope of the detection voltage VA when the amplitude of the input signal SIN is less than or equal to Al. Let “gl” be the gradient of the detection voltage VA when the amplitude of the input signal SIN is greater than or equal to Ah. Further, the weight for the detection voltage VA is “W1”, and the weight for the gain control voltage VGC is “W2”.

In this case, the slope of the input signal amplitude detection voltage VPA is “W1 · gl” when the amplitude of the input signal SIN is less than or equal to Al, and “W2 · gm” when the amplitude of the input signal SIN is between Al and Ah. When the amplitude of the input signal SIN is greater than or equal to Ah, “W1 · gh” is obtained.
By setting the values of “W1” and “W2” so that these inclinations “W1 · gl”, “W2 · gm”, and “W1 · gh” are equal, the input signal amplitude detection voltage VPA is The voltage can be monotonously increased as the amplitude of the input signal SIN increases. Specifically, if the ratio of W1 and W2 is set to be, for example, “W1 / W2≈2.gm / (gl + gh)”, the input signal amplitude detection voltage VPA increases the amplitude of the input signal SIN. Along with this, the characteristic increases almost monotonously. Note that the magnitudes of W1 and W2 may be determined so that the maximum change amount of the input signal amplitude detection voltage VPA becomes a desired value (for example, within a standard value).

  As described above, according to the receiving amplifier 100, it is possible to generate a voltage that changes linearly with respect to the amplitude of the input signal SIN by appropriately adjusting the weighting of the addition by the adder 3. A signal amplitude detection function can be realized. In addition, an amplitude detection circuit for detecting the amplitude of the input signal is not required as compared with the conventional receiving amplifier 500 having the input signal amplitude detection function as described above. Further, the adder 3 added in place of the conventional amplitude detection circuit only has to add the detection voltage VA close to the direct-current voltage changing at a low speed and the gain control voltage VGC. It can be realized with a circuit configuration with power consumption. That is, according to the receiving amplifier 100, the overall current consumption can be reduced as compared with the receiving amplifier 500 having the conventional input signal amplitude detecting function.

  Further, since it is not necessary to secure a wide band in the signal line connecting the amplitude detection circuit 14 and the adder 3 and the signal line connecting the gain control amplifier circuit 16 and the adder 3, There is no need to shorten or adjust the characteristic impedance of the signal line, and the circuit pattern layout can be relaxed compared to the conventional receiving amplifier 500.

Next, a specific circuit configuration of the functional units constituting the reception amplifier 100 will be described.
FIG. 4 illustrates a circuit configuration of the amplitude detection circuit 14, the adder 15, and the gain control amplifier circuit 16. In the present embodiment, the output signal SM of the second amplifier circuit 11 is a differential signal, the detection voltage VA and the gain control voltage VGC are generated as a differential signal, and the input signal amplitude detection voltage VPA is a single-ended signal. The case where it produces | generates is demonstrated as an example. The transistors (Q11, Q12, etc.) constituting each circuit are assumed to be HBTs.

The amplitude detection circuit 14 includes transistors Q11 to 15, resistors R21, R22, and R23, capacitors C1 and C2, and current sources I11 and I12.
The transistors Q11 and Q12 and the capacitor C1 hold a voltage that is lower than the peak voltage value of the output (differential) signal SM of the second amplifier circuit 11 by the base-emitter voltage Vbe of the transistors Q11 and Q12 at both ends of the capacitor C1. The Further, the transistor Q13 generates a voltage lower than the voltage of the capacitor C1 by the base-emitter voltage Vbe of the transistor Q13, and outputs it from the output terminal OVAT.

  Further, the average voltage of the output (differential) signal SM of the second amplifier circuit 11 is held at both ends of the capacitor C2 by the resistors R21 and R22 and the capacitor C2. Further, the transistors Q14 and Q15 generate a voltage lower than the voltage of the capacitor C2 by the sum of the base-emitter voltage Vbe of the transistor Q14 and the base-emitter voltage Vbe of the transistor Q15, and output from the output terminal OVAC.

  The base-emitter voltages of the transistors Q11, Q12, and Q14 are substantially equal, and the base-emitter voltages of the transistors Q13 and Q15 are substantially equal. As a result, the difference between the voltage of the emitter electrode of the transistor Q13 and the voltage of the emitter electrode of the transistor Q15 is the difference between the peak voltage and the average voltage of the differential output waveform of the second amplifier circuit 11, that is, the second amplifier circuit 11. Is equal to the amplitude value of the differential output waveform.

  The adder 15 is realized by inserting a resistor R23 between the emitter of the transistor Q13 constituting the amplitude detection circuit 14 and the current source I11. As shown in FIG. 4, the voltage at the connection node between the resistor R23 and the current source I11 becomes a voltage value lower by “R23 × I11” than the voltage value of the emitter electrode of the transistor Q13. Therefore, the resistance value of the resistor R23 and the current value of the current source I11 are determined so that the reference voltage VREF becomes a desired value. As a result, the voltage corresponding to the difference between the voltage VX of the connection node between the resistor R23 and the current source I11 and the voltage VY of the emitter electrode of the transistor Q15 is the amplitude value of the differential output waveform of the second amplifier circuit 11 and the reference voltage. It corresponds to the difference voltage according to the difference from VREF.

  The gain control amplifying circuit 16 includes, for example, transistors Q16 and Q17, resistors R24 and R25, and a current source I13. Although FIG. 4 illustrates the case where the amplification circuit 16 has one amplification stage, the amplification stages may be multistage depending on the required amplification factor.

  The amplifying circuit 16 inverts the polarity of the voltage according to the difference between the voltage at the connection node between the resistor R23 and the current source I11 and the voltage at the emitter electrode of the transistor Q15, and the difference between the reference voltage VREF and the second amplifying circuit 11 is reversed. A voltage obtained by subtracting the amplitude value of the dynamic output waveform is output from the output terminals OT and OC as the gain control voltage VGC.

  Next, a specific circuit configuration of the adder 3 will be described.

FIG. 5 is a diagram illustrating a circuit configuration of the adder 3.
As shown in the figure, the adder 3 includes an adder circuit 31 and an output circuit 32. The adder circuit 31 amplifies the detection voltage VA with the first amplification factor (W1), amplifies the control voltage VGC with the second amplification factor (W2), adds the amplified signals, and adds a voltage (differential signal). Output as V1 and V2. The output circuit 32 converts the differential signals V1 and V2 output from the adder circuit 31 into single-ended signals and outputs the signals. Here, the first amplification factor and the second amplification factor are set such that the rate of change of the differential signals V1 and V2 with respect to the input signal SIN is constant.

Specifically, the adder circuit 31 is based on the differential input circuit 310 that inputs the gain control voltage VGC, the differential input circuit 311 that inputs the detection voltage VA, and the current output from each differential input circuit. And a resistor circuit 312 that generates differential signals (voltages) V1 and V2.
The differential input circuit 310 includes transistors Q1 and Q2, resistors R3 and R4, and a current source I1. Transistor Q1 and transistor Q2 form a differential pair, and are formed to have the same emitter size. A gain control voltage VGC (differential signal) is input to the respective base electrodes of the transistors Q1 and Q2. One end of resistor 3 is connected to the emitter electrode of transistor Q1. The resistor R4 has one end connected to the emitter electrode of the transistor Q2 and the other end connected to the other end of the resistor R3. The resistor 3 and the resistor 4 have the same resistance value, for example. The current source I1 is connected between a reference node VEE to which a reference fixed voltage VEE (for example, ground voltage) is supplied and a connection node between the resistor R3 and the resistor R4. As a result, the gain control voltage VGC input to the differential input circuit 310 is amplified with the first amplification factor and output as differential currents from the collector electrodes of the transistors Q1 and Q2, respectively.

  Similarly, the differential input circuit 311 includes transistors Q3 and Q4, resistors R5 and R6, and a current source I2. Transistor Q3 and transistor Q4 form a differential pair, and are formed to have the same emitter size. A detection voltage VA (differential signal) is input to the base electrodes of the transistors Q3 and Q4. One end of the resistor R5 is connected to the emitter electrode of the transistor Q3. The resistor R6 has one end connected to the emitter electrode of the transistor Q4 and the other end connected to the other end of the resistor R5. The resistor R5 and the resistor R6 have, for example, the same resistance value. Current source I2 is connected between reference node VEE and a connection node between resistors R5 and R6. As a result, the detection voltage VA input to the differential input circuit 311 is amplified at the second amplification factor, and is output from the collector electrodes of the transistors Q3 and Q4 as differential currents.

The resistance circuit 312 includes resistors R1 and R2.
The resistor R1 has one end connected to a power supply node VCC to which a fixed voltage VCC (power supply voltage) higher than the reference fixed voltage VEE is supplied, and the other end common to the collector electrode of the transistor Q1 and the collector electrode of the transistor Q3. Connected to. As a result, the combined current of the collector current of transistor Q1 and the collector current of transistor Q3 is converted to voltage V1.
Resistor R2 has one end connected to power supply node VCC and the other end connected in common to the collector electrode of transistor Q2 and the collector electrode of transistor Q4. Thereby, the combined current of the collector current of transistor Q2 and the collector current of transistor Q4 is converted to voltage V2.

  Weighting at the time of addition by the adder circuit 31 is realized by adjusting the gains of the differential input circuits 310 and 311. For example, by adjusting the resistance values of the resistors R3 and R4, the resistance values of the resistors R5 and R6, and the current values of the current sources I1 and I2, the first gain of the differential input circuit 310 (to the above-mentioned weight “W1”) is adjusted. And the second amplification factor (corresponding to the above-mentioned weight “W2”) of the differential input circuit 311 can be adjusted. Specifically, as described above, the resistance values of the resistors R3 and R4, the resistance values of the resistors R5 and R6, and the current sources I1 and I2 are set so that “W1 / W2≈2.gm / (gl + gh)”. What is necessary is just to adjust the current value.

The output circuit 32 includes transistors Q5 to 10 and resistors R7 to R11.
The transistor Q5 inputs the voltage V1 output from the adder circuit 31 to the base electrode, and the transistor Q6 inputs the voltage V2 output from the adder circuit 31 to the base electrode. One end of the resistor R7 is connected to the emitter electrode of the transistor Q5. Resistor R8 has one end connected to the emitter electrode of transistor Q6. In the transistor Q7, the collector electrode and the base electrode are commonly connected to the other end of the resistor R7. The transistor Q8 has a base electrode connected in common with the base electrode of the transistor Q7, and a collector electrode connected to the other end of the resistor R8. Resistor R9 has one end connected to the emitter electrode of transistor Q7 and the other end connected to reference node VEE. Resistor R10 has one end connected to the emitter electrode of transistor Q8 and the other end connected to reference node VEE. In the transistor Q9, the collector voltage of the transistor Q8 is input to the base electrode. Load element R11 is connected between the emitter electrode of transistor Q9 and reference node VEE. The load element R11 is, for example, a resistor. Transistor Q10 is diode-connected between power supply node VCC and the collector electrode of transistor Q9.

  When the resistance values of the resistor R9 and the resistor R10 are the same, the same current flows through the resistors R7 and R8 by the transistors Q7 and Q8. Here, when the voltage VEE is 0 V and the current flowing through the resistors R7 and R8 is I, the voltage V1 can be expressed by (Expression 1).

  Similarly, the voltage V2 can be expressed by (Formula 2). Here, V3 represents the base voltage of the transistor Q9.

  When I is eliminated by the above (formula 1) and (formula 2), V3 can be represented by (formula 3).

  Here, since substantially the same current flows through the transistors Q5, Q6, and Q7, it can be considered that Vbe (Q5) = Vbe (Q6) = Vbe (Q7) = Vbe0. Further, when the resistance value is selected so that “R8 = R7 + R9”, (Expression 4) is established.

  The input signal amplitude detection voltage VPA output to the output terminal PA is lower than the voltage V3 by the base-emitter voltage Vbe of the transistor Q9. That is, the input signal amplitude detection voltage VPA is “VPA≈V2−V1” from (Equation 4).

  As described above, according to the output circuit 32, the voltage (input signal amplitude detection voltage VPA) corresponding to the difference between the voltage V1 and the voltage V2 generated by the adder circuit 31 is single-ended with the fixed voltage VEE as a reference. It can be output as a signal.

  Further, by determining the resistance values of the resistors R7 to R9 in the output circuit 32 so that “R8 = R7 + R9”, the input signal amplitude detection voltage VPA is the power supply voltage VCC or the base-emitter voltage of the transistors Q5 to Q10. It becomes less dependent on power supply voltage and temperature fluctuations.

  FIG. 6 is a diagram illustrating the characteristics of the input signal amplitude detection voltage VPA with respect to the amplitude of the input signal SIN in the reception amplifier 100. As shown in the figure, by configuring the receiving amplifier 100 as described above, the input signal amplitude detection voltage VPA monotonously increases as the amplitude of the input signal SIN increases in a wide voltage range of the input signal SIN. The characteristic increases, and the signal is suitable as a detection result of the input signal SIN.

  In order to further increase the sensitivity of the input amplitude detection voltage VPA, one or more differential amplifier circuits may be inserted between the adder circuit 31 and the output circuit 32. Further, when generating an output voltage with the fixed voltage VEE as a reference as a negative power supply and the voltage VCC as a reference (0 V), for example, the output circuit 32 is configured by a differential amplifier circuit as shown in FIG. Alternatively, the output circuit 32 may be deleted, and either the positive phase output voltage V1 or the negative phase output voltage V2 of the adder circuit 31 may be supplied to the output terminal PA as it is.

  As described above, according to the receiving amplifier 100 according to the first embodiment, it is possible to detect the input signal amplitude without providing an amplitude detection circuit for detecting the amplitude of the input signal. As a result, as described above, power consumption can be reduced as compared with the conventional receiving amplifier, and restrictions on the circuit pattern layout can be relaxed.

<< Embodiment 2 >>
FIG. 8 shows the configuration of the receiving amplifier according to the second embodiment.
The receiving amplifier 200 shown in the figure is different from the receiving amplifier 100 according to the first embodiment in that the gain of the first amplifier circuit in the input stage is variable, and the other configuration is the same as that of the receiving amplifier 100. is there. In the following description, components common to the receiving amplifier 100 according to Embodiment 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  Similarly to the second amplifier circuit 11, the gain of the first amplifier circuit 20 in the input stage is adjusted according to the gain control voltage VGC generated by the gain control unit 2. That is, the gain distribution of the first amplifier circuit 20 and the second amplifier circuit 11 is adjusted so that the amplitude of the output signal SM is constant. For example, the first amplifying circuit 20 in the input stage is controlled so that the gain decreases when the amplitude of the input signal SIN is larger than the target value.

  Note that the mechanism of gain control of the first amplifier circuit 20 can be variously changed depending on the circuit configuration of the first amplifier circuit 20. For example, as shown in FIG. 8, the first amplifier circuit 20 may be directly controlled by the gain control voltage VGC, or the gain control voltage VGC is input to a buffer circuit such as a level shift circuit and the buffer circuit is passed through the buffer circuit. The first amplifier circuit 20 may be controlled, and the gain control method is not particularly limited.

As described above, according to the receiving amplifier 200 according to the second embodiment, the amplification factors of the first amplification circuit 20 and the second amplification circuit 11 are adjusted so that the amplitude of the output signal SM of the amplification unit 1 is constant. Therefore, the input dynamic range of the receiving amplifier can be increased as compared with the case where only the amplification circuit 11 at the intermediate stage adjusts the amplification factor. Further, like the reception amplifier 500 having the conventional input signal amplitude detection function described above, the output amplitude of the input stage amplifier circuit (corresponding to the first amplifier circuit 20 according to the second embodiment) is detected by the amplitude detection circuit. Since it is not a configuration, even if the gain distribution of the first amplifier circuit 20 and the second amplifier circuit 11 fluctuates due to temperature and power supply voltage, the influence of the input signal amplitude detection voltage VPA is limited. .
That is, according to the receiving amplifier 200 according to the second embodiment, it is possible to expand the input dynamic range while suppressing deterioration in detection accuracy of the input signal amplitude.

<< Embodiment 3 >>
FIG. 9 shows another circuit configuration of the adder that generates the input signal amplitude detection voltage.
The adder 4 shown in the figure is different from the adder 3 according to the first embodiment in that the adder 4 includes an adder circuit 34 that is less weighted with respect to the gain control voltage VGC than the adder circuit 31. To do. In the following description, components common to the adder 3 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  Specifically, the adder circuit 34 includes differential input circuits 310 and 311 and a resistor circuit 313. Resistor circuit 313 is configured by dividing resistors R1 and R2 of resistor circuit 312 according to the first embodiment into resistors R1A and R1B and resistors R2A and R2B, respectively. Resistor R1A has one end connected to power supply node VCC and the other end connected to the collector electrode of transistor Q1. Resistor R2A has one end connected to power supply node VCC and the other end connected to the collector electrode of transistor Q2. The resistor R1B has one end connected to the other end of the resistor R1A and the other end connected to the collector electrode of the transistor Q3. Resistor R2B has one end connected to the other end of resistor R2A and the other end connected to the collector electrode of transistor Q4.

  The output circuit 32 inputs the voltage V1 at the connection node between the resistor R1B and the collector electrode of the transistor Q3 and the voltage V2 at the connection node between the resistor R2B and the collector electrode of the transistor Q4, and generates an input signal amplitude detection voltage VPA. To do.

  According to the adder 4 according to the third embodiment, it is possible to make the weight for the gain control voltage VGC extremely small compared to the detection voltage VA. The adder 4 is particularly effective when, for example, the rate of change of the gain control voltage VGC with respect to the input signal SIN is larger than the rate of change of the detection voltage VA.

<< Embodiment 4 >>
FIG. 10 shows still another circuit configuration of the adder that generates the input signal amplitude detection voltage.
The adder 5 shown in the figure is different from the adder 3 according to the first embodiment in that the adder 5 includes an adder circuit 35 that is less weighted with respect to the detection voltage VA than the gain control voltage VGC instead of the adder circuit 31. To do. In the following description, components common to the adder 3 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  Specifically, the adder circuit 35 includes differential input circuits 310 and 311 and a resistor circuit 314. Similarly to the resistor circuit 313 according to the second embodiment, the resistor circuit 314 has a configuration in which the resistor R1 and the resistor R2 are divided into resistors R1A and R1B and resistors R2A and R2B, respectively. Resistor R1A has one end connected to power supply node VCC and the other end connected to the collector electrode of transistor Q3. Resistor R2A has one end connected to power supply node VCC and the other end connected to the collector electrode of transistor Q4. The resistor R1B has one end connected to the other end of the resistor R1A and the other end connected to the collector electrode of the transistor Q1. The resistor R2B has one end connected to the other end of the resistor R2A and the other end connected to the collector electrode of the transistor Q2.

  The output circuit 32 inputs the voltage V1 at the connection node between the resistor R1B and the collector electrode of the transistor Q1 and the voltage V2 at the connection node between the resistor R2B and the collector electrode of the transistor Q2, and generates an input signal amplitude detection voltage VPA. To do.

  According to the adder 5 according to the fourth embodiment, it is possible to make the weighting for the detection voltage VA extremely smaller than the gain control voltage VGC. The adder 5 is particularly effective when, for example, the rate of change of the detection voltage VA with respect to the input signal SIN is larger than the rate of change of the gain control voltage VGC.

<< Embodiment 5 >>
FIG. 11 shows still another circuit configuration of the adder that generates the input signal amplitude detection voltage.
The adder 6 shown in the figure is different from the adder 3 according to the first embodiment in that an adder circuit 36 is provided instead of the adder circuit 31. In the following description, components common to the adder 3 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  Specifically, the adder circuit 36 includes differential input circuits 310 and 311 and a resistor circuit 315. Resistor circuit 315 includes resistors R1, R2, and R2X.

  Resistor R1 has one end connected to power supply node VCC and the other end connected in common to the collector electrodes of transistors Q1 and Q3. Resistor R2X has one end connected to power supply node VCC and the other end connected to the collector electrode of transistor Q2. Resistor R2 has one end connected to power supply node VCC and the other end connected to the collector electrode of transistor Q4.

  The output circuit 32 inputs the voltage V1 at the connection node between the resistor R1 and the collector electrodes of the transistors Q1 and Q3 and the voltage V2 at the connection node between the resistor R2 and the collector electrode of the transistor Q4, and inputs the input signal amplitude detection voltage VPA. Is generated.

  According to the adder 6 according to the fifth embodiment, it is possible to perform weighted addition only for the addition of the collector current of the transistor Q1 and the collector current of the transistor Q3. Further, according to this, since it is not necessary to connect the wiring in the adder with a differential pair, the circuit layout of the adder can be simplified.

  Although the invention made by the present inventors has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, although the case where the transistors Q1 to Q10 are NPN HBTs has been illustrated, some or all of these transistors are N-type electric fields represented by, for example, ordinary NPN bipolar transistors and MOS (metal-oxide-semiconductor) FETs. It may be replaced with an effect transistor or the like. A similar circuit can also be configured using a PNP bipolar transistor or a P-type field effect transistor.

  Further, the adder circuits 34 and 35 shown in the third and fourth embodiments are not limited to the circuit configuration of the weighted addition between the differential signals as shown in FIGS. 9 and 10, for example, as shown in FIG. A circuit configuration that performs weighted addition only for the addition of the collector current of the transistor Q1 and the collector current of the transistor Q3 may be employed.

  Further, the adders 3 to 6 are not limited to the circuit configuration based on the differential amplifier as shown in FIGS. 5 and 9 to 11, and can be realized by various circuit configurations having a weighted addition function. it can.

  DESCRIPTION OF SYMBOLS 100, 200 ... Reception amplifier, 1 ... Amplification part, 2 ... Gain control part, 3 ... Adder, 10 ... 1st amplification circuit, 11 ... 2nd amplification circuit, 13 ... Output stage amplification circuit, 14 ... Amplitude detection circuit, DESCRIPTION OF SYMBOLS 15 ... Adder, 16 ... Amplifier circuit for gain control, PI ... Input terminal, PO, PA ... Output terminal, SIN ... Input signal, SM ... Output signal of 2nd amplifier circuit, VA ... Detection voltage, VREF ... Reference voltage , VPA ... input signal amplitude detection voltage, VGC ... gain control voltage, 31, 34, 35, 36 ... adder circuit, 32, 33 ... output circuit, 310, 311 ... differential input circuit, 312-315 ... resistance circuit, V1, V2: Output voltages of the adder circuit.

Claims (11)

An amplifying unit for amplifying an input signal at an amplification factor according to a control voltage and outputting the amplified signal;
An amplitude detection unit that detects an amplitude of the signal amplified by the amplification unit and generates a detection voltage according to the amplitude;
A gain control unit that generates the control voltage such that a difference between the detection voltage generated by the amplitude detection unit and a reference voltage is reduced;
An amplifier comprising: an adder that weights and adds the detection voltage generated by the amplitude detection unit and the control voltage generated by the gain control unit. The amplifier of claim 1, wherein
The amplification unit is
A first amplifier circuit for amplifying the input signal;
A second amplifier circuit for amplifying the signal amplified by the first amplifier circuit,
Each of the first amplification circuit and the second amplification circuit has an amplification factor changed based on the control voltage. The amplifier according to claim 1 or 2,
The adder amplifies the detection voltage with a first amplification factor and amplifies the control voltage with a second amplification factor, adds the amplified voltages, and outputs the result.
The first amplification factor and the second amplification factor are set so that a rate of change of the differential signal with respect to the input signal is constant. The amplifier of claim 3, wherein
The adder is
An adder circuit that amplifies the detection voltage with a first amplification factor and amplifies the control voltage with a second amplification factor, adds the amplified voltages, and outputs the resultant as a differential signal;
An output circuit that converts the differential signal output from the adder circuit into a single-ended signal and outputs the signal. The amplifier according to claim 4, wherein
The adder circuit
A first transistor and a second transistor that form a differential input circuit and input the control voltage to a base electrode;
A first resistor having one end connected to the emitter electrode of the first transistor;
A second resistor having one end connected to the emitter electrode of the second transistor and the other end connected to the other end of the first resistor;
A first current source connected between a first fixed voltage node to which a first fixed voltage is supplied and a connection node between the first resistor and the second resistor;
A third transistor and a fourth transistor constituting a differential input circuit and inputting the detection voltage to a base electrode;
A third resistor having one end connected to the emitter electrode of the third transistor;
A fourth resistor having one end connected to the emitter electrode of the fourth transistor and the other end connected to the other end of the third resistor;
A second current source connected between the first fixed voltage node and a connection node between the third resistor and the fourth resistor;
A first voltage signal is generated based on the collector current of the first transistor and the collector current of the third transistor, and a second voltage is generated based on the collector current of the second transistor and the collector current of the fourth transistor. A resistor circuit for generating a signal,
The output circuit receives the first voltage signal and the second voltage signal, and generates the single-ended signal based on a difference between the first voltage signal and the second voltage signal. amplifier. The amplifier according to claim 5, wherein
The resistor circuit is
One end is connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied, and the other end is connected in common to the collector electrode of the first transistor and the collector electrode of the third transistor. A fifth resistor,
A sixth resistor having one end connected to the second fixed voltage node and the other end connected in common to the collector electrode of the second transistor and the collector electrode of the fourth transistor;
The output circuit receives the voltage at the other end of the fifth resistor as the first voltage signal, and inputs the voltage at the other end of the sixth resistor as the second voltage signal. The amplifier according to claim 5, wherein
The resistor circuit is
A fifth resistor having one end connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied and the other end connected to a collector electrode of the first transistor;
A sixth resistor having one end connected to the second fixed voltage node and the other end connected to the collector electrode of the second transistor;
A seventh resistor having one end connected to the other end of the fifth resistor and the other end connected to the collector electrode of the third transistor;
An eighth resistor having one end connected to the other end of the sixth resistor and the other end connected to a collector electrode of the fourth transistor;
The amplifier, wherein the output circuit inputs a voltage at the other end of the seventh resistor as the first voltage signal, and inputs a voltage at the other end of the eighth resistor as the second voltage signal. The amplifier according to claim 5, wherein
The resistor circuit is
A fifth resistor having one end connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied and the other end connected to the collector electrode of the third transistor;
A sixth resistor having one end connected to the second fixed voltage node and the other end connected to the collector electrode of the fourth transistor;
A seventh resistor having one end connected to the other end of the fifth resistor and the other end connected to the collector electrode of the first transistor;
An eighth resistor having one end connected to the other end of the sixth resistor and the other end connected to the collector electrode of the second transistor;
The amplifier, wherein the output circuit inputs a voltage at the other end of the seventh resistor as the first voltage signal, and inputs a voltage at the other end of the eighth resistor as the second voltage signal. The amplifier according to claim 5, wherein
The resistor circuit is
A fifth resistor having one end connected to a second fixed voltage node to which a second fixed voltage higher than the first fixed voltage is supplied and the other end connected in common to the collector electrodes of the first transistor and the third transistor When,
A sixth resistor having one end connected to the second fixed voltage node and the other end connected to the collector electrode of the second transistor;
A seventh resistor having one end connected to the second fixed voltage node and the other end connected to the collector electrode of the fourth transistor;
The amplifier, wherein the output circuit inputs a voltage at the other end of the fifth resistor as the first voltage signal, and inputs a voltage at the other end of the seventh resistor as the second voltage signal. The amplifier according to any one of claims 4 to 9,
The output circuit is
A fifth transistor for supplying current to a collector electrode from a power supply voltage node and inputting one of a pair of differential signals output from the adder circuit to a base electrode;
A sixth transistor that supplies current to the collector electrode from the power supply voltage node and inputs the other of the pair of differential signals to a base electrode;
A ninth resistor having one end connected to the emitter electrode of the fifth transistor;
A tenth resistor having one end connected to the emitter electrode of the sixth transistor;
A seventh transistor having a collector electrode and a base electrode commonly connected to the other end of the ninth resistor;
An eighth transistor having a base electrode connected to the base electrode of the seventh transistor and a collector electrode connected to the other end of the tenth resistor;
An eleventh resistor having one end connected to the emitter electrode of the seventh transistor and the other end connected to the first fixed voltage node;
A twelfth resistor having one end connected to the emitter electrode of the eighth transistor and the other end connected to the first fixed voltage node;
A ninth transistor that inputs a collector voltage of the eighth transistor to a base electrode;
An amplifier comprising: a load element connected between an emitter electrode of the ninth transistor and the first fixed voltage node. The amplifier of claim 10.
The amplifier according to claim 10, wherein the tenth resistor has a resistance value corresponding to a sum of a resistance value of the ninth resistor and a resistance value of the eleventh resistor.

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