JP6389144B2 - Current detection circuit - Google Patents

Description

  The present invention relates to a current detection circuit that detects a current, for example, a current detection circuit that detects a DC component of a current signal input to a transimpedance amplifier circuit.

  In recent years, communication devices used in optical communication, wireless communication, wired communication, and the like that handle broadband baseband signals have been required not only to increase the communication speed but also to improve the quality, but also to monitor the communication status and the like. ing. In particular, in an optical receiver used for optical communication, a transimpedance amplifier circuit (hereinafter referred to as “TIA”) that converts a photocurrent (current signal) generated in a light receiving element such as a photodiode into a voltage signal and amplifies the voltage signal. In addition to the function of amplifying the photocurrent, the function of detecting the DC component (DC current amount) of the current signal input to the TIA is required.

  In general, as a method for detecting a direct current flowing in a circuit, a method of calculating a current by inserting a highly accurate resistor in a path through which a current to be detected flows and detecting a potential difference between both ends of the resistor. Is known (see, for example, Non-Patent Document 1). Specifically, as shown in FIG. 15, a resistor Rs is inserted into the current path of the circuit whose current is to be measured, and the voltage Vs across the resistor Rs is obtained, thereby detecting the current I flowing through the circuit to be measured. can do. When current is detected by this method, it is necessary to reduce the resistance value of the current detection resistor as much as possible in order to prevent the operation of the target circuit from being affected by the insertion of the current detection resistor. is there. However, when the resistance value of the current detection resistor is reduced, the detected voltage Vs is also reduced, and in many cases, an amplifier circuit for amplifying the voltage Vs is required. In addition, when the operation of the target circuit has an AC property, a low-pass filter or the like is required to extract only the DC component of the voltage Vs.

Also for TIA, by applying the above-described method, it is possible to detect the DC component of the current signal input to TIA. This will be specifically described below.
FIG. 16 is a diagram showing a circuit configuration of a conventional TIA.
A TIA 50 shown in FIG. 16 is connected to a base-grounded transistor Q whose base electrode is supplied with a fixed voltage Vbias, a load resistor R connected to the collector electrode of the transistor Q, and an emitter electrode of the transistor Q. And a constant current source Ibias and an input terminal IN for inputting an input current Iin connected to the emitter electrode of the transistor Q. The gain of the TIA 50 is mainly determined by the resistance value of the load resistor R. A TIA such as the TIA 50 is called a base-grounded TIA, and is disclosed in Non-Patent Document 2, for example.

  When detecting the DC component of the input current Iin of the TIA 50 shown in FIG. 15, for example, by inserting a current detection resistor Rs between the emitter electrode of the transistor Q and the input terminal IN, the input current Iin Can be extracted by converting the DC component into a voltage signal.

Behzad Razavi, “Analog CMOS Integrated Circuit Design and Application”, 2nd edition, published on May 31, 2003, Maruzen, P309 8.1.3. Rania H. Mekky et al., “Ultra Low-Power Low-Noise Transimpedance Amplifier for MEMS-Based Reference Oscillators”, Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference, pp345-348. Dieter Knollman, [online], March 02, 1998, EDN NETWORK, “Designing with op amps: Single-formula technique keeps it simple”, [May 18, 2015 search], Internet <URL: http: // www .edn.com / design / analog / 4341150 / Designing-with-op-amps-Single-formula-technique-keeps-it-simplewww.edn.com>

  However, the method for detecting the DC component of the input current of the TIA by inserting the above-described current detection resistor between the input terminal of the TIA and the emitter electrode of the transistor has the following problems.

  Generally, the DC component of the input current of TIA is about several mA at the maximum, so if the resistance for current detection is reduced, the voltage (output voltage) at both ends of the resistance will also be reduced. Absent. In addition, by inserting a resistor between the input terminal IN and the emitter electrode of the transistor Q1, the parasitic capacitance of the resistor may deteriorate the frequency characteristic of the TIA. Further, the inserted resistor becomes a noise source, and there is a possibility that the noise characteristics of the TIA are deteriorated. For these reasons, it is not preferable to insert a current detection resistor as a technique for detecting the DC component of the TIA input current.

  The present invention has been made in view of the above problems, and an object of the present invention is to accurately detect a direct current component of an input current of a TIA while suppressing an influence on the operation of the TIA.

  The current detection circuit according to the present invention converts a current signal input to the first main electrode (emitter electrode) side of an amplifying transistor whose control electrode is connected to a fixed potential into a voltage signal to convert the second signal of the amplifying transistor. A current detection circuit for detecting a DC component of a current signal of a transimpedance amplifier output from a main electrode (collector electrode) side, which includes a differential amplifier circuit (200) and an inverting input terminal (− ) And the output terminal (OUT) of the differential amplifier circuit, one end is connected to the inverting input terminal (−) of the differential amplifier circuit, and the other end is connected to the transimpedance amplifier. A first resistor (R4) to which a first voltage (VCC, VCCA) based on a first fixed potential (VCC) for supplying power is supplied, and one end connected to an inverting input terminal (−) of the differential amplifier circuit; The other end A second resistor (R5) to which a second voltage (GND) is supplied that is lower than the first fixed potential and is based on a second fixed potential (GND) that serves as a reference for the operation of the transimpedance amplifier, and one end of the differential amplifier circuit. A third resistor (R6) connected to the non-inverting input terminal (+) and supplied with a third voltage (Vout) based on a current (I2) flowing to the second main electrode (collector electrode) side of the amplifying transistor at the other end. ) And one end connected to the non-inverting input terminal (+) of the differential amplifier circuit, and the other end is a fourth voltage (Vb) based on the current (I3) flowing to the first main electrode (emitter electrode) side of the amplifying transistor. ) Is supplied to the fourth resistor (R7).

  In the current detection circuit (21), the voltage of the second main electrode (collector electrode) of the amplifying transistor is level-shifted and supplied to the other end of the third resistor as a third voltage, and the voltage of the first fixed potential is supplied. You may further have a level shift circuit (201) which carries out level shift and supplies it to the other end of said 1st resistance as a 1st voltage.

  In the current detection circuit (22, 22A), the first voltage input terminal (Pon) and the second voltage input terminal (Pop), one end is connected to the first voltage input terminal, and the other end is an inversion of the differential amplifier circuit. A fifth resistor (Ron) connected to the input terminal (−) and a sixth resistor connected at one end to the second voltage input terminal and connected at the other end to the non-inverting input terminal (+) of the differential amplifier circuit (Rop).

  In the above description, as an example, constituent elements on the drawing corresponding to the constituent elements of the invention are represented by reference numerals with parentheses.

  According to the present invention, it is possible to accurately detect the direct current component of the input current of the TIA while suppressing the influence on the operation of the TIA.

FIG. 1 is a diagram illustrating a configuration of a current detection circuit according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of a weighted addition / subtraction circuit. FIG. 3 is a diagram illustrating a configuration of the current detection circuit according to the second embodiment. FIG. 4 is a diagram illustrating a configuration of a current detection circuit according to the third embodiment. FIG. 5 is a diagram illustrating another configuration of the current detection circuit according to the third embodiment. FIG. 6 is a diagram illustrating a configuration of a current detection circuit according to the fourth embodiment. FIG. 7 is a diagram illustrating a configuration of a current detection circuit according to the fifth embodiment. FIG. 8 is a diagram showing the configuration of the current detection circuit according to the sixth embodiment. FIG. 9 is a diagram illustrating a configuration of a current detection circuit according to the seventh embodiment. FIG. 10 is a diagram illustrating an amplifier using a TIA having an offset adjustment function. FIG. 11 is a diagram illustrating a configuration of a current detection circuit according to the eighth embodiment. FIG. 12 is a diagram illustrating a configuration of a current detection circuit according to the ninth embodiment. FIG. 13 is a diagram illustrating a configuration of the current detection circuit according to the tenth embodiment. FIG. 14 is a diagram showing a configuration of the current detection circuit according to the eleventh embodiment. FIG. 15 is a diagram for explaining a conventional technique for detecting a direct current. FIG. 16 is a diagram showing a circuit configuration of a conventional TIA.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< Embodiment 1 >>
FIG. 1 is a diagram illustrating a configuration of a current detection circuit according to the first embodiment.
FIG. 1 illustrates a transimpedance amplifier (TIA) 10 that converts a current signal into a voltage signal, and a current detection circuit 20 that detects a DC component of the current signal input to the TIA 10.

  The TIA 10 and the current detection circuit 20 shown in the figure constitute part of an amplifier mounted on a receiving apparatus such as an optical communication system or a wireless communication system. More specifically, the TIA 10 and the current detection circuit 20 are, for example, a current signal converted from an optical signal sent from a transmission path (optical fiber) by light-current conversion of a photodiode in a receiving device of an optical communication system. Is converted into a voltage signal, and a part of an amplifier for linearly amplifying the voltage to a voltage amplitude at which a subsequent circuit (for example, an analog / digital converter and a digital signal processor) can operate is configured.

  The TIA 10 and the current detection circuit 20 shown in FIG. 1 can be realized, for example, as a semiconductor integrated circuit formed on a semiconductor substrate by a known HBT (Heterojunction Bipolar Transistor) manufacturing process. The TIA 10 and the current detection circuit 20 may be realized as a one-chip semiconductor device formed on one semiconductor substrate, or have a multichip configuration in which the TIA 10 and the current detection circuit 20 are formed on separate semiconductor substrates. It may be realized as a semiconductor device.

Hereinafter, the configurations of the TIA 10 and the current detection circuit 20 will be described in detail.
The TIA 10 is a grounded base type TIA that converts a current signal input to the first main electrode side of the transistor QA having a control electrode connected to a fixed potential into a voltage signal and outputs the voltage signal from the second main electrode side of the transistor QA. is there. The TIA 10 is connected between a power supply line VCC that supplies a power supply voltage VCC as a first fixed potential and a ground line GND that supplies a ground voltage (0 V) lower than the power supply voltage VCC as a second fixed potential. Yes.

  The TIA 10 is a so-called single-input / single-output TIA, and specifically includes a transistor QA, a resistor R2, an input terminal IN, and a constant current circuit 101.

  The transistor QA is an amplifying transistor in the transimpedance amplifier 10. The transistor QA is, for example, an HBT as described above. In the following embodiments, description will be made assuming that not only the transistor QA but also the other transistors constituting the transimpedance amplifier 10, the current detection circuit 20, and the like are HBTs. In the following embodiments, the base electrode, emitter electrode, and collector electrode in all transistors (HBT) including the transistor QA are the control electrode, first main electrode, and second main electrode of the transistor according to the present invention. It explains as corresponding to each.

  A fixed DC voltage (bias voltage) VbiasA is supplied to a base electrode as a control electrode of the transistor QA.

  The input terminal IN is a terminal for inputting an input signal (current signal) to the transimpedance amplifier 10, and is connected to an emitter electrode as a first main electrode of the transistor QA.

  The resistor R2 has one end connected to the power supply line VCC and the other end connected to a collector electrode as the second main electrode of the transistor QA.

  The constant current circuit 101 is a circuit for generating a constant current I2. Specifically, the constant current circuit 101 includes, for example, a transistor QB1 and a resistor R3.

  The collector electrode of the transistor QB1 is connected to the input terminal IN and the emitter electrode of the transistor QA. A fixed DC voltage (bias voltage) Vbiasb is supplied to the base electrode of the transistor QB1. The resistor R3 has one end connected to the emitter electrode of the transistor QB1 and the other end connected to the ground line GND.

Next, the current detection circuit 20 will be described.
The current detection circuit 20 is a circuit for detecting the DC component Iin of the current signal input to the input terminal IN of the TIA 10. As shown in FIG. 1, the current detection circuit 20 is realized by a multi-input weighted addition / subtraction circuit.

Specifically, the current detection circuit 20 includes an OP amplifier 200 serving as a differential amplifier circuit, signal input resistors R4 to R7, and a feedback (feedback) resistor Rf.
The feedback resistor Rf is connected between the inverting input terminal (−) of the OP amplifier 200 and the output terminal OUTS of the OP amplifier 200. The resistor R4 has one end connected to the inverting input terminal (−) of the OP amplifier 200 and the other end connected to the power supply line VCC. The resistor R5 has one end connected to the inverting input terminal (−) of the OP amplifier 200 and the other end connected to the ground line GND.

  One end of the resistor R6 is connected to the non-inverting input terminal (+) of the OP amplifier 200, and the other end is supplied with a voltage Vout based on a current flowing on the second main electrode (collector electrode) side of the transistor QA. Specifically, the other end of the resistor R6 is connected to a node to which the collector electrode of the transistor QA and the resistor R2 are connected.

  One end of the resistor R7 is connected to the non-inverting input terminal (+) of the OP amplifier 200, and the other end is supplied with a voltage Vb based on a current flowing on the first main electrode (emitter electrode) side of the transistor QA. Specifically, the other end of the resistor R7 is connected to a node to which the emitter electrode of the transistor QB1 and the resistor R3 are connected.

Hereinafter, the operation principle of the current detection circuit 20 will be described.
First, consider TIA10.
Assuming that no current flows from the TIA 10 to the current detection circuit 20 (the current flowing from the TIA 10 to the resistors R6 and R7 is zero), the input current Iin, the current I2 flowing to the resistor R2, and the current I3 flowing to the resistor R3 The relationship shown by the formula (1) is established between the two.

  Here, focusing only on the direct current components of the input current Iin, the current I2, and the current I3, the direct current component of the input current Iin (hereinafter, also referred to as “input direct current”) Idc is expressed by Expression (2).

Next, the current detection circuit 20 will be considered.
FIG. 2 is a diagram illustrating a configuration of a weighted addition / subtraction circuit as the current detection circuit 20.
In general, the gain for each input voltage of the weighted addition / subtraction circuit can be expressed by Expression (3).

Here, the resistor Ri is a resistor for signal input in the weighted addition / subtraction circuit (corresponding to each of the resistors R4 to R7 in FIG. 2).
At this time, the sum of the gains with respect to all input voltages input to the weighted addition / subtraction circuit can be expressed by Expression (4).

This is known as Daisy's Theorem (see Non-Patent Document 3, for example).
Here, p is a constant, and in the case of gain gain with respect to the input voltage input to the inverting input terminal (−) side, p = −1, and the input voltage input to the non-inverting input terminal (+) side. In the case of gain for p, p represents the total sum of gains of input voltages input to the non-inverting input terminal (+) side. Therefore, in particular, when the following equation (5) holds, the output voltage Vo of the weighted addition / subtraction circuit can be expressed by equation (6). Here, Rpk is a signal input resistance on the non-inverting input terminal (+) side, Rnk is a signal input resistance on the inverting input terminal (−) side, and Vpk is a non-inverting input terminal (+ ) Side is input voltage through the resistor Rpk, and Vnk is input voltage from the inverting input terminal (−) side through the resistor Rnk.

  This is applied to the weighted addition / subtraction circuit 20A shown in FIG. That is, when the relationship between the signal input resistors R4 to R7 and the feedback resistor Rf is expressed by Expression (7) based on Expression (5), the output voltage Vo of the weighted addition / subtraction circuit 20A is expressed by Expression (8). Can be expressed as

  From the above, as shown in FIG. 1, the TIA 10 and the current detection circuit 20 are connected so that “V4 = VCC, V5 = GND (= 0), V6 = Vout, V7 = Vb”. When the ratio of R4 to R7 is “R4: R5: R6: R7 = R2: R3: R2: R3”, the relationship between the output voltage Vo and the input DC current Idc is expressed by Expression (9). Here, k = R7 / R3 = R6 / R2.

  As understood from the equation (9), the current detection circuit 20 can obtain the voltage Vo proportional to the direct current component (input direct current Idc) of the current input to the TIA 10.

  However, it is necessary to set k to a sufficiently large value (for example, 100 or more) in order to prevent the TIA 10 from being affected by connecting the current detection circuit 20 to the TIA 10. That is, the resistors R4 to R7 need to be set to resistance values sufficiently larger than the resistors R2 and R3.

  As described above, according to the current detection circuit 20 according to the first embodiment, the voltage Vout based on the current I2 flowing to the collector electrode side of the amplifying transistor QA in the base-grounded TIA and the emitter electrode side of the amplifying transistor QA By performing weighted addition / subtraction using the voltage Vb based on the current I3 flowing through the current I3, the DC component of the current signal input to the TIA 10 is calculated from the difference between the DC component of the current I2 and the DC component of the current I3. The direct current component of the current signal input to the TIA 10 can be detected without affecting the characteristics.

<< Embodiment 2 >>
FIG. 3 is a diagram illustrating a configuration of the current detection circuit according to the second embodiment.
The current detection circuit 21 shown in the figure is different from the current detection circuit according to the first embodiment in that the voltage Vout output from the TIA 10 and the voltage obtained by level shifting the power supply voltage VCC are used as the input voltage of the current detection circuit. The remaining points are the same as those of the current detection circuit 20 according to the first embodiment. In the following description, components common to the current detection circuit 20 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 3, the current detection circuit 21 further includes a level shift circuit 201.
The level shift circuit 201 is a circuit that shifts (lowers) the voltage Vout and the power supply voltage VCC output from the TIA 10 by a predetermined voltage and outputs them. Specifically, as shown in FIG. 3, the level shift circuit 201 includes transistors QL1 and QL2 and constant current sources IL1 and IL2.

  The collector electrode of transistor QL1 is connected to power supply line VCC, and the emitter electrode of transistor QL2 is connected to one end of resistor R6. Further, the voltage Vout of the TIA 10 is supplied to the base electrode of the transistor QL1. Constant current source IL1 is connected between an emitter electrode of transistor QL1 and ground line GND.

  The collector electrode and base electrode of transistor QL2 are connected to power supply line VCC, and the emitter electrode of transistor QL2 is connected to one end of resistor R4. The constant current source IL2 is connected between the emitter electrode of the transistor QL2 and the ground line GND.

According to the level shift circuit 201, the voltage Vout_LS obtained by reducing the voltage Vout of the TIA 10 by the base-emitter voltage of the transistor QL1, and the voltage VCC_LS obtained by reducing the power supply voltage VCC by the base-emitter voltage of the transistor QL2, respectively. It can be input to a weighted addition / subtraction circuit.
According to this, an OP amplifier that does not support Rail to Rail operation can be used as the OP amplifier 200. For example, when the power supply voltage VCC is input as the input voltage of the OP amplifier 200 (weighted addition / subtraction circuit) that operates between the power supply voltage VCC and the ground voltage GND, the OP amplifier 200 does not support the Rail to Rail operation. The OP amplifier 200 cannot perform a normal amplification operation.
On the other hand, as can be understood from the above equation (2), the parameter necessary for detecting the DC component of the input current of the TIA 10 is “the difference between VCC and Vout”. This is the case where the OP amplifier 200 does not support Rail to Rail operation by inputting the voltage VCC_LS and the voltage Vout_LS obtained by level shifting the power supply voltage VCC and the voltage Vout to the OP amplifier 200 as in the current detection circuit 21. Normal amplification operation can be expected.

  In order to match the level shift amounts of the power supply voltage VCC and the voltage Vout, the current values of the constant current sources IL1 and IL2 are made equal, the transistor sizes of the transistors QL1 and QL2 are made the same, and the transistors QL1 and QL2 are It is necessary to arrange the layouts close to each other.

<< Embodiment 3 >>
FIG. 4 is a diagram illustrating a configuration of a current detection circuit according to the third embodiment.
The current detection circuit 22 shown in the figure relates to the first embodiment in that an offset component can be added to the voltage corresponding to the DC component of the input current of the TIA 10 as the output voltage Vo of the current detection circuit. The current detection circuit 20 is different from the current detection circuit 20 in other respects, and is the same as the current detection circuit 20 according to the first embodiment. In the following description, components common to the current detection circuit 20 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

As shown in FIG. 4, the current detection circuit 22 further includes terminals Pop and Pon for applying a voltage for offset adjustment, and resistors Ron and Rop.
A reference voltage Vof for offset adjustment is supplied to the terminal Pop. The terminal Pon is connected to the ground line GND.

  The resistor Ron has one end connected to the inverting input terminal (−) of the OP amplifier 200 and the other end connected to the ground line GND. The resistor Rop has one end connected to the non-inverting input terminal (+) of the OP amplifier 200 and the other end supplied with a reference voltage Vof for offset adjustment.

  Here, when Ron = Rop, if the equation (10) holds between the resistors R4 to R7, Rf, Ron, and Rop, the output voltage Vo of the current detection circuit 22 is expressed by the equation (11). Can be represented.

  As understood from the equation (11), according to the current detection circuit 22, the offset voltage (Rf / Rop) × Vof is set to a voltage proportional to the DC component (input DC current Idc) of the current input to the TIA 10. The applied voltage Vo can be obtained. The value of the offset voltage can be set to an arbitrary value by adjusting the values of the offset adjustment reference voltage Vof and the resistor Rop (= Ron).

If a negative offset amount is desired to be added, the voltages input to the resistor Ron and the resistor Rop may be switched as shown in FIG.
FIG. 5 is a diagram illustrating another configuration of the current detection circuit according to the third embodiment.
As shown in FIG. 5, in the current detection circuit 22A, the reference voltage Vof for offset adjustment is supplied to the other end of the resistor Ron, and the other end of the resistor Rop is connected to the ground line GND. Thereby, the output voltage Vo of the current detection circuit 22A can be expressed by Expression (12).

  As understood from the equation (12), according to the current detection circuit 22A, the offset voltage (Rf / Rop) × Vof is set to a voltage proportional to the DC component (input DC current Idc) of the current input to the TIA 10. A reduced voltage Vo can be obtained. The value of the offset voltage can be set to an arbitrary value by adjusting the values of the offset adjustment reference voltage Vof and the resistor Rop (= Ron), as in the case of the current detection circuit 22 of FIG. it can.

  As described above, according to the current detection circuits 22 and 22A according to the third embodiment, an arbitrary offset component can be added to the voltage proportional to the DC component of the current input to the TIA 10 (input DC current Idc). Since the value of the input DC current Idc is small, the relative error can be reduced even when the corresponding voltage (= (Rf / k) Vof) is small. Thereby, the current detection accuracy can be further improved.

<< Embodiment 4 >>
FIG. 6 is a diagram illustrating a configuration of a current detection circuit according to the fourth embodiment.
The current detection circuit 23 shown in the figure is different from the current detection circuit 22 according to the third embodiment in that it further includes a regulator circuit that generates a reference voltage for offset adjustment. This is the same as the current detection circuit 22 according to the third embodiment. In the following description, components common to the current detection circuit 22 according to the third embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 6, the current detection circuit 23 further includes a regulator circuit 202 that generates a reference voltage Vof for offset adjustment. The regulator circuit 202 is a circuit that generates a constant reference voltage Vof from the power supply voltage VCC, for example. The regulator circuit 202 may be realized, for example, as a semiconductor integrated circuit formed by an HBT process together with the addition / subtraction circuit portion in the current detection circuit 23.

  As described above, according to the current detection circuit 23 according to the fourth embodiment, compared to the case where the reference voltage Vof is generated from the power supply voltage VCC or the like by the resistance voltage dividing circuit or the like, the fluctuation of the power supply voltage VCC or the change of the surrounding environment (for example, Therefore, it is possible to generate a stable reference voltage Vof that is not easily affected by a change in temperature or the like. Therefore, it is expected that the operation stability of the current detection circuit 23 and the current detection accuracy are improved.

<< Embodiment 5 >>
FIG. 7 is a diagram illustrating a configuration of a current detection circuit according to the fifth embodiment.
The current detection circuit 24 shown in the figure is different from the current detection circuit 22 according to the third embodiment in that it further includes a digital / analog conversion circuit that generates a reference voltage for offset adjustment. This is the same as the current detection circuit 22 according to the third embodiment. In the following description, components common to the current detection circuit 22 according to the third embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 7, the current detection circuit 24 further includes a digital / analog conversion circuit (DAC) 203 that generates a reference voltage Vof for offset adjustment, and a regulator circuit (REG) 204 that generates a constant voltage VREG. Prepare.

  The DAC 203 is a circuit that generates an analog voltage signal corresponding to the digital signal Din by performing digital / analog conversion processing on the input multi-bit digital signal Din. The voltage signal generated by the DAC 203 is supplied to the other end of the resistor Rop as a reference voltage Vof for offset adjustment. A stable voltage VREG generated by the regulator circuit 204 is used as the power source of the DAC 203.

  The DAC 203 and the regulator circuit 204 may be realized as, for example, a semiconductor integrated circuit formed by an HBT process together with an addition / subtraction circuit portion in the current detection circuit 23, or formed by a known CMOS process or the like, You may implement | achieve as a semiconductor chip separate from an addition / subtraction circuit part.

  As described above, according to the current detection circuit 24 according to the fifth embodiment, similarly to the current detection circuit 23 according to the fourth embodiment, the influence of fluctuations in the power supply voltage VCC and changes in the surrounding environment (for example, changes in temperature, etc.) are affected. Since it is possible to generate a stable reference voltage Vof that is difficult to receive, it is expected that the operation stability of the current detection circuit 25 and the current detection accuracy are improved.

  In addition, since the power supply of the DAC 203 is set to the voltage VREG generated by the regulator circuit 204, fluctuations in the power supply of the DAC 203 can be suppressed, so that an improvement in the accuracy of digital / analog conversion processing by the DAC 203 can be expected.

<< Embodiment 6 >>
FIG. 8 is a diagram showing the configuration of the current detection circuit according to the sixth embodiment.
The current detection circuit 25 shown in the figure is different from the current detection circuit 22 according to the third embodiment in that the resistance values of the resistors Ron and Rop for inputting the reference voltage for offset adjustment are variable. Other points are the same as those of the current detection circuit 22 according to the third embodiment. In the following description, components common to the current detection circuit 22 according to the third embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As shown in FIG. 8, in the current detection circuit 25, variable resistors are used as the resistors Ron and Rop. For example, the resistors Ron and Rop may be configured by a circuit in which a plurality of resistors and switch elements are combined, and the entire resistance values of the resistors Ron and Rop can be changed by switching the switches.

  Similarly, in the current detection circuit 22A according to the third embodiment, the resistors Ron and Rof can be variable. As the reference voltage Vof applied to the resistor Rop (or resistor Ron), as exemplified in the fourth and fifth embodiments, a stable voltage generated by the regulator circuit 202, the DAC 203, or the like can be used.

  As described above, according to the current detection circuit 25 according to the sixth embodiment, by adjusting the resistance values of the resistors Ron and Rop, a voltage proportional to the DC component (input DC current Idc) of the current input to the TIA 10 is applied. The offset amount can be adjusted. Further, according to the current detection circuit 25, the offset amount can be arbitrarily adjusted in a wider range as compared with the case where the offset amount is adjusted by adjusting the value of the offset adjustment reference voltage Vof to be applied. .

<< Embodiment 7 >>
FIG. 9 is a diagram illustrating a configuration of a current detection circuit according to the seventh embodiment.
The current detection circuit 26 shown in the figure is capable of switching whether or not to add an offset amount to the voltage corresponding to the DC component of the input current of the TIA 10, according to the first embodiment. Unlike the circuit 20, the other points are the same as those of the current detection circuit 20 according to the first embodiment. In the following description, components common to the current detection circuit 20 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  Specifically, the current detection circuit 26 further includes terminals Pof1 to Pof4 for applying a voltage for offset adjustment, resistors Ron_1, Ron_2, Rop_1, Rop_2, and switches SW1 to SW4.

  A reference voltage Vof for offset adjustment is supplied to the terminal Pof1. A resistor Ron_1 and a switch SW1 are connected in series between the terminal Pof1 and the inverting input terminal (−) of the OP amplifier 200.

  The terminal Pof2 is connected to the ground line GND. A resistor Ron_2 and a switch SW2 are connected in series between the terminal Pof2 and the inverting input terminal (−) of the OP amplifier 200.

  A reference voltage Vof for offset adjustment is supplied to the terminal Pof3. A resistor Rop_1 and a switch SW3 are connected in series between the terminal Pof3 and the non-inverting input terminal (+) of the OP amplifier 200.

  The terminal Pof4 is connected to the ground line GND. A resistor Rop_2 and a switch SW4 are connected in series between the terminal Pof4 and the non-inverting input terminal (+) of the OP amplifier 200.

As the reference voltage Vof applied to the resistors Rop_1 and Ron_1, as illustrated in the fourth and fifth embodiments, a stable voltage generated by the regulator circuit 202, the DAC 203, or the like can be used.
In addition, the variable resistors exemplified in Embodiment 2 may be used as the resistors Ron_1, Ron_2, Rop_1, and Rop_2.

  According to the current detection circuit 26 according to the seventh embodiment, an offset amount ((() is obtained with respect to the voltage corresponding to the DC component of the input current of the TIA 10 to be detected by the combination of ON / OFF of the switches SW1 to SW4. Rf / Rop) × Vof) can be added, subtracted, or not added. According to this, for example, whether or not the offset amount is added and the offset amount can be adjusted according to the manufacturing variation of the circuit elements of the current detection circuit 26 caused by the semiconductor process.

<< Embodiment 8 >>
In the above embodiment, the current detection circuit that detects the direct current component of the input current of a general single input / single output type TIA is exemplified. However, in the following eighth to eleventh embodiments, it is different from the above TIA. Several current detection circuits for detecting the direct current component of the input current of the TIA having the circuit configuration are exemplified.

Here, as a current detection circuit according to the eighth embodiment, a current detection circuit for detecting a DC component of an input current of a TIA having an offset adjustment function is illustrated.
FIG. 10 is a diagram illustrating an amplifier using a TIA having an offset adjustment function.
The amplifier 40 shown in the figure includes TIAs 11_1 and 11_2 having two offset adjustment functions, a differential amplifier circuit (AMP) 41, a buffer circuit 42, and an offset adjustment circuit 43.

  The TIA11_1 is a circuit that converts one current signal Iin1 input to the terminal IN1 out of a pair of differential current signals into a voltage signal. The TIA11_2 is a circuit that converts the other current signal Iin2 input to the terminal IN2 out of the differential current signals into a voltage signal.

  The differential amplifier circuit 41 is a circuit that amplifies the difference between the voltage signals output from the two TIAs 11_1 and 11_2. The buffer circuit 42 is an output circuit of the amplifier 40 that outputs the signal amplified by the differential amplifier circuit 41.

  An offset adjustment circuit (AOC: Auto Offset Control) 43 detects a difference between the output voltages of the differential amplifier circuit 41, generates an offset adjustment signal Vx according to the difference, and feeds back each of the two TIAs 11_1 and 11_2. By doing this, the circuit cancels the offset of the two TIAs 11_1 and 11_2 due to manufacturing variations, input conditions, and the like.

FIG. 11 shows a current detection circuit for detecting the input DC current of the TIAs 11_1 and 11_2.
In the figure, a current detection circuit 27 for detecting the direct current component of the input current Iin1 of the TIA11_1 is representatively shown out of the two TIA11_1 and TIA11_2. The circuit configurations of TIA11_2 and TIA11_2 are the same, and the current detection circuit for detecting the DC component of the input current Iin2 is also the same as the current detection circuit 27. Therefore, the current detection circuit on the TIA11_2 side is illustrated and Detailed description is omitted. In FIG. 11, the same components as those shown in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  As illustrated in FIG. 11, the TIA 11_1 includes a constant current circuit 102 instead of the constant current circuit 101. Specifically, the constant current circuit 102 includes transistors QB1 and QB2 and resistors R3 and R3x.

  The collector electrode of the transistor QB2 is connected to the input terminal IN and the collector electrode of the transistor QB1. An offset adjustment signal Vx is supplied from the offset adjustment circuit 43 to the base electrode of the transistor QB2. The resistor R3x has one end connected to the emitter electrode of the transistor QB2 and the other end connected to the ground line GND.

  By connecting the transistor QB2 and the resistor R3x as described above, a variable current source in which the current I3x changes according to the signal Vx is formed. Accordingly, in TIA11_1, “Iin = I3 + I3x−I2” is established, and therefore, the input DC current Idc of the current Iin1 input to the TIA11_1 can be expressed by Expression (13).

  Therefore, in the current detection circuit 27, in addition to the configuration of the current detection circuit 20 according to the first embodiment, a resistor R8 and a resistor 9 are further provided.

  The resistor R8 has one end connected to the inverting input terminal (−) of the OP amplifier 200 and the other end connected to the ground line GND. One end of the resistor R9 is connected to the non-inverting input terminal (+) of the OP amplifier 200, and the other end is supplied with a voltage Vbx of a node to which the resistor R3x and the emitter electrode of the transistor QB2 are connected.

  As described above, in addition to the voltage (Vout, VCC) at both ends of the resistor R2 and the voltage (Vb, GND) at both ends of the resistor R3, the voltage at both ends of the resistor R3x, that is, the voltage Vbx and the ground voltage GND are added and subtracted. As a result, the component (current I3x) corresponding to “Vbx / R3x” in the above equation (13) can be calculated.

  As described above, according to the current detection circuit 27 according to the eighth embodiment, the DC component of the input current can be accurately detected even for the TIAs 11_1 and 11_2 having the offset adjustment function.

<< Embodiment 9 >>
FIG. 12 is a diagram illustrating a configuration of a current detection circuit according to the ninth embodiment.
In FIG. 12, the same components as those in the circuits described in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof is omitted.
The TIA 12 shown in the figure is a TIA in which the gain of the TIA can be adjusted by the bias voltage Vbias1 and the bias voltage Vbias2.

Specifically, the TIA 12 further includes a transistor QB and a resistor R2x.
The transistor QB has an emitter electrode connected to the input terminal IN and the emitter electrode of the transistor QB1, and a bias voltage VbiasB is supplied to the base electrode.

  The resistor R2x has one end connected to the collector electrode of the transistor QB and the other end connected to a node where the collector electrode of the transistor QA and the resistor R2 are connected.

  Thereby, in TIA12, it becomes "Iin = I3-I2" similarly to TIA10. Therefore, the current detection circuit 28 also has a circuit configuration similar to that of the current detection circuit 20 according to the first embodiment. That is, in the current detection circuit 28, the other end of the resistor R4 is connected to the power supply line VCC, the other end of the resistor R5 is connected to the ground line GND, and the other end of the resistor R6 includes a resistor R2 and a resistor R2x. The voltage of the node to be connected is supplied, and the voltage of the node to which the emitter electrode of the transistor QB1 and the resistor R2 are connected is supplied to the other end of the resistor R7.

  As described above, according to the current detection circuit 28 according to the ninth embodiment, the DC component of the input current can be detected in the same manner as the current detection circuit 20 according to the first embodiment.

<< Embodiment 10 >>
FIG. 13 is a diagram illustrating a configuration of the current detection circuit according to the tenth embodiment.
In FIG. 13, the same components as those shown in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof is omitted.

The TIA 13 shown in the figure further includes a transistor QC and a resistor R2c.
In the transistor QC, the emitter electrode is connected to the collector electrode of the transistor QB1, and the bias voltage VbiasC is supplied to the base electrode. The resistor R2c has one end connected to the collector electrode of the transistor QC and the other end connected to the power supply line VCC.
Thereby, in TIA13, since "Iin = I3-I2-Ic", input DC current Idc of current Iin input to TIA13 can be expressed by Expression (14).

  Therefore, in the current detection circuit 29, a resistor R8 and a resistor 9 are further provided in addition to the configuration of the current detection circuit 20 according to the first embodiment.

  The resistor R8 has one end connected to the inverting input terminal (−) of the OP amplifier 200 and the other end connected to the power supply line VCC. One end of the resistor R9 is connected to the non-inverting input terminal (+) of the OP amplifier 200, and the other end is connected to the resistor R2c and the collector electrode of the transistor QC.

  As described above, in addition to the voltage across the resistor R2 (Vout, VCC) and the voltage across the resistor R3 (Vb, GND), the voltage across the resistor R2c, that is, the voltage Vpk and the power supply voltage VCC are added and subtracted. As a result, the components (current Ic) corresponding to “Vpk / R2c” and “VCC / R2c” in the equation (14) can be calculated.

  As described above, according to the current detection circuit 29 according to the tenth embodiment, the DC component of the input current can be detected even for the TIA 13.

<< Embodiment 11 >>
FIG. 14 is a diagram showing a configuration of the current detection circuit according to the eleventh embodiment.
In FIG. 14, the same components as those shown in the other embodiments described above are denoted by the same reference numerals, and detailed description thereof is omitted.
The TIA 14 shown in the figure is a transimpedance amplifier having a wider band than the TIA 10. Specifically, the TIA 14 has an inductor L connected between the resistor R2 and the power supply line VCC.

In the TIA 14, the input current Iin is “Iin = I3−I2” similarly to the TIA10.
Here, although there is a resistance component also in the inductor L, since the value of the resistance component cannot be accurately obtained at the design stage, the current detection circuit 30 uses the resistor R2 to calculate the component of the current I2. Are input to a current detection circuit 30 as an addition / subtraction circuit. Specifically, as shown in FIG. 14, the other end of the resistor R4 is connected to a node to which the inductor L and the resistor R2 are connected, and the other end of the resistor R6 is connected to the resistor R2 and the collector electrode of the transistor QA. Connect to the node to which is connected. Thereby, regardless of the inductor L, the component corresponding to the current I2 can be calculated.

  As described above, according to the current detection circuit 30 according to the eleventh embodiment, the TIA 14 having the configuration in which the inductor L is connected in series to the resistor R2 as the load is the same as the current detection circuit 20 according to the first embodiment. In addition, the DC component of the input current can be detected.

  Although the invention made by the present inventors has been specifically described based on the embodiment, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the scope of the invention. Yes.

  For example, in the above embodiment, the case where each of the transistors (Q1 and the like) constituting the TIA 10 to 14 and the current detection circuits 20 to 30 is an HBT. An NPN bipolar transistor or an N-type field effect transistor typified by a MOS (metal-oxide-semiconductor) FET may be used.

  The characteristic structures shown in each embodiment can be combined with the structures shown in other embodiments as appropriate. For example, the level shift circuit 201 shown in the second embodiment may be combined with each of the current detection circuits 22 to 30 shown in the third to eleventh embodiments, or the current detection circuit shown in the eighth to eleventh embodiments. 27 to 30 may be combined with the resistors Ron and Rop for offset adjustment shown in the third embodiment.

  In the above embodiment, the case where the first fixed potential is the power supply voltage VCC and the second fixed potential is the ground voltage has been described as an example. However, the first fixed potential only needs to be higher than the second fixed potential. It is not limited to the combination. For example, the second fixed potential may be a negative potential (<0V).

  10, 11, 12, 13, 14 ... TIA, 20-30 ... current detection circuit, IN ... input terminal, Pop, Pon, Pof1 to Pof2 ... terminal, 101,102 ... constant current circuit, 201 ... level shift circuit, 202 , 204 ... regulator circuit, 203 ... DAC, R2, R3, R4 to R4, Rf, Ron, Rop, Ron_1, Ron_2, Rop_1, Rop_2, R3x, R2b, R2c ... resistors, QA to QC, QB1, QB2, QL1, QL2 ... transistor, IL1, IL2 ... constant current source, L ... inductor.

Claims (12)

The current of the transimpedance amplifier that converts the current signal input to the first main electrode side of the amplifying transistor whose control electrode is connected to a fixed potential into a voltage signal and outputs the voltage signal from the second main electrode side of the amplifying transistor. A current detection circuit for detecting a DC component of a signal,
A differential amplifier circuit;
A feedback resistor connected between an inverting input terminal of the differential amplifier circuit and an output terminal of the differential amplifier circuit;
A first resistor having one end connected to the inverting input terminal of the differential amplifier circuit and the other end supplied with a first voltage based on a first fixed potential for supplying power to the transimpedance amplifier;
One end is connected to the inverting input terminal of the differential amplifier circuit, and the other end is supplied with a second voltage that is lower than the first fixed potential and based on a second fixed potential serving as a reference for the operation of the transimpedance amplifier. A second resistor;
A third resistor having one end connected to the non-inverting input terminal of the differential amplifier circuit and the other end supplied with a third voltage based on a current flowing to the second main electrode side of the amplifying transistor;
One end is connected to the non-inverting input terminal of the differential amplifier circuit, and the other end has a fourth resistor to which a fourth voltage based on a current flowing to the first main electrode side of the amplification transistor is supplied. A current detection circuit. The current detection circuit according to claim 1,
The voltage of the second main electrode of the amplifying transistor is level-shifted and supplied as the third voltage to the other end of the third resistor, and the voltage of the first fixed potential is level-shifted and the first voltage A current detection circuit further comprising: a level shift circuit that supplies the other end of the first resistor. In the current detection circuit according to claim 1 or 2,
A first voltage input terminal and a second voltage input terminal;
A fifth resistor having one end connected to the first voltage input terminal and the other end connected to the inverting input terminal of the differential amplifier circuit;
A current detection circuit, further comprising: a sixth resistor having one end connected to the second voltage input terminal and the other end connected to a non-inverting input terminal of the differential amplifier circuit. The current detection circuit according to claim 3,
A regulator circuit for generating a reference voltage;
The reference voltage generated by the regulator circuit is supplied to one of the first voltage input terminal and the second voltage input terminal;
The current detection circuit, wherein the second voltage is supplied to the other of the first voltage input terminal and the second voltage input terminal. The current detection circuit according to claim 3,
A digital / analog conversion circuit for generating a reference voltage corresponding to the input digital signal;
The reference voltage generated by the digital / analog conversion circuit is supplied to one of the first voltage input terminal and the second voltage input terminal;
The current detection circuit, wherein the second voltage is supplied to the other of the first voltage input terminal and the second voltage input terminal. The current detection circuit according to any one of claims 3 to 5,
The current detection circuit, wherein the fifth resistor and the sixth resistor are variable resistors. In the current detection circuit according to claim 1 or 2,
A first voltage input terminal, a second voltage input terminal, a third voltage input terminal, and a fourth voltage input terminal;
A fifth resistor and a first switch connected in series between the first voltage input terminal and the inverting input terminal;
A sixth resistor and a second switch connected in series between the second voltage input terminal and the inverting input terminal;
A seventh resistor and a third switch connected in series between the third voltage input terminal and the non-inverting input terminal;
The current detection circuit further comprising: an eighth resistor and a fourth switch connected in series between the fourth voltage input terminal and the non-inverting input terminal. In the current detection circuit according to any one of claims 1 to 7,
The transimpedance amplifier is
A first transistor as the amplifying transistor, wherein a first bias voltage is supplied to the control electrode;
A load resistor connected between the second main electrode of the first transistor and the first fixed potential;
An input terminal connected to a first main electrode of the first transistor;
A second transistor in which a second bias voltage is supplied to the control electrode, and a second main electrode is connected to the first main electrode and the input terminal of the first transistor;
A bias resistor connected between the first main electrode of the second transistor and the second fixed potential;
A voltage at a node to which the second main electrode of the first transistor and the load resistor are connected is supplied to the other end of the third resistor as the third voltage;
The voltage of a node to which the first main electrode of the second transistor and the bias resistor are connected is supplied to the other end of the fourth resistor as the fourth voltage. The current detection circuit according to claim 1,
A fifth resistor having one end connected to the inverting input terminal of the differential amplifier circuit;
A sixth resistor having one end connected to the non-inverting input terminal of the differential amplifier circuit;
The transimpedance amplifier is
A first transistor as the amplifying transistor in which a first bias voltage is supplied to the control electrode;
A load resistor connected between the second main electrode of the first transistor and the first fixed potential;
An input terminal connected to a first main electrode of the first transistor;
A second transistor in which a second bias voltage is supplied to the control electrode and a second main electrode is connected to the input terminal;
A third transistor in which a signal for offset adjustment is supplied to the control electrode, and a second main electrode is connected to the input terminal;
A first bias resistor connected between the first main electrode of the second transistor and the second fixed potential;
A second bias resistor connected between the first main electrode of the third transistor and the second fixed potential;
A voltage at a node to which the second main electrode of the first transistor and the first load resistor are connected is supplied to the other end of the third resistor as the third voltage;
A voltage at a node to which the first main electrode of the second transistor and the first bias resistor are connected is supplied to the other end of the fourth resistor as the fourth voltage;
The second voltage is supplied to the other end of the fifth resistor;
The voltage of a node to which the first main electrode of the third transistor and the second bias resistor are connected is supplied to the other end of the sixth resistor. The current detection circuit according to claim 1,
The transimpedance amplifier is
A first transistor as the amplification transistor in which a first bias voltage is supplied to the control electrode;
A second transistor as the amplifying transistor, wherein a second bias voltage is supplied to the control electrode, and the first main electrode is connected to the first main electrode of the first transistor;
A first load resistor having one end connected to the first fixed potential and the other end connected to the first main electrode of the first transistor;
A second load resistor connected between the other end of the first load resistor and a second main electrode of the second transistor;
An input terminal connected to the first main electrode of the first transistor and the first main electrode of the second transistor;
A third transistor in which a third bias voltage is supplied to the control electrode and a second main electrode is connected to the input terminal;
A bias resistor connected between the first main electrode of the third transistor and the second fixed potential;
A voltage at a node to which the first load resistor and the second load resistor are connected is supplied to the other end of the third resistor as the third voltage;
The voltage of a node to which the first main electrode of the third transistor and the bias resistor are connected is supplied to the other end of the fourth resistor as the fourth voltage. The current detection circuit according to claim 1,
A fifth resistor having one end connected to the inverting input terminal of the differential amplifier circuit;
A sixth resistor having one end connected to the non-inverting input terminal of the differential amplifier circuit;
The transimpedance amplifier is
A first load resistor having one end connected to the first fixed potential;
A second load resistor having one end connected to the first fixed potential;
A first transistor as the amplification transistor in which a first bias voltage is supplied to the control electrode and a second main electrode is connected to the other end of the first load resistor;
A second transistor in which a second bias voltage is supplied to the control electrode, a second main electrode is connected to the other end of the second load resistor, and a first main electrode is connected to the second main electrode of the first transistor; ,
An input terminal connected to a first main electrode of the first transistor;
A third transistor in which a third bias voltage is supplied to the control electrode and a second main electrode is connected to the input terminal and the first main electrode of the first transistor;
A bias resistor connected between the first main electrode of the third transistor and the second fixed potential;
A voltage at a node to which the second main electrode of the first transistor and the first load resistor are connected is supplied to the other end of the third resistor as the third voltage;
A voltage at a node to which the first main electrode of the third transistor and the bias resistor are connected is supplied to the other end of the fourth resistor as the fourth voltage;
The first voltage is supplied to the other end of the fifth resistor;
A current detection circuit , wherein a voltage of a node to which the second main electrode of the second transistor is connected to the second load resistor is supplied to the other end of the sixth resistor.
The current detection circuit according to claim 1,
The transimpedance amplifier is
A first transistor in which a first bias voltage is supplied to the control electrode;
A load resistor having one end connected to the second main electrode of the first transistor;
An inductor having one end connected to the first fixed potential and the other end connected to the other end of the second load resistor;
An input terminal connected to a first main electrode of the first transistor;
A second transistor in which a second bias voltage is supplied to the control electrode and a second main electrode is connected to the input terminal;
A bias resistor connected between the first main electrode of the second transistor and the second fixed potential;
A voltage of a node to which the inductor and the load resistor are connected is supplied to the other end of the first resistor as the first voltage,
A voltage at a node to which the second main electrode of the first transistor and the load resistor are connected is supplied to the other end of the third resistor as the third voltage;
The voltage of a node to which the first main electrode of the second transistor and the bias resistor are connected is supplied to the other end of the fourth resistor as the fourth voltage.

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