JP2015170776A - Nitride semiconductor laminate and field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor laminate, having high breakdown voltage, capable of reducing a vertical direction leakage current and to provide a field effect transistor.SOLUTION: The field effect transistor includes a nitride semiconductor laminate formed by laminating on a substrate (1) a buffer layer (2), a first nitride semiconductor layer (3), a second nitride semiconductor layer (4), and a barrier layer (5) in this order. C concentration on a front surface side of the buffer layer (2) is equal to or more than 1.0×10^19/cm.

Description

  The present invention relates to a nitride semiconductor multilayer body and a field effect transistor, and more particularly to a nitride semiconductor multilayer body and a field effect transistor that can reduce leakage current and improve breakdown voltage when a high voltage is applied.

  Since the nitride semiconductor multilayer body is characterized by having a high breakdown voltage and high carrier mobility, it is expected to be used in applications such as power devices.

  A field effect transistor formed from a nitride semiconductor stacked body used for a power device or the like is desired to have a high breakdown voltage and a small leakage current particularly in an off state when a high voltage is applied.

  Nitride semiconductor multilayer structure that achieves a good balance between reduction in the in-plane direction between the source and drain, that is, lateral leakage current, and lateral breakdown voltage characteristics, and improvement in the depth direction, that is, longitudinal breakdown voltage Is disclosed in JP 2010-245504 A (Patent Document 1).

JP2010-245504

  However, even in the structure of the nitride semiconductor stacked body described in Patent Document 1, in the off state when a high voltage exceeding 300 V is applied, a phenomenon in which a vertical leakage current flows from the drain to the back surface of the substrate occurs. The present inventor has found that the problem that the withstand voltage decreases as the current increases cannot be sufficiently solved.

  Accordingly, an object of the present invention is to provide a nitride semiconductor multilayer body and a field effect transistor in which the vertical leakage current flowing on the back surface of the substrate is reduced to improve the breakdown voltage.

In order to solve the above problems, the nitride semiconductor laminate of the present invention is
A buffer layer made of a nitride semiconductor layer provided on a substrate;
A first nitride semiconductor layer stacked on the buffer layer;
A second nitride semiconductor layer stacked on the first nitride semiconductor layer;
A barrier layer made of a nitride semiconductor layer stacked on the second nitride semiconductor layer,
The C concentration on the surface side of the buffer layer is 1.0 × 10 ^ 19 / cm ³ or more.

In this specification, 10 ^x is expressed as “10 ^ X”. Here, X is an arbitrary number.

In one embodiment,
The C concentration of the first nitride semiconductor layer is 4.0 × 10 ^ 18 / cm ³ or more over the entire depth direction.

In one embodiment,
The C concentration on the second nitride semiconductor layer side of the first nitride semiconductor layer is 1.5 × 10 ^ 19 / cm ³ or more.

In one embodiment,
The C concentration of the first nitride semiconductor layer increases from the buffer layer side toward the second nitride semiconductor layer side.

The field effect transistor of the present invention is
The nitride semiconductor laminate;
A source electrode and a drain electrode that are spaced apart from each other on the nitride semiconductor laminate;
It is characterized by comprising a gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor multilayer body.

  As described above, according to the present invention, it is possible to have a high withstand voltage and reduce a substrate back surface leakage current in an off state when a high voltage is applied.

It is typical sectional drawing of 1st Embodiment of the nitride semiconductor laminated body of this invention. It is a schematic diagram of the pattern which measures the vertical direction leakage current and the proof pressure of the nitride semiconductor laminated body of the said 1st Embodiment. It is a longitudinal direction leakage current measurement result of the nitride semiconductor laminated body of the said embodiment. It is typical sectional drawing of the field effect transistor of 2nd Embodiment of this invention. In the nitride semiconductor laminated body of a comparative example, it is a leak characteristic IV curve of the drain leak current Id, the gate leak current Ig, and the substrate back surface leak current Isub when the drain voltage Vd is changed in the off state. In the field effect transistor of the present invention, the drain leakage current Id, the gate leakage current Ig when the drain voltage Vd is changed in the off state in a structure in which the substrate back surface leakage current is suppressed to one-twentieth or less of the drain leakage current, It is a leakage characteristic IV curve of the substrate back surface leakage current Isub. In the field effect transistor of the present invention in which the substrate back surface leakage current is suppressed as compared with FIG. 6 and is 1/100 or less of the drain leakage current, the drain leakage current Id and the gate leakage current when the drain voltage Vd is changed in the off state. It is a leakage characteristic IV curve of Ig and a substrate back surface leakage current Isub. In the field effect transistor of the present invention in which the substrate back surface leakage current is further suppressed than in FIG. 7, the leakage characteristics of the drain leakage current Id, the gate leakage current Ig, and the substrate back surface leakage current Isub when the drain voltage Vd is changed in the off state. IV curve. 6 is a graph showing the relationship between the maximum value of substrate back surface leakage current Isub and the C concentration on the buffer layer side of the first nitride semiconductor layer. 6 is a graph showing the relationship between the maximum value of substrate back surface leakage current Isub and the C concentration of the first nitride semiconductor layer on the second nitride semiconductor layer side. It is the graph which showed the relationship between the maximum value of board | substrate back surface leakage current Isub, and C density | concentration on the surface side of a buffer layer. It is a figure showing C density | concentration in conditions A, B, C, and D. FIG.

(First embodiment)
FIG. 1 is a schematic cross-sectional view showing an example of a nitride semiconductor multilayer body according to the first embodiment of the present invention.

  As shown in FIG. 1, the nitride semiconductor multilayer body according to the first embodiment has a buffer layer 2, a first nitride semiconductor layer 3, a second nitride semiconductor layer 4, and a barrier layer 5 on a substrate 1. Are stacked in this order. The buffer layer 2, the first nitride semiconductor layer 3, the second nitride semiconductor layer 4 and the barrier layer 5 are made of a nitride semiconductor.

  As the substrate 1, a silicon substrate is used in the first embodiment. The substrate 1 is acceptable as long as a nitride semiconductor layer can be stacked. For example, a sapphire substrate, a GaN substrate, a SiC substrate, or the like may be used.

In the first embodiment, the buffer layer 2 is an example in which an AlN layer 2a and an Al _x Ga _1-x N (0 ≦ x <1) layer 2b are alternately stacked as an example of a nitride semiconductor layer. The nitride semiconductor layer has a lattice structure and has a thickness of 2.3 μm. The main purpose of the buffer layer 2 is to ensure a breakdown voltage from the upper part of the nitride semiconductor multilayer body to the substrate 1, as long as it satisfies the required breakdown voltage of the nitride semiconductor multilayer body. In the present invention, the surface side of the buffer layer 2 (the region of the buffer layer 2 closest to the first nitride semiconductor layer 3) is 1.0 × 10 ^ 19 / cm ³ or more, preferably The C concentration is 1.5 × 10 ^ 19 / cm ³ or more. The surface side of the buffer layer 2 preferably has a C concentration of 1.0 × 10 ^ 21 / cm ³ or less. If the C concentration on the surface side of the buffer layer 2 exceeds 1.0 × 10 ^ 21 / cm ³ , the crystallinity of the nitride semiconductor deteriorates, and there is a case where the breakdown voltage decreases or the leakage starts to occur. It is.

  Although not shown, an AlN layer, for example, may be formed between the buffer layer 2 and the substrate 1 as a base layer for crystal growth.

In the first embodiment, the first nitride semiconductor layer 3 is a GaN layer having a high C concentration and has a thickness of 840 nm. The main purpose of the first nitride semiconductor layer 3 is to reduce leakage between the source and drain below the second nitride semiconductor layer 4 and has a high electrical resistance. The first nitride semiconductor layer 3 has a C concentration of 4.0 × 10 18 / cm ³ or more, preferably 4.9 × 10 18 / cm ³ or more over the entire region. Further, the C concentration of the first nitride semiconductor layer 3 on the second nitride semiconductor layer 4 side (the region of the first nitride semiconductor layer 3 closest to the second nitride semiconductor layer 4) is 1 .5 × 10 ^ 19 / cm ³ or more, preferably 1.8 × 10 ^ 19 / cm ³ or more. Further, the second nitride semiconductor layer 4 side of the first nitride semiconductor layer 3 preferably has a C concentration of 1.0 × 10 ^ 21 / cm ³ or less. When the C concentration of the first nitride semiconductor layer 3 on the second nitride semiconductor layer 4 side exceeds 1.0 × 10 ^ 21 / cm ³ , the crystallinity of the nitride semiconductor deteriorates and the breakdown voltage decreases. This is because an increase in leakage may start to occur.

  Further, the C concentration distribution in the depth direction of the first nitride semiconductor layer 3 increases from the buffer layer 2 side toward the second nitride semiconductor layer 4 side. That is, the C concentration of the first nitride semiconductor layer 3 increases as it approaches the second nitride semiconductor layer 4 side from the buffer layer 2 side. This has an effect on compensation of carriers caused by lattice mismatch between the buffer layer 2 having a superlattice structure and the first nitride semiconductor layer 3 that is a GaN layer, and leads to reduction of leakage current.

In the first embodiment, the second nitride semiconductor layer 4 is a GaN layer with a low C concentration and has a thickness of 800 nm. This second nitride semiconductor layer 4 functions as a channel. The C concentration of the second nitride semiconductor layer 4 is preferably as low as possible, and is preferably 1 × 10 ^ 17 / cm ³ or less. When the C concentration is high, when a field effect transistor is fabricated using this nitride semiconductor multilayer body, a collapse phenomenon is likely to occur in which the on-resistance during high-voltage operation is higher than the on-resistance during low-voltage operation. It is because it ends up.

  In the first embodiment, the barrier layer 5 is an AlGaN layer having an Al mixed crystal ratio of about 17% and a thickness of 34 nm. A heterojunction is formed between the second nitride semiconductor layer 4 and the barrier layer 5, and a two-dimensional electron gas (2DEG) 41 is formed on the second nitride semiconductor layer 4 side of the interface. . When the second nitride semiconductor layer 4 is in the on state, electrons flow through 2DEG 41. When the second nitride semiconductor layer 4 is in the off state, a depletion layer is formed below the gate electrode, and electrons do not flow. The Al mixed crystal ratio of the barrier layer 5 is an example, and it is possible if 2DEG 41 is generated between the second nitride semiconductor layer 4 and the barrier layer 5.

  Although not shown, an AlN layer may be formed between the second nitride semiconductor layer 4 and the barrier layer 5 as a spacer layer for improving mobility in the 2DEG 41.

  Although not shown, a GaN layer may be formed on the barrier layer 5 as a cap layer. The cap layer is for preventing the oxidation of Al in the AlGaN of the barrier layer 5 and for preventing the incorporation of impurities. The cap layer and the second nitride semiconductor layer are made of the AlGaN barrier layer 5. Therefore, it is possible to prevent the distortion of the barrier layer 5 due to the difference in lattice constant.

  In the first embodiment, as shown in FIG. 12, the entire area in the thickness direction of the first nitride semiconductor layer 3, the second nitride semiconductor layer 4 side of the first nitride semiconductor layer, and the buffer layer 2. The C concentration on the surface side of was set. In FIG. 12, the present invention is Condition B, Condition C, and Condition D, and Condition A is a comparative example.

  In order to measure the longitudinal leakage current of the nitride semiconductor laminate, measurement was performed using a pattern as shown in FIG.

  Ohmic electrodes 10 are formed on the nitride semiconductor multilayer body according to the first embodiment so as to be in contact with 2DEG 41. The ohmic electrodes 10, 10 are formed by etching a 1 mm × 1 mm square frame on the barrier layer 5 and the second nitride semiconductor layer 4, cutting 2DEG 41 outside the square frame, and within the square frame Provided. Further, an insulating film 21 is formed on the barrier layer 5 where the ohmic electrodes 10 and 10 are not provided, on the first nitride semiconductor layer 3 and the like, thereby electrically insulating them.

  The leakage current and breakdown voltage between 2DEG 41 and the substrate 1 were measured by setting the back surface of the substrate 1 to 0 V and applying a voltage to the ohmic electrodes 10 and 10 with respect to the nitride semiconductor laminate having the pattern of FIG. .

  The result is shown in FIG. The vertical axis in FIG. 3 is the vertical leakage current between the 2DEG 41 and the back surface of the substrate 1, and the horizontal axis is the voltage applied to the ohmic electrodes 10 and 10. As shown in FIG. 3, in condition A (see FIG. 12), the vertical leakage current increases rapidly from around 250V, whereas in conditions B, C, and D, up to about 800V is not destroyed. It can be seen that the current falls within a certain vertical leakage current.

  When the leakage path of the vertical leakage current flowing between the 2DEG 41 and the back surface of the substrate 1 is analyzed, the 2DEG 41 passes through the second nitride semiconductor layer 4 and then passes through the first nitride semiconductor layer 3. Then, after flowing to the interface between the first nitride semiconductor layer 3 and the buffer layer 2, it flows in the in-plane direction at the interface between the first nitride semiconductor layer 3 and the buffer layer 2, and thereafter the measurement pattern It has been clarified for the first time by the inventors that the material flows to the back surface of the substrate 1 through a longitudinally broken portion, a chip side surface, a wafer side surface, or the like, which is located on the outer side.

  The phenomenon in which the vertical leakage current is generated is that the leakage path does not pass directly through the buffer layer 2 in spite of the presence of the buffer layer 2 for ensuring the substrate breakdown voltage, and the above-mentioned insulating weak points are caused. Means. Therefore, when the above phenomenon occurs, it means that the vertical breakdown voltage is supported not by the buffer layer 2 but by the first nitride semiconductor layer 3, and this phenomenon is caused by a decrease in vertical breakdown voltage and vertical leakage. This is thought to be the cause of the increase in current.

  In the present invention, the surface concentration of the buffer layer 2 and the C concentration of the first nitride semiconductor layer 3 are controlled as a method of improving the vertical breakdown voltage of the semiconductor and reducing the vertical leakage current.

In the first embodiment, the C concentration on the surface side of the buffer layer 2 (the region of the buffer layer 2 closest to the first nitride semiconductor layer 3) is 1.0 × 10 ^ 19 / cm ³ or more ( (Corresponding to condition B), desirably 1.5 × 10 ^ 19 / cm ³ or more (corresponding to condition C), and by eliminating the low resistance portion on the surface side of the buffer layer 2, the vertical leakage current, that is, the substrate Back surface leakage current is reduced.

  This is because the leakage current near the surface of the buffer layer 2 can be reduced by increasing the C concentration on the surface side of the buffer layer 2, and the low resistance portion on the surface side of the buffer layer 2 is eliminated. Since it is possible to prevent a high electric field from being applied to the first nitride semiconductor layer 3, it is considered that the breakdown voltage can be improved.

In the first embodiment of the present invention, the C concentration over the entire thickness direction of the first nitride semiconductor layer 3 is 4.0 × 10 ^ 18 / cm ³ or more (corresponding to the condition B), preferably 4.9 × 10 ^ 18 / cm ³ or more (corresponding to condition C).

  Thus, the vertical leakage current, that is, the substrate back surface leakage current is reduced by blocking the vertical leakage current from the ohmic electrodes 10 and 10 with the first nitride semiconductor layer 3. This prevents the vertical leakage current on the first nitride semiconductor layer 3 having a high C concentration, particularly on the second nitride semiconductor layer 4 side of the first nitride semiconductor layer 3 having a higher C concentration. It is considered that the longitudinal leakage current can be reduced.

In the first embodiment of the present invention, the C concentration on the surface side of the first nitride semiconductor layer 3 is 1.5 × 10 ^ 19 / cm ³ or more (corresponding to the condition B), preferably 1.8. × 10 ^ 19 / cm ³ or more (corresponding to condition C and condition D).

  Thus, the first nitride semiconductor layer 3 and the portion on the substrate 1 side of the first nitride semiconductor layer 3 can be prevented from being subjected to high electric field strength, and the vertical leakage current can be reduced to the first nitride. By blocking the surface of the semiconductor layer 3, the leakage current on the back surface of the substrate is reduced.

(Second Embodiment)
FIG. 4 is a schematic cross-sectional view showing an example of a field effect transistor according to the second embodiment of the present invention. 4, since the nitride semiconductor multilayer body has the same configuration as the nitride semiconductor multilayer body shown in FIG. 1, the same reference numerals as those shown in FIG. 1 denote the same constituent elements as those shown in FIG. The description is omitted.

  A source electrode 11 and a drain electrode 12 are provided on the nitride semiconductor laminate, a gate electrode 13 is provided between the source electrode 11 and the drain electrode 12, and an insulating film 21 is provided between the electrodes. Is electrically insulated.

  The source electrode 11 and the drain electrode 12 are ohmically connected to the 2DEG 41 of the second nitride semiconductor layer 4. As an ohmic connection method, a groove called a recess is dug in the second embodiment, and the 2DEG 41 is contacted from the horizontal direction. This is possible as long as the ohmic connection can be made. Ion implantation may be performed without digging a recess, or annealing at a high temperature to infiltrate the metal of the source and drain electrodes 11 and 12 up to 2DEG 41. The source and drain electrodes 11 and 12 and the 2DEG 41 may be electrically connected.

  The gate electrode 13 is formed between the source electrode 11 and the drain electrode 12. In the second embodiment, an insulating film (not shown) is formed under the gate electrode 13. The gate electrode 13 only needs to be able to turn on and off the transistor, and the gate electrode 13 may be formed with a Schottky junction on the surface of the barrier layer 5.

  In the second embodiment, as an example, the distance between the gate electrode 13 and the drain electrode 12 is 15 μm, the distance between the gate electrode 13 and the source electrode 11 is 2 μm, the gate length is 2 μm, and the gate width is It is 600 μm.

In the second embodiment, stoichiometric SiN is used for the insulating film 21. The insulating film 21 may be any film that can insulate the source electrode 11, the drain electrode 12, and the gate electrode 13. For example, another insulating film such as SiO ₂ may be used, and the above-described collapse is suppressed. Alternatively, it may have a multilayer structure in which Si-rich SiN is formed on the semiconductor surface and another insulating film is formed thereon.

  Hereinafter, the characteristics and breakdown voltage of the substrate back surface leakage current Isub in the field effect transistor will be described with reference to FIGS.

  5 to 8 show drain leakage current Id, gate leakage current Ig, and substrate backside leakage current when the drain voltage Vd is changed in the off state of source voltage 0V, substrate backside voltage 0V, and gate voltage Vg = −10V. It is a leak characteristic IV curve of Isub.

  5, FIG. 6, FIG. 7 and FIG. 8 are leakage characteristics IV curves of the field effect transistor using the nitride semiconductor stacked body under the conditions A, B, C and D shown in FIG. FIG. 5 is a leakage characteristic IV curve of a field effect transistor of a comparative example in which the substrate back surface leakage current Isub is not reduced, and FIGS. 6 to 8 are leakage characteristic IV curves of the present invention.

  As shown in FIG. 5, when the drain voltage Vd is 350 V and the substrate back surface leakage current Isub exceeds about 1/20 of the drain leakage current Id, the substrate back surface leakage current Isub increases rapidly between the drain and the substrate back surface. ing. Although it has not been completely destroyed, it can be said that 350 V is a substantial breakdown voltage of the field-effect transistor because the substrate back surface leakage current Isub is increasing rapidly.

  When the leakage path of the substrate back surface leakage current Isub flowing between the drain and the substrate back surface is analyzed, in FIG. 4, the drain electrode 12 passes through the second nitride semiconductor layer 4 and then the first nitride semiconductor. After passing through the layer 3 and then flowing to the interface between the first nitride semiconductor layer 3 and the buffer layer 2, it flows in the in-plane direction at the interface between the first nitride semiconductor layer 3 and the buffer layer 2. Thereafter, the inventors have clarified for the first time that the current flows to the back surface of the substrate 1 through a longitudinally broken portion outside the field-effect transistor and a weakly insulating portion such as a chip side surface or a wafer side surface. The present invention has been made based on this new elucidation.

  The phenomenon that the substrate back surface leakage current Isub is generated is that the leakage path does not pass directly through the buffer layer 2 but goes around the insulating weak portion in spite of the presence of the buffer layer 2 for securing the substrate withstand voltage. Means. Therefore, when the above phenomenon occurs, it means that the vertical breakdown voltage is supported not by the buffer layer 2 but by the first nitride semiconductor layer 3, and this means that the vertical breakdown voltage drop, the vertical leakage current, That is, it is considered that this causes an increase in the substrate back surface leakage current Isub.

  Therefore, in the structure of FIG. 6 (corresponding to the condition B of FIG. 12) of the second embodiment of the present invention, even if the drain voltage Vd is 800 V, the substrate back surface leakage current Isub is 1/20 of the drain leakage current Id. Reduced to: More specifically, as shown in FIG. 6, the substrate back surface leakage current Isub increases once until the drain voltage Vd = 500 V, and has a maximum value near Vd = 500 V, but the substrate back surface between the drain and the substrate back surface. This has not led to an increase in the leakage current Isub, and the substantial substrate breakdown voltage can be improved. In addition, it was concluded that the substrate back surface leakage current Isub decreased when Vd = 500 V because the electric field between the gate and the drain became strong and the current toward the substrate back surface was directed to the gate electrode 13.

  Further, in the structure of FIG. 7 (corresponding to condition C in FIG. 12) and FIG. 8 (corresponding to condition D in FIG. 12) of the present invention, the substrate back surface leakage current Isub is 100 minutes of the drain leakage current Id. Reduced to 1 or less. By doing so, when the drain voltage Vd = 600 V or less, the substrate back surface leakage current Isub does not increase, and stable reverse bias leakage characteristics are obtained.

  As described above, as a method for reducing the substrate back surface leakage current Isub, the C concentration of the front surface side of the buffer layer 2 and the first nitride semiconductor layer 3 was controlled.

  The C concentration in the first nitride semiconductor layer 3 is the second nitride semiconductor layer 4 side of the first nitride semiconductor layer 3 (second of the first nitride semiconductor layers 3). The C concentration in the region closest to the nitride semiconductor layer 4 is the highest, and the C concentration decreases as it approaches the buffer layer 2 side, so that the first nitride semiconductor layer 3 on the buffer layer 2 side (first nitride) The C concentration of the semiconductor layer 3 in the region closest to the buffer layer 2 is the lowest. That is, in the second column of the table of FIG. 12, “the entire area of the first nitride semiconductor layer” is described, and the lower limit value of the C concentration is described. This is equal to the C concentration on the buffer layer 2 side.

In the second embodiment of the present invention, the C concentration in the entire thickness direction of the first nitride semiconductor layer 3 is set to 4.0 × 10 ^ 18 / cm ³ or more (satisfies Condition B), 4.9 × 10 ^ 18 / cm ³ or more (condition C is satisfied). Thereby, the vertical leakage current from the drain electrode 12 is blocked by the first nitride semiconductor layer 3, and the substrate back surface leakage current Isub is reduced.

FIG. 9 shows the relationship between the C concentration on the buffer layer 2 side of the first nitride semiconductor layer 3 and the maximum value of the substrate back surface leakage current Isub (the maximum value at Vd = 600 V or less unless the maximum value is taken). Show. As described above, the first nitride semiconductor layer 3 has the highest C concentration on the surface side, and the C concentration decreases as the depth increases, and the first nitride semiconductor layer 3 has the lowest C concentration on the buffer layer 2 side. The C concentration on the buffer layer 2 side of the first nitride semiconductor layer 3 is the lower limit value of the C concentration over the entire thickness direction of the first nitride semiconductor layer 3. Therefore, the C concentration on the buffer layer 2 side of the first nitride semiconductor layer 3 on the horizontal axis in FIG. 9 means the lower limit value of the C concentration over the entire thickness direction of the first nitride semiconductor layer 3. . As can be seen from FIG. 9, when the C concentration on the buffer layer 2 side of the first nitride semiconductor layer 3 becomes 4.0 × 10 ^ 18 / cm ³ or more as the first critical value (Condition B) The substrate back surface leakage current Isub is drastically reduced, and the C concentration on the buffer layer 2 side of the first nitride semiconductor layer 3 is 4.9 × 10 ^ 18 / as the second critical value. When it becomes cm ³ or more (when Condition C is satisfied), it can be seen that the substrate back surface leakage current Isub is drastically reduced. The theoretical basis for the generation of the first critical value (4.0 × 10 ^ 18 / cm ³ ) and the second critical value (4.9 × 10 ^ 18 / cm ³ ) is unknown, From the experimental data of 9, it is clear that the C concentration of 4.0 × 10 18 / cm ^{3 and} the C concentration of 4.9 × 10 18 / cm ³ are critical. The above-mentioned critically significant C concentration values of 4.0 × 10 ^ 18 / cm ³ and 4.9 × 10 ^ 18 / cm ³ are simply higher than the C concentration on the buffer layer 2 side. Of the first nitride semiconductor layer 3 on the second nitride semiconductor layer 4 side (region of the first nitride semiconductor layer 3 closest to the second nitride semiconductor layer 4) It is believed that there is some physical structure (although currently unknown) that accounts for more critical behavior than the reason for the reduction. The present invention uses the newly discovered first and second critical values, and the C concentration of the first nitride semiconductor layer 3 on the buffer layer 2 side, that is, the depth of the first nitride semiconductor layer 3. The lower limit of the C concentration in the entire direction is limited numerically.

In addition, the surface side of the first nitride semiconductor layer 3, that is, the second nitride semiconductor layer 4 side of the first nitride semiconductor layer 3 (the second nitride in the first nitride semiconductor layer 3). The C concentration in the region closest to the physical semiconductor layer 4 is set to 1.5 × 10 ^ 19 / cm ³ or more (satisfying the condition B), preferably 1.8 × 10 ^ 19 / cm ³ or more (condition C is set to Satisfaction). As a result, the first nitride semiconductor layer 3 and the portion closer to the substrate than the first nitride semiconductor layer 3 can be prevented from being subjected to high electric field strength, and the substrate back surface leakage current Isub can be reduced to the first nitride. Since it is blocked by the surface of the semiconductor layer 3, the substrate back surface leakage current Isub is reduced.

FIG. 10 shows the C concentration on the surface side of the first nitride semiconductor layer 3 (the region of the first nitride semiconductor layer 3 closest to the second nitride semiconductor layer 4) and the substrate back surface leakage current Isub. And a maximum value of Vd (maximum value at Vd = 600 V or less if the maximum is not taken). As can be seen from FIG. 10, the C concentration on the surface side of the first nitride semiconductor layer 3 (the second nitride semiconductor layer 4 side of the first nitride semiconductor layer 3) is certainly the first critical value. When the condition becomes 1.5 × 10 ^ 19 / cm ³ or more (when Condition B is satisfied), the substrate back surface leakage current Isub rapidly decreases, and further, the C concentration on the surface side of the first nitride semiconductor layer 3 Is 1.8 × 10 ^ 19 / cm ³ or more as the second critical value (when Condition C is satisfied), it can be seen that the substrate back surface leakage current Isub is drastically reduced. Although the theoretical basis for the generation of the first critical value (1.5 × 10 ^ 19 / cm ³ ) and the second critical value (1.8 × 10 ^ 19 / cm ³ ) is unknown, From the 10 experimental data, it is clear that the C concentration of 1.5 × 10 ^ 19 / cm ^{3 and} the C concentration of 1.8 × 10 ^ 19 / cm ³ are critical. The critically significant C concentration values 1.5 × 10 ^ 19 / cm ³ and 1.8 × 10 ^ 19 / cm ³ described above indicate the first nitride semiconductor layer 3 having a high C concentration. Critical behavior beyond the reason that the substrate back surface leakage current Isub is reduced by the second nitride semiconductor layer 4 side (the region of the first nitride semiconductor layer 3 closest to the second nitride semiconductor layer 4). It is thought that there is some physical structure to explain (although it is currently unknown). In the present invention, the C concentration on the surface side of the first nitride semiconductor layer 3 is numerically limited by the newly discovered first and second critical values.

Further, the C concentration on the surface side of the buffer layer 2 (the region closest to the first nitride semiconductor layer 3 in the buffer layer 2) is set to 1.0 × 10 ^ 19 / cm ³ or more (condition B is satisfied). ), Preferably 1.5 × 10 ^ 19 / cm ³ or more (substantially satisfying condition C), and by eliminating the low resistance portion on the surface side of the buffer layer 2, the substrate back surface leakage current Isub is reduced. Yes.

FIG. 11 shows the relationship between the C concentration on the front surface side of the buffer layer 2 and the maximum value of the substrate back surface leakage current Isub (the maximum value at Vd = 600 V or less unless the maximum is taken). As can be seen from FIG. 11, when the C concentration on the front surface side of the buffer layer 2 is 1.0 × 10 ^ 19 / cm ³ or more as the first critical value (when the condition B is satisfied), the back surface of the substrate When the leakage current Isub is drastically reduced and the C concentration on the surface side of the buffer layer 2 becomes 1.5 × 10 ^ 19 / cm ³ or more as the second critical value (substantially satisfying the condition C), It can also be seen that the substrate back surface leakage current Isub is drastically reduced. The theoretical basis for the occurrence of the first critical value (1.0 × 10 ^ 19 / cm ³ ) and the second critical value (1.5 × 10 ^ 19 / cm ³ ) is unknown, but From the 11 experimental data, it is clear that the C concentration of 1.0 × 10 19 / cm ^{3 and} the C concentration of 1.5 × 10 19 / cm ³ have a critical significance. The above-mentioned critically significant C concentration values of 1.0 × 10 19 / cm ³ and 1.5 × 10 19 / cm ³ are simply determined by the surface side of the buffer layer 2 having a high C concentration. It is considered that there is some physical structure (although unknown at present) that explains the critical behavior beyond the reason that the back surface leakage current Isub is reduced. In the present invention, the lower limit of the C concentration on the surface side of the buffer layer 2 is numerically limited by the newly discovered first and second critical values.

  The present invention and the embodiments are summarized as follows.

The nitride semiconductor laminate of the present invention is
A buffer layer 2 made of a nitride semiconductor layer provided on the substrate 1, and
A first nitride semiconductor layer 3 made of a nitride semiconductor layer stacked on the buffer layer 2;
A second nitride semiconductor layer 4 made of a nitride semiconductor layer stacked on the first nitride semiconductor layer 3;
A barrier layer 5 made of a nitride semiconductor layer stacked on the second nitride semiconductor layer 4;
The buffer layer 2 is characterized in that the C concentration on the surface side is 1.0 × 10 ^ 19 / cm ³ or more.

  With the above configuration, the leakage current on the surface side of the buffer layer 2 is reduced, and the low resistance portion on the surface side of the buffer layer 2 can be eliminated, so that a high electric field is applied to the first nitride semiconductor layer 3. Can be prevented, and the breakdown voltage can be improved.

In one embodiment,
The C concentration of the first nitride semiconductor layer 3 is 4.0 × 10 ^ 18 / cm ³ or more over the entire depth direction.

  Thereby, since the vertical leakage current from the drain or the like to which a high voltage is applied is blocked by the first nitride semiconductor layer 3, it is possible to reduce the substrate back surface leakage current Isub.

In one embodiment,
The C concentration of the first nitride semiconductor layer 3 on the second nitride semiconductor layer 4 side is 1.5 × 10 ^ 19 / cm ³ or more.

  Thereby, it is possible to prevent a high electric field intensity from being applied to the first nitride semiconductor layer 3 and a portion closer to the substrate 1 than the first nitride semiconductor layer 3, and from the drain electrode 12 to which a high voltage is applied. Since the vertical leakage current is blocked by the surface of the first nitride semiconductor layer 3, the substrate back surface leakage current Isub can be further reduced.

In one embodiment,
The C concentration of the first nitride semiconductor layer 3 increases from the buffer layer 2 side toward the second nitride semiconductor layer 4 side.

  This has an effect on compensation of carriers generated by lattice mismatch between the buffer layer 2 and the first nitride semiconductor layer 3 and leads to reduction of leakage current.

The field effect transistor of the present invention is
The nitride semiconductor laminate;
A source electrode 11 and a drain electrode 12 spaced apart from each other on the nitride semiconductor laminate;
A gate electrode 13 formed between the source electrode 11 and the drain electrode 12 and on the nitride semiconductor multilayer body is provided.

  According to the field effect transistor having the above configuration, the nitride semiconductor multilayer body can prevent a dielectric breakdown induced by a substrate back surface leakage current Isub flowing in a leakage path between the drain electrode 12 and the substrate 1 back surface. High breakdown voltage can be obtained.

  More specifically, according to the above-described field effect transistor, a gate voltage to be turned off is applied to the gate electrode 13, the back surface of the substrate 1 is set to the same potential as the source electrode 11, and a drain voltage of 600 V or less is applied to the drain electrode 12. When the voltage is applied, the substrate back surface leakage current Isub flowing into the substrate 1 back surface can be reduced to 1/20 or less of the drain leakage current flowing out from the drain electrode 12.

  Further, in a remarkable case, when a gate voltage for an off-state operation is applied to the gate electrode 13, the back surface of the substrate 1 is set to the same potential as the source electrode 11, and a drain voltage of 600 V or less is applied to the drain electrode 12, It is also possible to set the substrate back surface leakage current Isub flowing into the back surface to 1/100 or less of the drain leakage current flowing out from the drain electrode 12.

  In the first and second embodiments, the C concentration of the first nitride semiconductor layer 3 gradually increases from the buffer layer 2 side toward the second nitride semiconductor layer 4 side. The C concentration of the first nitride semiconductor layer may be uniform in the thickness direction, and may increase stepwise from the buffer layer side to the second nitride semiconductor layer 4 side. May be.

  In the first and second embodiments, the buffer layer 2 has a superlattice structure, but may not have a superlattice structure.

  In the first and second embodiments, the GaN layer, the AlN layer, the AlGaN layer, and the like are described as the nitride semiconductor layer, but a BAlGaInN layer may be used.

  The specific first and second embodiments of the present invention have been described above. However, the present invention is not limited to the first and second embodiments, and various modifications can be made within the scope of the present invention. Can be implemented.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 1st nitride semiconductor layer 4 2nd nitride semiconductor layer 5 Barrier layer 10 Ohmic electrode 11 Source electrode 12 Drain electrode 13 Gate electrode 21 Insulating film

Claims (5)

A buffer layer made of a nitride semiconductor layer provided on a substrate;
A first nitride semiconductor layer comprising a nitride semiconductor layer stacked on the buffer layer;
A second nitride semiconductor layer comprising a nitride semiconductor layer stacked on the first nitride semiconductor layer;
A barrier layer made of a nitride semiconductor layer stacked on the second nitride semiconductor layer,
The nitride semiconductor multilayer body, wherein the C concentration on the surface side of the buffer layer is 1.0 × 10 ^ 19 / cm ³ or more. The nitride semiconductor multilayer body according to claim 1,
The nitride semiconductor multilayer body, wherein the C concentration of the first nitride semiconductor layer is 4.0 × 10 ^ 18 / cm ³ or more over the entire depth direction. The nitride semiconductor multilayer body according to claim 1 or 2,
The nitride semiconductor multilayer body, wherein the C concentration of the first nitride semiconductor layer on the second nitride semiconductor layer side is 1.5 × 10 ^ 19 / cm ³ or more. The nitride semiconductor multilayer body according to any one of claims 1 to 3,
The nitride semiconductor multilayer body, wherein the C concentration of the first nitride semiconductor layer increases from the buffer layer side toward the second nitride semiconductor layer side. The nitride semiconductor multilayer body according to any one of claims 1 to 4,
A source electrode and a drain electrode that are spaced apart from each other on the nitride semiconductor laminate;
A field effect transistor comprising: a gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor multilayer body.

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