JP2015167254A - Semiconductor device, method for mounting the same, and method of manufacturing the same - Google Patents

Semiconductor device, method for mounting the same, and method of manufacturing the same Download PDF

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Publication number
JP2015167254A
JP2015167254A JP2015103968A JP2015103968A JP2015167254A JP 2015167254 A JP2015167254 A JP 2015167254A JP 2015103968 A JP2015103968 A JP 2015103968A JP 2015103968 A JP2015103968 A JP 2015103968A JP 2015167254 A JP2015167254 A JP 2015167254A
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semiconductor device
columnar
external connection
guide layer
connection electrode
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JP2015103968A
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Japanese (ja)
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智之 小杉
Tomoyuki Kosugi
智之 小杉
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株式会社テラプローブ
Tera Probe Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

A semiconductor device capable of suppressing the occurrence of cracks in a solder bump and obtaining good electrical connection with a circuit board is provided. In a semiconductor device in which a plurality of columnar electrodes (16) and a sealing layer (17) are provided on the upper surface side of a semiconductor substrate (11), and the upper surface of each columnar electrode (16) is exposed on the upper surface of the sealing layer (17). Insulating guide layer 19 is provided on the upper surface of each of the electrodes, and a plurality of external connection electrodes 18 that are individually connected to each columnar electrode 16 and whose upper portion protrudes from the upper surface of guide layer 19 are provided. Have. Here, the upper part of the external connection electrode 18 is provided so as not to protrude above the guide layer 19 covering the peripheral side surface of the external connection electrode 18. [Selection] Figure 2

Description

  The present invention relates to a semiconductor device using a high-density mounting technique, a mounting structure thereof, and a manufacturing method thereof.

  In recent years, portable electronic devices such as cellular phones, portable information terminals, digital cameras, and multimedia players have been widely used. In portable electronic devices, market demands for miniaturization and higher functionality are high, and high-density mounting technology for semiconductor devices mounted on electronic devices plays an important role in order to meet such demands.

  Conventionally, as a semiconductor device using a high-density mounting technology, a chip size package (hereinafter referred to as “CSP”) that can bring the size of the semiconductor device close to the external dimensions of the individual semiconductor chips. There is known a semiconductor device having a structure abbreviated. In recent years, as one form of the CSP, a wafer level CSP (or WLP; Wafer) which is completed by forming a sealing layer while maintaining the size of the semiconductor wafer and then singulating into individual CSPs. A semiconductor device called “Level Package” (hereinafter simply abbreviated as “semiconductor device”) has been put into practical use.

  This semiconductor device includes a semiconductor substrate such as gallium arsenide, which is a compound semiconductor made of a compound of silicon or Ga (gallium) and As (arsenic), having a thickness between a pair of main surfaces (upper surface and lower surface), A desired integrated circuit or semiconductor element is formed on one main surface (hereinafter referred to as an upper surface) of the pair of main surfaces. An insulating film is provided on the semiconductor substrate so as to cover these integrated circuits and the like, and a rewiring is further provided on the insulating film. The rewiring is connected to a connection pad such as an integrated circuit through an opening provided in the insulating film. A columnar electrode for external connection is provided on the land of the rewiring formed on the insulating film. A sealing layer made of a resin material is provided on the upper surface of the semiconductor substrate on which the rewiring and insulating film are formed. The upper surface of the columnar electrode is exposed on the upper surface of the sealing layer, and the solder bump is provided so as to be connected to the upper surface of the columnar electrode. As a result, connection pads such as integrated circuits and solder bumps are electrically connected. An integrated circuit or the like formed on the upper surface of the semiconductor substrate is protected by a sealing layer.

  Such a semiconductor device is generally manufactured as follows. First, a semiconductor wafer in which an integrated circuit and a semiconductor element are formed in each of a plurality of regions partitioned on the upper surface of the semiconductor substrate is prepared. The semiconductor wafer is subjected to a wiring formation process including the insulating film formation, rewiring formation, and columnar electrode formation processes. Next, after the respective steps of resin sealing, resin grinding, and solder bump formation are performed in the state of the semiconductor wafer, each semiconductor device is completed by dicing into individual pieces.

  According to such a semiconductor device, it is possible to achieve a reduction in size and performance, an increase in packaging density, and an increase in manufacturing process efficiency. Such a semiconductor device and a manufacturing method thereof are described in, for example, Patent Document 1.

JP 2008-218731 A

  By the way, when mounting the semiconductor device as described above on the circuit board, each solder bump provided on the upper surface (package surface) of the sealing layer constituting the package is connected to each connection pad provided on the upper surface of the circuit board. The face-down mounting to be bonded to is applied.

  In such a semiconductor device mounting structure, it is known that cracks may occur in solder bumps when a temperature cycle test is performed or an excessive thermal load is repeatedly applied to an actual product. This solder bump crack is caused by stress concentration on the solder bump that joins the semiconductor device and the circuit board due to the difference in thermal expansion coefficient (or linear expansion coefficient) between the package of the semiconductor device and the circuit board. It has been found to be. When cracks occur in the solder bumps as described above, the electrical connection between the semiconductor device and the circuit board becomes poor, which causes a problem that the manufacturing yield and the reliability of the semiconductor device are deteriorated.

  Therefore, in view of the above-described problems, the present invention provides a semiconductor device capable of suppressing the occurrence of cracks in a solder bump and obtaining good electrical connection with a circuit board, its mounting structure, and its manufacturing method. The purpose is to do.

A semiconductor device according to the present invention includes:
A semiconductor device in which an external connection electrode is provided on one side of a semiconductor substrate,
A guide layer on the semiconductor substrate;
The external connection electrode is:
Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
The peripheral side surface of the columnar part is covered with the guide layer,
The protrusion protrudes from the guide layer;
The external connection electrode does not protrude from a region corresponding to the guide layer as seen from the one surface side of the semiconductor substrate,
The columnar part and the protruding part are integrally formed of a solder material,
It is characterized by that.

The mounting structure of the semiconductor device according to the present invention is as follows:
In the mounting structure of the semiconductor device in which the external connection electrode of the semiconductor device in which the external connection electrode is provided on one surface side of the semiconductor substrate is bonded and mounted to the connection pad provided in the circuit board.
The external connection electrode is:
Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
The columnar part and the protruding part are integrally formed of a solder material,
The peripheral side surface of the columnar part is covered with a guide layer,
The protruding portion protrudes from the guide layer and is bonded to the connection pad,
Furthermore, the diameter of the projecting portion viewed in plan from one surface of the semiconductor substrate is 110% or less of the diameter of the columnar portion viewed in plan from one surface of the semiconductor substrate.
It is characterized by that.
A method for manufacturing a semiconductor device according to the present invention includes:
A first step of preparing a semiconductor device according to the present invention;
A second step of bonding the external connection electrode of the semiconductor device to the connection pad of a circuit board having a connection pad on the surface;
It is characterized by including.

  According to the semiconductor device, the mounting structure thereof, and the manufacturing method thereof according to the present invention, it is possible to suppress the occurrence of solder bump cracks due to temperature cycles and the like and to ensure good electrical connection between the semiconductor device and the circuit board. Thus, the manufacturing yield can be improved and the reliability of the semiconductor device can be improved.

1 is a schematic plan view showing a first embodiment of a semiconductor device according to the present invention. 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. It is a schematic sectional drawing which shows the state which mounted the semiconductor device which concerns on 1st Embodiment on the circuit board. FIG. 6 is a process cross-sectional view (part 1) illustrating the example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view (part 2) illustrating the example of the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view (part 3) illustrating the example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 4) illustrating the example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 10 is a process cross-sectional view (part 5) illustrating the example of the method for manufacturing the semiconductor device according to the first embodiment; FIG. 11 is a process cross-sectional view (No. 6) illustrating the example of the method for manufacturing the semiconductor device according to the first embodiment. It is process sectional drawing (the 7) which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing (the 8) which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing (the 9) which shows an example of the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a schematic block diagram which shows the semiconductor device used as a comparative example. It is a figure for demonstrating the problem in the semiconductor device used as a comparative example. It is a schematic sectional drawing which shows the junction structure for improving the problem in the semiconductor device used as a comparative example. It is a figure which shows the joining structure used as the test object in a temperature cycle test. It is a graph which shows the preset temperature and preset time in a temperature cycle test. It is a graph and a table | surface which show the measurement result in a temperature cycle test. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a schematic block diagram which shows 3rd Embodiment of the semiconductor device which concerns on this invention. It is a schematic sectional drawing which shows the state which mounted the semiconductor device which concerns on 3rd Embodiment on the circuit board. It is process sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is the schematic which shows the structural example of the semiconductor device which integrated the several semiconductor chip in the single package.

Hereinafter, a semiconductor device and a semiconductor device mounting structure according to the present invention will be described in detail with reference to embodiments.
<First Embodiment>
(Semiconductor device)
First, a semiconductor device according to the present invention will be described.

  FIG. 1 is a schematic plan view showing a first embodiment of a semiconductor device according to the present invention, and FIG. 2 is a schematic sectional view showing the semiconductor device according to the first embodiment. 2 is a line II-II in the semiconductor device shown in FIG. 1 (in this specification, “II” is used for convenience as a symbol corresponding to the Roman numeral “2” shown in FIG. 1). It is a figure which shows the cross section along. FIG. 3 is a schematic cross-sectional view showing a state where the semiconductor device according to the first embodiment is mounted on a circuit board.

  In the semiconductor device 10 according to the first embodiment, for example, as shown in FIGS. 1 and 2, an integrated circuit (not shown) having a predetermined function is provided on the upper surface side (the front side in FIG. 1 and FIG. 2). The semiconductor substrate 11 is formed on the upper surface side; Here, the integrated circuit is formed by a known element such as a transistor, a diode, a resistor, or a capacitor.

  As shown in FIGS. 1 and 2, a plurality of connection pads 12 made of aluminum-based metal or the like connected to each element of the integrated circuit are provided on the upper surface of the semiconductor substrate 11. A passivation film 13 made of silicon oxide, silicon nitride, or the like is provided on the upper surface of the semiconductor substrate 11 so as to cover the plurality of connection pads 12. Here, the passivation film 13 is viewed from the direction of the normal line with respect to the upper surface of the semiconductor substrate 11 (corresponding to the front side in FIG. 1 or the upper side in FIG. 2), that is, in a plan view of the semiconductor substrate 11. The outer peripheral edge portion of the upper surface of the semiconductor substrate 11 is provided to be exposed in a frame shape. In addition, the passivation film 13 is provided with a plurality of openings 13 h that expose a part (for example, a central portion) of the upper surface of each connection pad 12. A protective film 14 made of polyimide resin or the like is provided on the upper surface of the passivation film 13 so as to have substantially the same shape as the passivation film 13 when the semiconductor substrate 11 is viewed in plan view. An opening 14 h is provided in the protective film 14 corresponding to the opening 13 h of the passivation film 13. That is, a part of the upper surface of each connection pad 12 is exposed through the opening 13 h provided in the passivation film 13 and the opening 14 h provided in the protective film 14. In the present embodiment, as shown in FIG. 1, a case is shown in which a plurality of connection pads 12 are arranged in a substantially rectangular frame shape along the outer peripheral edge of the upper surface of the semiconductor substrate 11. The arrangement of the connection pads 12 is not limited to this.

  As shown in FIGS. 1 and 2, a plurality of wirings 15 are provided on the upper surface of the protective film 14. The wiring 15 includes, for example, a base metal layer 15-1 formed of a copper thin film or a titanium thin film provided on the upper surface of the protective film 14, or a thin film obtained by stacking copper on titanium, and an upper surface of the base metal layer 15-1. It has a two-layer structure with an upper metal layer 15-2 made of copper or the like. One end portion 15 a of each wiring 15 is electrically connected to the upper surface of each connection pad 12 through openings 13 h and 14 h provided in the passivation film 13 and the protective film 14. A land 15 b is formed at the other end of each wiring 15. The one end portion 15a and the other end portion (land 15b) of each wiring 15 are connected by a lead wire portion 15c formed integrally therewith.

  As shown in FIGS. 1 and 2, a columnar electrode 16 made of copper or the like is provided on the upper surface of the land 15b of each wiring 15, and the land 15b and the columnar electrode 16 are electrically connected. Here, as shown in FIG. 1, for example, the columnar electrodes 16 are squarely arranged so as to have equal intervals in each side direction (vertical direction and horizontal direction in the drawing) of the rectangular semiconductor substrate 11.

  Further, as shown in FIG. 2, a sealing layer 17 made of an epoxy resin containing silica filler or the like is formed on the upper surface of the semiconductor substrate 11 provided with the wiring 15 and the protective film 14 on the peripheral side surface of the columnar electrode 16. Is provided. The upper surface of the sealing layer 17 is flattened and is provided so as to be substantially flush with the upper surface (end portion) of the columnar electrode 16 described above.

  Further, as shown in FIG. 2, a columnar external connection electrode 18 made of a solder material is provided on the upper surface of each columnar electrode 16, and the columnar electrode 16 and the external connection electrode 18 are electrically connected. . That is, as shown in FIG. 1, for example, each external connection electrode 18 is squarely arranged in the same manner as the columnar electrode 16 described above, and is provided at a position matching the arrangement of the columnar electrodes 16.

  As shown in FIG. 2, a guide layer 19 made of an insulating material such as resin is provided on the upper surface of the sealing layer 17. Thus, one surface of the sealing layer 17 and the other surface of the guide layer 19 are joined. The upper surface of the guide layer 19 is substantially flattened. Here, the external connection electrode 18 described above is provided so that the upper portion thereof protrudes from the upper surface of the guide layer 19. The guide layer 19 can be made of an insulating material such as resin as described above, or a metal film in which conduction between the external connection electrodes 18 is blocked by an oxide film.

  In the semiconductor device 10 according to the present embodiment, as shown in FIG. 2, when the II-II cross section of FIG. 1 is viewed from the side, in particular, the upper portion of the external connection electrode 18 is the external connection electrode 18. It is characterized in that it protrudes from the upper surface of the guide layer 19 only on an opening provided in the guide layer 19 (details will be described later). That is, the upper portion of the external connection electrode 18 protrudes from the upper surface of the guide layer 19 within the range of the planar shape of the external connection electrode 18 when the semiconductor substrate 11 is viewed in plan. In other words, the upper portion of the external connection electrode 18 is provided above the guide layer 19 covering the peripheral side surface of the external connection electrode 18 so as not to protrude. That is, as shown in FIG. 2, the region on the guide layer 19 between the perpendicular (dotted line) and the perpendicular (dotted line) orthogonal to the upper surface of the guide layer 19 (guide viewed from one surface side of the semiconductor substrate 11). In the region corresponding to the layer 19, the external connection electrode 18 does not protrude.

  When the semiconductor device 10 having such a configuration is mounted on the circuit board 31 as shown in FIG. 3, the upper surface of the guide layer 19 of the semiconductor device 10 shown in FIG. In this state, the upper part of the external connection electrode 18 provided so as to protrude from the upper surface of the guide layer 19 is bonded to the connection pad 32 provided on the upper surface of the circuit board 31. As a result, an integrated circuit (not shown) provided on the semiconductor substrate 11 of the semiconductor device 10 is electrically connected to the connection pad 32 on the upper surface of the circuit substrate 31 via the wiring 15, the columnar electrode 16, and the external connection electrode 18. Connected.

  Here, in the junction structure of the semiconductor device 10 and the circuit board 31 according to the present embodiment, the peripheral side surface of each external connection electrode 18 is regulated by the guide layer 19 provided on one surface of the sealing layer 17. A region that is provided in a columnar shape and is not regulated by the guide layer 19 at one end of the external connection electrode 18 that is joined to the circuit board 31 side does not protrude from one surface of the guide layer 19. Is provided. Even if it protrudes, the diameter of the external connection electrode 18 protruding from the guide layer 19 in plan view is 110% or less of the diameter of the external connection electrode 18 whose peripheral side surface is covered with the guide layer 19. Desirably, it is 105% or less. Further, the height hEL (see FIG. 2) of the portion of the external connection electrode 18 protruding from the guide layer 19 is 20% of the height of the portion of the external connection electrode 18 whose peripheral side surface is covered with the guide layer 19. Or less, preferably 10% or less. According to such a joint structure, the cross-sectional shape of the peripheral side surface of the external connection electrode 18 can be approximated to a straight line or a straight line as shown in the cross-sectional view of FIG. The distance (hereinafter referred to as stand-off) SH1 from one surface of the circuit board 31 to the upper surface of the connection pad 32 provided on the circuit board 31 can be set high. Further, according to the joint structure according to the present embodiment, the amount of solder material forming the external connection electrode 18 can be increased, and the external connection electrodes 18 can be well insulated from each other.

  Therefore, according to the present embodiment, generation of cracks in the external connection electrode 18 that joins the semiconductor device 10 and the circuit substrate 31 due to a temperature cycle or the like is suppressed, and the semiconductor device 10 and the circuit substrate 31 are Therefore, it is possible to secure a good electrical connection, and to improve the manufacturing yield and the reliability of the semiconductor device. In FIG. 3, reference numeral 33 denotes an underfill for improving the bonding strength between the semiconductor device 10 and the circuit board 31. For example, a liquid thermosetting epoxy resin or the like is used. Specific verification of the operational effects of the present embodiment will be described later in detail.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
4 to 12 are process cross-sectional views illustrating an example of the semiconductor device manufacturing method according to the first embodiment. Here, a manufacturing method of the semiconductor device having the cross-sectional structure shown in FIG. 2 will be described.

  In the method for manufacturing the semiconductor device 10 described above, first, as shown in FIG. 4A, a semiconductor substrate in a wafer state (hereinafter referred to as a semiconductor wafer 21) is prepared. Here, a plurality of connection pads 12 made of aluminum light metal or the like connected to an integrated circuit (not shown) are formed on the upper surface of the semiconductor wafer 21. A passivation film 13 made of silicon oxide or the like and a protective film 14 made of polyimide resin or the like are laminated on the upper surface of the semiconductor wafer 21 so as to cover the connection pads 12. Openings 13h and 14h are respectively formed in the passivation film 13 and the protective film 14 on each connection pad 12, and a part of the upper surface of each connection pad 12 (for example, a central portion) is formed through the openings 13h and 14h. Exposed. The thickness of the semiconductor wafer 21 is set to be thicker than the thickness of the semiconductor substrate 11 shown in FIG. In FIG. 4A, a region indicated by reference numeral 22 is a dicing street. The dicing street 22 and the passivation film 13 and the protective film 14 in the vicinity of both sides thereof are removed in advance, and the upper surface of the semiconductor wafer 21 is exposed.

  Next, as shown in FIG. 4B, the upper surface of the connection pad 12 exposed through the openings 13h and 14h of the passivation film 13 and the protective film 14, the upper surface of the protective film 14, and the dicing street 22 and A base metal layer 15-1 is formed on the upper surface of the semiconductor wafer 21 exposed in the vicinity of both sides. Here, the base metal layer 15-1 may be, for example, only a copper layer formed by electroless plating, or may be only a copper layer formed by a sputtering method. A copper layer may be formed by sputtering on a thin film layer of titanium or the like formed by the method.

  Next, as shown in FIG. 4C, a first plating resist film 23 made of a positive liquid resist is patterned on the upper surface of the base metal layer 15-1. Here, an opening 23h is formed in the first plating resist film 23 in a portion corresponding to a formation region of the upper metal layer 15-2 described later. Next, as shown in FIG. 5A, the base exposed in the opening 23h of the first plating resist film 23 by performing electrolytic plating of copper using the base metal layer 15-1 as a plating current path. An upper metal layer 15-2 is formed on the upper surface of the metal layer 15-1. Thereafter, the first plating resist film 23 is peeled off from the upper surface of the base metal layer 15-1.

  Next, as shown in FIG. 5B, a second plating resist film 24 made of a negative dry film resist is formed on each upper surface of the upper metal layer 15-2 and the base metal layer 15-1. Here, an opening 24h is formed in the second plating resist film 24 in a portion corresponding to a land (a formation region of a columnar electrode 16 described later) of the upper metal layer 15-2.

  Next, as shown in FIG. 6A, the upper portion exposed in the opening 24h of the second plating resist film 24 by performing electrolytic plating of copper using the base metal layer 15-1 as a plating current path. The columnar electrode 16 is formed on the land upper surface of the metal layer 15-2. Thereafter, as shown in FIG. 6B, the second plating resist film 24 is peeled off from the upper surfaces of the upper metal layer 15-2 and the base metal layer 15-1. In this state, the height of the columnar electrode 16 is set to be higher than the height of the columnar electrode 16 shown in FIG.

  Next, as shown in FIG. 7A, by using the upper metal layer 15-2 as a mask, the base metal layer 15-1 other than the region immediately below the upper metal layer 15-2 is removed by etching. The base metal layer 15-1 is left only immediately below the metal layer 15-2. Thereby, the wiring 15 having a two-layer structure including the upper metal layer 15-2 and the underlying metal layer 15-1 remaining immediately below the upper metal layer 15-2 is formed. In the step of forming the wiring 15, an ashing process is further performed on the protective film 14, the semiconductor wafer 21, and the like in the region where the base metal layer 15-1 has been removed by etching using an oxygen plasma method or the like. There may be. According to this, the residue of the base metal layer 15-1 remaining on the protective film 14 and the semiconductor wafer 21 can be removed, and the protective film 14 and the semiconductor wafer 21 are formed in the sealing layer 17 forming step described later. And the sealing layer 17 can be improved in adhesion.

  Next, as shown in FIG. 7B, a screen printing method or the like is applied to each upper surface of the wiring 15, the columnar electrode 16, and the protective film 14 and to the upper surface of the semiconductor wafer 21 in the dicing street 22 and the neighboring regions on both sides. A liquid sealing material made of epoxy resin containing silica filler or the like is applied. At this time, the sealing material is applied so as to cover the entire circumference including the upper surface and side surfaces of the columnar electrode 16. Thereafter, the gas component contained in the sealing material is removed (defoamed) in a reduced-pressure atmosphere, and then the baking process is performed to form the sealing layer 17. Here, as shown in FIG. 7B, the sealing layer 17 is formed so as to contact the columnar electrode 16, and the thickness thereof covers the upper surface of the columnar electrode 16. It is set to be slightly thicker than the height.

  Next, as shown in FIG. 8A, the upper surface side of the sealing layer 17 and the upper portion of the columnar electrode 16 are mechanically ground and removed, so that a columnar shape is formed on the grinding surface CS1 in the drawing. The upper surface of the electrode 16 is exposed and is formed substantially flush with the upper surface of the sealing layer 17. Thereby, the height from the reference surface (corresponding to the lower surface of the semiconductor wafer 21) of the stage (not shown) on which the semiconductor wafer 21 is placed and fixed to the grinding surface CS1, that is, the upper surface of the columnar electrode 16 is reached. The height is set to an arbitrary dimension. In addition, when a burr | flash generate | occur | produces on the upper surface of the columnar electrode 16 by this mechanical grinding, this burr | flash is removed by wet etching etc., and also in order to prevent subsequent oxidation, it is electroless on the upper surface of the columnar electrode 16. You may make it perform surface treatments, such as forming a nickel layer by plating.

  Next, as shown in FIG. 8B, the thickness of the semiconductor wafer 21 is reduced by mechanically grinding the lower surface side of the semiconductor wafer 21 to the grinding surface CS2 in the drawing. Here, with the upper surface side of the semiconductor wafer 21 placed and fixed on a stage (not shown), the lower surface side of the semiconductor wafer 21 is mechanically ground to thereby obtain a reference surface (FIG. The height from the grinding surface CS2 to the grinding surface CS2 (that is, the thickness of the semiconductor device 10 main body) is set to an arbitrary dimension.

  Next, as shown in FIG. 9, a guide layer 19 made of a resin material such as photosensitive polyimide is patterned on the upper surface of the sealing layer 17. Here, an opening 19h is formed in the guide layer 19 at a portion corresponding to the columnar electrode 16 exposed on the upper surface of the sealing layer 17, and the upper surface of the columnar electrode 16 is exposed in the opening 19h. Yes. For the opening 19 h of the guide layer 19, for example, the same dry film resist as that used to form the opening 24 h in the second plating resist film 24 when the above-described columnar electrode 16 is formed is used. It can be formed by performing exposure and development processing. The guide layer 19 may be a dry film in which an opening 19h is formed in advance so that the alignment of the columnar electrodes 16 and the position of the opening 19h are aligned, or a sealing layer 17 such as photosensitive polyimide. A photosensitive resin material may be applied and cured thereon, and then exposed and developed to form a pattern of the opening 19h where the upper surface of the columnar electrode 16 is exposed. Here, when a dry film is applied as the guide layer 19, a relatively flat upper surface can be easily obtained. Although the case where a photosensitive resin film is used as the guide layer 19 has been described in the present embodiment, the present invention is not limited to this. That is, the guide layer 19 may be, for example, a metal film in which conduction is cut off by an oxide film as long as it can satisfactorily insulate at least the external connection electrodes 18 described later. .

  Next, as shown in FIG. 10, one or a plurality of solder balls 18 b having a predetermined volume or particle diameter are mounted (inserted) in the opening 19 h formed in the guide layer 19. FIG. 10 shows a case where two solder balls 18b are mounted in each opening 19h. Next, heat treatment (reflow) is performed to melt the mounted solder ball 18b and fill the opening 19h with a solder material, so that the upper surface of the columnar electrode 16 is electrically connected as shown in FIG. An external connection electrode 18 is formed which comes into contact with and protrudes from the upper surface of the guide layer 19. Here, when the semiconductor substrate 11 is viewed in plan so that the upper part of the external connection electrode 18 does not protrude above the guide layer 19, the external connection electrode 18 whose peripheral side surface is covered with the guide layer 19. It is formed so as to protrude from the upper surface of the guide layer 19 within the range of the formation region (that is, only on the opening 19h).

Here, a specific numerical setting when forming the external connection electrode 18 in the opening 19h provided in the guide layer 19 will be described. For example, when two solder balls 18b having a diameter of 260 μm are mounted on the opening 19h having a diameter of 260 μm provided in the guide layer 19, the total amount of solder material (solder amount) constituting the solder ball 18b is given by It can be obtained as in (1). This amount of solder corresponds to the volume of the external connection electrode 18 formed in the opening 19h of the guide layer 19 using the solder ball 18b.
(4 × π × (240/2) 3 ) / 3 × 2≈14,476,000 [μm 3 ] (1)

On the other hand, the volume of the external connection electrode 18 can be obtained by the following equation (2), where H is the height of the external connection electrode 18. The height H of the external connection electrode 18 corresponds to a standoff that is a distance between the opposing surfaces of the sealing layer 17 of the semiconductor device 10 and the connection pad 32 of the circuit board 31.
(260/2) 2 × π × H≈53,092H [μm 3 ] (2)
Here, when H = 272 μm, the numerical value shown in the following equation (3) is obtained.
(260/2) 2 × π × 272≈14,441,000 [μm 3 ] (3)

  Therefore, according to this numerical value setting, the standoff between the opposing surfaces of the sealing layer 17 of the semiconductor device 10 and the circuit board 31 can be set to approximately 272 μm or more. The numerical value of this stand-off is in a joining structure using solder bumps having a volume substantially equal to the amount of solder shown in the above-described equation (1) (described in detail in comparative verification described later; see FIG. 13B). Since the value is larger than the value of the standoff, the standoff can be made sufficiently high. If the height of the guide layer 19 is 272 μm, the height of the external connection electrode 18 after reflowing the solder balls 18 b slightly exceeds the height of the guide layer 19. In this case, considering that the diameter 260 μm of the opening 19 h is slightly larger than the diameter 240 μm of the solder ball 18 b, if two solder balls 18 b are mounted in the opening 19 h of the guide layer 19, the solder mounted on the upper side. The height of the opening 19h of the guide layer 19 that guides the ball 18b is only slightly higher than 32 μm. However, even if the height of the opening 19h of the guide layer 19 around the solder ball 18b having a diameter of 240 μm is 32 μm, the solder ball 18b does not roll on the guide layer 19 and can be guided. Also, as shown in FIG. 3, solder is not printed on the connection pads 32 provided on the circuit board 31, but solder is printed on the connection pads 32 in advance to provide a solder layer. May be. Then, there is no problem even if the height of the external connection electrode 18 is lower than the height of the guide layer 19. In addition, the height of the standoff SH1 can be further increased.

  In this numerical setting, it goes without saying that the thickness of the guide layer 19 is set to be thinner than the height H of the external connection electrode 18 assumed in the equation (3). As a result, as shown in FIG. 11, the upper portion of the external connection electrode 18 is formed to protrude from the upper surface of the guide layer 19 above the formation region of the opening 19h.

  Next, as shown in FIG. 12, the guide layer 19, the sealing layer 17, and the semiconductor wafer 21 are cut along the dicing street 22 into individual pieces, whereby the semiconductor device 10 shown in FIGS. 1 and 2 is obtained. Several are obtained.

(Verification of effects)
Next, the effects of the semiconductor device according to the above-described embodiment will be specifically verified.
FIG. 13 is a schematic configuration diagram showing a semiconductor device as a comparative example of the present embodiment. FIG. 13A is a schematic cross-sectional view of a semiconductor device as a comparative example, and FIG. 13B is a schematic cross-sectional view showing a state where the semiconductor device as a comparative example is mounted on a circuit board. Here, in order to simplify the comparison with the semiconductor device according to the above-described embodiment, the same components are denoted by the same reference numerals. Further, in FIG. 13B, in order to simplify the illustration, the connection pad 12, the passivation film 13, and the protective film 14 provided on the semiconductor substrate 11 shown in FIG. 13A are omitted. FIG. 14 is a diagram for explaining problems in the semiconductor device as a comparative example. Here, FIG. 14A is a conceptual diagram showing a problem in the semiconductor device as a comparative example, and FIGS. 14B and 14C are for demonstrating the problem in the semiconductor device as a comparative example. FIG.

  It is assumed that the following device structure is applied to a semiconductor device as a comparative example of the present embodiment. That is, as shown in FIG. 13A, a semiconductor device 10p as a comparative example includes a semiconductor substrate 11 on which an integrated circuit (not shown) and connection pads 12 are provided. A protective film 14 is provided. A wiring 15 is provided on the protective film 14, and one end side of the wiring is connected to each connection pad 12 through openings 13 h and 14 h provided in the passivation film 13 and the protective film 14. On the other hand, a columnar electrode 16 is provided on the upper surface on the other end side of the wiring. A sealing layer 17 is provided on the upper surface of the semiconductor substrate 11 including the region where the protective film 14 and the wiring 15 are provided, and the upper surface of the columnar electrode 16 is exposed on the upper surface of the sealing layer 17. . Then, solder bumps 18p are provided on the upper surface of each columnar electrode 16 so as to protrude.

  When the semiconductor device 10p having such a configuration is mounted on the circuit board 31 as shown in FIG. 13B, one of the sealing layers 17 of the semiconductor device 10p shown in FIG. Solder bumps 18 p provided so as to protrude from the sealing layer 17 are bonded to connection pads 32 provided on the upper surface of the circuit board 31 with the surface and the upper surface of the circuit board 31 facing each other. Thereby, an integrated circuit (not shown) provided on the semiconductor substrate 11 of the semiconductor device 10p is electrically connected to the connection pads 32 on the upper surface of the circuit substrate 31 via the wirings 15, the columnar electrodes 16, and the solder bumps 18p. Connected.

Here, an example is shown and demonstrated about the general numerical setting at the time of mounting the semiconductor device 10p on the circuit board 31. FIG. In the mounting structure shown in FIG. 13B, when the diameter of the solder bump 18p is 300 μm, the amount of solder can be obtained by the following equation (4).
(4 × π × (300/2) 3 ) / 3≈14,173,000 μm 3 (4)

  Further, in the case of this numerical setting, the standoff SH11 which is a separation distance between the surfaces where the sealing layer 17 of the semiconductor device 10p and the connection pad 32 of the circuit board 31 face each other is larger than the diameter of the solder bump 18p of 300 μm. It is set to a small value of about 210 to 220 μm. The numerical value of the standoff SH11 is that the semiconductor device 10p in which a plurality of solder bumps 18p are arranged is mounted on the circuit board 31 and then subjected to a heat treatment (reflow) to connect the solder bumps 18p and the connection pads on the circuit board 31. In the case of bonding to 32, it is determined based on the sum of the bonding areas of the solder bumps 18p and the weight of the semiconductor device 10p. Therefore, when the semiconductor device 10p is bonded by heat-treating the solder bump 18p, generally, the numerical value of the standoff SH11 is smaller than the diameter of the solder bump 18p.

  As shown in FIG. 13B, in the mounting structure in which the semiconductor device 10p is directly bonded to the circuit board 31 through the solder bumps 18p, a temperature cycle test is performed or an excessive thermal load is applied to the actual product. It is known that, when repeatedly applied, as shown in FIG. 14A, a crack 18c may occur in the solder bump 18p. FIGS. 14B and 14C show examples of micrographs of cross sections of the solder bumps 18p when the temperature cycle test is performed in the mounting structure shown in FIG. 13B. FIG. 14B shows a cross section of the solder bump 18p in an initial state before the temperature cycle test is performed, and FIG. 14C shows the solder bump 18p in which the crack 18c is generated when the temperature cycle test is performed. A cross section is shown.

  It has been found that the crack 18c in the solder bump 18p is generated due to a difference in thermal expansion coefficient (or linear expansion coefficient) between the semiconductor substrate 11 and the circuit board 31 constituting the package of the semiconductor device 10p. That is, when a thermal load such as a temperature cycle test is repeatedly applied, as shown by an arrow in FIG. 14A, a difference occurs in the amount of expansion / contraction between the semiconductor substrate 11 and the circuit substrate 31, and thus the semiconductor device 10p and the circuit The stress concentrates on the solder bump 18p that joins the substrate 31, and the crack 18c is generated.

  In order to suppress the occurrence of such cracks 18c, the difference in thermal expansion coefficient between the semiconductor substrate 11 and the circuit board 31 containing, for example, glass epoxy resin, that is, the semiconductor when a thermal load is repeatedly applied. It is conceivable to apply a joint structure that relieves stress applied to the solder bump 18p and distortion generated in the solder bump 18p due to the difference in expansion and contraction between the substrate 11 and the circuit board 31. Here, in the mounting structure shown in FIG. 13B, the standoff SH11 which is a separation distance between the opposing surfaces of the semiconductor device 10p (or the sealing layer 17) and the circuit board 31 (or the connection pad 32). A joint structure that suppresses the concentration of stress on the solder bump 18p by setting a high value for the following will be considered.

  FIG. 15 is a schematic cross-sectional view showing a junction structure for improving problems in a semiconductor device as a comparative example. Here, in order to simplify the illustration, the connection pad 12, the passivation film 13, the protective film 14, the wiring 15 and the columnar electrode 16 provided under the semiconductor substrate 11 are omitted, and only the sealing layer 17 is shown. FIG. 16 is a diagram showing a joint structure to be tested in the temperature cycle test, FIG. 17 is a graph showing the set temperature and set time in the temperature cycle test, and FIG. 18 shows the measurement results in the temperature cycle test. It is the graph and table | surface which are shown.

  First, as a first bonding structure that alleviates the difference in expansion and contraction between the sealing layer 17 and the circuit board 31 when a thermal load is repeatedly applied, for example, as shown in FIG. Alternatively, the standoff SH12 that is the separation distance between the sealing layer 17) and the connection pad 32 provided on the circuit board 31 is set higher than the standoff SH11 in the mounting structure shown in FIG. SH12> SH11). Here, in the first bonding structure, the solder amount of the solder bump 18pa for bonding the semiconductor device 10p and the circuit board 31 is the same as the solder amount of each solder bump 18p in the mounting structure shown in FIG. It is set so that only the standoff SH12 becomes high. In such a joint structure, as shown in FIG. 15A, the cross-sectional shape of the side surface portion of the solder bump 18pa is a gentle arc shape compared to the solder bump 18p shown in FIG. Or the shape approximated to the straight line is shown. That is, the radius of curvature when the local side surface portion is approximated to a circle is set larger than in the case shown in FIG.

  Further, as the second joining structure, for example, as shown in FIG. 15B, the solder amount of the solder bump 18pb is made larger than the solder amount of the solder bump 18p in the mounting structure shown in FIG. 13B. By setting to, the standoff SH13 is set higher (SH13> SH11) than the standoff SH11 in the mounting structure shown in FIG. In such a joint structure, as shown in FIG. 15B, the cross-sectional shape of the side surface portion of the solder bump 18pb shows an arc shape like the solder bump 18p shown in FIG. 13B. That is, the curvature radius of the side surface portion is set to be small as in the case shown in FIG.

  In FIGS. 13B, 15A, and 15B, the mounting structure of the semiconductor device 10p on the circuit board 31 is simplified for the sake of convenience. However, in the actual wafer level CSP, FIG. Are arranged on the lower surface (package surface) of the sealing layer 17 of the semiconductor device 10p reduced in size by several mm square, for example, 16 × 16 = 256. Here, the arrangement interval (pitch) between the solder bumps means a distance from the center of the external connection electrode 18 to the center, and becomes narrower as the number of solder bumps arranged on the upper surface of the sealing layer 17 increases. In particular, in the second joint structure shown in FIG. 15B, since the solder amount of the solder bump 18pb is increased, the side surfaces of adjacent solder bumps 18pb are close to each other and a short circuit is likely to occur. Becomes prominent. Therefore, it is considered difficult to apply the second joint structure as it is to the actual product. Therefore, in the following, attention is paid to the first bonding structure shown in FIG. 15A, and verification is made while comparing with the bonding structure shown in FIG.

First, the junction structure used for comparison verification will be described.
The semiconductor device 10p used for this comparison verification has a square shape with a side of 8.0 mm × 8.0 mm when viewed in plan, and 16 × 16 = 256 solder bumps are square on the surface of the package. Assume that they are arranged. In addition, the arrangement interval (pitch) between adjacent solder bumps is set to 0.5 mm. As the solder bump, a solder material having a ratio of tin (Sn), silver (Ag), copper (Cu), and nickel (Ni) of 1: 1.2: 0.5: 0.05 was applied.

  Further, the circuit board 31 used for the comparison verification has a rectangular shape with an outer shape of 30 mm × 40 mm when viewed in plan, and has a plate thickness of 0.8 mm. Among the 256 solder bumps arranged on the package surface of the semiconductor device 10p described above, the connection pads 32 corresponding to 12 × 12 = 144 solder bumps are squarely arranged on the upper surface of the circuit board 31. And Here, the material of the connection pad 32 is copper (Cu).

  Then, the solder bumps 18p arranged on the package surface of the semiconductor device 10p described above are bonded in correspondence with the connection pads 32 provided on the upper surface of the circuit board 31, and a predetermined heat treatment is performed. A new junction structure was formed. That is, verification example 1 corresponding to the bonding structure shown in FIG. 13B and verification example 2 corresponding to the bonding structure shown in FIG. 15A are shown in FIGS. 16A and 16B. As described above, the parameters of the thickness (A) of the semiconductor substrate 11, the height (B) of the columnar electrode 16, the thickness (C) of the sealing layer 17, and the standoff (D) are set. Here, the solder amount of the solder bump 18p in the verification example 1 and the verification example 2 is set to be substantially the same, and compared with the standoff (D = 243.1 μm) in the verification example 1, the verification example. 2 standoff (D = 267.6 μm) is set higher. FIG. 16C shows an example of a micrograph of a cross section of each solder bump 18p of the verification example 1 and the verification example 2 under the above conditions.

Next, the setting of conditions for the temperature cycle test performed in this comparative verification will be described.
In this comparative verification, as temperature cycle conditions (set temperature and set time), as shown in FIG. 17, after heating at 125 ° C. for 9 minutes, after returning to room temperature (RT) for 1 minute, −25 ° C. A series of temperature cycles through an interval of 1 minute for cooling for 9 minutes and then returning to room temperature (RT) is taken as one period, and this is repeated. The temperature cycle test in this comparative verification measures the ratio of occurrence of defects caused by cracks in the solder bumps 18p with respect to the number of temperature cycles.

    As a measurement result in such a temperature cycle test, the relationship of the defect occurrence ratio of the solder bump 18p to the number of temperature cycles is shown as a logarithmic graph in FIG. 18 (a) and as a table in FIG. 18 (b). From the logarithmic graph shown in FIG. 18A, the slope of the approximate line (m = 6.5) in Verification Example 1 and the slope of the approximate curve in Verification Example 2 (m = 5.0) are both greater than 1. It turns out that it is a wear-out failure. Here, the slope of the approximate line is the slope of the defect occurrence ratio (y-axis) indicated by the log scale with respect to the temperature cycle number (x-axis) indicated by the log scale in the logarithmic graph shown in FIG. It is. The difference in the slope of the approximate straight line is that the number of temperature cycles until the specific defect occurrence ratio is reached (that is, the average number of defect occurrence cycles in the table shown in FIG. Compared to the case (1632 times), the case of verification example 2 (1982 times) is larger, which means that the occurrence of cracks (occurrence of defects) is less likely to occur. In addition, in the temperature cycle test in this comparative verification, from the table shown in FIG. 18B, the result of the verification example 2 that the average number of defective occurrences is improved by about 20% compared to the verification example 1. Got.

  Although specific disclosure of the verification result is omitted, as shown in FIG. 15B, even when the solder amount of the solder bump is set large, the arrangement interval at which no short circuit between adjacent solder bumps occurs. Thus, in the case where each solder bump is provided, the same result as the comparative verification described above could be obtained.

  From the above, the inventor of the present application is set so that the standoff in the mounting structure is high and the curvature radius of the side surface section of the solder bump is large (in other words, the side surface section approximates a straight line). In addition, as the solder amount of the solder bump is set to be larger, even when a thermal load is repeatedly applied, the solder bump is less likely to crack, and good electrical connection is maintained. Drew conclusions.

  Therefore, in the semiconductor device 10 according to the present embodiment, as shown in FIG. 2, a plurality of columnar electrodes 16 and a sealing layer 17 are provided on the upper surface side of the semiconductor substrate 11, and each columnar electrode is formed on the upper surface of the sealing layer 17. In the semiconductor device in which the upper surface of the electrode 16 is exposed, an insulating guide layer 19 is provided on the upper surface of the sealing layer 17 and is individually connected to each columnar electrode 16. A plurality of columnar external connection electrodes 18 projecting from the surface are provided. That is, the semiconductor device according to the present embodiment has a guide layer on the sealing layer 17 in a configuration in which the solder bumps 18p are removed from the upper surface of each columnar electrode 16 of the semiconductor device 10p shown as a comparative example in FIG. 19 and a plurality of external connection electrodes 18 that are connected to each columnar electrode 16 and whose upper portion protrudes from the upper surface of the guide layer 19.

  When the semiconductor device 10 according to the present embodiment is mounted on the circuit board 31, as shown in FIG. 3, the upper portions of the external connection electrodes 18 protruding from the upper surface of the guide layer 19 are Each external connection electrode 18 and the connection pad 32 on the circuit board 31 are joined by performing a heat treatment while being placed on each connection pad 32 on the 31 side.

  At this time, the peripheral side surface of the external connection electrode 18 is covered with the guide layer 19 and regulated linearly, and the upper portion of the external connection electrode 18 is only on the opening 19 h provided in the guide layer 19. The guide layer 19 is formed so as to protrude from the upper surface. Thereby, even when the semiconductor device 10 is mounted on the circuit board 31, the adjacent external connection electrodes 18 do not contact each other and short-circuit. Further, as shown in the above-described formulas (1) to (4), the amount of solder constituting the external connection electrode 18 can be increased and the standoff can be increased.

  Therefore, according to the semiconductor device and the mounting structure of the semiconductor device according to the present embodiment, it is possible to suppress the occurrence of cracks at the junction between the semiconductor device 10 and the circuit board 31, and the semiconductor device 10 and the circuit board 31. Therefore, it is possible to secure a good electrical connection, and to improve the manufacturing yield and the reliability of the semiconductor device.

<Second Embodiment>
Next, a second embodiment of the semiconductor device according to the present invention will be described.
19 to 22 are process cross-sectional views illustrating an example of a semiconductor device manufacturing method according to the second embodiment. Here, the description of the steps equivalent to those of the first embodiment described above is simplified or omitted.

  In the semiconductor device according to the first embodiment described above, as a method of forming the external connection electrode 18 provided in the opening 19h of the guide layer 19, after mounting a plurality of solder balls 18b in the opening 19h, The method for forming the external connection electrode 18 that is connected to the columnar electrode 16 in the opening 19h and protrudes from the upper surface of the guide layer 19 at a time by performing the heat treatment only once has been described. In the second embodiment, a series of steps of placing one or a plurality of solder balls in the opening portion 19h of the guide layer 19 and performing heat treatment to melt the solder balls are repeated a plurality of times to open the openings. The external connection electrode 18 is connected to the columnar electrode 16 in the part 19h and the upper part protrudes from the upper surface of the guide layer 19 in a stepwise manner.

  In the manufacturing method of the semiconductor device according to the present embodiment, first, the passivation film 13, the protective film 14, the wiring 15, and the columnar electrode 16 are formed on the upper surface of the semiconductor wafer 21, as in the manufacturing method described in the first embodiment. After the sealing layer 17 is formed (see FIGS. 4 to 8), as shown in FIG. 9, the guide layer is provided with an opening 19h on the top surface of the sealing layer 17 where the top surface of the columnar electrode 16 is exposed. 19 is formed.

  Next, as shown in FIG. 19, one or more solder balls 18 b-1 having a predetermined volume or particle size are mounted in the opening 19 h formed in the guide layer 19. FIG. 19 shows a case where two solder balls 18b-1 are mounted in each opening 19h. Next, the first heat treatment (reflow) is performed to melt the solder ball 18b-1 and fill the opening 19h with a solder material, whereby the upper surface of the columnar electrode 16 is electrically charged as shown in FIG. The solder layer 18ba in contact with the target is formed. At this time, the upper surface of the solder layer 18ba is lower than the upper surface of the guide layer 19 and has a shape that is lower (dented) near the center than the contact portion with the inner surface of the opening 19h. That is, the upper part in the opening 19h is not filled with a solder material and is in a hollow state.

  Next, as shown in FIG. 21, one or more solder balls 18b-2 having a predetermined volume or particle size are again mounted in the opening 19h in which the solder layer 18ba is formed, and the second heat treatment ( Reflow). FIG. 20 shows a case where one solder ball 18b-2 is mounted in each opening 19h. As a result, the solder ball 18b-2 is melted and the solder material is filled on the solder layer 18ba in the opening 19h (that is, the upper portion in the opening 19h), and as shown in FIG. The external connection electrode 18 is formed which is in electrical contact with the upper surface of the guide layer 19 and protrudes from the upper surface of the guide layer 19. Here, the external connection electrode 18 is integrally formed by melting the solder layer 18ba and the solder ball 18b-2 formed in the lower portion in the opening 19h by the second heat treatment.

  In the present embodiment, as shown in FIGS. 19 to 22, a series of processes in which one or a plurality of solder balls are mounted in the opening 19 h provided in the guide layer 19 and are melted by heat treatment. However, the present invention is not limited to this. That is, in the present invention, one or a plurality of solder balls are mounted in the opening 19h, and a series of processes of melting by heat treatment is repeated three or more times (a plurality of times) to form the external connection electrode 18. It may be.

  Here, the numerical setting when the external connection electrode 18 is formed in the opening 19h provided in the guide layer 19 will be described. Here, the case where the external connection electrode 18 is formed by mounting and melting two solder balls in the opening 19h for the first time and mounting and melting one solder ball for the second time. This will be described with reference to FIGS.

First, it is assumed that the radius of the opening 19h provided in the guide layer 19 and the radius of the solder balls 18b-1 and 18b-2 are r, and the height (thickness of the guide layer 19) h of the opening 19h is h = 3r. . In this case, the volume V1 of the opening 19h can be obtained as in the following equation (11).
V1 = π × r 2 × h = π × r 2 × 3r = 3πr 3 (11)
As shown in FIG. 19, when two solder balls 18b-1 are mounted in the opening 19h as the first step, the amount of solder (total volume of the solder balls) V2 is expressed by the following formula ( 12).
V2 = 4 × π × r 3 /3 × 2 = 8πr 3/3 ··· (12)

The volume V3 of the hollow portion in the opening 19h when the two solder balls 18b-1 mounted in the opening 19h are heat-treated can be obtained by the following equation (13).
V3 = V1-V2 = 3πr 3 -8πr 3/3 = πr 3/3 ··· (13)
That is, by performing the heat treatment on the two solder balls 18b-1 mounted on the opening 19h, as shown in FIG. 20, the height h = 3r of the opening 19h is 8r / 3. The solder layer 18ba is formed by being filled with the melted solder material, and a cavity portion having a height of r / 3 remains from the upper surface of the opening 19h.

Then, as shown in FIG. 21, with respect to the opening 19h, the case of mounting one solder ball 18b-2 as the second step, since the amount of solder V4 is a 4πr 3/3, this The volume V5 of the solder material that protrudes from the opening 19h when one solder ball 18b-2 mounted in the opening 19h is heat-treated can be obtained by the following equation (14).
V5 = V4-V3 = 4πr 3 /3-πr 3/3 = πr 3 ··· (14)
That is, as shown in FIG. 22, the solder material having a volume V5 = πr 3 protrudes from the upper surface of the guide layer 19 to form the upper portion of the external connection electrode 18.

  Also in the manufacturing method of the semiconductor device according to the present embodiment, the adjacent external connection electrodes 18 are well insulated from each other and the external connection is performed as in the semiconductor device described in the first embodiment. Thus, a semiconductor device having a large amount of solder constituting the working electrode 18 can be realized. Therefore, when the semiconductor device 10 is mounted on the circuit board 31, the standoff can be increased to suppress the occurrence of cracks at the joint portion, and good electrical connection between the semiconductor device 10 and the circuit board 31 can be achieved. Therefore, the manufacturing yield can be improved and the reliability of the semiconductor device can be improved.

In the numerical setting described above, the case where the diameter of the opening 19h and the diameter of the solder balls 18b-1 and 18b-2 are set to the same 2r has been described. However, in the actual manufacturing process, the opening 19h The diameters of the solder balls 18b-1 and 18b-2 are larger than the diameter 2r of the opening 19h so that the solder balls 18b-1 and 18b-2 to be mounted are satisfactorily placed in the opening 19h. It is set to be smaller. Further, since the volatile component is usually contained in the solder material, when the two solder balls 18b-1 are mounted on the opening 19h and heat-treated in the first process described above, volume V3 of the cavity portion (13) to become larger than pi] r 3/3 shown formula, the height of the hollow portion from the upper surface of the opening 19h is greater than r / 3. Therefore, when the diameter of the solder ball 18b-1 is set to be smaller than the diameter 2r of the opening 19h, the solder ball 18b-2 is satisfactorily mounted in the opening 19h in the second process described above, and the opening 19h. It is possible to prevent problems such as overhanging and rolling.

  In the above numerical setting, the case where the height h of the opening 19h is larger than the radius r of the solder balls 18b-1 and 18b-2 (h = 3r) has been described. However, the height h of the opening 19h Is smaller than the radius r of the solder balls 18b-1 and 18b-2 (h <r), the opening 19h has a height enough to prevent the solder ball 18b-2 from protruding from the opening 19h and rolling. If the height h (that is, the thickness of the guide layer 19) is set, the above-described manufacturing method can be applied satisfactorily. Needless to say, such a technical idea related to numerical setting is not only applied to the present embodiment, but also applied to the first embodiment described above.

<Third Embodiment>
Next, a third embodiment of the semiconductor device according to the present invention will be described.
FIG. 23 is a schematic configuration diagram showing a third embodiment of a semiconductor device according to the present invention. FIG. 23A is a schematic plan view showing the semiconductor device according to this embodiment, and FIG. 23B is a schematic cross-sectional view showing the semiconductor device according to this embodiment. Here, FIG. 23B is a symbol XXIIIB-XXIIIB in the semiconductor device shown in FIG. 23A (in this specification, as a symbol corresponding to the Roman numeral “23” shown in FIG. 23). Is a diagram showing a cross section along “XXIII”. FIG. 24 is a schematic cross-sectional view showing a state where the semiconductor device according to the third embodiment is mounted on a circuit board. Here, the description of the configuration equivalent to that of the first embodiment described above is simplified or omitted.

(Semiconductor device)
In the semiconductor device according to the first and second embodiments described above, the guide layer 19 is provided over the entire upper surface of the sealing layer 17 and is connected to all the columnar electrodes 16 exposed on the upper surface of the sealing layer 17. Thus, the case where it has the structure which provided the electrode 18 for several external connection was demonstrated. That is, the external connection electrodes 18 are arranged so as to match the arrangement of the columnar electrodes 16, and the number of the columnar electrodes 16 and the external connection electrodes 18 is set to be equal. In the third embodiment, a joint opening is formed by partially removing the guide layer 19 and the external connection electrode 18 provided on the upper surface of the sealing layer 17, and the sealing layer 17 is formed in the joint opening. The upper surface and the upper surface of the columnar electrode 16 are exposed.

  A semiconductor device 10-1 according to the third embodiment includes, for example, the semiconductor device 10 (see FIGS. 1 and 2) 10 according to the first embodiment, as shown in FIGS. Of the guide layer 19 provided on the semiconductor substrate 11, the semiconductor substrate 11 is viewed in plan view, and the guide layer 19 in the central region is removed to provide a bonding opening 19 m. The upper surface of the sealing layer 17 and the upper surface of the columnar electrode 16 are exposed in the bonding opening 19m. In other words, in the semiconductor device 10-1 according to the present embodiment, the guide layer 19 is partially provided on the upper surface of the sealing layer 17 provided on the semiconductor substrate 11, and the region where the guide layer 19 is provided ( The external connection electrode 18 is provided so as to match the arrangement of the columnar electrodes 16 only in the first region), and the sealing layer 17 is provided in the region where the other guide layer 19 is not provided (second region). In addition, the upper surfaces of the columnar electrodes 16 are exposed.

  When the semiconductor device 10-1 having such a configuration is mounted on the circuit board 31, for example, as shown in FIG. 24, in the region where the guide layer 19 of the semiconductor device 10-1 is provided, the guide layer 19 The external connection electrodes 18 provided so as to protrude from the upper surface of the circuit board 31 are joined to the connection pads 32 on the upper surface of the circuit board 31. As a result, an integrated circuit (not shown) provided on the semiconductor substrate 11 of the semiconductor device 10 is electrically connected to the connection pad 32 on the upper surface of the circuit substrate 31 via the wiring 15, the columnar electrode 16, and the external connection electrode 18. Connected.

  On the other hand, another semiconductor device 10-2 having a CSP structure, for example, is bonded to the bonding opening 19m, which is a region where the guide layer 19 of the semiconductor device 10-1 is not provided. Specifically, the solder bumps 20 provided on the package surface of the semiconductor device 10-2 are formed on the upper surface of the columnar electrode 16 exposed in the joint opening 19m provided in the guide layer 19 of the semiconductor device 10-1. Be joined. As a result, the integrated circuit (not shown) and wiring of the semiconductor device 10-2 are connected to the integrated circuit (not shown) and wiring 15 provided on the semiconductor substrate 11 of the semiconductor device 10-1, and the solder bump 20. Electrically connected.

  In the mounting structure shown in FIG. 24, the semiconductor device 10-2 to be joined in the joint opening 19m of the semiconductor device 10-1 is not particularly limited. For example, as shown in the first embodiment. The semiconductor device 10 (see FIGS. 1 and 2) having the above configuration may be applied. In this case, the upper portion of the external connection electrode protruding from the upper surface of the guide layer provided in the semiconductor device 10-2 is used as the solder bump 20 described above, and the semiconductor device 10-1 exposed in the bonding opening 19m. The semiconductor device 10-1 and the semiconductor device 10-2 are electrically connected by bonding to the upper surface of the columnar electrode 16.

  In the mounting structure shown in FIG. 24, for example, from the lower surface (upper surface side of the drawing) of the semiconductor substrate 11 of the semiconductor device 10-1 to the protruding point of the external connection electrode 18 protruding from the upper surface of the guide layer 19. Compared with the dimension T1, the lower surface of the semiconductor device 10-2 bonded to the bonding opening 19m from the lower surface of the semiconductor substrate 11 of the semiconductor device 10-1 (on the side opposite to the surface on which the solder bumps 20 are provided). The dimension T2 up to the surface (the lower surface side of the drawing) is set to be smaller. That is, as shown in FIG. 24, in a state where the semiconductor device 10-1 is mounted on the circuit board 31, the semiconductor devices 10-1 and 10-are arranged so that the lower surface of the semiconductor device 10-2 does not contact the circuit board 31. Each dimension in the thickness direction (vertical direction in the drawing) of 2 is set.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
FIG. 25 is a process cross-sectional view illustrating an example of a semiconductor device manufacturing method according to the third embodiment. Here, the characteristic part of the manufacturing method of the semiconductor device having the cross-sectional structure shown in FIG. The description of the steps equivalent to those in the first or second embodiment described above is simplified or omitted.

  In the manufacturing method of the semiconductor device according to the present embodiment, first, the passivation film 13, the protective film 14, the wiring 15, and the columnar electrode 16 are formed on the upper surface of the semiconductor wafer 21, as in the manufacturing method described in the first embodiment. And after forming the sealing layer 17 (refer FIG. 4-8), as shown to Fig.25 (a), the guide layer 19 is formed in the sealing layer 17 upper surface. Here, the guide layer 19 is provided with an opening 19h for forming the columnar electrode 16 and a bonding opening 19m for bonding another semiconductor device 10-2 having a CSP structure, for example. The upper surface of the columnar electrode 16 is exposed in the opening 19h. Further, the bonding opening 19m has an opening size corresponding to the outer dimension of the semiconductor device 10-2 to be bonded, and the upper surface of the sealing layer 17 and the upper surface of the columnar electrode 16 are exposed in the bonding opening 19m. Has been.

  As with the first embodiment described above, the guide layer 19 is formed by attaching a dry film on which the opening 19h and the bonding opening 19m are formed by performing exposure and development in advance on the semiconductor wafer 21. Alternatively, the photosensitive resin material may be applied and cured on the sealing layer 17, and then exposed and developed to form the opening 19h and the joint opening 19m in a pattern. Good.

  Next, as shown in FIG. 25 (b), one or a plurality of solder balls 18b having a predetermined volume or particle size are mounted in the opening 19h formed in the guide layer 19, and heat treatment (reflow) is performed. The process to be performed is repeated one or more times. As a result, the melted solder ball 18b is filled in the opening 19h, so that it is in electrical contact with the upper surface of the columnar electrode 16 and from the upper surface of the guide layer 19 as shown in FIG. An external connection electrode 18 having a protruding upper part is formed. Here, a state in which the upper surfaces of the sealing layer 17 and the columnar electrode 16 are exposed is maintained in the joint opening 19 m provided in the guide layer 19.

  In the semiconductor device according to this embodiment as well, the adjacent external connection electrodes 18 are well insulated from each other and the external connection is performed, as in the semiconductor devices shown in the first and second embodiments. Thus, a semiconductor device having a large amount of solder constituting the working electrode 18 can be realized. Therefore, when the semiconductor device 10 is mounted on the circuit board 31, the standoff can be increased to suppress the occurrence of cracks at the joint portion, and good electrical connection between the semiconductor device 10 and the circuit board 31 can be achieved. Can be secured.

  Further, according to the semiconductor device of the present embodiment, the semiconductor device 10-2 having a CSP structure, for example, can be bonded into the bonding opening 19m provided in the guide layer 19, so that a plurality of semiconductor chips are high. It is possible to easily realize a small-sized semiconductor device that is mounted in density. This will be specifically described below.

FIG. 26 is a schematic diagram illustrating a configuration example of a semiconductor device in which a plurality of semiconductor chips are integrated in a single package.
In general, when a plurality of semiconductor chips are integrated in a single package, for example, as shown in FIG. 26A, a plurality of semiconductor chips 10p-1, 10p-2 are formed on the upper surface side of an interposer (relay substrate) 41. Is known as a semiconductor device 10p having a configuration (hereinafter referred to as a first configuration example for convenience) that is disposed in a flat state and sealed with a sealing layer 42. Further, when a plurality of semiconductor chips are integrated in a single package, for example, as shown in FIG. 26B, a plurality of semiconductor chips 10p-1 and 10p-2 are stacked (stacked) on the upper surface side of the interposer 41. A semiconductor device 10p having a configuration (referred to as a second configuration example for the sake of convenience) that is disposed and sealed with a sealing layer 42 is also known.

  In these semiconductor devices 10p, the integrated circuits provided on the semiconductor chips 10p-1 and 10p-2 are connected to the connection pads 32 on the upper surface of the circuit board 31 via the solder bumps 44 provided on the lower surface side of the interposer 41. Is electrically connected. In FIGS. 26A and 26B, reference numeral 43 denotes a bonding wire that electrically connects the interposer 41 and the semiconductor chips 10p-1 and 10p-2.

  By the way, in the first configuration example, since the plurality of semiconductor chips 10p-1 and 10p-2 are arranged flat on the upper surface side of the interposer 41, an increase in the thickness of the package of the semiconductor device 10p is suppressed. Although possible, there is a problem that the mounting area increases. On the other hand, in the second configuration example, since the plurality of semiconductor chips 10p-1 and 10p-2 are stacked on the upper surface side of the interposer 41, an increase in mounting area can be suppressed, but the semiconductor device 10p. There is a problem that the thickness of the package increases.

  On the other hand, according to the mounting structure to which the semiconductor device according to the present embodiment is applied, the other semiconductor device 10-2 can be bonded in the bonding opening 19m provided in the guide layer 19. A small semiconductor device in which a plurality of semiconductor chips are mounted at high density can be easily realized while suppressing an increase in package thickness and mounting area.

  In each of the above-described embodiments, the case where the external connection electrode 18 is formed by mounting a solder ball in the opening 19h provided in the guide layer 19 and melting by heating is described. The present invention is not limited to this. That is, according to the present invention, the external connection electrode 18 may be formed by applying a solder paste to the opening 19h and melting it by heat treatment. Here, when the external connection electrode 18 is formed using a solder paste, since about half of the solder paste is flux, only about half of the solder paste applied to the opening 19 h contributes to the formation of the external connection electrode 18. do not do. Therefore, in such a case, the external connection electrode 18 can be formed by repeating a series of steps of applying a solder paste to the opening 19h, performing heat treatment, and melting a plurality of times.

  In the semiconductor device shown in each of the above-described embodiments, the wiring 15 having the two-layer structure including the base metal layer 15-1 and the upper metal layer 15-2 is used as the wiring 15 connected to the connection pad 12 and the columnar electrode 16. The case where it has is demonstrated. This wiring structure is merely an example for explaining the embodiment, and the present invention is not limited to this. That is, the wiring applied to the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the present invention may be composed of, for example, a single metal layer or a conductive layer, or a plurality of three or more layers. It may have a wiring structure in which metal layers or conductive layers are laminated.

  As mentioned above, although some embodiment of this invention was described, this invention is not limited to embodiment mentioned above, It includes the invention described in the claim, and its equivalent range.

Hereinafter, the invention described in the scope of claims of the present application will be appended.

(Appendix)
The invention described in claim 1
A semiconductor device in which an external connection electrode is provided on one side of a semiconductor substrate,
A guide layer on the semiconductor substrate;
The external connection electrode is:
Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
The peripheral side surface of the columnar part is covered with the guide layer,
The protrusion protrudes from the guide layer;
The external connection electrode does not protrude from a region corresponding to the guide layer as seen from the one surface side of the semiconductor substrate,
The columnar part and the protruding part are integrally formed of a solder material,
This is a semiconductor device.

The invention described in claim 2
2. The semiconductor device according to claim 1, wherein a height of the protruding portion is 20% or less of a height of the columnar portion whose peripheral side surface is covered with the guide layer.

The invention according to claim 3
The height of the columnar portion is larger than the diameter of the columnar portion, and the height of the protruding portion is 10% or less of the height of the columnar portion whose peripheral side surface is covered with the guide layer. The semiconductor device according to claim 1.
The invention according to claim 4
The external connection electrode is formed on a columnar electrode provided on one surface of the semiconductor substrate,
The columnar part of the external connection electrode and the columnar electrode have the same shape as viewed from one side of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.

The invention described in claim 5
In the mounting structure of the semiconductor device in which the external connection electrode of the semiconductor device in which the external connection electrode is provided on one surface side of the semiconductor substrate is bonded and mounted to the connection pad provided in the circuit board.
The external connection electrode is:
Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
The columnar part and the protruding part are integrally formed of a solder material,
The peripheral side surface of the columnar part is covered with a guide layer,
The protruding portion protrudes from the guide layer and is bonded to the connection pad,
Furthermore, the diameter of the projecting portion viewed in plan from one surface of the semiconductor substrate is 110% or less of the diameter of the columnar portion viewed in plan from one surface of the semiconductor substrate.
This is a mounting structure of a semiconductor device.
The invention described in claim 6
In the mounting structure of the semiconductor device in which the external connection electrode of the semiconductor device in which the external connection electrode is provided on one surface side of the semiconductor substrate is bonded and mounted to the connection pad provided in the circuit board.
The external connection electrode is:
Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
The columnar part and the protruding part are integrally formed of a solder material,
The peripheral side surface of the columnar part is covered with a guide layer,
The protruding portion protrudes from the guide layer and is bonded to the connection pad,
The height of the protruding portion is 20% or less of the height of the columnar portion whose peripheral side surface is covered with the guide layer.

The invention described in claim 7
The external connection electrode is formed on a columnar electrode provided on one surface of the semiconductor substrate,
The columnar part of the external connection electrode and the columnar electrode have the same shape as viewed from one side of the semiconductor substrate,
7. A semiconductor device mounting structure according to claim 5, wherein the semiconductor device mounting structure is a semiconductor device mounting structure.

The invention according to claim 8 provides:
A first step of preparing the semiconductor device according to claim 1;
A second step of bonding the external connection electrode of the semiconductor device to the connection pad of a circuit board having a connection pad on the surface;
A method for manufacturing a semiconductor device, comprising:

The invention according to claim 9 is:
The external connection electrode of the semiconductor device prepared in the first step has a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
And as for the diameter of the protrusion that is bonded to the connection pad of the circuit board in the second step when the protrusion is viewed in plan from one surface of the semiconductor substrate, the peripheral side surface is covered by the guide layer. 110% or less of the diameter of the columnar part
The method of manufacturing a semiconductor device according to claim 8.

The invention according to claim 10 is:
Prepare a semiconductor substrate with a conducting part on one side,
Forming a guide layer having an opening through which an end of the conducting portion is exposed;
A method of manufacturing a semiconductor device, wherein one end is connected to an end of the conducting portion in the opening, and the other end forms an external connection electrode protruding from the guide layer,
The external connection electrode is composed of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
The peripheral side surface of the columnar part is covered with the guide layer,
The protruding portion is formed so as to protrude from the guide layer within a range of the columnar portion in a plan view of the semiconductor substrate from the one surface,
The columnar part and the protruding part are integrally formed of a solder material,
This is a method for manufacturing a semiconductor device.
The invention according to claim 11
The external connection electrode is formed on a columnar electrode provided on one surface of the semiconductor substrate,
The columnar part of the external connection electrode and the columnar electrode have the same shape as viewed from one side of the semiconductor substrate,
The method of manufacturing a semiconductor device according to claim 10.
The invention according to claim 12
Bonding the external connection electrode to the connection pad of the circuit board having a connection pad on the surface,
The diameter of the protruding portion in plan view from one surface of the semiconductor substrate is 110% or less of the diameter of the columnar portion whose peripheral side surface is covered with the guide layer.
12. The method of manufacturing a semiconductor device according to claim 10, wherein the method is a semiconductor device manufacturing method.
The invention according to claim 13
Bonding the external connection electrode to the connection pad of the circuit board having a connection pad on the surface,
The height of the protruding portion of the protruding portion from the guide layer is 20% or less of the height of the columnar portion whose peripheral side surface is covered by the guide layer.
13. The method of manufacturing a semiconductor device according to claim 10, wherein the method is a semiconductor device manufacturing method.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 10-1 Semiconductor device 11 Semiconductor substrate 12 Connection pad 13 Passivation film 14 Protective film 15 Wiring 16 Columnar electrode 17 Sealing layer 18 External connection electrode 18b Solder ball 18b-1 Solder ball 18b-2 Solder ball 18c Crack 19 Guide layer 19h Opening 19m Joint opening 20 Solder bump 21 Semiconductor wafer 31 Circuit board 32 Connection pad

A semiconductor device according to the present invention includes:
A semiconductor device in which a right columnar columnar electrode is provided on one surface side of a semiconductor substrate, and an external connection electrode is provided on the columnar electrode ,
The external connection electrode is:
Consists of a right columnar columnar part and an upper part on one end side of the columnar part,
The columnar portion of the external connection electrode and the columnar electrode have the same shape in plan view from one surface of the semiconductor substrate,
The upper portion is formed so as to project from one end side of the columnar portion in a plan view from the one surface side of the semiconductor substrate, in a range of the planar shape of the columnar portion, and in a side view,
The height of the upper part is 20% or less of the height of the columnar part,
The columnar part and the upper part are integrally formed of a solder material,
It is characterized by that.

The mounting structure of the semiconductor device according to the present invention is as follows:
A conductive portion is provided on one surface side of the semiconductor substrate, and the external connection electrode of the semiconductor device in which the external connection electrode is provided on the conductive portion is bonded to a connection pad provided on the substrate. In the mounting structure of the semiconductor device
The external connection electrode is:
Consists of a right columnar columnar part and an upper part on one end side of the columnar part,
A resin layer is formed between the substrate and the semiconductor device, and the peripheral side surface of the columnar portion of the external connection electrode is covered with the resin layer,
The columnar part and the upper part are integrally formed of a solder material,
The upper part is formed to project from one end side of the columnar part in a side view and is joined to the connection pad,
Furthermore, the diameter of the upper part when viewed from one surface of the semiconductor substrate is 110% or less of the diameter when the columnar part is viewed from one surface of the semiconductor substrate.
It is characterized by that.
The mounting structure of the semiconductor device according to the present invention is as follows:
A cylindrical columnar electrode is provided on one surface side of the semiconductor substrate, and the external connection electrode of the semiconductor device in which the external connection electrode is provided on the columnar electrode is bonded to a connection pad provided on the substrate. In the mounting structure of the semiconductor device to be mounted,
The external connection electrode is:
Consists of a right columnar columnar part and an upper part on one end side of the columnar part,
The columnar portion of the external connection electrode and the columnar electrode have the same shape in plan view from one surface of the semiconductor substrate,
A resin layer is formed between the substrate and the semiconductor device, and the peripheral side surface of the columnar portion of the external connection electrode is covered with the resin layer,
The columnar part and the upper part are integrally formed of a solder material,
The upper part is formed to project from one end side of the columnar part in a side view and is joined to the connection pad,
Furthermore, the diameter of the upper part when viewed from one surface of the semiconductor substrate is 110% or less of the diameter when the columnar part is viewed from one surface of the semiconductor substrate.
It is characterized by that.
A method for manufacturing a semiconductor device according to the present invention includes:
A first step of preparing the semiconductor device according to claim 1 ;
A second step of bonding the external connection electrode of the semiconductor device to the connection pad of a substrate having a connection pad on its surface, and a method of manufacturing a semiconductor device ,
At the time of joining, the peripheral side surface of the columnar portion of the external connection electrode is covered with a resin layer .
A method for manufacturing a semiconductor device according to the present invention includes:
Preparing a semiconductor substrate provided with an insulating resin layer having a conductive portion on one surface and an opening from which an end of the conductive portion is exposed;
A method of manufacturing a semiconductor device, wherein an external connection electrode having one end connected to an end of the conductive portion is formed in the opening.
The external connection electrode is composed of a right columnar columnar part and an upper part on one end side of the columnar part,
The upper part is formed in a range of the columnar part formation region in plan view of the semiconductor substrate from the one surface;
The height of the upper part is 20% or less of the height of the columnar part,
The columnar part and the upper part are integrally formed of a solder material.
It is characterized by that.
A method for manufacturing a semiconductor device according to the present invention includes:
Preparing a semiconductor substrate provided with an insulating resin layer having a columnar electrode having a right cylindrical shape on one surface and an opening from which an end of the columnar electrode is exposed;
A method of manufacturing a semiconductor device, wherein an external connection electrode having one end connected to an end of the columnar electrode is formed in the opening.
The external connection electrode comprises a right columnar columnar part and an upper part protruding from one end side of the columnar part,
The columnar portion of the external connection electrode and the columnar electrode have the same shape in plan view from one surface of the semiconductor substrate,
The upper part is formed in a range of the columnar part formation region in plan view of the semiconductor substrate from the one surface;
The columnar part and the upper part are integrally formed of a solder material.
It is characterized by that.

Claims (13)

  1. A semiconductor device in which an external connection electrode is provided on one side of a semiconductor substrate,
    A guide layer on the semiconductor substrate;
    The external connection electrode is:
    Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
    The peripheral side surface of the columnar part is covered with the guide layer,
    The protrusion protrudes from the guide layer;
    The external connection electrode does not protrude from a region corresponding to the guide layer as seen from the one surface side of the semiconductor substrate,
    The columnar part and the protruding part are integrally formed of a solder material,
    A semiconductor device.
  2.   2. The semiconductor device according to claim 1, wherein a height of the protruding portion is 20% or less of a height of the columnar portion whose peripheral side surface is covered with the guide layer.
  3.   The height of the columnar portion is larger than the diameter of the columnar portion, and the height of the protruding portion is 10% or less of the height of the columnar portion whose peripheral side surface is covered with the guide layer. The semiconductor device according to claim 1.
  4. The external connection electrode is formed on a columnar electrode provided on one surface of the semiconductor substrate,
    The columnar part of the external connection electrode and the columnar electrode have the same shape as viewed from one side of the semiconductor substrate,
    The semiconductor device according to claim 1, wherein:
  5. In the mounting structure of the semiconductor device in which the external connection electrode of the semiconductor device in which the external connection electrode is provided on one surface side of the semiconductor substrate is bonded and mounted to the connection pad provided in the circuit board.
    The external connection electrode is:
    Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
    The columnar part and the protruding part are integrally formed of a solder material,
    The peripheral side surface of the columnar part is covered with a guide layer,
    The protruding portion protrudes from the guide layer and is bonded to the connection pad,
    Furthermore, the diameter of the projecting portion viewed in plan from one surface of the semiconductor substrate is 110% or less of the diameter of the columnar portion viewed in plan from one surface of the semiconductor substrate.
    A mounting structure of a semiconductor device.
  6. In the mounting structure of the semiconductor device in which the external connection electrode of the semiconductor device in which the external connection electrode is provided on one surface side of the semiconductor substrate is bonded and mounted to the connection pad provided in the circuit board.
    The external connection electrode is:
    Consists of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
    The columnar part and the protruding part are integrally formed of a solder material,
    The peripheral side surface of the columnar part is covered with a guide layer,
    The protruding portion protrudes from the guide layer and is bonded to the connection pad,
    The semiconductor device mounting structure is characterized in that a height of the protruding portion is 20% or less of a height of the columnar portion whose peripheral side surface is covered with the guide layer.
  7. The external connection electrode is formed on a columnar electrode provided on one surface of the semiconductor substrate,
    The columnar part of the external connection electrode and the columnar electrode have the same shape as viewed from one side of the semiconductor substrate,
    7. The semiconductor device mounting structure according to claim 5, wherein the semiconductor device mounting structure is a semiconductor device mounting structure.
  8. A first step of preparing the semiconductor device according to claim 1;
    A second step of bonding the external connection electrode of the semiconductor device to the connection pad of a circuit board having a connection pad on the surface;
    A method for manufacturing a semiconductor device, comprising:
  9. The external connection electrode of the semiconductor device prepared in the first step has a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
    And as for the diameter of the protrusion that is bonded to the connection pad of the circuit board in the second step when the protrusion is viewed in plan from one surface of the semiconductor substrate, the peripheral side surface is covered by the guide layer. 110% or less of the diameter of the columnar part
    The method for manufacturing a semiconductor device according to claim 8.
  10. Prepare a semiconductor substrate with a conducting part on one side,
    Forming a guide layer having an opening through which an end of the conducting portion is exposed;
    A method of manufacturing a semiconductor device, wherein one end is connected to an end of the conducting portion in the opening, and the other end forms an external connection electrode protruding from the guide layer,
    The external connection electrode is composed of a right columnar columnar portion and a protruding portion on one end side of the columnar portion,
    The peripheral side surface of the columnar part is covered with the guide layer,
    The protruding portion is formed so as to protrude from the guide layer within a range of the columnar portion in a plan view of the semiconductor substrate from the one surface,
    The columnar part and the protruding part are integrally formed of a solder material,
    A method for manufacturing a semiconductor device.
  11. The external connection electrode is formed on a columnar electrode provided on one surface of the semiconductor substrate,
    The columnar part of the external connection electrode and the columnar electrode have the same shape as viewed from one side of the semiconductor substrate,
    The method of manufacturing a semiconductor device according to claim 10.
  12. Bonding the external connection electrode to the connection pad of the circuit board having a connection pad on the surface,
    The diameter of the protruding portion in plan view from one surface of the semiconductor substrate is 110% or less of the diameter of the columnar portion whose peripheral side surface is covered with the guide layer.
    12. The method of manufacturing a semiconductor device according to claim 10, wherein the method is a semiconductor device.
  13. Bonding the external connection electrode to the connection pad of the circuit board having a connection pad on the surface,
    The height of the protruding portion of the protruding portion from the guide layer is 20% or less of the height of the columnar portion whose peripheral side surface is covered by the guide layer.
    13. The method for manufacturing a semiconductor device according to claim 10, wherein the method is a semiconductor device manufacturing method.
JP2015103968A 2015-05-21 2015-05-21 Semiconductor device, method for mounting the same, and method of manufacturing the same Pending JP2015167254A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005503020A (en) * 2001-09-12 2005-01-27 ダウ コーニング コーポレーション Semiconductor device with compliant electrical terminal, apparatus including semiconductor device, and manufacturing method thereof
US7067350B1 (en) * 2005-01-31 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device using electrical contacts formed in an isolation layer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005503020A (en) * 2001-09-12 2005-01-27 ダウ コーニング コーポレーション Semiconductor device with compliant electrical terminal, apparatus including semiconductor device, and manufacturing method thereof
US7067350B1 (en) * 2005-01-31 2006-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device using electrical contacts formed in an isolation layer

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