JP2015146607A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage identification device and a clock control device, which can identify a magnitude of an identification object voltage with high efficiency while inhibiting increases in circuit size and power consumption.SOLUTION: A semiconductor device comprises: a reference voltage generation circuit 12 to which power is supplied; an output terminal to which an output voltage is supplied; an identification circuit 14 which is connected to the reference voltage generation circuit 12 and the output terminal and in which an output voltage is generated based on an identification object voltage; and a constant current source 22 which is connected to the identification circuit 14 and ground potential GND, for generating a constant current.

Description

  The present invention relates to a semiconductor device that identifies the magnitude of a voltage.

  Clock hands (hereinafter referred to as “pointers”) such as a second hand, a minute hand and an hour hand operate by receiving a driving force generated by a motor. Control related to the operation of the hands is performed using a clock LSI (Large Scale Integration). The clock LSI temporarily cuts off the supply of current to the motor after a predetermined time (for example, several ms) from the start of supplying the drive current to the motor in order to move the hands with the minimum power. . At this time, if the pointer moves, a counter electromotive voltage is generated from the motor, and if the pointer does not move, no counter electromotive voltage is generated. When the pointer does not move, it is necessary to supply current to the motor again for a longer time. The clock LSI needs to identify whether or not the hands have moved in order to continuously control the operation of the hands. As a method for identifying whether or not the pointer has moved, a method for identifying the magnitude of the counter electromotive voltage generated from the motor is known.

  If the threshold value to be compared in identifying the magnitude of the back electromotive voltage is lower than the originally planned value, erroneous identification due to noise may occur. That is, the timepiece LSI recognizes that the pointer has moved even though the pointer has not moved. For this reason, the driving current is not supplied to the motor again, and as a result, a problem that the pointer does not move occurs. On the other hand, if the threshold value is higher than the originally scheduled value, the timepiece LSI recognizes that the pointer has not moved although the pointer has moved. For this reason, an unnecessary driving current is supplied to the motor again, and as a result, a problem of increased current consumption occurs. For this reason, when identifying the magnitude of the back electromotive voltage, it is necessary to set the threshold value to be compared to an optimum value (allowable range of the value initially planned). The optimum value varies depending on the motor used.

  FIG. 8 shows an example of the configuration of a NAND circuit 100 mounted on a timepiece and used for identifying the magnitude of the back electromotive voltage. As shown in the figure, the NAND circuit 100 includes P-channel MOS field effect transistors (hereinafter referred to as “PMOS transistors”) 104 and 106 and N-channel MOS field effect transistors (hereinafter referred to as “NMOS transistors”). 108 and 110 are included. The NAND circuit 100 also has a voltage line VDD to which a power supply voltage is applied from a power supply, and an enable line to which a voltage for selectively switching the on state and the off state of each of the PMOS transistor 106 and the NMOS transistor 108 is applied. EN and an output terminal 112 to which a voltage corresponding to a comparison result obtained by comparing the magnitude of the back electromotive force with a threshold value is applied. In the NAND circuit 100 configured as described above, when the power supply is shared with the power supply of the clock LSI, the gate length of each of the PMOS transistor 104 and the NMOS transistor 108 in accordance with the power supply (for example, battery) and the motor 102 used. The threshold is adjusted by adjusting the gate width.

  However, as timepieces become smaller, the power generation voltage decreases due to, for example, a reduction in the number of batteries or the number of solar battery panels, and a decrease in the power supply voltage of the clock LSI due to the use of rechargeable small secondary batteries. Accordingly, it has become necessary to make the thresholds correspond to a wide range of power supply voltages. For this reason, if the power supply is shared with the power supply of the timepiece LSI as in the NAND circuit 100, the threshold value depends on the magnitude of the power supply voltage. In the conventional NAND circuit 100, in order to set the threshold value to a value close to the power supply voltage, the gate width of the PMOS transistor 104 is increased to increase the ability of the PMOS transistor 104 to pass current, and the NMOS transistor 108. It is necessary to reduce the capability of flowing current in the NMOS transistor 108 by increasing the gate length of the transistor, and to greatly shift the ratio of the capability of flowing current between the PMOS transistor 104 and the NMOS transistor 108, increasing the circuit area. There was a problem of inviting.

  Therefore, the present inventor examined the application of the NAND circuit 100A shown in FIG. 9 as an example instead of the NAND circuit 100 in order to suppress an increase in circuit area. In the NAND circuit 100A, the regulator 114 is used to make the power supply voltage applied to the voltage line VDD constant by the power supply, and the reference voltage obtained by making the constant voltage is applied to the voltage line VSH. As a result, a reference voltage independent of the power supply voltage can be supplied to VSH, and a NAND circuit having a threshold independent of the power supply voltage is realized.

  However, when the NAND circuit 100A is applied, it is difficult to apply a capacitive element having a sufficient capacitance in the regulator 114 due to the recent demand for further downsizing of the timepiece LSI, so that the voltage line VSH ( When a back electromotive force is applied to each gate terminal of the PMOS transistor 104 and the NMOS transistor 108 because there is no capacitor of sufficient capacity on the output side of the regulator 114, a through current is generated in the NAND circuit 100A, and the regulator 114 There was a problem in that the output decreased instantaneously and the threshold also decreased. In this specification, the through current indicates a current that passes through a so-called CMOS circuit (switching circuit) configured by combining, for example, a PMOS transistor and an NMOS transistor (for example, Patent Document 1 and Patent Document 2). See). In the example shown in the figure, when the signal level of a signal input from the motor 102 to the NAND circuit 100A as a back electromotive voltage transitions from a low level to a high level, or from a high level to a low level, the PMOS transistor 104 only for a predetermined period. Each of the NMOS transistor 108 and the NMOS transistor 108 is turned on, and a current flowing from the voltage line VSH to the ground line GND is a through current.

  The cause of the problem that occurs when the NAND circuit 100A shown in FIG. 9 is applied will be described with reference to an example of the regulator shown in FIG. 10 and FIG. As shown in FIG. 10, the regulator 114 includes an operational amplifier 116, a PMOS transistor 118, a constant current source 120, and a capacitor 122. Note that the capacitor 122 is generally used for suppressing a delay in switching operation by discharging a charge and turning on the PMOS transistor 118 even when a load current is generated when the PMOS transistor 118 is off. Used for the regulator 114. In the regulator 114, the PMOS transistor 118 is in an off state in the state where there is no current load on the output side VSH. However, in this state, when a sudden current load is generated in the VSH due to the through current, Since the PMOS transistor 118 is in the off state, a current corresponding to the capacitance stored in the capacitor 122 is temporarily applied to VSH. However, as described above, since it is difficult to secure a sufficient area of the capacitor 122, the regulator 114 is used as an example as shown in FIG. 11 from the time when the capacitance of the capacitor 122 reaches the bottom until the PMOS transistor 118 is turned on. To VSH is temporarily reduced. Along with this, as an example, the threshold value instantaneously decreases as shown in FIG.

  Here, as means for solving the problem that occurs in the NAND circuit 100A, for example, the inventor outputs the output of the regulator 114 to the outside as a terminal of a watch LSI as shown in FIG. A configuration in which a capacitor 124 is added was examined. According to this configuration, as shown in FIG. 11, it was found that an instantaneous decrease in the output of the regulator 114 and, as an example, an instantaneous decrease in the threshold as shown in FIG. 11 can be prevented.

JP 2001-44822 A JP 2007-249712 A

  However, the above-mentioned measure of adding the capacitor 124 to the output side of the regulator 114 has a problem that the number of parts increases and the cost and mounting area increase. Therefore, the inventor further connected the current load to the output side of the regulator 114 in the example shown in FIG. 9 as a method for solving the problem caused in the NAND circuit 100A without adding a capacitor, and always grounded the current. A method for preventing the PMOS transistor 118 of the regulator 114 from temporarily transitioning from the on state to the off state by flowing the signal to the line GND was examined. However, in this case, an increase in mounting area due to the addition of a capacitor can be avoided, but a problem that current consumption increases occurs.

  These problems are not limited to identifying the magnitude of the back electromotive voltage in order to control the operation of the pointer, but also include a circuit having a switching circuit in which a through current flows (for example, a NAND circuit, an AND circuit, an OR circuit). Needless to say, this is also applicable to any device that identifies the magnitude of the identification target voltage using a NOR circuit or the like.

  The present invention has been made to solve the above problems, and provides a semiconductor device capable of accurately identifying the magnitude of the voltage to be identified while suppressing an increase in circuit scale and current consumption. Objective.

  To achieve the above object, the semiconductor device according to claim 1 is connected to a reference voltage generating circuit to which power is supplied, an output terminal to which an output voltage is supplied, the reference voltage generating circuit and the output terminal. And an identification circuit that generates the output voltage based on a voltage to be identified, and a constant current source that is connected to the identification circuit and a ground potential and generates a constant current.

  According to the present invention, it is possible to accurately identify the magnitude of the identification target voltage while suppressing an increase in circuit scale and current consumption.

It is a block diagram which shows an example of the principal part structure of the voltage identification apparatus which concerns on embodiment. It is a block diagram which shows an example of a structure of the timepiece control apparatus which concerns on 1st Embodiment. It is a flowchart which shows the flow of a process of the voltage identification instruction | indication processing program which concerns on 1st Embodiment. It is a circuit diagram which shows an example of the equivalent circuit of the principal part of the voltage identification apparatus which concerns on 1st Embodiment. The graph which shows the correlation with the magnitude | size of the voltage between the gate terminal and source terminal of a PMOS transistor in the CMOS circuit which concerns on 1st Embodiment, and the largest magnitude | size of the electric current which can be sent between the source terminal and drain terminal of a PMOS transistor. Indication It is a block diagram which shows an example of a structure of the timepiece control apparatus which concerns on 2nd Embodiment. It is a block diagram which shows an example of a structure of the timepiece control apparatus which concerns on 3rd Embodiment. It is a block diagram which shows an example of a structure of the NAND circuit mounted in the conventional timepiece control apparatus. It is a block diagram which shows another example of a structure of the NAND circuit mounted in the conventional timepiece control apparatus. It is a circuit diagram which shows an example of a structure of a regulator in the conventional timepiece control apparatus. It is a time chart for demonstrating the reason a threshold value changes. It is a circuit diagram which shows another example of a structure of a regulator in the conventional timepiece control apparatus.

  FIG. 1 is a block diagram showing an example of a main configuration of a voltage identification device 10 according to the present invention. As shown in FIG. 1, the voltage identification device 10 includes a reference voltage generation circuit 12, an identification circuit 14, and a control unit 16.

  The reference voltage generation circuit 12 generates a reference voltage having a predetermined magnitude. The identification circuit 14 is an applied line 18 to which the identification target voltage is applied, a voltage line VSH to which the reference voltage generated by the reference voltage generation circuit 12 is applied, and another reference voltage having a magnitude different from the reference voltage. Switching according to the magnitude of the identification target voltage applied to the applied line 18 and inserted between the voltage line VSH and the ground line GND so that the ground line GND to which a certain ground voltage is applied becomes conductive. And a switching circuit 20 for performing the identification, and the magnitude of the identification target voltage is identified by comparing the magnitude of the identification target voltage applied to the applied line 18 with a threshold value.

  The control unit 16 performs switching so that the magnitude of the current flowing between the voltage line VSH and the ground line GND is maintained at a predetermined magnitude while the discrimination circuit 14 identifies the magnitude of the identification target voltage. By controlling the magnitude of the resistor 22 between the circuit 20 and the ground line GND, the magnitude (current amount) of the current flowing between the voltage line VSH and the ground line GND is controlled.

  Hereinafter, in each embodiment of the present invention, the voltage identification device 10 is positioned as a voltage identification device that identifies the magnitude of the counter electromotive voltage generated from a motor that generates power for moving the hands, A case where the present invention is applied to a timepiece control device that controls operations will be described as an example.

  [First Embodiment]

  FIG. 2 is a configuration diagram showing an example of a configuration when applied to a timepiece control device 11 including a voltage identification device 10A as a specific example of the voltage identification device 10 shown in FIG. As shown in the figure, the timepiece control device 11 includes a power supply 30 and a motor 13 in addition to the voltage identification device 10A. The motor 13 is connected to the power supply 30 so that a driving voltage is applied from the power supply 30. A drive shaft (not shown) of the motor 13 is connected via a gear mechanism or the like so that a drive force can be transmitted to a rotation shaft of a watch pointer (not shown). Therefore, the pointer operates by receiving the driving force generated by the motor 13.

  The voltage identification device 10A includes a regulator 15, a NAND circuit 14A, and a control unit 16A. The NAND circuit 14A functions as the identification circuit 14 shown in FIG. The control unit 16A controls the operation of the watch hands by controlling the drive of the motor 13 by controlling the power source 30, and functions as the control unit 16 shown in FIG.

  The regulator 15 functions as the reference voltage generation circuit 12 shown in FIG. 1, and is connected to the power supply 30 via the voltage line VDD. The regulator 15 is connected to the NAND circuit 14A via the voltage line VSH.

  The NAND circuit 14 </ b> A is connected to the motor 13 via the applied line 18. The NAND circuit 14A is connected to the control unit 16A. Further, the control unit 16A is connected to the voltage line VDD so that the power supply voltage is applied from the power supply 30. The control unit 16A is connected to the power supply 30 so that the power supply 30 can be controlled. Further, the motor 13 is connected to the power supply 30 so that a driving voltage is applied from the power supply 30.

  In the regulator 15, as shown in FIG. 10 as an example, the source terminal of the PMOS transistor 15B is connected to the voltage line VDD, the drain terminal of the PMOS transistor 15B is one terminal of the constant current source 15C, one electrode of the capacitor 15D, and It is connected to the voltage line VSH. The other terminal of the constant current source 15C is connected to the ground line GND.

  The non-inverting input terminal of the operational amplifier 15A is connected to the drain terminal of the PMOS transistor 15B, and the output terminal of the operational amplifier 15A is connected to the gate terminal of the PMOS transistor 15B and the other electrode of the capacitor 15D. A predetermined voltage (voltage having a constant magnitude) is applied to the inverting input terminal of the operational amplifier 15A. Further, the operational amplifier 15A is connected to the voltage line VDD and the ground line GND, whereby a driving voltage is supplied from the power supply 30 via the voltage line VDD.

  As shown in FIG. 2 as an example, the NAND circuit 14A includes a CMOS circuit 32 functioning as the switching circuit 20 shown in FIG. 1, a PMOS transistor 19 as second switching means, an NMOS transistor 23 as first switching means, and a back electromotive force. The output terminal 25 is configured to output a signal corresponding to a comparison result obtained by comparing the magnitude of the voltage with the magnitude of the threshold voltage. The CMOS circuit 32 includes a PMOS transistor 17 as a first switching element and an NMOS transistor 21 as a second switching element. In the PMOS transistor 17, the source terminal is connected to the voltage line VSH, the drain terminal is connected to the drain terminal of the NMOS transistor 21, and the gate terminal is connected via the applied line 18 so that the counter electromotive voltage of the motor 13 is applied. It is connected to the motor 13. In the NMOS transistor 21, the source terminal is connected to the drain terminal of the NMOS transistor 23, and the gate terminal is connected to the motor 13 via the applied line 18 so that the counter electromotive voltage of the motor 13 is applied. A connection point between the drain terminal of the PMOS transistor 17 and the drain terminal of the NMOS transistor 21 is connected to the output terminal 25 via a wiring OUT as a third voltage line.

  In the PMOS transistor 19, the source terminal is connected to the voltage line VSH, and the drain terminal is connected to the wiring OUT.

  The timepiece control device 11 includes a system controller 36. The system controller 36 executes a predetermined program process to control the entire clock control device 11 (a central processing unit), a control program for controlling the basic operation of the clock control device 11, and a voltage identification instruction to be described later. It includes a ROM (Read Only Memory) that is a storage medium in which processing programs are stored in advance, a RAM (Random Access Memory) that is a storage medium used as a work area when executing various programs, and a nonvolatile memory. It is a general purpose computer. The system controller 36 is connected to the power supply 30. The system controller 36 is connected to the gate terminal of the PMOS transistor 19 and the gate terminal of the NMOS transistor 23 via the enable line EN. Accordingly, the system controller 36 can control the power supply 30 and control the switching operations of the PMOS transistor 19 and the NMOS transistor 23 of the NAND circuit 14A.

  The control unit 16A includes a current mirror circuit 38 and a reference current generation circuit 40. The current mirror circuit 38 includes a reference current generation circuit 40 and an NMOS transistor 42 as a third switching element. The reference current generation circuit 40 generates a reference current i1 having a predetermined magnitude based on the power supply voltage applied from the power supply 30 via the voltage line VDD. The reference current generation circuit 40 includes a resistor 44, NMOS transistors 46 and 48, and PMOS transistors 50 and 52. One end of the resistor 44 is connected to the ground line GND, and the other end of the resistor 44 is connected to the source terminal of the NMOS transistor 46. The drain terminal of the NMOS transistor 46 is connected to the drain terminal of the PMOS transistor 50. The source terminal of the PMOS transistor 50 is connected to the voltage line VDD, and the gate terminal of the PMOS transistor 50 is connected to the gate terminal of the PMOS transistor 52 and its own drain terminal.

  The source terminal of the NMOS transistor 48 is connected to the ground line GND, and the gate terminal of the NMOS transistor 48 is connected to the gate terminal of the NMOS transistor 46 and its own drain terminal. The drain terminal of the PMOS transistor 52 is connected to the drain terminal of the NMOS transistor 48, and the source terminal of the PMOS transistor 52 is connected to the voltage line VDD.

  The current mirror circuit 38 has a wiring 54 as a constant voltage line to which a constant voltage corresponding to the reference current i1 is applied. The wiring 54 is arranged across the reference current generation circuit 40 and the current mirror circuit 38, and the connection point α between the drain terminal of the NMOS transistor 48 and the drain terminal of the PMOS transistor 52 is connected to the wiring 54 as a constant voltage line. To the gate terminal of the NMOS transistor 42. The source terminal of the NMOS transistor 42 is connected to the ground line GND, and the drain terminal of the NMOS transistor 42 is connected to the source terminal of the NMOS transistor 23. As described above, the current mirror circuit 16A is configured such that the gate terminal of the NMOS transistor 42 inserted between the NMOS transistor 23 and the ground line GND and the connection point α of the reference current generation circuit 40 are current mirror connected. Therefore, a mirror current corresponding to the reference current i1 flows between the source terminal and the drain terminal of the NMOS transistor 42. In the figure, an example in which a current having the same magnitude as the reference current i1 flows as the mirror current is shown. However, the present invention is not limited to this, and the mirror current is changed to the reference current i1 by changing the current mirror ratio. A current having a magnitude different from the magnitude may be used.

  In the voltage identification device 10A configured as described above, the resistance 22 between the switching circuit 20 and the ground line GND shown in FIG. 1, that is, the on-resistance of the NMOS transistor 42 shown in FIG. It becomes possible to control the magnitude (current amount) of the current flowing between VSH and the ground line GND, and as a result, a mirror current corresponding to the reference current i1 flows between the voltage line VSH and the ground line GND. It will be.

  Next, the operation of the timepiece control device 11 will be described.

  In order to operate the hands of the timepiece, when current is supplied from the power supply 30 to the motor 13 in accordance with an instruction from the system controller 36, the motor 13 starts driving. When the supply of current is stopped in accordance with an instruction from the system controller 36 after a predetermined time (for example, several ms) after the supply of current from the power supply 30 to the motor 13 is started at the start of the operation of the pointer, the driving of the motor 13 is stopped. This stops the operation of the pointer. When the pointer operates in this way, a counter electromotive voltage is generated from the motor 13. The magnitude of the back electromotive voltage is identified by the NAND circuit 14A (for example, whether or not the magnitude of the back electromotive voltage exceeds a threshold value), and a signal based on the voltage indicating the identification result is output from the output terminal 25. The This makes it possible to grasp whether or not the pointer has operated.

  However, the threshold value may fluctuate when a through current flows through the CMOS circuit 32 during the period for identifying the magnitude of the back electromotive voltage (including the time when the back electromotive voltage is applied to the applied line 18). In this case, the magnitude of the back electromotive voltage cannot be accurately identified.

  Therefore, in the voltage identification device 10A according to the first embodiment, when identifying the magnitude of the counter electromotive voltage, the voltage identification instruction that instructs the NAND circuit 14A to identify the magnitude of the counter electromotive voltage. Processing is executed.

  With reference to FIG. 3, the operation of the voltage identification device 10 </ b> A when the voltage identification instruction process is being executed will be described. FIG. 3 is a flowchart showing a process flow of a voltage identification instruction process program executed by the system controller 36 when a power supply voltage is applied to the voltage line VDD. Further, here, in order to avoid complications, a description will be given of a case where the voltage identification instruction process is started in a state where a low level voltage (a voltage that can transition to a high level) is applied to the enable line EN as an initial state. To do.

  In step 200 in the figure, the process waits until an identification start condition that is a condition for starting identification of the magnitude of the back electromotive voltage is satisfied. As the identification start condition, for example, a condition that a predetermined time has passed as a time for generating the counter electromotive voltage after the motor 13 is instructed to drive, or a timing for generating the counter electromotive voltage is predetermined. The condition that the new timing has come. It is assumed that the “predetermined timing” arrives every time a predetermined time (for example, several ms) elapses.

  If the identification start condition is satisfied in the process of step 200, an affirmative determination is made and the routine proceeds to step 202. In step 202, the level of the voltage (period signal) applied to the enable line EN is changed from the low level as the identification period level to the high level as the non-identification period level, and then the process proceeds to step 204. In the NAND circuit 14A, in accordance with the processing in step 202, the PMOS transistor 19 changes from the on state to the off state, while the NMOS transistor 23 changes from the off state to the on state. As a result, the magnitude of the voltage applied to the output terminal 25, that is, the signal level of the signal output from the output terminal 25 changes according to the magnitude of the voltage applied to the applied line 18.

  Here, in the NAND circuit 14A, when the magnitude of the back electromotive voltage is identified, a threshold value to be compared with the magnitude of the back electromotive voltage (the magnitude of the voltage applied to the applied line 18 is determined by the NAND circuit 14A). A method of setting a voltage magnitude necessary for outputting an inverted logic signal will be described. Here, as an example, a case where the magnitude of the reference voltage applied to the voltage line VSH is 1.3 V and the threshold is set to 1.0 V will be described.

  In this case, for example, the NMOS transistor 21 is formed so as to have a gate length and a gate width at which a voltage (gate voltage) applied to the gate terminal is 0.5 V and a current can flow 10 uA or more. Therefore, the NMOS transistor 21 is turned on in the same manner as the NMOS transistor 23 with respect to the threshold value of 1.0 V, and is not affected by the threshold value of 1.0 V as in the NMOS transistor 23. By setting both the NMOS transistors 21 and 23 so that the on-resistance is negligible with respect to the threshold value of 1.0 V, the NAND circuit 14A is expressed as an equivalent circuit using a constant current source iS1 as shown in FIG. can do.

  On the other hand, for the PMOS transistor 17, the size of the PMOS transistor 17 is set so that the magnitude of the voltage P1Vgs between the gate terminal and the source terminal is 0.3V and the magnitude of the current P1ids flowing between the source terminal and the drain terminal is 100 nA. Set. If the reference voltage applied to the voltage line VSH is 1.3V and the voltage applied to the applied line 18 ("IN" in the example shown in FIG. 5) is 1.0V, the PMOS The magnitude of the voltage P1Vgs between the gate terminal and the source terminal of the transistor 17 is 1.3V-1.0V = 0.3V. Therefore, since the magnitude of the current P1ids flowing between the source terminal and the drain terminal is correlated with the magnitude of the voltage P1Vgs between the gate terminal and the source terminal, the current P1ids is caused to flow between the source terminal and the drain terminal of the PMOS transistor 17. The maximum current P1ids that can be generated is 100 nA. On the other hand, the constant current iS1 is also set so that a maximum current of 100 nA can flow regardless of the magnitude of the voltage applied to the drain terminal of the NMOS transistor 21.

  FIG. 5 shows the magnitude of the voltage P1Vgs between the gate terminal and the source terminal of the PMOS transistor 17 according to the first embodiment and the maximum magnitude of the current P1ids that can flow between the source terminal and the drain terminal of the PMOS transistor 17. The graph which shows the correlation with is shown. When the magnitude of the reference voltage applied to the voltage line VSH is 1.3 V and the magnitude of the voltage applied to the applied line 18 is 1.0 V, as shown in FIG. A maximum current of 100 nA can flow between the 17 source terminal and the drain terminal, and the maximum current that can flow from the source terminal of the NMOS transistor 21 to the ground line GND via the NMOS transistor 23 and the NMOS transistor 42. It will be the same size. Therefore, the magnitude of the reference voltage applied to the voltage line VSH is theoretically divided by 1/2 between the PMOS transistor 17 and the NMOS transistors 21, 23, 42, and the output terminal 25 is connected to the voltage line VSH. A voltage that is 1/2 the magnitude of the applied reference voltage is applied.

  Further, when the voltage applied to the applied line 18 becomes larger than 1.0V, the voltage between the gate terminal and the source terminal of the PMOS transistor 17 becomes smaller than 0.3V. Therefore, the maximum magnitude of the current P1ids that can flow between the source terminal and the drain terminal of the PMOS transistor 17 is smaller than 100 nA as shown in FIG. On the other hand, since the maximum magnitude of the constant current iS1 that can flow from the source terminal of the NMOS transistor 21 to the ground line GND through the NMOS transistor 23 and the NMOS transistor 42 remains 100 nA, the ability to flow the current of the PMOS transistor 17 Is lower than the ability of the NMOS transistors 21, 23 and 42 to pass current. Therefore, a voltage smaller than ½ of the reference voltage applied to the voltage line VSH is applied to the output terminal 25.

  On the contrary, when the magnitude of the voltage applied to the applied line 18 becomes smaller than 1.0V, the magnitude of the voltage P1Vgs between the gate terminal and the source terminal of the PMOS transistor 17 becomes larger than 0.3V. Therefore, the maximum magnitude of the current P1ids that can flow between the source terminal and the drain terminal of the PMOS transistor 17 is larger than 100 nA as shown in FIG. On the other hand, since the maximum magnitude of the constant current iS1 that can flow from the source terminal of the NMOS transistor 21 to the ground line GND through the NMOS transistor 23 and the NMOS transistor 42 remains 100 nA, the ability to flow the current of the PMOS transistor 17 Becomes higher than the ability of the NMOS transistors 21, 23 and 42 to pass current. For this reason, a voltage larger than ½ of the reference voltage applied to the voltage line VSH is applied to the output terminal 25.

  In step 204, the process waits until an identification end condition, which is a condition for ending the identification of the magnitude of the back electromotive voltage, is satisfied. As the identification end condition, for example, a counter electromotive voltage is generated after the driving instruction of the motor 13 is performed, and a predetermined time has elapsed as the time until the identification of the magnitude of the generated counter electromotive voltage is completed. And a condition that a predetermined timing has arrived as a timing for completing the identification of the back electromotive voltage.

  In the process of step 204, if the identification end condition is satisfied, an affirmative determination is made and the routine proceeds to step 206. In step 206, the voltage applied to the enable line EN is changed from the high level to the low level, and then the voltage identification instruction processing program is terminated. In the NAND circuit 14A, the PMOS transistor 19 transitions from the off state to the on state, while the NMOS transistor 23 transitions from the on state to the off state in accordance with the processing of step 206.

  As described above in detail, in the voltage identification device 10A according to the first embodiment, the reference voltage is supplied to the NAND circuit 14A for identifying the back electromotive voltage by the regulator 15, and the NMOS transistor 21 of the NAND circuit 14A is connected to the ground. Since the constant current source iS1 is inserted between the line GND and the through current of the CMOS circuit 32 when the counter electromotive voltage is applied, the constant current source iS1 is limited to a certain level. Occurrence of a problem that the magnitude of the applied reference voltage temporarily decreases can be suppressed. As a result, the threshold used in the NAND circuit 14A can be kept constant without depending on the magnitude of the power supply voltage supplied from the power supply 30 to the regulator 15. Further, a threshold shift caused by manufacturing variations of elements (for example, the PMOS transistor 17 and the NMOS transistor 21) constituting the CMOS circuit 32 can be easily adjusted by adjusting the constant current source is1. .

  Further, when the threshold value used in the NAND circuit 14A is set to a value close to the magnitude of the power supply voltage, the ability to flow the current of the PMOS transistor 17 and the ability to flow the current of the NMOS transistor 21 compared to the case where the present invention is not applied. Therefore, it is not necessary to greatly shift the ratio, which can contribute to reduction of the circuit area.

  In addition, the through current of about several tens of uA generated in the conventional NAND circuit can be reduced to about several tens of nA to 100 nA by making the current flowing toward the ground line GND constant, thereby reducing current consumption. Can do. Further, the capacitance of the capacitor provided on the output side of the regulator 15 can be reduced to about several pF, and the capacitor that is conventionally required to be about 1000 pF is unnecessary. Therefore, it is possible to contribute to the cost reduction and the mounting area reduction by reducing the number of terminals and external parts.

  Further, according to the voltage identification device 10A according to the first embodiment, since the reference current generation circuit 40 and the regulator 15 share the power supply 30, it is possible to contribute to downsizing of the timepiece control device 11.

  [Second Embodiment]

  In the second embodiment, differences from the timepiece control device 11 according to the first embodiment will be described.

  FIG. 6 is a configuration diagram showing an example of the configuration of the timepiece control apparatus 11A according to the second embodiment. As shown in the figure, the timepiece control apparatus 11A according to the second embodiment applies a voltage identification apparatus 10B instead of the voltage identification apparatus 10A compared to the timepiece control apparatus 11 according to the first embodiment. The point is different. The voltage identification device 10B is different from the voltage identification device 10A according to the first embodiment in that a control unit 16B is applied instead of the control unit 16A. The control unit 16B is different from the control unit 16A according to the first embodiment in that a current mirror circuit 38A is applied instead of the current mirror circuit 38. The current mirror circuit 38A differs from the current mirror circuit 38 according to the first embodiment in that a reference current generation circuit 40A is applied instead of the reference current generation circuit 40. The reference current generation circuit 40A is different from the reference current generation circuit 40 according to the first embodiment in that a variable resistor 44A is applied instead of the resistor 44.

  In the voltage identification device 10B of the timepiece control device 11A configured as described above, when the resistance value of the variable resistor 44A is decreased, the reference current i1 flowing between the source terminal and the drain terminal of the NMOS transistor 48 is increased accordingly. The mirror current flowing between the source terminal and the drain terminal of the NMOS transistor 42 connected to the connection point α in the current mirror is also increased. Therefore, the threshold value used in the NAND circuit 14A can be reduced.

  On the contrary, when the resistance value of the variable resistor 44A is increased, the reference current i1 flowing between the source terminal and the drain terminal of the NMOS transistor 48 is reduced accordingly, and the connection point α and the NMOS transistor 42 connected in a current mirror connection are reduced. The mirror current flowing between the source terminal and the drain terminal is also reduced. Therefore, the threshold value used in the NAND circuit 14A can be increased.

  As described above, according to the second embodiment, the threshold used in the NAND circuit 14A can be easily adjusted by providing the variable resistor 44A capable of adjusting the reference current i1 in the current mirror circuit 38A. The adjustment of the threshold value is performed, for example, at the time of the probing process (first test process) after the wafer process process of the semiconductor device is completed.

  [Third Embodiment]

  In the third embodiment, differences from the timepiece control device 11A according to the second embodiment will be described.

  FIG. 7 is a configuration diagram showing an example of the configuration of the timepiece control apparatus 11B according to the third embodiment. As shown in the figure

  The clock control device 11B according to the third embodiment is different from the clock control device 11A according to the second embodiment in that a voltage identification device 10C is applied instead of the voltage identification device 10B. The voltage identification device 10C is different from the voltage identification device 10B according to the second embodiment in that the NAND circuit 14B is applied instead of the NAND circuit 14A and the control unit 16C is applied instead of the control unit 16B. Is different. The NAND circuit 14B is different from the NAND circuit 14A according to the second embodiment in that the NMOS transistor 23 is excluded. The control unit 16C is different from the control unit 16B according to the second embodiment in that a current mirror circuit 38B is applied instead of the current mirror circuit 38A. The current mirror circuit 38B is different from the current mirror circuit 38A according to the second embodiment in that a reference current generation circuit 40B is applied instead of the reference current generation circuit 40A. The reference current generation circuit 40B is different from the reference current generation circuit 40A according to the second embodiment in that it further includes an NMOS transistor 60, an inverting logic device 62, and a PMOS transistor 64. In the third embodiment, the NMOS transistor 60 and the PMOS transistor 64 function as first switching means.

  In the reference current generation circuit 40B, the drain terminal of the NMOS transistor 60 is connected to the wiring 54, the source terminal of the NMOS transistor 60 is connected to the ground line GND, and the gate terminal of the NMOS transistor 60 is connected to the output terminal of the inverting logic unit 62. Has been. The input terminal of the inverting logic unit 62 is connected to the enable line EN. The gate terminal of the PMOS transistor 64 is connected to the enable line EN, the source terminal of the PMOS transistor 64 is connected to the voltage line VDD, and the drain terminal of the PMOS transistor 64 is connected to the gate terminals of the PMOS transistors 50 and 52.

  In the voltage identification device 10C of the clock control device 11B configured as described above, when the voltage applied to the enable line EN is at a high level, the PMOS transistor 64 is turned off, and the output of the inverting logic device 62 is at a low level. . In response to this, the NMOS transistor 60 transitions from the on state to the off state, and the reference current i1 flows between the source terminal and the drain terminal of the NMOS transistor 48. On the other hand, the PMOS transistor 19 is also turned off, and the NAND circuit 14B is in a state where the magnitude of the back electromotive voltage can be identified.

  Conversely, when the voltage applied to the enable line EN is at a low level, the PMOS transistor 64 is turned off, and the output of the inverting logic unit 62 is at a high level. In response to this, the NMOS transistor 60 transitions from the off state to the on state, and no current flows between the source terminal and the drain terminal of the NMOS transistor 48. On the other hand, the PMOS transistor 19 is also turned on, and the voltage at the output terminal 25 is fixed at a high level.

  As described above, according to the third embodiment, the NMOS transistor 60, the inverting logic device 62, and the PMOS transistor 64 are provided so as to cut off the reference current i1 in the reference current generation circuit 40B. The current consumption in the reference current generation circuit 40B when not identified can be reduced.

  In each of the above embodiments, the CMOS circuit 32 has been described as an example. However, the present invention is not limited to this, and a switching circuit that can perform the same switching as the CMOS circuit 32 (the back electromotive force applied to the applied line 18). Any switching circuit may be used as long as a through current flows in response to a voltage level transition. For example, instead of the switching circuit configured by combining the PMOS transistor 17 and the NMOS transistor 21, a switching circuit configured by combining a pair of bipolar transistors having different conductivity types may be used.

  In each of the above embodiments, the example of identifying the magnitude of the back electromotive voltage using the NAND circuit 14A (14B) has been described. However, the present invention is not limited to this, and an AND circuit, an OR circuit, a NOR circuit, etc. Needless to say, the present invention can also be applied to logic circuits.

  In each of the above embodiments, the timepiece control device 11 (11A, 11B) has been described as an example. However, the present invention is not limited to this. For example, the threshold voltage varies due to the occurrence of a through current, and the magnitude of the identification target voltage is increased. It goes without saying that the present invention may be applied to a circuit that cannot be accurately identified.

10, 10A, 10B, 10C Voltage identification circuit 11, 11A, 11B Clock control device 12 Reference voltage generation circuit 13 Motor 14, 14A, 14B Identification circuit 16, 16A, 16B, 16C Control unit 17, 19, 64 PMOS transistor 18 Covered Application line 20 Switching circuit 21, 23, 42, 60 NMOS transistor 22 Resistance 30 Power supply 32 CMOS circuit 36 System controller 38, 38A, 38B Current mirror circuit 40, 40A, 40B Reference current generation circuit 44A Variable resistor 54 Wiring 62 Inversion logic vessel

Claims (5)

A reference voltage generation circuit to which power is supplied;
An output terminal to which an output voltage is supplied;
An identification circuit that is connected to the reference voltage generation circuit and the output terminal, and that generates the output voltage based on an identification target voltage;
A constant current source connected to the identification circuit and a ground potential and generating a constant current;
A semiconductor device comprising: The identification circuit is a CMOS circuit composed of an NMOS transistor and a PMOS transistor,
The semiconductor device according to claim 1, wherein the identification target voltage is input to gate electrodes of the NMOS transistor and the PMOS transistor. The semiconductor device according to claim 1, wherein the constant current source is a current mirror circuit. The semiconductor device according to claim 3, wherein the current mirror circuit includes a variable resistor capable of adjusting the current. The semiconductor device according to claim 4, wherein the current mirror circuit includes switching means for stopping the current.

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