JP2005227124A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate an operation margin test for an internal power source voltage. <P>SOLUTION: A P-test enable terminal 515 is provided, the terminal is brought into a low level to bring a VCL-MIN test mode, and the internal power source voltage VCL of a desired level is supplied to internal logic circuits 501-504 from an LSI tester via a VCL power source terminal 512, in the test mode. Since a level of a power source voltage VCC is not required to be lowered in the test mode, an operation of an input-output circuit supplied with the power source voltage VCC is carried out without getting unstable. A VCL-MIN test is thereby executed easily. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit, and further to an operation margin test technique therefor, for example, a technique effective when applied to a microcomputer.

  In a semiconductor integrated circuit, for example, a semiconductor memory device, a power margin test for confirming an operation margin for a power supply variation within an allowable range of a memory cell, a data retention test for confirming information retention characteristics under the power supply variation, etc. Is needed. These tests are performed exclusively by a tester connected to the outside in the test process (see, for example, Patent Document 1).

  In addition, a technique for applying a test voltage from the outside while operating a step-down circuit during aging is known (see, for example, Patent Document 2).

  Furthermore, a semiconductor integrated circuit is known in which a voltage higher than a reference voltage (such as an external input step-down voltage) is supplied to an internal circuit while operating the step-down circuit during an acceleration test of the semiconductor integrated circuit (for example, (See Patent Document 3).

Japanese Unexamined Patent Publication No. 2000-200904 (FIG. 1)

Japanese Patent Laid-Open No. 2003-7835 (FIG. 1)

Japanese Patent Laid-Open No. 07-301665 (FIG. 7)

  The semiconductor integrated circuit usually includes an input / output circuit that operates with a power supply voltage VCC supplied from the outside, and an internal logic circuit that operates with an internal power supply voltage VCL lower than the power supply voltage VCC. The internal power supply voltage VCL is formed by stepping down the power supply voltage VCC with a step-down circuit.

  By performing a function test while reducing the level of the power supply voltage VCC, it is possible to grasp the operation margin for fluctuations in the power supply voltage. However, even if the value of power supply voltage VCC is lowered, the output voltage of the step-down circuit is not lowered accordingly, so that it is not possible to test the operation margin against the drop in internal power supply voltage VCL. If the power supply voltage VCC is decreased until the internal power supply voltage VCL reaches the target level, the operation of the input / output circuit to which the power supply voltage VCC is supplied becomes unstable, which hinders the function test. It is not possible to test the operating margin for the drop in voltage VCL. Therefore, in a semiconductor integrated circuit including an input / output circuit that operates with a power supply voltage VCC supplied from the outside and an internal logic circuit that operates with an internal power supply voltage VCL lower than the power supply voltage VCC, The operation margin test is considered difficult.

  An object of the present invention is to provide a semiconductor integrated circuit capable of easily performing an operation margin test on an internal power supply voltage.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  An internal logic circuit that operates by being supplied with an internal power supply voltage; an internal power supply line capable of supplying the internal power supply voltage to the internal logic circuit; and a first power supply terminal for taking in the power supply voltage from the outside; When a semiconductor integrated circuit is configured including a step-down circuit capable of stepping down a power supply voltage supplied from outside via the first power supply terminal to form the internal power supply voltage, the semiconductor integrated circuit is conducted to the internal power supply line. A second power supply terminal and an enable terminal capable of selectively setting a mode in which a voltage equal to or lower than the lowest level of the test power supply voltage supplied from the outside through the second power supply terminal is formed by the step-down circuit are provided. .

  According to the above means, the mode in which the voltage lower than the lowest level of the test power supply voltage supplied from the outside via the second power supply terminal is formed by the step-down circuit is selectively set by the enable terminal. In this mode, an internal power supply voltage of a desired level can be supplied to the internal logic circuit via the second power supply terminal by an LSI tester, for example. Moreover, since it is not necessary to lower the level of the power supply voltage in this code, the operation of the input / output circuit to which the power supply voltage is supplied does not become unstable. This achieves an easy operation margin test for the internal power supply voltage.

  Further, the second power supply terminal conducted to the internal power supply line, a register capable of holding control information for determining the level of the internal power supply voltage formed by the step-down circuit, and the second power supply terminal An enable terminal capable of selectively setting a mode in which a voltage lower than the lowest level of the test power supply voltage supplied from the outside is formed by the step-down circuit, and a level lower than the lowest level of the test power supply voltage The semiconductor integrated circuit can be configured to include a selector capable of selectively supplying the control information for forming the voltage at the step-down circuit to the step-down circuit according to the logic state of the enable terminal. In such a configuration as well, the operation margin test for the internal power supply voltage can be facilitated as in the case of the above configuration.

  At this time, a pull-up element for pulling up the enable terminal, a reset terminal for capturing a reset signal from the outside, and the reset state by the reset signal captured via the reset terminal are released. A latch circuit capable of holding the logic level of the enable terminal, and control information for forming a voltage of a level lower than the lowest level of the test power supply voltage by the step-down circuit based on the output signal of the latch circuit Can be selectively supplied to the step-down circuit according to the logic state of the enable terminal.

  The pull-up element can be a p-channel MOS transistor capable of pulling up the enable terminal to the power supply voltage level.

  A level shifter for shifting the power supply voltage system signal level to the internal power supply voltage system signal level may be interposed between the enable terminal and the latch circuit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a semiconductor integrated circuit that can easily perform an operation margin test on the internal power supply voltage.

  FIG. 1 shows a microcomputer as an example of a semiconductor integrated circuit according to the present invention. The microcomputer 5 shown in FIG. 1 includes, but is not limited to, a power supply circuit 500, a RAM (Random Access Memory) 501, a ROM (Read Only Memory) 502, a CPU (Central Processing Unit) 503, and other built-in modules 504. It is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. At the edge of the microcomputer, a plurality of I / O (input / output) terminals 517 for enabling various signals to be exchanged with the outside of the chip and the power supply voltage VCC can be taken in from the outside of the chip. VCC power source terminal 511, ground terminal 513, VCL power source terminal 512 that enables internal power source voltage VCL to be taken in from the outside during an operation margin test for internal power source voltage VCL, and P test enable for enabling probe inspection A terminal 515, a reset terminal 514 for receiving a reset signal, and the like are provided.

  The CPU 503 executes a predetermined calculation process by executing a program. A program executed by the CPU 503 is stored in the ROM 502. The RAM 501 is used as a work area in the arithmetic processing by the CPU 503. The built-in module 504 is a peripheral circuit of the CPU 503 such as a timer. The RAM 501, ROM 502, CPU 503, and built-in module 504 are coupled to a VCL power supply line 516 and a ground line 519, and take in a voltage applied between the VCL power supply line 516 and the ground line 519 as an operation power supply voltage. The internal power supply voltage VCL is generated by the power supply circuit 500 and applied to the VCL power supply line 516. In the operation margin test for the internal power supply voltage VCL, it is supplied from an LSI tester (not shown) via the VCL power supply terminal 512. When the microcomputer 5 is mounted on the user board, a capacitor for stabilizing the internal power supply voltage VCL is externally connected between the VCL power supply terminal 512 and the ground (GND).

  The power supply circuit 500 includes a register 506, a P detection control circuit 507, a selector 508, a pull-up p-channel MOS transistor 509, a step-down control circuit 505, and a step-down n-channel MOS transistor 510. The register 506 holds a tap control signal set by the CPU 503. The selector 508 selectively transmits the tap control signal held in the register 506 to the step-down control circuit 505. The level of the internal power supply voltage VCL is determined by a combination of 3-bit configuration tap control signals TCON1, TCON2, and TCON3 output from the selector 508. The source electrode of p-channel MOS transistor 509 is coupled to VCC power supply line 518, and the gate electrode of p-channel MOS transistor 509 is coupled to ground line 519. As a result, the gate electrode of the p-channel MOS transistor 509 is coupled to the ground line 519. As a result, the p-channel MOS transistor 509 is turned on, and the P detection enable terminal 515 and the input terminal of the P detection control circuit 507 are pulled up to the power supply voltage VCC level (5 V). Further, when the output signal of the P detection control circuit 507 is at a low level, the selector 508 receives the tap control signals TCON1, TCON2, and the like supplied to the step-down control circuit 505 regardless of the tap control signal output from the register 506. All TCON3 are set to the logical value “0”. The step-down control circuit 505 forms a control signal VCON for driving and controlling the n-channel MOS transistor 510 in accordance with tap control signals TCON1, TCON2, and TCON3 supplied from the selector. The n-channel MOS transistor 510 is coupled to the VCC power supply line 518 and the VCL power supply line 516, and supplies the internal power supply voltage VCL obtained by stepping down the power supply voltage VCC of the VCC power supply line 518 to the VCL power supply line 516.

  Here, the n-channel MOS transistor 510 and the step-down control circuit 505 are collectively referred to as a step-down circuit.

  FIG. 2 shows a configuration example of the P detection control circuit 507.

  As shown in FIG. 2, the P detection control circuit 507 includes level shifters 71 and 72, an internal reset signal generation circuit 73, and a latch circuit 74. Since the enable signal fetched from the outside via the P detection enable terminal 515 and the reset signal fetched from the outside via the reset terminal 514 have the signal level of the power supply voltage VCC system (for example, 5V system), respectively. In level shifters 71 and 72, the signal level is converted to the signal level of the internal power supply voltage VCL system (for example, 3.3V system). The internal reset signal generation circuit 73 forms an internal reset signal based on the output signal of the level shifter 72. The internal reset signal and the output signal of the level shifter 71 are transmitted to the latch circuit 74. When the reset terminal 514 is set to high level by an LSI tester or the like, the output signal of the internal reset signal generation circuit 73 is set to high level, thereby resetting the latch circuit 74. When the reset terminal 514 is set to a low level by an LSI tester or the like, the output signal of the internal reset signal generation circuit 73 is also set to a low level, thereby releasing the reset state of the latch circuit 74. While the output signal of the internal reset signal generation circuit 73 is at a high level, the latch circuit 74 takes in the output signal of the level shifter 71. When the reset state is released, the latch circuit 74 is held and the output logic to the selector 508 is determined. For this reason, even if the logic of the P detection enable terminal 515 changes after reset release, the output logic of the latch circuit 74 does not need to change.

  The latch circuit 74 is configured as follows.

  Inverters 741 and 742 are connected in series, tristate buffer 743 and inverter 745 are coupled in a loop, and tristate buffer 744 and inverter 746 are connected in series. The output terminal of tristate buffer 743 and the output terminal of tristate buffer 744 are coupled. The tristate buffers 743 and 744 are complementarily controlled by the output signals of the inverters 741 and 742. When the output signal of the internal reset signal generation circuit 73 is at a high level, the tristate buffer 743 is turned off and the tristate buffer 744 is turned on, so that the output signal of the level shifter 71 is transferred to the latch circuit 74. Is taken in. At this time, the output logic of the inverter 746 is changed according to the output logic of the level shifter 71. On the other hand, when the output signal of the internal reset signal generation circuit 73 is at a low level, the tristate buffer 743 is turned on and the tristate buffer 744 is turned off, so that the output logic of the inverter 746 is fixed. Is done.

  Since the P detection enable terminal 515 is pulled up by the p-channel MOS transistor 509, the output logic of the level shifter 71 is set to a high level unless charge is drawn through the P detection enable terminal 515. .

  FIG. 3 shows a configuration example of the step-down control circuit 505.

  As shown in FIG. 3, the step-down control circuit 505 includes a band gap reference circuit 51, operational amplifiers 52 and 62, n-channel MOS transistors 53, 54, 55, and 56, and resistors 57, 58, 59, and 60. . The band gap reference circuit 51 forms a stable reference voltage Vref1 using the band gap of the MOS transistor. This reference voltage Vref1 is transmitted to the non-inverting input terminal (+) in the operational amplifier 52 at the subsequent stage. An n-channel MOS transistor 56 and resistors 57-60 are connected in series. A power supply voltage VCC is supplied to the drain electrode of the n-channel MOS transistor 56. One end of resistor 60 is coupled to ground GND. The output signal of the operational amplifier 52 is transmitted to the gate electrode of the n-channel MOS transistor 56, and the voltage at the series connection point (referred to as “tap”) of the resistors 57 to 60 according to the output signal of the operational amplifier 52. Is changed. The taps of resistors 57-60 are coupled to the inverting input terminal (-) of operational amplifier 52 through corresponding n-channel MOS transistors 53, 54, 55, respectively. Tap control signals TCON1, TCON2, and TCON3 from the selector 508 are transmitted to the gate electrodes of the n-channel MOS transistors 53, 54, and 55, respectively. In response to the signals TCON1, TCON2, and TCON3, the signal is selectively conducted to the inverting input terminal (−) of the operational amplifier 52. By such tap selection, the level of the reference voltage Vref2 obtained from the source electrode of the n-channel MOS transistor 56 can be changed. The reference voltage Vref2 is transmitted to the non-inverting input terminal (+) in the operational amplifier 62 at the subsequent stage. The output voltage VCON of the operational amplifier 62 is transmitted to the gate electrode of the n-channel MOS transistor 510. The inverting input terminal of the operational amplifier 62 is coupled to the source electrode of the n-channel MOS transistor 510, and the internal power supply voltage VCL is fed back to the inverting input terminal of the operational amplifier 62, so that the internal power supply voltage VCL is stabilized. It is planned.

  Next, the test of the microcomputer 5 having the above configuration will be described.

  FIG. 4 shows the terminal states in each test of the microcomputer 5, and FIG. 5 shows the correspondence between the tap control signals TCON1, TCON2, TCON3 and the internal power supply voltage VCL.

  The tests performed in the state (wafer state) before the microcomputer 5 having the above configuration is cut out as a chip include an operation margin test (VCL-MIN test) for the internal power supply voltage VCL and other normal tests. It is done.

  As shown in FIG. 4A, when the P detection enable terminal 515 is in an open state, the P detection enable terminal 515 is set to the power supply voltage VCC (5 V) level by pulling up the p-channel MOS transistor 509. . At this time, when the reset state is canceled by setting the reset terminal 514 to the low level, the output signal of the P detection control circuit 507 is fixed to the high level. This state is the normal test mode, and the logic of the tap control signals TCON1, TCON2, TCON3 is determined according to the setting information of the register 506. Then, step-down control circuit 505 determines the level of internal power supply voltage VCL in accordance with the logic of tap control signals TCON1, TCON2, and TCON3. According to the initial value of the register 506, the tap control signals TCON1, TCON2, and TCON3 are set to “0”, “1”, and “1”. At this time, the internal power supply voltage VCL is set to 3.36V. Further, the level of the internal power supply voltage VCL can be changed by changing the logic of the tap control signals TCON1, TCON2, and TCON3 in accordance with the setting information of the register 506. At a desired level, the LSI tester transfers the microcomputer 5 to the microcomputer 5. On the other hand, a function test is performed by supplying a predetermined pattern. In the normal test mode, a capacitor for stabilizing the internal power supply voltage VCL is connected to the VCL power supply terminal 512 via an LSI tester and a probe.

  Further, as shown in FIG. 4B, when the P test enable terminal 515 is set to a low level (0 V) by the LSI tester, the charge is extracted through the P test enable terminal 515, so that this P test is enabled. The enable terminal 515 is set to a low level. At this time, when the reset state is canceled by setting the reset terminal 514 to the low level, the output signal of the P detection control circuit 507 is fixed to the low level. This state is the VCL-MIN test mode, and the tap control signals TCON1, TCON2, and TCON3 are fixed to “0”, “0”, and “0” regardless of the setting of the register 506, and are controlled by the step-down control circuit 505. Internal power supply voltage VCL is controlled to 2.35V. In this state, a voltage of 2.35 V or more can be appropriately supplied to the VCL power supply terminal 512 via the LSI tester and the probe. In other words, the step-down control circuit 505 is controlled so that the internal power supply voltage VCL becomes 2.35 V, but when a voltage of 2.35 V or more is externally applied to the VCL power supply terminal 512 by the LSI tester, The power supply line 516 has a voltage level applied from the outside. For this reason, the level of the internal power supply voltage VCL can be appropriately switched by switching the voltage level supplied to the VCL power supply terminal 512 by the LSI tester, so that the function test is performed while appropriately switching the level of the internal power supply voltage VCL. Thus, the VCL-MIN test can be performed. In addition, in the VCL-MIN test, the level of the internal power supply voltage VCL is switched regardless of the setting information in the register 506, so that the test pattern used in the normal test can be used as it is. That is, since the test pattern can be shared between the normal test and the VCL-MIN test, it is not necessary to newly create a test pattern for the VCL-MIN test.

  According to the above example, the following effects can be obtained.

  (1) A VCL-MIN test mode can be set by setting the P detection enable terminal 515 to a low level. In this VCL-MIN test mode, an internal power supply voltage of a desired level is supplied from the LSI tester via the VCL power supply terminal 512. VCL can be supplied to internal logic circuits (501-504). In addition, in this VCL-MIN test, it is not necessary to lower the level of the power supply voltage VCC, so that the operation of the input / output circuit to which the power supply voltage VCC is supplied does not become unstable. Thereby, the VCL-MIN test can be easily performed.

  (2) In the VCL-MIN test, the level of the internal power supply voltage VCL is switched regardless of the setting information in the register 506, so that the test pattern used in the normal test can be used as it is. Since the test pattern can be shared between the normal test and the VCL-MIN test, an increase in test cost can be suppressed.

  (3) Since the P detection enable terminal 515 is pulled up by the p-channel MOS transistor 509, if the VCL-MIN test is not performed, the P detection enable terminal 515 may be left open. There is no need to worry about the logic of the enable terminal 515. The P detection enable terminal 515 is a terminal used only when the vendor performs the VCL-MIN test, and does not need to be opened to the user.

  (4) Since the latch circuit 74 capable of holding the logic of the P detection enable terminal 515 is provided, even when the logic of the P detection enable terminal 515 changes after reset release, the output logic of the latch circuit 74 does not change. Therefore, the operation of the selector 508 in the VCL-MIN test can be stabilized.

  (5) Since the level shifter 71 is provided, the signal level of the power supply voltage VCC system at the P detection enable terminal 515 can be converted to the signal level of the internal power supply voltage VCL system before being supplied to the latch circuit 74.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above example, in the VCL-MIN test mode, the tap control signals TCON1, TCON2, and TCON3 are fixed to “0”, “0”, and “0” regardless of the setting of the register 506, and the step-down control circuit 505 Although the internal power supply voltage VCL is controlled to 2.35V by the control of (2), it is not limited to this. A voltage equal to or lower than the lowest level of the test power supply voltage supplied from the outside via the VCL power supply terminal 512 may be formed by the step-down circuit (n-channel MOS transistor 510 and step-down control circuit 505).

  In the above description, the case where the invention made by the present inventor is applied to the microcomputer which is the field of use that has been used as the background has been described. However, the present invention is not limited thereto, and is widely applied to various semiconductor integrated circuits. Can be applied.

  The present invention can be applied on condition that a step-down circuit for stepping down the power supply voltage is included.

1 is a block diagram illustrating a configuration example of a main part of a microcomputer as an example of a semiconductor integrated circuit according to the present invention. It is a circuit diagram of a configuration example of a P detection control circuit in the microcomputer. It is a circuit diagram of a configuration example of a step-down control circuit in the microcomputer. It is explanatory drawing of the terminal state in each test of the said microcomputer. FIG. 4 is a diagram illustrating a correspondence relationship between a tap control signal and an internal power supply voltage in the microcomputer.

Explanation of symbols

5 Microcomputer 501 RAM
502 ROM
503 CPU
504 Built-in module 505 Step-down control circuit 506 Register 507 P detection control circuit 508 Selector 509 p channel type MOS transistor 510 n channel type MOS transistor 511 VCC power supply terminal 512 VCL power supply terminal 513 Ground terminal 514 Reset terminal 515 P detection enable terminal 516 VCL power supply Line 517 I / O terminal 518 VCC power line

Claims (5)

An internal logic circuit that operates by being supplied with an internal power supply voltage;
An internal power supply line capable of supplying the internal power supply voltage to the internal logic circuit;
A first power supply terminal for taking in a power supply voltage from the outside;
A step-down circuit capable of stepping down a power supply voltage supplied from the outside through the first power supply terminal to form the internal power supply voltage, and a semiconductor integrated circuit comprising:
A second power supply terminal connected to the internal power supply line;
A semiconductor integrated circuit including: an enable terminal capable of selectively setting a mode in which a voltage equal to or lower than a lowest level of a test power supply voltage supplied from outside via the second power supply terminal is formed by the step-down circuit. An internal logic circuit that operates by being supplied with an internal power supply voltage;
An internal power supply line capable of supplying the internal power supply voltage to the internal logic circuit;
A first power supply terminal for taking in a power supply voltage from the outside;
A step-down circuit capable of stepping down a power supply voltage supplied from the outside through the first power supply terminal to form the internal power supply voltage, and a semiconductor integrated circuit comprising:
A second power supply terminal connected to the internal power supply line;
A register capable of holding control information for determining the level of the internal power supply voltage formed by the step-down circuit;
An enable terminal capable of selectively setting a mode in which a voltage lower than the lowest level of the test power supply voltage supplied from the outside via the second power supply terminal is formed by the step-down circuit;
A selector capable of selectively supplying control information for forming a voltage of a level lower than the lowest level of the test power supply voltage by the step-down circuit to the step-down circuit according to the logic state of the enable terminal; Including semiconductor integrated circuit. A pull-up element for pulling up the enable terminal;
A reset terminal for receiving a reset signal from the outside;
A latch circuit capable of holding the logic level of the enable terminal when the reset state by the reset signal taken in via the reset terminal is released,
Based on the output signal of the latch circuit, the selector selects control information for forming a voltage at a level lower than the lowest level of the test power supply voltage by the step-down circuit according to the logic state of the enable terminal. 3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is supplied to the step-down circuit. 4. The semiconductor integrated circuit according to claim 3, wherein the pull-up element is a p-channel MOS transistor capable of pulling up the enable terminal to the power supply voltage level. 5. The semiconductor integrated circuit according to claim 4, wherein a level shifter for shifting the power supply voltage system signal level to the internal power supply voltage system signal level is interposed between the enable terminal and the latch circuit.

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