JP5620718B2 - Integrated circuit device having voltage regulator - Google Patents

Integrated circuit device having voltage regulator Download PDF

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JP5620718B2
JP5620718B2 JP2010129853A JP2010129853A JP5620718B2 JP 5620718 B2 JP5620718 B2 JP 5620718B2 JP 2010129853 A JP2010129853 A JP 2010129853A JP 2010129853 A JP2010129853 A JP 2010129853A JP 5620718 B2 JP5620718 B2 JP 5620718B2
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直樹 那須
直樹 那須
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スパンションエルエルシー
スパンション エルエルシー
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body

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Description

本発明は，電圧レギュレータを有する集積回路装置に関する。   The present invention relates to an integrated circuit device having a voltage regulator.

マイクロプロセッサなど，近年の集積回路装置には，省電力化のために外部電源を降圧または昇圧する電圧レギュレータを内蔵する。電圧レギュレータは，外部電源から予め決められた電圧の内部電源を生成し，内部回路の電源電圧として供給する。   Recent integrated circuit devices such as microprocessors incorporate a voltage regulator that steps down or boosts the external power supply to save power. The voltage regulator generates an internal power supply having a predetermined voltage from an external power supply and supplies it as a power supply voltage for the internal circuit.

電圧レギュレータを内蔵する集積回路装置については，例えば，特許文献１，２などに記載されている。   An integrated circuit device incorporating a voltage regulator is described in, for example, Patent Documents 1 and 2.

特開２００２−３５８１３０号公報JP 2002-358130 A 特開２００２−８３８７２号公報JP 2002-83872 A

一方で，集積回路装置は，様々な動作モードで動作することが求められる。そのために，集積回路装置は，外部から動作モードを指定するためのモード端子を有し，モード端子に入力されるモード信号をデコードして要求されている動作モードを判定するモードデコーダを内蔵する。   On the other hand, an integrated circuit device is required to operate in various operation modes. For this purpose, the integrated circuit device has a mode terminal for designating an operation mode from the outside, and has a built-in mode decoder that decodes a mode signal input to the mode terminal and determines a requested operation mode.

それと同時に，試験モードでは，内部回路の内部電源の電圧レベルに対する動作マージンを検査するために，外部からテスト電源を供給する動作モードが存在する。この場合，モード端子からその試験の動作モードであることを指定するモード信号を入力し，さらに，内部電源に接続される端子からテスト電源を供給することが行われる。   At the same time, in the test mode, there is an operation mode in which a test power supply is supplied from the outside in order to inspect an operation margin with respect to the voltage level of the internal power supply of the internal circuit. In this case, a mode signal designating that the operation mode of the test is input from the mode terminal, and the test power is supplied from the terminal connected to the internal power supply.

このように動作モードを指定するためのモード端子は，集積回路装置の限られた外部端子の自由度を低下させ，本来の動作に必要な入出力端子の数に制限を加えることになる。   As described above, the mode terminal for designating the operation mode reduces the degree of freedom of the limited external terminals of the integrated circuit device, and restricts the number of input / output terminals necessary for the original operation.

そこで，本発明の目的は，モード端子の数を節減した集積回路装置を提供することにある。   Accordingly, an object of the present invention is to provide an integrated circuit device in which the number of mode terminals is reduced.

集積回路装置の第１の側面は，第１の電源端子に接続され第１の電源電圧を供給する第１の電源配線と，
前記第１の電源電圧から第２の電源電圧を生成し第２の電源配線に出力する電圧レギュレータと，
前記電圧レギュレータの出力に接続され外部キャパシタが接続されるキャパシタ端子と，
モード信号に応じて動作モードを判定するモードデコーダと，
前記第２の電源電圧が供給される内部回路とを有し，
前記キャパシタ端子に第３の電源電圧が印加されないで前記電圧レギュレータが動作する第１の動作モードと，前記キャパシタ端子に前記第３の電源電圧が印加されると共に前記電圧レギュレータが停止する第２の動作モードとを有し，
さらに，前記キャパシタ端子に前記第３の電源電圧が印加されない第１の状態と印加される第２の状態とを判定し，当該判定結果を前記モードデコーダに前記モード信号として供給し，当該判定結果が前記第１の状態の場合に前記電圧レギュレータを動作させ，第２の状態の場合に前記電圧レギュレータを停止させる判定回路を有する。 The first side surface of the integrated circuit device includes a first power supply wiring connected to the first power supply terminal and supplying a first power supply voltage;
A voltage regulator that generates a second power supply voltage from the first power supply voltage and outputs the second power supply voltage to a second power supply wiring;
A capacitor terminal connected to the output of the voltage regulator and connected to an external capacitor;
A mode decoder for determining an operation mode according to a mode signal;
An internal circuit to which the second power supply voltage is supplied,
A first operation mode in which the voltage regulator operates without applying a third power supply voltage to the capacitor terminal; and a second operation in which the voltage regulator is stopped while the third power supply voltage is applied to the capacitor terminal. Operating mode, and
Further, a first state in which the third power supply voltage is not applied to the capacitor terminal and a second state in which the third power supply voltage is applied are determined, and the determination result is supplied to the mode decoder as the mode signal. Has a determination circuit for operating the voltage regulator when in the first state and stopping the voltage regulator when in the second state.

第１の側面によれば，第２の動作モードのときに第３の電源電圧が印加されるキャパシタ端子の状態がモード信号としてモードデコーダに供給されるので，動作モードを指定するモード端子の数を低減することができる。   According to the first aspect, since the state of the capacitor terminal to which the third power supply voltage is applied in the second operation mode is supplied as a mode signal to the mode decoder, the number of mode terminals specifying the operation mode Can be reduced.

本実施の形態に関連する集積回路装置の構成図である。It is a block diagram of the integrated circuit device relevant to this Embodiment. 本実施の形態に関連する集積回路装置の構成図である。It is a block diagram of the integrated circuit device relevant to this Embodiment. 図１，２の集積回路装置の各端子の状態と動作モードを示す図表である。3 is a chart showing states of terminals and operation modes of the integrated circuit device of FIGS. 本実施の形態における集積回路装置の各端子の状態と動作モードを示す図表である。It is a chart which shows the state and operation mode of each terminal of the integrated circuit device in this Embodiment. 本実施の形態における集積回路装置の構成図である。It is a block diagram of the integrated circuit device in this Embodiment. 図５の集積回路装置の動作を示す図である。FIG. 6 is a diagram illustrating an operation of the integrated circuit device of FIG. 5. 本実施の形態における集積回路装置の構成図である。It is a block diagram of the integrated circuit device in this Embodiment. 図７の集積回路装置の動作を示す図である。It is a figure which shows operation | movement of the integrated circuit device of FIG. 本実施の形態における集積回路装置の構成図である。It is a block diagram of the integrated circuit device in this Embodiment.

図１，図２は，本実施の形態に関連する集積回路装置の構成図である。この集積回路装置１０は，第１の電源端子ＶＣＣに接続され第１の電源電圧ＶＤＤＥを供給する第１の電源配線１１と，第１の電源電圧ＶＤＤＥから第２の電源電圧ＶＤＤIを生成し第２の電源配線１３に出力する電圧レギュレータ１２と，電圧レギュレータ１２の出力１３に接続され外部キャパシタＣｏｕｔが接続されるキャパシタ端子Ｃとを有する。さらに，集積回路装置１０は，モード端子ＭＤ１，ＭＤ０から入力されるモード信号に応じて動作モードＭ１〜Ｍ４を判定するモードデコーダ１４と，第２の電源電圧ＶＤＤIが供給される内部回路１６と，第１の電源電圧ＶＤＤＥが供給される入出力回路１８と，それに接続されている入出力端子群２０とを有する。また，内部回路１６に開始信号を供給する外部リセット端子ＩＮＩＴＸを有し，外部システム側のリセット回路１から開始信号が供給される。   1 and 2 are configuration diagrams of an integrated circuit device related to the present embodiment. This integrated circuit device 10 is connected to a first power supply terminal VCC and supplies a first power supply wiring 11 for supplying a first power supply voltage VDDE, and generates a second power supply voltage VDDI from the first power supply voltage VDDE. Voltage regulator 12 that outputs to the second power supply wiring 13 and a capacitor terminal C that is connected to the output 13 of the voltage regulator 12 and to which the external capacitor Cout is connected. Further, the integrated circuit device 10 includes a mode decoder 14 that determines the operation modes M1 to M4 according to mode signals input from the mode terminals MD1 and MD0, an internal circuit 16 that is supplied with the second power supply voltage VDDI, It has an input / output circuit 18 to which a first power supply voltage VDDE is supplied and an input / output terminal group 20 connected thereto. In addition, the external circuit has an external reset terminal INITX that supplies a start signal to the internal circuit 16, and the start signal is supplied from the reset circuit 1 on the external system side.

電圧レギュレータ１２は，たとえば，外部電源Ｖｃｃである第１の電源電圧ＶＤＤＥを降圧して内部電源である第２の電源電圧ＶＤＤIを生成する。第２の電源電圧ＶＤＤIの電圧レベルが安定するように，キャパシタ端子Ｃには外部キャパシタＣｏｕｔが接続される。降圧された第２の電源電圧ＶＤＤIは，内部回路１６の内部電源として使用される。内部回路１６が降圧された第２の電源電圧を使用することで，内部回路１６の消費電力が省力化される。また，第１の電源電圧ＶＤＤＥは，入出力回路１８の電源として使用され，外部システムの電源Ｖｃｃとの電圧レベルの整合がとられる。   For example, the voltage regulator 12 steps down the first power supply voltage VDDE that is the external power supply Vcc and generates the second power supply voltage VDDI that is the internal power supply. An external capacitor Cout is connected to the capacitor terminal C so that the voltage level of the second power supply voltage VDDI is stabilized. The lowered second power supply voltage VDDI is used as an internal power supply for the internal circuit 16. By using the second power supply voltage with the internal circuit 16 stepped down, the power consumption of the internal circuit 16 is saved. The first power supply voltage VDDE is used as a power supply for the input / output circuit 18 and is matched in voltage level with the power supply Vcc of the external system.

モードデコーダ１４は，例えば２つのモード端子ＭＤ１，ＭＤ０から入力されるモード信号の組み合わせから，４つの動作モードＭ１〜Ｍ４を判定する。この例では，モード端子ＭＤ１は電圧レギュレータ１２に接続され，モード端子ＭＤ１のモード信号に応じて，電圧レギュレータ１２は電圧生成動作をして第２の電源電圧ＶＤＤIを出力するか（図１の場合），動作停止して第２の電源電圧ＶＤＤIを出力しないか（図２の場合）の異なる動作モードに制御される。電圧レギュレータが停止する動作モードでは，図２に示すとおり，キャパシタ端子Ｃから第３の電源電圧Vtestが内部電源ＶＤＤIとして印加される。この異なる動作モードの区別はモード端子ＭＤ１のモード信号によって行われる。   For example, the mode decoder 14 determines four operation modes M1 to M4 from a combination of mode signals input from two mode terminals MD1 and MD0. In this example, the mode terminal MD1 is connected to the voltage regulator 12, and according to the mode signal of the mode terminal MD1, the voltage regulator 12 performs a voltage generation operation and outputs the second power supply voltage VDDI (in the case of FIG. 1). ), The operation is stopped and the second power supply voltage VDDI is not output (in the case of FIG. 2), the operation mode is controlled differently. In the operation mode in which the voltage regulator is stopped, the third power supply voltage Vtest is applied as the internal power supply VDDI from the capacitor terminal C as shown in FIG. The distinction between the different operation modes is performed by the mode signal of the mode terminal MD1.

図３は，図１，２の集積回路装置の各端子の状態と動作モードを示す図表である。第１の電源端子ＶＣＣには，外部電源Ｖｃｃとして例えば３Ｖが印加される。一方，モード端子ＭＤ１，ＭＤ０のモード信号の組み合わせで，モードデコーダ１４は４つの動作モードＭ１〜Ｍ４（モード１〜４）を判別する。   FIG. 3 is a table showing the states and operation modes of the terminals of the integrated circuit device of FIGS. For example, 3V is applied to the first power supply terminal VCC as the external power supply Vcc. On the other hand, the mode decoder 14 determines four operation modes M1 to M4 (modes 1 to 4) based on a combination of mode signals of the mode terminals MD1 and MD0.

さらに，動作モードＭ１，Ｍ２の場合に，キャパシタ端子Ｃには，図１のように第３の電源電圧Vtestが印加されない。そして，モード端子ＭＤ１のモード信号（Lレベルまたは「０」）に応答して電圧レギュレータ１２が動作し，第２の電源電圧ＶＤＤIを生成する。したがって，キャパシタ端子Ｃには，その生成された第２の電源電圧ＶＤＤIが出力され，外部キャパシタＣｏｕｔによりその電圧レベルが安定化される。動作モードＭ１，Ｍ２の区別はモード端子ＭＤ０のモード信号により行われる。   Further, in the operation modes M1 and M2, the third power supply voltage Vtest is not applied to the capacitor terminal C as shown in FIG. Then, the voltage regulator 12 operates in response to the mode signal (L level or “0”) of the mode terminal MD1, and generates the second power supply voltage VDDI. Therefore, the generated second power supply voltage VDDI is output to the capacitor terminal C, and the voltage level is stabilized by the external capacitor Cout. The operation modes M1 and M2 are distinguished by a mode signal from the mode terminal MD0.

一方，動作モードＭ３，Ｍ４の場合に，キャパシタ端子Ｃには，図２のように第３の電源電圧Vtestが印加される。そして，モード端子ＭＤ１のモード信号（Ｈレベルまたは「１」）に応答して電圧レギュレータが動作を停止する。つまり，内部電源である第２の電源電圧ＶＤＤIとしてキャパシタ端子Ｃから第３の電源電圧Vtestが入力される。たとえば，試験工程において，この動作モードＭ３，Ｍ４に制御し，外部の第３の電源電圧Vtestを例えば１．８Vの近傍で可変制御しながら内部回路の動作試験を行うことで，第２の電源電圧ＶＤＤIの動作マージンを確認することが行われる。この場合も，動作モードＭ３，Ｍ４の区別はモード端子ＭＤ１のモード信号により行われる。   On the other hand, in the operation modes M3 and M4, the third power supply voltage Vtest is applied to the capacitor terminal C as shown in FIG. Then, the voltage regulator stops operating in response to the mode signal (H level or “1”) of the mode terminal MD1. That is, the third power supply voltage Vtest is input from the capacitor terminal C as the second power supply voltage VDDI which is an internal power supply. For example, in the test process, the second power supply is controlled by controlling the operation modes M3 and M4 and performing an operation test of the internal circuit while variably controlling the external third power supply voltage Vtest in the vicinity of 1.8V, for example. An operation margin of the voltage VDDI is confirmed. Also in this case, the operation modes M3 and M4 are distinguished by the mode signal of the mode terminal MD1.

図４は，本実施の形態における集積回路装置の各端子の状態と動作モードを示す図表である。また，図５は，本実施の形態における集積回路装置の構成図である。   FIG. 4 is a table showing the states and operation modes of the terminals of the integrated circuit device according to this embodiment. FIG. 5 is a configuration diagram of the integrated circuit device according to the present embodiment.

この集積回路装置は，図１，２と同様に，第１の電源端子ＶＣＣと，第１の電源配線１１と，電圧レギュレータ１２と，第２の電源配線１３と，モードデコーダ１４と，内部回路１６と，入出力回路１８と，入出力端子群２０と，キャパシタ端子Ｃと，モード端子ＭＤ０と，外部リセット端子ＩＮＩＴＸとを有する。しかし，モード端子ＭＤ１は設けられていない。   1 and 2, the integrated circuit device includes a first power supply terminal VCC, a first power supply wiring 11, a voltage regulator 12, a second power supply wiring 13, a mode decoder 14, an internal circuit, and the like. 16, an input / output circuit 18, an input / output terminal group 20, a capacitor terminal C, a mode terminal MD0, and an external reset terminal INITX. However, the mode terminal MD1 is not provided.

さらに，図５の集積回路装置は，判定回路２１を有し，この判定回路２１は，キャパシタ端子Ｃに第３の電源電圧Vtestが印加されない第１の状態と印加される第２の状態とを判定し，当該判定結果に対応する信号Ｓ２１をモードデコーダ１４にモード信号として供給し，同時に信号Ｓ２１を電圧レギュレータ１２に制御信号として供給し，当該信号Ｓ２１が第１の状態の場合に電圧レギュレータ１２を動作させ，第２の状態の場合に電圧レギュレータ１２を停止させる。   Further, the integrated circuit device of FIG. 5 includes a determination circuit 21. The determination circuit 21 has a first state in which the third power supply voltage Vtest is not applied to the capacitor terminal C and a second state in which the third power supply voltage Vtest is applied. The signal S21 corresponding to the determination result is supplied to the mode decoder 14 as a mode signal, and at the same time, the signal S21 is supplied to the voltage regulator 12 as a control signal. When the signal S21 is in the first state, the voltage regulator 12 And the voltage regulator 12 is stopped in the second state.

また，図５の集積回路装置は，キャパシタ端子Ｃには，外部キャパシタＣｏｕｔに加えて，外部抵抗Ｒ１が接続され，キャパシタ端子Ｃに第３の電源電圧Vtestが印加されていない第１の状態では，電圧レギュレータ１２が動作開始前において，キャパシタ端子Ｃの電圧がグランドレベル（Ｌレベルまたは「０」）になる。   In the integrated circuit device of FIG. 5, the capacitor terminal C is connected to the external resistor R1 in addition to the external capacitor Cout, and in the first state where the third power supply voltage Vtest is not applied to the capacitor terminal C. Before the voltage regulator 12 starts operation, the voltage at the capacitor terminal C becomes the ground level (L level or “0”).

図５の集積回路装置では，図１，２と異なり，モード端子ＭＤ１が除去され，その代わりに，キャパシタ端子Ｃの電圧レベルが判定回路２１により判別され，その判別結果に対応する信号Ｓ２１がモード信号としてモードデコーダ１４に供給される。つまり，キャパシタ端子Ｃが，図１，２のモード端子ＭＤ１の機能を代替している。   In the integrated circuit device of FIG. 5, unlike FIGS. 1 and 2, the mode terminal MD1 is removed, and instead, the voltage level of the capacitor terminal C is determined by the determination circuit 21, and the signal S21 corresponding to the determination result is the mode S21. The signal is supplied to the mode decoder 14 as a signal. That is, the capacitor terminal C replaces the function of the mode terminal MD1 of FIGS.

図５の集積回路装置では，キャパシタ端子Ｃに第３の電源電圧Vtestが入力されていないので，少なくとも電圧レギュレータ１２が動作する前はその電圧はグランド（０V，Lレベルまたは「０」）であり，図４に示した動作モードのモード１，２の構成である。   In the integrated circuit device of FIG. 5, since the third power supply voltage Vtest is not input to the capacitor terminal C, the voltage is at least ground (0 V, L level or “0”) before the voltage regulator 12 operates. FIG. 4 is a configuration of modes 1 and 2 of the operation mode shown in FIG.

判定回路２１は，図示されるとおり，第１の電源電圧Ｖｃｃが第１の電源端子ＶＣＣに印加された後，所定時間後の判定タイミングで，キャパシタ端子Ｃの電圧をラッチするラッチ回路２２を有する。そして，判定回路２１は，ラッチ回路２２がキャパシタ端子Ｃに第３の電源Vtestが入力されない第１の状態（Ｌレベルまたは「０」）をラッチした時に，Ｈレベルまたは「１」の信号Ｓ２１を電圧レギュレータ１２に動作信号として供給し，キャパシタ端子に第３の電源Vtestが入力される第２の状態（Ｈレベルまたは「１」）をラッチした時に，Ｌレベルまたは「０」の信号Ｓ２１を電圧レギュレータ１２に停止信号として供給する。   The determination circuit 21 includes a latch circuit 22 that latches the voltage at the capacitor terminal C at a determination timing after a predetermined time after the first power supply voltage Vcc is applied to the first power supply terminal VCC, as shown in the figure. . When the latch circuit 22 latches the first state (L level or “0”) in which the third power supply Vtest is not input to the capacitor terminal C, the determination circuit 21 outputs the signal S21 of H level or “1”. When the second state (H level or “1”) is supplied to the voltage regulator 12 as an operation signal and the third power supply Vtest is input to the capacitor terminal, the L level or “0” signal S21 is applied as a voltage. The regulator 12 is supplied as a stop signal.

さらに，判定回路２１は，判定タイミングを示す信号C_DETECTとしてパワーオンリセット信号を出力するパワーオンリセット回路２４と，ANDゲート２６とを有する。パワーオンリセット回路２４は，第１の電源端子VCCに第１の電源Vccが印加されて第１の電源配線１１の電圧が立ち上がったことを検出して，パワーオンリセット信号を判定タイミング信号C_DETECTとして出力する。ラッチ回路２２は，ゲート信号Gの入力に応答してデータ端子Dの信号をラッチし保持する。判定タイミング信号C-DETECTがＨレベルに立ち上がったときにキャパシタ端子Ｃの電圧C-LEVELがラッチ回路２２にラッチされ，アンドゲート２６を介して，判定信号S21が出力される。   Furthermore, the determination circuit 21 includes a power-on reset circuit 24 that outputs a power-on reset signal as a signal C_DETECT indicating determination timing, and an AND gate 26. The power-on reset circuit 24 detects that the first power supply Vcc is applied to the first power supply terminal VCC and the voltage of the first power supply wiring 11 rises, and uses the power-on reset signal as the determination timing signal C_DETECT. Output. The latch circuit 22 latches and holds the signal at the data terminal D in response to the input of the gate signal G. When the determination timing signal C-DETECT rises to H level, the voltage C-LEVEL of the capacitor terminal C is latched by the latch circuit 22 and the determination signal S21 is output via the AND gate 26.

したがって，キャパシタ端子CがLレベルのときに判定信号S21はＨレベルになり，電圧レギュレータ１２が動作し，キャパシタ端子CがHレベルのときに判定信号S21はLレベルになり，電圧レギュレータ１２は停止する。   Therefore, when capacitor terminal C is at L level, determination signal S21 is at H level, voltage regulator 12 operates, and when capacitor terminal C is at H level, determination signal S21 is at L level, and voltage regulator 12 is stopped. To do.

上記の第１の状態は，図４のモード１，２に対応し，第２の状態は，図４のモード３，４に対応する。モード端子ＭＤ０のモード信号は，図３と同様に，モード１，２の区別，またはモード３，４の区別に使用されている。   The first state corresponds to modes 1 and 2 in FIG. 4, and the second state corresponds to modes 3 and 4 in FIG. The mode signal at the mode terminal MD0 is used to distinguish between modes 1 and 2, or between modes 3 and 4, as in FIG.

図６は，図５の集積回路装置の動作を示す図である。前述のとおり，図５の集積回路装置は，図４のモード１，２の第１の状態に対応し，図６は，そのモード１，２の第１の状態の動作を示す。図６において，VCCは第１の電源端子VCCと第１の電源配線１１の電圧を示し，C_LEVELはC端子の電圧を示し，C-DETECTは判定タイミング信号でありパワーオンリセット回路２４の出力信号であり，C_JUDGEはラッチ回路の出力信号であり，S21はアンドゲート２６の出力で電圧レギュレータへの制御信号を示し，INITXは外部リセット信号を示す。   FIG. 6 is a diagram illustrating the operation of the integrated circuit device of FIG. As described above, the integrated circuit device in FIG. 5 corresponds to the first state in modes 1 and 2 in FIG. 4, and FIG. 6 shows the operation in the first state in modes 1 and 2. In FIG. 6, VCC indicates the voltage of the first power supply terminal VCC and the first power supply wiring 11, C_LEVEL indicates the voltage of the C terminal, C-DETECT is a determination timing signal, and the output signal of the power-on reset circuit 24 C_JUDGE is an output signal of the latch circuit, S21 is an output of the AND gate 26 and indicates a control signal to the voltage regulator, and INITX indicates an external reset signal.

図５に示されるとおり，モード１，２の第１の状態では，キャパシタ端子Cには第３の電源電圧Vtestが印加されておらず，抵抗R1によりグランド電位になっている。図６において，時間ｔ１で第１の電源電圧Vccが第１の電源端子VCCに印加されると，パワーオンリセット回路２４が第１の電源配線１１の電源電圧VDDEの立ち上がりを検出し，電源電圧VDDEの立ち上がりから所定時間経過後の時間ｔ２で判定タイミング信号C_DETECTをHレベルに立ち上げる。   As shown in FIG. 5, in the first state of modes 1 and 2, the third power supply voltage Vtest is not applied to the capacitor terminal C, and is at the ground potential by the resistor R1. In FIG. 6, when the first power supply voltage Vcc is applied to the first power supply terminal VCC at time t1, the power-on reset circuit 24 detects the rise of the power supply voltage VDDE of the first power supply wiring 11, and the power supply voltage The determination timing signal C_DETECT is raised to H level at time t2 after a predetermined time has elapsed from the rise of VDDE.

この判定タイミング信号C_DETECTの立ち上がりに応答して，時間ｔ３では，ラッチ回路２２がキャパシタ端子CのLレベルの電圧C_LEVEL＝Lをラッチし，ラッチ回路の出力C_JUDGEはLレベルのままである。それに伴い，アンドゲート２６の出力S21はHレベルになり，電圧レギュレータ１２は動作開始する。また，出力S21は，モード信号としてモードデコーダ１４にも供給される。   In response to the rise of the determination timing signal C_DETECT, at time t3, the latch circuit 22 latches the L-level voltage C_LEVEL = L of the capacitor terminal C, and the output C_JUDGE of the latch circuit remains at the L level. Accordingly, the output S21 of the AND gate 26 becomes H level, and the voltage regulator 12 starts to operate. The output S21 is also supplied to the mode decoder 14 as a mode signal.

電圧レギュレータ１２の動作開始により，第２の電源配線１３の電源電圧VDDIはHレベルに立ち上がり，時間ｔ５で第２の電源配線１３に接続されているキャパシタ端子Cの電圧C_LEVELはHレベルに立ち上がる。なお，外部抵抗R1はキャパシタ端子CがHレベルを維持する程度に高い抵抗である。また，後述するとおり抵抗R1は内部回路１６が動作開始した後はキャパシタ端子Cから切断されてもよい。   When the operation of the voltage regulator 12 starts, the power supply voltage VDDI of the second power supply wiring 13 rises to H level, and the voltage C_LEVEL of the capacitor terminal C connected to the second power supply wiring 13 rises to H level at time t5. The external resistor R1 is high enough to keep the capacitor terminal C at the H level. As will be described later, the resistor R1 may be disconnected from the capacitor terminal C after the internal circuit 16 starts operating.

やがて，外部に設けられているリセット回路１から開始信号が外部リセット端子ＩＮＩＴＸに供給され，内部回路１６が動作を開始する。この時点で，モードデコーダ１４は，モード信号S12とモード端子MD0からのモード信号とに基づいて，４つのモードのうちモード１または２のいずれかを検出している。   Eventually, a start signal is supplied from the externally provided reset circuit 1 to the external reset terminal INITX, and the internal circuit 16 starts its operation. At this time, the mode decoder 14 detects either mode 1 or 2 out of the four modes based on the mode signal S12 and the mode signal from the mode terminal MD0.

図７は，本実施の形態における集積回路装置の構成図である。この集積回路装置は，図４のモード３，４の第２の状態に対応し，キャパシタ端子Cに第３の電源電圧Vtestが印加され，キャパシタ端子Cに抵抗は接続されていない。それ以外の構成は，図５と同じである。   FIG. 7 is a configuration diagram of the integrated circuit device according to the present embodiment. This integrated circuit device corresponds to the second state of modes 3 and 4 in FIG. 4, the third power supply voltage Vtest is applied to the capacitor terminal C, and no resistor is connected to the capacitor terminal C. The other configuration is the same as FIG.

図７の集積回路装置では，キャパシタ端子Cに第３の電源電圧Vtestが印加されHレベルにされているので，判定回路２１がキャパシタ端子Cの電圧C_LEVELのHレベルを検出し，信号S21がLレベルになり，電圧レギュレータ１２は動作停止状態にされる。その代わりに，第２の電源配線１３にはキャパシタ端子Cに印加されている外部の第３の電源電圧Vtestが印加される。   In the integrated circuit device of FIG. 7, since the third power supply voltage Vtest is applied to the capacitor terminal C and is set to the H level, the determination circuit 21 detects the H level of the voltage C_LEVEL of the capacitor terminal C, and the signal S21 is L At this level, the voltage regulator 12 is stopped. Instead, an external third power supply voltage Vtest applied to the capacitor terminal C is applied to the second power supply wiring 13.

図８は，図７の集積回路装置の動作を示す図である。図中の各信号は，図６と同じである。   FIG. 8 is a diagram illustrating the operation of the integrated circuit device of FIG. Each signal in the figure is the same as in FIG.

図４に示されるとおり，モード３，４の第２の状態では，キャパシタ端子Cに第３の電源電圧Vtestが印加される。それに対応して，図８においても，時間ｔ１１でキャパシタ端子Cの電圧C_LEVELが立ち上がる。そして，時間ｔ１２で第１の電源電圧Vccが第１の電源端子VCCに印加されて立ち上がる。この第１の電源配線１１の電源電圧VDDEの立ち上がりに応答して，ラッチ回路２２が動作を開始し，そのデータ端子Dに印加されているデータ端子Cの電圧C_LEVELのHレベルを出力端子Qに出力し，判定信号C_JUDGEもHレベルになる。   As shown in FIG. 4, in the second state of modes 3 and 4, the third power supply voltage Vtest is applied to the capacitor terminal C. Correspondingly, also in FIG. 8, the voltage C_LEVEL of the capacitor terminal C rises at time t11. At time t12, the first power supply voltage Vcc is applied to the first power supply terminal VCC and rises. In response to the rise of the power supply voltage VDDE of the first power supply wiring 11, the latch circuit 22 starts to operate, and the H level of the voltage C_LEVEL of the data terminal C applied to the data terminal D is applied to the output terminal Q. Is output, and the judgment signal C_JUDGE also goes high.

時間ｔ１２後所定時間経過後の時間ｔ１３で，パワーオンリセット回路２４が出力の判定タイミング信号C_DETECTをHレベルに立ち上げる。これに応答して，時間ｔ１４で，ラッチ回路２２はデータ端子Cの電圧C_LEVELのHレベルを取り込み，出力Qの判定信号C_JUDGE＝Hを確定する。その結果，時間ｔ１５では，アンドゲート２６の出力信号S21がLレベルを維持し，電圧レギュレータ１２は動作停止のままになるとともに，出力信号S21のLレベルはモード信号としてモードデコーダ１４に供給される。それにより，モードデコーダ１４は，モード３または４を判定する。   At time t13 after a predetermined time has elapsed after time t12, the power-on reset circuit 24 raises the output determination timing signal C_DETECT to H level. In response to this, at time t14, the latch circuit 22 takes in the H level of the voltage C_LEVEL of the data terminal C and determines the determination signal C_JUDGE = H of the output Q. As a result, at time t15, the output signal S21 of the AND gate 26 is maintained at the L level, the voltage regulator 12 remains stopped, and the L level of the output signal S21 is supplied to the mode decoder 14 as a mode signal. . Thereby, the mode decoder 14 determines the mode 3 or 4.

やがて，時間ｔ１６で，外部リセット信号INITXが立ち上がり，内部回路１６が動作を開始する。この状態では，電圧レギュレータ１２は動作停止し，キャパシタ端子Cに印加されている第３の電源電圧Vtestが第２の電源電圧VDDIとして内部回路１６に供給される。また，モードデコーダ１４は，モード端子MD0からのモード信号と，判定回路２１からの信号S21とに応じて，モード３または４を判定する。   Eventually, at time t16, the external reset signal INITX rises and the internal circuit 16 starts operating. In this state, the voltage regulator 12 stops operating, and the third power supply voltage Vtest applied to the capacitor terminal C is supplied to the internal circuit 16 as the second power supply voltage VDDI. The mode decoder 14 determines mode 3 or 4 according to the mode signal from the mode terminal MD0 and the signal S21 from the determination circuit 21.

図９は，本実施の形態の集積回路装置の変型例の構成図である。図９の集積回路装置は，図５に対応するものであり，キャパシタ端子Cには第３の電源電圧Vtestは印加されていない。そして，外部抵抗R１に代えて，キャパシタ端子Cに接続されたNチャネルMOSトランジスタN1と，抵抗R2と，インバータ３０とが，集積回路装置１０内に内蔵されている。   FIG. 9 is a configuration diagram of a modified example of the integrated circuit device of the present embodiment. The integrated circuit device of FIG. 9 corresponds to FIG. 5, and the third power supply voltage Vtest is not applied to the capacitor terminal C. Instead of the external resistor R1, an N-channel MOS transistor N1, a resistor R2, and an inverter 30 connected to the capacitor terminal C are built in the integrated circuit device 10.

トランジスタN1のゲートは，外部リセット信号INITXをインバータ３０で反転した信号が印加されている。したがって，外部リセット信号INITXがLレベルの間は，トランジスタN1は導通し，キャパシタ端子Cが導通しているトランジスタN1と抵抗R2を介してグランドに接続される。この状態は，図５の構成と同じである。   A signal obtained by inverting the external reset signal INITX by the inverter 30 is applied to the gate of the transistor N1. Therefore, while the external reset signal INITX is at the L level, the transistor N1 is conductive, and is connected to the ground through the resistor R2 and the transistor N1 in which the capacitor terminal C is conductive. This state is the same as the configuration of FIG.

一方，外部リセット信号INITXがHレベルになり内部回路１６が動作を開始すると，トランジスタN1は非導通状態になり，抵抗R2はキャパシタ端子Cから切り離される。それにより，第２の電源配線１３の内部電源電圧VDDIが，抵抗R2を介してグランドに接続されることが回避される。これは，省電力効果をもたらす。   On the other hand, when the external reset signal INITX becomes H level and the internal circuit 16 starts to operate, the transistor N1 is turned off and the resistor R2 is disconnected from the capacitor terminal C. As a result, the internal power supply voltage VDDI of the second power supply wiring 13 is prevented from being connected to the ground via the resistor R2. This brings about a power saving effect.

以上説明したとおり，本実施の形態によれば，外部からの電源Vtestが印加されるキャパシタ端子Cの状態により，電圧レギュレータ１２の動作状態を制御するとともに，モード信号としてモードデコーダ１４に入力することで，モード端子を節約することができる。   As described above, according to the present embodiment, the operation state of the voltage regulator 12 is controlled by the state of the capacitor terminal C to which the external power supply Vtest is applied, and the mode signal is input to the mode decoder 14. Thus, the mode terminal can be saved.

１０：集積回路装置 Ｖｃｃ：第１の電源
ＶＣＣ：第１の電源端子 １１：第１の電源配線
ＶＤＤＥ：第１の電源電圧 １２：電圧レギュレータ
ＶＤＤI：第２の電源電圧 １３：第２の電源配線
１４：モードデコーダ Ｃ：キャパシタ端子
ＭＤ１：モード端子 １６：内部回路
１８：入出力回路 ２０：入出力信号端子群
ＩＮＩＴＸ：外部リセット信号 10: integrated circuit device Vcc: first power supply VCC: first power supply terminal 11: first power supply wiring VDDE: first power supply voltage 12: voltage regulator VDDI: second power supply voltage 13: second power supply wiring 14: Mode decoder C: Capacitor terminal MD1: Mode terminal 16: Internal circuit 18: Input / output circuit 20: Input / output signal terminal group INITX: External reset signal

Claims (4)

第１の電源端子に接続され第１の電源電圧を供給する第１の電源配線と，
前記第１の電源電圧から第２の電源電圧を生成し第２の電源配線に出力する電圧レギュレータと，
前記電圧レギュレータの出力に接続され外部キャパシタが接続されるキャパシタ端子と，
モード端子から入力されるモード信号に応じて動作モードを判定するモードデコーダと，
前記第２の電源電圧が供給される内部回路とを有し，
前記キャパシタ端子に第３の電源電圧が印加されないで前記電圧レギュレータが動作する第１の動作モードと，前記キャパシタ端子に前記第３の電源電圧が印加されると共に前記電圧レギュレータが停止する第２の動作モードとを有し，
さらに，前記キャパシタ端子に前記第３の電源電圧が印加されない第１の状態と印加される第２の状態とを判定し，当該判定結果を前記モードデコーダに前記モード信号として供給し，当該判定結果が前記第１の状態の場合に前記電圧レギュレータを動作させ，前記第２の状態の場合に前記電圧レギュレータを停止させる判定回路を有し、
前記モードデコーダは、前記モード端子から入力されるモード信号と、前記動作モードとの組み合わせに基づいて、少なくとも３つのモードを識別する集積回路装置。 A first power supply wiring connected to a first power supply terminal for supplying a first power supply voltage;
A voltage regulator that generates a second power supply voltage from the first power supply voltage and outputs the second power supply voltage to a second power supply wiring;
A capacitor terminal connected to the output of the voltage regulator and connected to an external capacitor;
A mode decoder for determining an operation mode according to a mode signal input from a mode terminal ;
An internal circuit to which the second power supply voltage is supplied,
A first operation mode in which the voltage regulator operates without applying a third power supply voltage to the capacitor terminal; and a second operation in which the voltage regulator is stopped while the third power supply voltage is applied to the capacitor terminal. Operating mode, and
Further, a first state in which the third power supply voltage is not applied to the capacitor terminal and a second state in which the third power supply voltage is applied are determined, and the determination result is supplied to the mode decoder as the mode signal. There have a determination circuit, wherein to operate said voltage regulator when in the first state, stopping the voltage regulator in the case of the second state,
The integrated circuit device , wherein the mode decoder identifies at least three modes based on a combination of a mode signal input from the mode terminal and the operation mode . 請求項１において，
前記判定回路は，前記第１の電源電圧が前記第１の電源端子に印加された後，所定時間後の判定タイミングで前記キャパシタ端子の電圧をラッチするラッチ回路を有し，前記ラッチ回路が前記第１の状態での前記キャパシタ端子の電圧をラッチした時に前記電圧レギュレータに動作信号を供給し，前記第２の状態での前記キャパシタ端子の電圧をラッチした時に前記電圧レギュレータに停止信号を供給する集積回路装置。 In claim 1,
The determination circuit includes a latch circuit that latches the voltage of the capacitor terminal at a determination timing after a predetermined time after the first power supply voltage is applied to the first power supply terminal. An operation signal is supplied to the voltage regulator when the voltage at the capacitor terminal in the first state is latched, and a stop signal is supplied to the voltage regulator when the voltage at the capacitor terminal in the second state is latched. Integrated circuit device. 請求項２において，
前記判定回路のラッチ回路は，前記第１の電源電圧が前記第１の電源端子に印加されたことを検出するパワーオンリセット回路のリセット信号を前記判定タイミングとして，前記キャパシタ端子の電圧をラッチする集積回路装置。 In claim 2,
The latch circuit of the determination circuit latches the voltage of the capacitor terminal using the reset signal of the power-on reset circuit that detects that the first power supply voltage is applied to the first power supply terminal as the determination timing. Integrated circuit device. 請求項２または３において，
前記キャパシタ端子には，前記外部キャパシタに接続されることに加えて，少なくとも前記判定タイミングまでグランドに接続されることを特徴とする集積回路装置。 In claim 2 or 3,
The integrated circuit device, wherein the capacitor terminal is connected to the ground at least until the determination timing in addition to being connected to the external capacitor.
JP2010129853A 2010-06-07 2010-06-07 Integrated circuit device having voltage regulator Active JP5620718B2 (en)

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