KR100718039B1 - Test mode control circuit of semiconductor memory apparatus - Google Patents

Abstract

A test mode control circuit of a semiconductor memory device according to the present invention includes a fuse for applying and blocking an external supply voltage to a first node; Initialization means for applying a ground voltage to the first node in response to an initialization pulse signal; Control means for receiving a test mode signal and outputting a test mode selection signal in response to the voltage level of the first node; And mode selection means for selectively activating and outputting any one of a base selection signal and an option selection signal in response to the test mode selection signal.

Fuse, test mode select signal

Description

Test mode control circuit of semiconductor memory device

1 is a circuit diagram illustrating a test mode control circuit of a general semiconductor memory device;

2 is a circuit diagram showing a general mask revision,

3 is a block diagram illustrating a test mode control circuit of a semiconductor memory device according to the present invention;

FIG. 4 is a circuit diagram illustrating the test mode control circuit shown in FIG. 3.

<Description of the symbols for the main parts of the drawings>

10, 200: fuse 100: power supply

300: initialization unit 400: power holding unit

500: control unit 600: mode selection unit

The present invention relates to a test mode control circuit of a semiconductor memory device, and more particularly, to a test mode control circuit of a semiconductor memory device that can be used by extending the test mode even after fuse programming.

When designing a semiconductor memory chip, a base circuit and an optional circuit are implemented according to a designer's judgment. For example, in implementing a delay circuit, the designer determines that the most appropriate delay is selected, and after the memory chip is completed, a test can be adjusted to adjust the delay.

Therefore, there are metal options between delay circuits to determine the proper timing through a focused ion beam (FIB) experiment. Also, if it is only a metal option, the option cannot be subdivided and it takes a long time to verify. In addition, a test mode can be added to determine the optimized delay without FIB.

In general, a FUSE circuit is used to repair a memory cell, to adjust an internal circuit operation of a memory device, or to adjust an internal power supply level without a design change. In other words, the timing of the operation and the power level of the internal circuit can be adjusted to a desired level through fuse programming.

Hereinafter, a test mode control circuit of a general semiconductor memory device will be described with reference to FIG. 1.

1 is a circuit diagram illustrating a test mode control circuit of a general semiconductor memory device.

In a test mode control circuit of a conventional semiconductor memory device, a PMOS transistor P1 having a gate terminal applied with a ground voltage VSS and a source terminal receiving an external supply voltage VDD, and an input terminal having the PMOS transistor A fuse 10 connected to the drain terminal of P1, a first inverting means IV1 connected to an output terminal of the fuse 10, a gate terminal to receive an initialization pulse signal PWRUP_P, and a drain terminal to the fuse A first NMOS transistor (N1) connected to an output terminal of (10) and a source terminal applied with the ground voltage VSS, and a drain terminal connected to an input terminal of the first inverting means IV1 and a gate terminal A second NMOS transistor N2 connected to an output terminal of the first inverting means IV1 and receiving a ground voltage VSS, and an input terminal of one of two input terminals is the first inversion Connected to the output stage of the means IV1 The other is input stage and a second inverting means (IV2) connected to the output terminal of the test mode, NOR receiving a signal (TM) (NOR) gate (NR1) and said NOR input stage (NOR) gate (NR1).

An operation of a test mode control circuit of a general semiconductor memory device will be described with reference to FIG. 1.

The external supply voltage VDD is applied through the PMOS transistor P1 and the fuse 10 to output a low level through the first inverting means IV1.

When the test mode signal TM is at a low level, the NOR gate NR1 which inputs the output level of the test mode signal TM and the first inverting means IV1 is high at the node nodeA. Since the base selection signal BASE_SEL of the level is output, the base selection signal BASE_SEL is activated to select a base mode.

On the other hand, when the test mode signal TM is activated to a high level, the NOR gate NR1 outputs a low level to the node A, and thus, the base select signal BASE_SEL is inactivated and the second The inverting means IV2 inverts the low level of the node nodeA and outputs a high level option selection signal OPTION_SEL. That is, the option selection signal OPTION_SEL is activated to select an option mode.

According to the control of the test mode signal TM, a test is performed such that one of the base mode and the option mode is selected, and then a default is determined.

In this case, the base mode is selected by default when the test mode signal TM is deactivated, and the option mode (Option) is enabled as the test mode signal TM is enabled to a high level. Mode is selected to test.

However, if a default is changed from the base mode to the option mode after the test, the fuse 10 may be cut or a mask revision may be performed.

2 is a circuit diagram showing a general mask revision.

As shown in FIG. 2, the general mask revision has a fourth inversion regardless of whether the test mode signal TM activates the base selection signal BASE_SEL through a third inversion means IV3. Always activate a specific test mode (e.g., option mode) to a high level by opening the node connected to the means IV and activating the option selection signal OPTION_SEL with the external supply voltage VDD always applied. This is how you do it.

Once fuse cutting and mask revision, only a specific test mode (e.g., option mode) is selected, regardless of the activation of the test mode signal TM, and the fuse cutting and There is a problem that prevents the use of other test modes (base mode) before mask revision.

For example, when the fuse 10 is cut, the input terminal of the first inverting means IV1 has a low level by the activated initialization pulse signal PWRUP_P, and the first inverting means ( IV1) outputs a high level, and the latch operation is performed such that the second NMOS transistor N2 is turned on so that the input terminal of the first inverting means IV1 maintains the low level. Lose.

That is, since the first inversion means IV1 always outputs a high level, the NOR gate NR1 always outputs a low level regardless of the activation of the test mode signal TM, so that the option selection signal OPTION_SEL ) Is activated and the test is performed only in the option mode.

As described above, when the test results are not satisfied after the fuse cutting and the test is performed in the original default mode, the base mode cannot be used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a test mode control circuit of a semiconductor memory device capable of testing in a state in which the test mode is reduced to the original test mode even after the fuse programming.

According to another aspect of the present invention, there is provided a test mode control circuit of a semiconductor memory device, the fuse including an external supply voltage to a first node; Initialization means for applying a ground voltage to the first node in response to an initialization pulse signal; Control means for receiving a test mode signal and outputting a test mode selection signal in response to the voltage level of the first node; And mode selection means for selectively activating and outputting any one of a base selection signal and an option selection signal in response to the test mode selection signal.

In addition, the test mode control circuit of the semiconductor memory device according to the present invention includes a power supply means for protecting the fuse; And power supply means for causing the first node to maintain a ground voltage.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a test mode control circuit of a semiconductor memory device according to the present invention.

The test mode control circuit of the semiconductor memory device according to the present invention includes a power supply unit 100 that receives an external supply voltage VDD, and a fuse that applies and cuts the external supply voltage VDD to the first node node3A. 200, in response to an initialization pulse signal PWRUP_P, an initialization unit 300 for applying a ground voltage VSS to the first node node3A, and the first node node3A applies the ground voltage VSS. In response to the voltage level of the first node (node3A), the power supply holding unit 400, the control unit 500 for receiving a test mode signal (TM) and outputs a test mode selection signal (TM_SEL) and the test In response to the mode selection signal TM_SEL, a mode selection unit 600 selectively activates and outputs one of the base selection signal BASE_SEL and the option selection signal OPTION_SEL.

FIG. 4 is a circuit diagram illustrating the test mode control circuit shown in FIG. 3.

The power supply unit 100 includes a PMOS transistor P41 to which a ground voltage VSS is applied to a gate terminal and the external supply voltage VDD is applied to a source terminal.

The PMOS transistor P41 filters and supplies the external supply voltage VDD to prevent the fuse 200 from being damaged by the external supply voltage VDD.

The fuse 200 is connected to the drain terminal of the PMOS transistor P41 and the first node.

The initialization unit 300 receives the initialization pulse signal PWRUP_P at a gate terminal thereof, a drain terminal thereof is connected to the first node node3A, and an NMOS transistor N41 to which the ground voltage VSS is applied to a source terminal. It is composed of

Although the initialization unit 300 is configured as the NMOS transistor N41 in the present invention, the initialization unit 300 may be replaced with another switching device applying the ground voltage VSS in response to the initialization pulse signal PWRUP_P.

The power holding unit 400 may include a first inverting means configured to latch and maintain a voltage level of the capacitor C41 and the first node node3A connected between the first node node3A and the ground terminal VSS. IV41) and second inverting means IV42.

The controller 500 may further include third inverting means IV43 for inverting the test mode signal and outputting an inverted test mode signal, fourth inverting means IV44 for inverting the voltage level of the first node node3A, and a third inverting means IV44. A reversal means IV45, a first transmission gate TG41 for controlling the output of the test mode signal TM to the second node node3B in response to the voltage level of the first node node3A and the The second transmission gate TG42 and the second node node3B controlling the output of the inversion test mode signal TMb to the second node node3B in response to the voltage level of the first node node3A. The sixth inversion means IV46 and the seventh inversion means IV47 which drive non-inverting a signal are comprised.

The first transfer gate TG41 and the second transfer gate TG42 may be replaced by a switching element capable of controlling input and output of signals in response to the voltage level of the first node node3A.

The test mode selection signal TM_SEL is output from the second node node3B.

The mode selector 600 inverts the signal of the eighth inversion means IV48 and the third node node3C by inverting the test mode selection signal TM_SEL and outputting it to the third node node3C. 9th inversion means IV49.

The signal output from the third node node3C is a base selection signal BASE_SEL, and the signal output from the ninth inversion means IV49 is an option selection signal OPTION_SEL.

The operation of the test mode control circuit of the semiconductor memory device according to the present invention will be described with reference to FIGS. 3 and 4 as follows.

The external power supply unit 100 filters the external supply voltage VDD to supply the external supply voltage VDD to the fuse 200.

If the fuse 200 is connected, the first node node3A is at a high level. The voltage level of the first node node3A, which is a high level, controls the test mode signal TM input to the controller 500 to output the test mode selection signal TM_SEL.

When the fuse 200 is cut, the initialization pulse signal PWRUP_P is activated to apply the ground voltage VSS to the first node node3A.

The first node node3A is at a low level, and the voltage level of the first node node3A at the low level controls the test mode signal TM and outputs the test mode selection signal TM_SEL.

The test mode selection signal TM_SEL output when the voltage level of the first node node3A is high level and the test mode selection signal output when the voltage level of the first node node3A is low level. TM_SEL has levels reversed from each other.

The test mode selection signal TM_SEL activates the base selection signal BASE_SEL or the option selection signal OPTION_SEL.

In more detail, when the fuse 200 is connected, the external supply voltage VDD is supplied so that the voltage level of the first node node3A becomes a high level and the voltage of the first node node3A. The first transfer gate TG41 controlled by the level and the voltage level output from the fourth inverting means IV44 is turned on, so that the test mode signal TM is turned on to the second node. output as (node3B)

In this case, when the test mode signal TM is at a low level, the second node node3B is also at a low level, and the sixth inverting means IV46 and the seventh inverting means IV47 which are driven non-inverted are operated. The test mode selection signal TM_SEL output through the signal is at a low level.

Since the test mode selection signal TM_SEL is output to the third node node3C through the eighth inverting means IV48, the base selection signal BASE_SEL is activated to a high level so that a base mode is obtained. Is selected.

On the other hand, when the test mode signal TM is activated at the high level, the second node node3B is also at the high level, and the sixth inverting means IV46 and the seventh inverting means IV47 which are driven non-inverted. The test mode selection signal (TM_SEL) outputted through the C1 is activated to a high level.

Since the test mode selection signal TM_SEL is output to the third node node3C through the eighth inverting means IV48, the base selection signal BASE_SEL is at a low level.

Since the voltage level of the third node node3C is inverted by the ninth inversion means IV49, the output option selection signal OPTION_SEL is activated to select an option mode.

That is, when the fuse 200 is connected, the base mode is selected as a default, and when the test mode signal TM is activated at a high level, the option mode is selected. Is selected.

When the fuse is cut, the external supply voltage VDD is cut off, and the initialization pulse signal PWRUP_P is activated to turn on the NMOS transistor N41.

The power holding unit 400 maintains the voltage level of the first node node3A as the ground voltage VSS.

The ground voltage VSS is applied to the first node node3A to become a low level, and is controlled by the voltage level of the first node node3A and the voltage level output from the fifth inverting means IV45. The second transfer gate TG42 is turned on, and the inversion test mode signal TMb output from the third inversion means IV43 is output to the second node node3B.

In this case, when the test mode signal TM is at a low level, the inversion test mode signal TMb is activated at a high level, the second node node3B is also at a high level, and the sixth inversion means IV46. ) And the test mode selection signal TM_SEL output through the seventh inversion means IV47 are also activated to a high level.

Since the test mode selection signal TM_SEL is output to the third node node3C through the eighth inverting means IV48, the base selection signal BASE_SEL is at a low level.

Since the voltage level of the third node node3C is inverted by the ninth inversion means IV49, the output option selection signal OPTION_SEL is activated to select the option mode.

On the other hand, when the test mode signal TM is activated at a high level, the inversion test mode signal TMb is at a low level, and the second node node3B is at a low level, and thus the sixth inversion means IV46. ) And the test mode selection signal TM_SEL output through the seventh inverting means IV47 are also at a low level.

Since the test mode selection signal TM_SEL is output to the third node node3C through the eighth inverting means IV48, the base selection signal BASE_SEL is activated to a high level so that the base mode is selected. Is selected.

That is, when the fuse 200 is cut, the option mode is selected as a default, and when the test mode signal TM is activated at a high level, the base mode Mode) is selected.

As described above, after testing when the fuse is connected, if the default should be changed from the base mode to the option mode, the fuse may be cut. If the base mode is to be tested while the option mode is applied as a default, the base mode can be switched by using the test mode signal TM.

That is, although the original default mode cannot be tested after fuse cutting, the test mode control circuit of the semiconductor memory device according to the present invention can test the original default mode even after fuse cutting, thereby increasing the flexibility of the test. It can also shorten product development time.

The test mode control circuit of the semiconductor memory device according to the present invention has the following effects.

First, the test mode can be extended to be used even after fuse programming, thereby reducing development time.

Second, it has the effect of increasing test flexibility.

Claims (11)

A fuse for applying and blocking an external supply voltage to the first node; Initialization means for applying a ground voltage to the first node in response to an initialization pulse signal; Control means for receiving a test mode signal and outputting a test mode selection signal in response to the voltage level of the first node; And Mode selection means for selectively activating and outputting any one of a base selection signal and an option selection signal in response to the test mode selection signal; The test mode control circuit of the semiconductor memory device comprising a. The method of claim 1, Power supply means for protecting the fuse; And Power supply means for causing the first node to maintain a ground voltage; The test mode control circuit of the semiconductor memory device further comprises. The method of claim 1, The initialization means, And a switching device responsive to the initialization pulse signal. The method of claim 1, The control means, First inverting means for inverting the test mode signal and outputting an inverted test mode signal; A first switching element configured to output the test mode signal to a second node in response to the voltage level of the first node; And a second switching device configured to output the inversion test mode signal to the second node in response to the voltage level of the first node. The method of claim 2, The power supply means, And a PMOS transistor to which the ground voltage is applied at a gate terminal and the external supply voltage is applied to a source terminal. The method of claim 2, The power holding means, And a capacitor connected between the first node and a ground terminal, a first inverting means and a second inverting means forming a latch structure and connected to the first node. The method of claim 3, wherein And the switching element is a PMOS transistor which receives the initialization pulse signal at a gate terminal, a drain terminal is connected to the first node, and a source terminal is connected to a ground terminal. The method of claim 4, wherein And the first switching element and the second switching element are transfer gates. The method of claim 4, wherein The test mode selection signal, And the test mode signal or the inverted test mode signal. The method of claim 9, The mode selection means, And second inverting means for inverting and outputting the test mode selection signal to a third node and a third inverting means for inverting and outputting a voltage level of the third node. . The method of claim 10, And the base selection signal is output from the third node, and the option selection signal is output from the third inverting means.

Images