JP3875434B2 - Semiconductor device and reference potential adjusting method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a reference potential adjustment method thereof, and more particularly to a semiconductor device including a reference potential generation circuit with an adjustment function and a reference potential adjustment method thereof, for example, used for a semiconductor device incorporating an analog circuit. Is.
[0002]
[Prior art]
Many recent LSIs incorporate analog circuits such as a PLL (Phase Locked Loop) circuit that performs clock frequency division and shaping for the purpose of high-speed operation, and an internal power supply circuit for the purpose of stable chip operation. In addition, there are LSIs with built-in A / D converters that handle analog inputs and D / A converters that handle analog outputs. Further, there is an LSI having an impedance matching circuit for an input / output circuit in order to realize a high-speed input / output terminal.
[0003]
In order to generate a reference potential required by many of these analog circuits, a reference potential generation circuit is built in. As the accuracy of the output potential of this reference potential generation circuit, 1 mV to several tens of mV can be guaranteed. Required.
[0004]
However, the reference potential generated from the reference potential generation circuit is generally affected by variations in elements in the LSI manufacturing process, and may deviate from the set potential, requiring adjustment.
[0005]
In order to adjust the reference potential for each LSI chip, a method of controlling the fusing of the fuse element in a test process or a method of adding an external element at the time of mounting is used. Adjusting the reference potential of each chip increases the manufacturing cost of the LSI.
[0006]
In other words, the adjustment by fusing the fuse leads to an increase in test cost, and the addition of the external element itself causes an increase in cost. In addition, since a test process takes a long time in manufacturing a semiconductor memory, a large number of chips are simultaneously tested. In this case, since different test signals cannot be input to the individual chips, it is difficult to adjust both the reference potential of each chip and to simultaneously test a large number of chips.
[0007]
[Problems to be solved by the invention]
As described above, the conventional semiconductor device controls the fusing element during the test process, or adjusts it during mounting in order to adjust that the reference potential generated inside deviates from the set potential due to the influence of element variation in the manufacturing process. Although a method of adding an external element is employed, there is a problem in that the manufacturing cost increases.
[0008]
In addition, when performing simultaneous testing of a large number of chips when manufacturing a conventional semiconductor memory, there is a problem that it is difficult to adjust the reference potential in each chip.
[0009]
The present invention has been made to solve the above-described problems, and a reference potential having low power supply potential dependency and low temperature dependency generated inside is set to a reference potential that is less affected by variations in elements used. An object of the present invention is to provide a semiconductor device that can be adjusted, eliminates the need for external elements for adjustment, reduces test costs, reduces power consumption, and reduces the chip area, and a reference potential adjustment method thereof.
[0010]
[Means for Solving the Problems]
The semiconductor device of the present invention is controlled by the first reference potential generation circuit and the second reference potential generation circuit, a control circuit for selecting and controlling the normal operation state and the other special operation states, and is controlled by the control circuit. In the operation state, the output potential of the first reference potential generation circuit is adjusted and output with reference to the output potential of the second reference potential generation circuit, and in the normal operation state, the adjustment of the first reference potential generation circuit is performed. And a reference potential adjusting circuit for outputting the output potential.
[0011]
The semiconductor device reference potential adjusting method according to the present invention includes a first reference potential generation circuit that generates a first reference potential that is relatively less affected by power supply potential and ambient temperature, and the influence of power supply potential and ambient temperature. The second reference potential generating circuit that generates the second reference potential that is affected by the variation of the used elements but is relatively small, and the output potential of the first reference potential generating circuit is adjusted to adjust the output potential of the semiconductor device. A reference potential adjusting circuit for outputting a reference potential used internally is provided in the semiconductor device, the second reference potential generating circuit is operated, and the reference potential adjusting circuit is referred to by referring to the output potential. Thus, the output potential of the first reference potential generating circuit is adjusted, and the adjusted output potential is output as a reference potential used inside the semiconductor device.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0013]
First, the outline of the present invention will be described.
[0014]
A first reference potential generating circuit that is relatively less affected by the power supply potential and the ambient temperature, and a second reference potential that is affected by the power supply potential and the ambient temperature but is less affected by variations in the elements used. A generation circuit and a reference potential adjustment circuit for adjusting the output potential of the first reference potential generation circuit and outputting it as a reference potential used inside the semiconductor device are provided inside the semiconductor device.
[0015]
Then, when adjustment of the reference potential used inside the semiconductor device is required, the second reference potential generation circuit is operated, and the reference potential adjustment circuit refers to the output potential and the reference potential adjustment circuit uses the first reference potential adjustment circuit. The output potential of the generation circuit is adjusted, and in the subsequent normal operation state, the adjusted output potential is output as a reference potential used inside the semiconductor device.
[0016]
<First Embodiment>
FIG. 1 shows a first embodiment of a reference potential generating circuit with adjustment function formed in a semiconductor device of the present invention.
[0017]
In the reference potential generating circuit with the adjusting function, the first reference potential generating circuit 10 and the second reference potential generating circuit 20 have different characteristics. In the present example, the first reference potential generation circuit 10 has a feature that it is significantly affected by variations in device manufacturing, although it has low power supply potential dependency and temperature dependency.
[0018]
On the other hand, the second reference potential generation circuit 20 is highly dependent on the power supply potential, but has an advantage that the second reference potential generation circuit 20 is hardly affected by variations in device manufacturing.
[0019]
The control circuit 30 controls a normal operation state and other special operation states (for example, a chip test state).
[0020]
The reference potential adjustment circuit 40 is controlled by the control circuit 30 and adjusts the output potential of the first reference potential generation circuit 10 based on the output potential of the second reference potential generation circuit 20 in the chip test state. It is output as the potential Vref, and in the normal operation state, the adjusted output potential of the first reference potential generating circuit 10 is output as the reference potential Vref.
[0021]
FIG. 2 shows a band-gap reference circuit as an example of the first reference potential generation circuit 10 in FIG.
[0022]
This band-gap reference circuit is connected in series between a PMOS transistor P3 whose source is connected to a VCC node to which a power supply potential VCC is applied, and a VSS node to which the drain of the PMOS transistor P3 and a ground potential VSS are applied. The first resistor element R1, the second resistor element R2, the first diode D1, and the third resistor element R3 and the second resistor connected in series between the drain of the PMOS transistor P3 and the VSS node. And the potential A of the series connection node of the first resistance element R1 and the second resistance element R2 and the potential B of the series connection node of the third resistance element R3 and the second diode D2 are input. And a differential amplifier DA for controlling the gate of the PMOS transistor P3 according to the output potential. Then, the drain potential of the PMOS transistor P3 is taken out as the first reference potential Vbgr.
[0023]
The differential amplifier DA is connected to two NMOS transistors N1 and N2 forming a differential pair to which the potentials A and B are input, and between the differential pair transistors N1 and N2 and the VSS node. An NMOS transistor N3 having a drain / gate connected as a current source and two PMOS transistors P2 and P3 connected in a current mirror as a load connected between the differential pair transistors N1 and N2 and the VCC node It consists of.
[0024]
In the above circuit configuration, the resistance value R1 of the first resistance element and the resistance value of the third resistance element R3 are set to, for example, 10 times the resistance value of the second resistance element R2. Further, the pattern area of the first diode D1 is set to 10 times the pattern area of the second diode D2, for example.
[0025]
In this band-gap reference circuit, when the supplied power supply potential VCC is 2.5V, the output potential (reference potential Vbgr) is about 1.25V, and the reference potential Vbgr has power supply potential dependency and temperature dependency. It is characterized by being low.
[0026]
In general, in the normal operation state of a chip, the current consumption of the chip increases, the voltage drop of the power supply occurs due to the influence of the resistance parasitic on the power supply wiring, and further, the chip generates heat due to the current consumption, and the temperature of the chip also increases. It becomes unstable. Even in such an environment, the band-gap reference circuit of FIG. 2 can generate a stable output potential (first reference potential Vbgr).
[0027]
Further, the output potential Vbgr of the band-gap reference circuit of FIG. 2 has a characteristic that it is significantly affected by variations in device manufacturing. That is, the variation of the thermal voltage VT of the diodes D1 and D2, which are constituent elements of the circuit, the coincidence of the forward voltages Vf of the two diodes D1 and D2, and the coincidence and difference of the two resistance ratios R1 / R2 and R1 / R3 It is affected by the coincidence of the threshold values Vt of the NMOS transistors N1 and N2 and the PMOS transistors P2 and P3 constituting the dynamic amplifier DA. Among these, the influence of the Vt variation of the PMOS transistor or the NMOS transistor is dominant, and when the difference in Vt between the two transistors N1, N2 or P2, P3 in the pair is 10 mV, the output potential Vbgr is designed to be 100 mV or more. Deviation from the value. Therefore, potential adjustment is performed on the output potential Vbgr of the band-gap reference circuit shown in FIG. 2 as described later.
[0028]
FIG. 3 shows an example of the second reference potential generating circuit 20 in FIG.
[0029]
The second reference potential generating circuit 20 includes two resistor elements R4 and R5 and one NMOS transistor N4 connected in series between the VCC node and the VSS node, and the two resistor elements. The potential of the series connection node of R4 and R5 is taken out as the second reference potential Vdiv.
[0030]
The second reference potential generation circuit 20 does not pass through current when the NMOS transistor N4 is off, but simply supplies the power supply potential VCC when the NMOS transistor N4 is controlled to be on. Is divided by resistors R4 and R5 to generate a reference potential Vdiv. Therefore, since the reference potential Vdiv has a characteristic proportional to the power supply potential VCC, an accurate reference potential Vdiv can be obtained in a state where the supplied power supply potential VCC is accurately controlled.
[0031]
Here, if the resistance values of the two resistance elements R4 and R5 are R and the relationship with the mutual conductance gm of the NMOS transistor N4 is set to R >> 1 / gm, the supplied power supply potential VCC Is 2.5V, the reference potential Vdiv obtained by resistance division is 1.25V.
[0032]
Furthermore, since it is relatively easy to suppress the local variation of the resistance elements R4 and R5, which are constituent elements of the circuit, to about 1%, the accuracy of the reference potential Vdiv can be expected to be 1 mV or less.
[0033]
However, as described above, in the normal operation state of the chip, the power supply potential VCC is not stable due to the influence of current consumption and parasitic resistance of the power supply wiring. Therefore, the output potential Vdiv of the second reference potential generation circuit 20 shown in FIG. 3 cannot be used in the normal operation state.
[0034]
FIG. 4 shows an example of the reference potential adjustment circuit 40 in FIG.
[0035]
The reference potential adjusting circuit 40 generates a plurality of reference potentials Vref1, Vref3, Vref5, Vref7 from the first reference potential Vbgr by a feedback control differential amplifier circuit 41 and a voltage dividing resistor element. Among the reference potentials Vref1, Vref3, Vref5, and Vref7, the one closest to the second reference potential Vdiv is selected and output as the adjusted reference potential Vref.
[0036]
That is, the PMOS transistor P4 and the eight resistance elements R41 to R48 are connected in series between the VCC node to which the power supply potential VCC is applied and the VSS node to which the ground potential VSS is applied.
[0037]
Of the reference potentials Vref1 to Vref7 at the connection nodes of the resistor elements R41 to R48, for example, the reference potential Vref5 and the first reference potential Vbgr are input to the differential amplifier circuit 41, and the output potential of the differential amplifier circuit 41 is output. Is supplied to the gate of the PMOS transistor P4. Thereby, feedback control is performed so that the reference potential Vref5 becomes equal to the first reference potential Vbgr.
[0038]
The nodes of Vref1, Vref3, Vref5, and Vref7 of the reference potentials Vref1 to Vref7 are respectively connected to one ends of NMOS transistors NS0 to NS3 for selection switches, and each of the NMOS transistors NS0 to NS3 is connected. The other end is connected to the output node of the adjusted reference potential Vref collectively.
[0039]
Then, the reference potential Vref1, Vref3, Vref5, Vref7 is determined to be closest to the second reference potential Vdiv, and the selection switch NMOS transistors NS0 to NS3 are selectively turned on according to the determination result. Select signal SELECT to set to <0> to SELECT A selection signal generation circuit 42 for generating <3> is provided.
[0040]
The selection signal generation circuit 42 includes differential voltage comparison circuits 430 to 432 for comparing each of the reference potentials Vref2, Vref4, and Vref6 with the second reference potential Vdiv, and the voltage comparison circuits 430 to 432. The first buffer circuit 440 to the third buffer circuit 442, which take out the comparison outputs correspondingly, and the first buffer circuit 440 to the third buffer circuit 442, respectively, input the reference potential Vref1 based on the comparison result. , Vref3, Vref5, Vref7, which is closest to the second reference potential Vdiv, and a determination circuit 45 that selectively activates (outputs) one of the four determination signals H0 to H3; When the set signal SET is “H”, the four determination signals H0 to H3 output from the determination circuit 45 are latched. When the set signal SET is “L”, the latch circuits (register circuits) 460 to hold the state. 463. The outputs of the latch circuits 460 to 463 correspond to the selection signal SELECT. <1> to SELECT <3>, which are respectively supplied to the gates of the NMOS transistors NS0 to NS3 for the selection switch. The set signal SET is generated by the test control circuit 30 in FIG.
[0041]
When the second reference potential Vdiv, which is the other input, is lower than the reference potentials Vref2, Vref4, Vref6, which are one input, the voltage comparison circuits 430 to 432 correspond to each other. When the second reference potential Vdiv, which is the other input, is higher than the reference potentials Vref2, Vref4, Vref6, which are one of the inputs, the comparison output becomes the “L” level.
[0042]
The determination circuit 45 includes an inverter circuit 450 that inverts the output of the first buffer circuit 440, and a negative-logic two-input first input that receives the output of the inverter circuit 450 and the output of the second buffer circuit 441. NAND gate 451 (in the positive logic, a NOR gate with two inputs) 451, a negative logic three-input second input to which the output of the inverter circuit 450, the output of the first NAND gate 451, and the output of the third buffer circuit 442 are input. NAND gate 452 (a three-input NOR gate in positive logic), a negative three-input third input to which the output of the inverter circuit 450, the output of the first NAND gate 451, and the output of the second NAND gate 452 are input. NAND gate (three-input NOR gate in positive logic) 453.
[0043]
Next, the reference potential adjustment operation by the reference potential adjustment circuit of FIG. 4 will be described.
[0044]
This reference potential adjustment operation is performed, for example, in a chip test state. At this time, the test control circuit 30 in FIG. 1 operates the second reference potential generation circuit 20 in FIG. 1 by setting the set signal SET to the active state (“H” level). 4 is set to a state in which the latch circuits 460 to 463 in FIG.
[0045]
Here, the test state of the chip may be a chip operation evaluation process in the production line, or on the board after mounting. Done It may be a chip operation evaluation. In either case, the current consumption of the chip is suppressed, and it is relatively easy to keep the potential of the power supply constant.
[0046]
If the second reference potential Vdiv is lower than the reference potential Vref2, each comparison output of the voltage comparison circuits 430 to 432 is “H”. As a result, each output of the first buffer circuit 440 to the third buffer circuit 442 becomes “L”. As a result, the output of the inverter circuit 450 becomes “H”, and the outputs of the first NAND gate 451 to the third NAND gate 453 become “L”.
[0047]
Therefore, the determination circuit 45 selectively activates one determination signal H0 out of the four determination signals H0 to H3. When these four determination signals H0 to H3 are latched by the latch circuits 460 to 463, the selection signal SELECT <0> to SELECT Select signal from <3> SELECT <0> is selectively activated, and NS0 of the selection switch NMOS transistors NS0 to NS3 is selected. As a result, Vref1 closest to the second reference potential Vdiv is selected from the reference potentials Vref1, Vref3, Vref5, and Vref7, and is output as the adjusted reference potential Vref.
[0048]
On the other hand, when the second reference potential Vdiv is between Vref2 and Vref4, the comparison output of the voltage comparison circuit 430 is “L”, and the comparison outputs of the voltage comparison circuits 431 to 432 are “ H ”. As a result, the output of the first buffer circuit 440 becomes “H”, and the outputs of the second buffer circuit 441 to the third buffer circuit 442 become “L”, respectively. As a result, the output of the inverter circuit 450 becomes “L”, the output of the first NAND gate 451 becomes “H”, and the outputs of the second NAND gate 451 to the third NAND gate 452 become “L”, respectively. .
[0049]
Therefore, the determination circuit 45 selectively activates the determination signal H1 among the four determination signals H0 to H3. When these four determination signals H0 to H3 are latched by the latch circuits 460 to 463, the selection signal SELECT <0> to SELECT Select signal from <3> SELECT <1> is selectively activated, and NS1 among the NMOS transistors NS0 to NS3 for the selection switch is selected. As a result, Vref3 closest to the second reference potential Vdiv is selected from the reference potentials Vref1, Vref3, Vref5, and Vref7, and is output as the adjusted reference potential Vref.
[0050]
On the other hand, when the second reference potential Vdiv is between Vref4 and Vref6, the comparison outputs of the voltage comparison circuits 430 to 431 are “L”, and the comparison output of the voltage comparison circuit 432 is “ H ”. As a result, the outputs of the first buffer circuit 440 to the second buffer circuit 441 become “H”, and the output of the third buffer circuit 442 becomes “L”. As a result, the output 450 of the inverter circuit becomes “L”, the output 451 of the first NAND gate becomes “L”, the output 452 of the second NAND gate becomes “H”, and the output of the third NAND gate 453. Becomes “L”.
[0051]
Therefore, the determination circuit 45 selectively activates the determination signal H2 among the four determination signals H0 to H3. When these four determination signals H0 to H3 are latched by the latch circuits 460 to 463, the selection signal SELECT <0> to SELECT Select signal from <3> SELECT <2> is selectively activated, and NS2 of the selection switch NMOS transistors NS0 to NS3 is selected. As a result, Vref5 closest to the second reference potential Vdiv is selected from the reference potentials Vref1, Vref3, Vref5, and Vref7, and is output as the adjusted reference potential Vref.
[0052]
On the other hand, when the second reference potential Vdiv is higher than Vref6, the comparison outputs of the voltage comparison circuits 430 to 432 are “L”. As a result, the outputs of the first buffer circuit 440 to the third buffer circuit 442 become “H”. As a result, the output of the inverter circuit 450 becomes “L”, the outputs of the first NAND gate 451 to the second NAND gate 452 become “L”, and the output of the third NAND gate 453 becomes “H”.
[0053]
Therefore, determination circuit 45 selectively activates determination signal H3 among four determination signals H0 to H3. When these four determination signals H0 to H3 are latched by the latch circuits 460 to 463, the selection signal SELECT <0> to SELECT Select signal from <3> SELECT <3> is selectively activated, and NS3 of the selection switch NMOS transistors NS0 to NS3 is selected. As a result, Vref7 closest to the second reference potential Vdiv is selected from the reference potentials Vref1, Vref3, Vref5, and Vref7, and is output as the adjusted reference potential Vref.
[0054]
That is, according to the first embodiment described above, when the reference potential is adjusted by external control, the first reference potential Vbgr having the characteristics of low power supply potential dependency and low temperature dependency is temporarily set. Even if variations occur due to device manufacturing variations, the first reference potential Vbgr is automatically adjusted with reference to the second reference potential Vdiv, which is less affected by device manufacturing variations. It is possible to select a reference potential closest to Vdiv from among the reference potentials.
[0055]
After the output potential is adjusted in this way, when the chip is brought into a normal operation state, the reference potential Vref adjusted according to the design value can be supplied to the circuit inside the chip, and the chip is operating at high speed. In this case, a stable operation can be obtained due to the low power supply potential dependency and the low temperature dependency of the adjusted reference potential Vref.
[0056]
Furthermore, according to the first embodiment, the following effects can be obtained.
[0057]
(1) Eliminates the need for external elements for adjustment.
[0058]
Since the circuit 40 for adjusting the first reference potential Vbgr used in the normal operation state is built in, an external element for adjustment is not required.
[0059]
(2) Reduction of test cost.
[0060]
The built-in reference potential adjustment circuit 40 operates with reference to the second reference potential Vdiv generated from the built-in second reference potential generation circuit 20, so that different adjustments are made for each chip from the outside. It is not necessary to input a signal, and the test can be facilitated. This enables, for example, simultaneous testing of a large number of semiconductor memory chips, and is effective in reducing test costs.
[0061]
(3) Low power consumption.
[0062]
In general, the output potential of the reference potential generating circuit is affected by manufacturing variations of elements, but there are cases where the influence can be suppressed by setting a large current consumption of the circuit. Focusing on this point, in the normal operation state where low current consumption is required, there is some manufacturing variation, but the power supply using the first reference potential generation circuit 10 with low power consumption and relatively low current consumption is not required. At the time of turning on, the output potential of the first reference potential generation circuit 10 is adjusted with reference to the second reference potential generation circuit 20 which consumes a large amount of power but has a small manufacturing variation. As a result, a reference potential generating circuit that is less affected by element variations and consumes less power can be constructed, and the power consumption of the semiconductor device can be reduced.
[0063]
(4) Reduction of chip area.
[0064]
Due to the recent demand for high-speed operation for integrated circuits, the increase in power consumption of the chip is significant. When the consumption current is large, a potential gradient is generated in the chip even in the ground potential line. Also, digital signals that operate at high speed generate noise. In such a chip, it is necessary to disperse a plurality of reference potential generation circuits, and the area cannot be ignored. In this case, generally, the accuracy of the output potential is high, and the reference potential generating circuit that is not affected by disturbance, that is, the influence of the power supply potential or the ambient temperature, has a large area.
[0065]
Therefore, a plurality of circuits having inferior characteristics but a small area are arranged in the chip as the first reference potential generation circuit 10 and one second reference potential generation circuit 20 having a large area but good characteristics is arranged. Then, the output potential of the first reference potential generation circuit 10 is adjusted with reference to the second reference potential Vdiv while the current consumption of the chip is small.
[0066]
In this way, it is not affected by the potential gradient or noise generated in the chip. Thereby, when it is necessary to arrange a plurality of reference potential generation circuits in the chip, the chip area can be reduced.
[0067]
<Modification of the first embodiment>
In the first embodiment, the reference potential adjustment circuit 40 and the first reference potential generation circuit 10 are provided separately. However, a part of the reference potential adjustment circuit 40 shown in FIG. It is also possible to modify the configuration so that a part of the first reference potential generation circuit 10 is shared, an example of which is shown in FIG.
[0068]
In the first reference potential generation circuit 10a and the reference potential adjustment circuit 40a shown in FIG. 5, the resistance element R3 of the first reference potential generation circuit shown in FIG. 2 is divided into a plurality of resistance elements R51 to R58. The plurality of divided resistance elements R51 to R58 also serve as the plurality of resistance elements R41 to R48 connected in series in the reference potential adjustment circuit shown in FIG. 4, and the reference potential adjustment corresponding to 41 in FIG. The differential amplifier circuit 41 for feedback control in the circuit is omitted. Other portions are denoted by the same reference numerals as those of the reference potential adjusting circuit 40 shown in FIG. 2 and the first reference potential generating circuit 10 shown in FIG.
[0069]
That is, the reference potentials Vref1 to Vref7 at the connection nodes of the plurality of resistance elements R51 to R58 divided in the first reference potential generation circuit 10a are compared with the second reference potential Vdiv.
[0070]
According to the modification of the first embodiment described above, the same effect can be obtained by basically the same operation as in the first embodiment, and the configuration can be simplified.
[0071]
<Second Embodiment>
In the second embodiment, in the first embodiment, a means for outputting potential difference information between the first reference potential Vbgr and the second reference potential Vdiv to the outside of the chip, and the first reference potential Vbgr A means for programming the initial value of the output level is added to the chip.
[0072]
The reference potential generation circuit with an adjustment function shown in FIG. 6 has a first reference potential Vbgr and a second reference potential generation circuit as compared with the reference potential generation circuit with an adjustment function according to the first embodiment described above with reference to FIG. An output circuit 61 for outputting the result of detecting the potential difference of the reference potential Vdiv to the outside of the chip via the output pad 60, and the program content is referred to during the power-on operation, and the initial output level of the first reference potential Vbgr The difference is that a program means 62 for adjusting the reference potential for setting the value in the reference potential adjusting circuit 40b is added, and the rest is the same.
[0073]
Compared with the reference potential adjusting circuit 40 shown in FIG. 4 or the reference potential adjusting circuit 40a shown in FIG. 5, the reference potential adjusting circuit 40b is an output signal from the program means 62 for adjusting the reference potential according to the test control signal. And latch to select signal SELECT <0> to SELECT It has been modified to generate <3>.
[0074]
As a circuit for detecting the potential difference between the first reference potential Vbgr and the second reference potential Vdiv, the reference potential adjustment circuit 40 shown in FIG. 4 or the reference potential adjustment circuit 40a shown in FIG. 5 or FIG. The reference potential adjustment circuit 40b shown in FIG.
[0075]
The reference potential adjusting circuits 40, 40a, 40b as described above compare the plurality of reference potentials Vref1, Vref3, Vref5, Vref7 generated from the first reference potential Vbgr with the second reference potential Vdiv. The one closest to the reference potential Vdiv of 2 is selected. Therefore, information indicating which reference potential is selected (a plurality of selection signal selection signals SELECT <0> to SELECT The selection signal that is alternatively activated among <3> corresponds to the potential difference detection signal.
[0076]
Note that the above-described potential difference detection circuit that detects the potential difference between the first reference potential Vbgr and the second reference potential Vdiv is a selection signal in which the potential difference (analog value) is selectively activated among a plurality of selection signals. Since it can be regarded as an A / D conversion circuit that converts it into a (digital value), it can be configured by various forms of A / D conversion circuits.
[0077]
FIG. 7A shows an example of the program means 62 for adjusting the reference potential in FIG. 6, and an example of the operation waveform is shown in FIG. 7B.
[0078]
7A includes three fuse elements F1 to F3, three latch circuits LT1 to LT3 having a set / reset function, three inverter circuits IV1 to IV3, and one of three inputs. A 4-bit signal for selecting and controlling one of the four reference potentials Vref1, Vref3, Vref5 and Vref7 generated by the first reference potential generating circuit shown in FIG. Default <0> to Default It is configured to generate <3>.
[0079]
That is, in each of the latch circuits LT1 to LT3 with a set / reset function, the source is connected to the power supply node, the reset PMOS transistor 71 whose reset signal FCLRn is input to the gate, and the drain of the PMOS transistor 71 has the drain The set NMOS transistor 72 connected to the gate and receiving the set signal FSETp at the gate, and reset by the reset signal FCLRn to latch the potential of the drain interconnection node of the reset PMOS transistor 71 and the set NMOS transistor 72 Latch circuit 73.
[0080]
The inverter circuits IV1 to IV3 are correspondingly connected to the subsequent stage of the latch circuits LT1 to LT3, and there is a correspondence between the source of the NMOS transistor 72 for setting the latch circuits LT1 to LT3 and the VSS node. The fuse elements F1 to F3 are provided, and the fuse elements F1 to F3 are blown out as necessary. The outputs of the inverter circuits IV1 to IV3 are input to the NOR circuit NOR.
[0081]
Next, a typical operation of the latch circuit LT1 among the latch circuits LT1 to LT3 with the set / reset function having the above-described configuration will be described with reference to FIG.
[0082]
When the reset signal FCLRn is “L” after the power supply potential VCC rises from 0V to the operable potential of the circuit, the latch circuit 73 is reset to output “L”. After the reset signal FCLRn for storing the state of the fuse element F1 becomes “H” level, the set signal FSETp for transmitting the state of the fuse element F1 to the latch circuit 73 is changed from “L” to “H”. → Transition to “L”. At this time, when the fuse element F1 is blown, the latch circuit 73 is set to output “H”, and when the fuse element F1 is not blown, the latch circuit 73 is set to output “L”. Is done.
[0083]
Therefore, in the program means of FIG. 7A, when only F1 of the fuse elements F1 to F3 is blown, the 4-bit signal Default <0> to Default Default of <3> Only <0> is “H”.
[0084]
On the other hand, when only F2 of the fuse elements F1 to F3 is blown, the 4-bit signal Default <0> to Default Default of <3> Only <1> becomes “H”.
[0085]
On the other hand, when all the fuse elements F1 to F3 are not blown (initial state of the program), the 4-bit signal Default <0> to Default Default of <3> Only <2> is “H”.
[0086]
On the other hand, when only F3 of the fuse elements F1 to F3 is blown, the 4-bit signal Default <0> to Default Default of <3> Only <3> becomes “H”.
[0087]
Therefore, based on the test control signal, the 4-bit signal Default <0> to Default <3> is latched by the reference potential adjustment circuit 40b and the select signal SELECT <0> to SELECT If <3> is generated, it is possible to alternatively output a plurality of reference potentials Vref1, Vref3, Vref5, Vref7 generated from the first reference potential Vbgr.
[0088]
FIG. 8 shows an example in which a reference potential adjustment circuit having an initial value setting function at power-on is configured as the reference potential adjustment circuit 40b in FIG.
[0089]
Compared with the reference potential adjustment circuit 40 described above with reference to FIG. 4, the reference potential adjustment circuit having the initial value setting function is (1) the inverter circuit 450 and the first NOR gate 451 to the third NOR gate 453. Multiplexer circuits 80 to 83 are inserted correspondingly between the output nodes and the input nodes of the latch circuits 460 to 463, respectively. (2) The multiplexer circuits 80 to 83 receive the set signal SET. Sometimes, control is performed to select the determination signals H0 to H3 from the determination circuit 45, but when the signal CHRDYp indicating that the power is turned on is inverted by the inverter circuit 84, the signal Default <0> to Default (3) The set signal SET and the inverted signal of the signal CHRDYp are input to a two-input OR gate 85, and the output of the OR gate 85 is used to set the latch circuits 460 to 463. The input is different and the others are the same.
[0090]
Each of the multiplexer circuits 80 to 83 receives the inverted signal of the signal CHRDYp as one input, and the signal Default <0> to Default The first AND gate 86 having two inputs in which one of <3> is the other input, and one of the determination signals H0 to H3 output from the determination circuit 45, the set signal SET being one input. One input is a two-input second AND gate 87 which is the other input, and a two-input OR gate 88 to which the outputs of the two AND gates 86 and 87 are input. Each output of the OR gate 88 is input to the latch circuits 460 to 463 correspondingly.
[0091]
In the above configuration, the signal CHRDYp indicating that the power is turned on is the signal Default that is programmed in the fuses F1 to F3 from the program means shown in FIG. <0> to Default Waiting for output as <3>, transition from "L" to "H".
[0092]
Therefore, when the signal CHRDYp is "L" (its inverted signal is "H"), the multiplexer circuits 80 to 83 receive the signal Default from the program means shown in FIG. <0> to Default <3> is selected, and the latch circuits 460 to 463 latch it. When the signal CHRDYp becomes “H” (its inverted signal is “L”), the latch circuits 460 to 463 hold the latched state.
[0093]
As in the case of the reference potential adjustment circuit 40 described above with reference to FIG. 4, when the set signal SET becomes “H”, the multiplexer circuits 80 to 83 select the determination signals H0 to H3 output from the determination circuit 45, and The latch circuits 460 to 463 latch it. When the set signal SET becomes “L”, the latch circuits 460 to 463 hold the latch state.
[0094]
Therefore, the chip in which the program means shown in FIG. 7 is programmed can set the initial value of the output level of the reference potential adjustment circuit by referring to the program contents of the program means during the power-on operation. .
[0095]
<An example of a reference potential adjustment method in a semiconductor device including a reference potential generation circuit with an adjustment function according to the second embodiment>
Next, an example of a method of adjusting the reference potential in the chip shipping test process in the manufacturing process of the semiconductor device including the reference potential generating circuit with the adjustment function according to the second embodiment as described above will be described with reference to FIG. This will be described with reference to the flowchart shown in FIG.
[0096]
First, in the wafer state, the output level of the first reference potential Vbgr is adjusted with reference to the second reference potential Vdiv. At this time, the method for adjusting the output level of the first reference potential Vbgr is the same as the method described above in the first embodiment, and a description thereof will be omitted. At this time, information on detection of the potential difference between the first reference potential Vbgr and the second reference potential Vdiv is output and acquired externally.
[0097]
Thereafter, a chip operation test is performed using the adjusted output level of the first reference potential Vbgr (reference potential Vref in which the influence of manufacturing variation is suppressed). The operation test of the chip is performed in a normal operation state or a state equivalent thereto.
[0098]
Therefore, as compared with the conventional case where a chip operation test is performed with the first reference potential Vbgr as it is (that is, the adjusted reference potential Vref of this example is not used), many chips operate normally. Is expected to do. In the chip operation test, a chip having a defective operation is discarded.
[0099]
Further, in order to perform an operation test of the chip in a state close to actual use, the second reference potential Vdiv is affected by the power supply potential VCC, so that its use is not desirable, and the adjusted first reference potential Vbgr is used. It is desirable to implement it. That is, when the chip is operating, it is difficult to keep the power supply potential VCC constant due to the influence of the power consumption. Therefore, in a state where the second reference potential Vdiv is used, the chip operation test cannot be accurately performed.
[0100]
Next, the process proceeds to a step of programming the program means for adjusting the reference potential based on the potential difference information.
[0101]
By performing this programming process, a fuse element blowing process is added to the manufacturing process. In the semiconductor memory device manufacturing process, a program process for repairing a defective memory element (fuse element blowing process). Already exists, if the adjustment program is executed at the same time, the number of steps does not increase.
[0102]
Next, a final operation test of the chip is performed through cutting of the chip from the wafer and a packaging process (for example, a resin sealing process). At this time, as already described above, since the program is executed for the program means for adjusting the reference potential, the output level of the first reference potential Vbgr is adjusted just by turning on the power. That is, in the final operation test stage of the chip, a procedure for adjusting the first reference potential Vbgr is not required.
[0103]
As described above, according to the semiconductor device according to the second embodiment having the function of programming the output level of the first reference potential Vbgr, the first reference with reference to the second reference potential Vdiv in actual use. The adjustment operation of the reference potential Vbgr is unnecessary. In other words, normal operation is possible when the power is turned on, which is convenient. In addition, an electrical fuse, a PROM, or the like may be used as the fuse element. In this case, if a fuse element having the same configuration as the fuse element used in the programming process for relieving the defective memory element is used, the output level of the first reference potential Vbgr can be programmed without increasing the number of processes. Become.
[0104]
<Third Embodiment>
When analog circuits that require the reference potential Vref are scattered in the chip, a method of generating the reference potential Vref at one point in the chip and distributing it to the scattered analog circuits can be considered. Has a problem.
[0105]
That is, a semiconductor device that operates at high speed generally consumes a large amount of power, and a voltage gradient is generated due to the resistance of the power supply wiring. Therefore, even if the reference potential Vref can be accurately generated as a potential difference from the ground potential VSS, It cannot be accurately communicated.
[0106]
Furthermore, although the reference potential Vref is transmitted through a high impedance signal line, there are many digital wirings operating at high speed in the chip, and these serve as noise sources, and the transmission of the reference potential Vref is affected by noise. easy.
[0107]
In order to solve these problems, it is desirable to arrange the reference potential generating circuit in the vicinity of the analog circuit. However, in such a configuration, it becomes a problem how to adjust a plurality of reference potential generation circuits scattered in the chip.
[0108]
In order to solve this problem, in the semiconductor device according to the third embodiment, a plurality of first reference potential generation circuits are provided in the chip as shown in FIG.
[0109]
In FIG. 10, the plurality of first reference potential generation circuits 10 each use a band-gap reference circuit as described above with reference to FIG. On the other hand, one second reference potential generation circuit 90 may be a circuit having supply power supply potential dependency as described above with reference to FIG. 3, but in this example, A band-gap reference circuit that has a circuit configuration similar to that of the reference potential generation circuit and is realized so that variation in element characteristics is reduced, and the band-gap reference circuit and the power supply node for controlling the operation of the band-gap reference circuit And a switching PMOS transistor 91 inserted between them and an inverter circuit 92 that inverts the control signal supplied from the test control circuit 30 and supplies the inverted signal to the gate of the switching PMOS transistor 91.
[0110]
That is, even if the first reference potential generation circuit 10 and the second reference potential generation circuit 90 have the same circuit configuration as the band-gap reference circuit shown in FIG. It becomes a thing.
[0111]
In general, it is known that variation in device characteristics is inversely proportional to the square root of the area. For example, when the channel length L and the channel width W of the MOS transistor are set large, the variation of the threshold value Vt is (WL) ^1/2 It becomes smaller in inverse proportion to. In the band-gap reference circuit shown in FIG. 2, by setting the channel length L and the channel width W of the MOS transistors constituting the differential amplifier large, the variation in elements is reduced and the accuracy of the reference potential is improved. Can be expected.
[0112]
The resistance element can be expected to have the same effect as described above, and a plurality of options may be prepared for its type. A diffusion resistance or a polysilicon resistance having a large area but a small manufacturing variation and a large manufacturing resistance but a small area may be considered.
[0113]
Therefore, for the second reference potential generating circuit 90 that is required to be highly accurate, the band-gap reference circuit shown in FIG. 2 is realized using an element having a large area but small manufacturing variation. In this case, since only one second reference potential generation circuit 90 exists in the chip, a slight increase in area is allowed.
[0114]
On the other hand, the first power supply potential generation circuit 10 built in a large number of chips has a strict requirement for the area, and therefore, an element with a small area is used even if there is some manufacturing variation, as shown in FIG. A band-gap reference circuit is realized.
[0115]
In this way, the influence of the manufacturing variation generated in the first reference potential Vbgr1 generated from the first reference potential generation circuit 10 refers to the second reference potential Vbgr2 generated from the second reference potential generation circuit 90. And can be adjusted.
[0116]
<Example of Reference Potential Adjustment Method in Semiconductor Device with Reference Function Generating Circuit with Adjustment Function According to Third Embodiment>
The adjustment operation of the reference potential generating circuit in the semiconductor device according to the third embodiment is performed as follows.
[0117]
First, when the entire chip is put into a test state, the current consumption of the entire chip is suppressed, and the potential gradient of the power supply wiring becomes almost negligible. Further, since the chip is hardly operated, noise generated from the digital wiring is also reduced. That is, the environment for transmitting the second reference potential Vbgr2 to the entire chip is prepared.
[0118]
In this state, when a signal indicating the potential adjustment state is input from the test control circuit 30 to the second reference potential generation circuit 90 and the operation thereof is started, the second reference potential Vbgr2 having almost no influence of manufacturing variations. Occurs.
[0119]
The reference potential adjustment circuit 40 provided corresponding to each of the plurality of first reference potential generation circuits 10 existing in the chip refers to the second reference potential Vbgr2 transmitted from the second reference potential generation circuit 90. Then, the respective first reference potentials Vbgr1 are adjusted, and the subsequent positions are maintained. Thereafter, when the chip is brought into a normal operation state, each analog circuit in the chip refers to the adjusted accurate reference potential Vref output from the first reference potential generation circuit 10 disposed in the vicinity thereof. Therefore, it is possible to perform a stable and normal operation that is not affected by the potential gradient generated in the power supply wiring and that is not affected by noise.
[0120]
In general, in the case of an analog circuit, accuracy can be improved by increasing current consumption. For example, in the band-gap reference circuit shown in FIG. 2, the current flowing through the differential amplifier DA is set to about 100 μA, or the current flowing through the diode is set to about 100 μA, so that there is little influence of device manufacturing variations. An output potential can be expected.
[0121]
In the normal operation state, the second reference potential Vbgr2 is not necessary, and the operation of the second reference potential generation circuit 90 can be stopped. Therefore, the current of the above level is set in the second reference potential generation circuit 90. It is permissible.
[0122]
Therefore, according to the third embodiment, it is possible to reduce power consumption and obtain a highly accurate reference potential with little influence of manufacturing variations.
[0123]
On the other hand, since the plurality of first reference potential generation circuits 10 existing in the chip continue to operate in the normal operation state, it is required to suppress the power consumption. In particular, in the case of a CMOS semiconductor device, the power consumption of the entire chip is about several tens of μA in a standby state where most circuits are not operating.
[0124]
In such a chip, it is required to suppress the current consumed by the first reference potential generation circuit 10 to about 1 μA, and in order to satisfy this requirement, it is not possible to suppress the influence of manufacturing variations of elements. It is effective to provide a reference potential adjusting circuit 40 corresponding to the first reference potential generating circuit 10.
[0125]
<Variation 1 of the third embodiment>
In the third embodiment, the second reference potential Vbgr2 is transmitted to the vicinity of the plurality of first reference potential generation circuits 10 and compared therewith. However, the present invention is not limited to this. For example, the configuration can be changed as follows.
[0126]
That is, the plurality of reference potential adjustment circuits 40c are respectively a plurality of reference potential generating resistor elements R41 to R48, a feedback control operational amplifier circuit 41, a PMOS transistor P4, and a selection circuit (latch). The reference potential selector circuit 101 for extracting a plurality of reference potentials for comparison is added to the circuit 100 having the circuits 460 to 463 and the selection switch MOS transistors NS0 to NS3).
[0127]
The plurality of reference potential adjusting circuits 40c are provided in the vicinity of each of the plurality of first reference potential generating circuits 10 and the first reference potential generating circuits 10 respectively input from the corresponding first reference potential generating circuits 10 are provided. A plurality of reference potentials are generated in response to the reference potentials Vbgr11 to Vbgr1n.
[0128]
The reference potential comparison circuit 103 is provided in common to the plurality of reference potential adjustment circuits 40c. Among the reference potential adjustment circuits, a voltage comparison circuit (430 to 432) and a selection signal generation circuit (determination circuit 440) are provided. 104 including 450 to 453), and is provided in the vicinity of the second reference potential generation circuit 90.
[0129]
Further, a reference potential transmission wiring group 105 is formed in common between the plurality of reference potential adjustment circuits 40c and the reference potential comparison circuit 103.
[0130]
During the test, the plurality of reference potential adjustment circuits 40c are sequentially selected and controlled by the test control circuit 30c. A plurality of reference potentials for comparison extracted from the reference potential selector circuit 101 of the selected reference potential adjustment circuit 40c are input to the reference potential comparison circuit 103 via the reference potential transmission wiring group 105.
[0131]
In the reference potential comparison circuit 103, the transmitted plurality of reference potentials are compared with the second reference potential Vbgr2 by the voltage comparison circuits (430 to 433), and the selection signal generated by the selection signal generation circuit 104 based on the comparison result is used. The selection circuit 100 of the currently selected reference potential adjustment circuit 40c is selectively controlled to control the output. Note that the latch circuit in the selection circuit 100 is the test control circuit 30c. By Latch control is performed.
[0132]
By sequentially performing such a control operation on the plurality of reference potential adjustment circuits 40c, the output levels of the first reference potentials Vbgr11 to Vbgr1n can be adjusted.
[0133]
According to such a configuration, the same effect as that of the third embodiment can be obtained. However, since the reference potential comparison circuit 103 is used as a whole, the overall pattern area can be reduced or the flexibility of the pattern layout can be achieved. It becomes possible to have.
[0134]
In the third embodiment, an example in which the reference potential inside the semiconductor device is adjusted at the time of test control input has been described. Further, as in the second embodiment described above, the first reference potential and It is possible to automatically adjust the reference potential by outputting information detecting the potential difference of the second reference potential to the outside and executing a program by a technique such as fuse blowing based on the information.
[0135]
【The invention's effect】
As described above, according to the present invention, the reference potential having low power supply potential dependency and low temperature dependency generated inside can be adjusted to be a reference potential that is less affected by variations in the elements used. It is possible to provide a semiconductor device and a reference potential adjusting method thereof that can eliminate the need for external elements, reduce test costs, reduce power consumption, and reduce the chip area.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of a reference potential generation circuit with an adjustment function formed in a semiconductor device of the present invention.
FIG. 2 is a circuit diagram showing a band-gap reference circuit as an example of a first reference potential generating circuit in FIG. 1;
FIG. 3 is a circuit diagram showing an example of a second reference potential generation circuit in FIG. 1;
4 is a circuit diagram showing an example of a reference potential adjustment circuit in FIG. 1. FIG.
FIG. 5 is a circuit diagram showing an example in which a part of the reference potential adjustment circuit and a part of the first reference potential generation circuit are shared as a modification of the first embodiment;
FIG. 6 is a block diagram showing a second embodiment of a reference potential generating circuit with adjustment function formed in a semiconductor device of the present invention.
7 is a diagram showing an example of the configuration of the program means for adjusting the reference potential in FIG. 6 and an example of operation waveforms;
8 is a circuit diagram showing an example in which a reference potential adjustment circuit having an initial value setting function at power-on is configured as the reference potential adjustment circuit in FIG. 6;
FIG. 9 is a flowchart showing an example of a method for adjusting a reference potential in a chip shipping test process in a manufacturing process of a semiconductor device including a reference potential generating circuit with an adjustment function according to a second embodiment;
FIG. 10 is a block diagram showing a third embodiment of a reference potential generating circuit with an adjustment function formed in a semiconductor device of the present invention.
11 is a circuit diagram showing a modification of the reference potential generation circuit of FIG.
[Explanation of symbols]
10: First reference potential generation circuit,
20: Second reference potential generation circuit,
30 ... Control circuit,
40: Reference potential adjustment circuit.

Claims (17)

A first reference potential generation circuit and a second reference potential generation circuit;
A control circuit for selectively controlling the normal operation state and the other special operation states;
Controlled by the control circuit, adjusts and outputs the output potential of the first reference potential generation circuit with reference to the output potential of the second reference potential generation circuit in the special operation state, and in the normal operation state, the first reference potential generation circuit outputs the first reference potential generation circuit. A semiconductor device comprising: a reference potential adjustment circuit that outputs the adjusted output potential of a reference potential generation circuit. And a means for comparing the output potential of the first reference potential generation circuit with the output potential of the second reference potential generation circuit in the special operation state and outputting the potential difference information outside the semiconductor chip. The semiconductor device according to claim 1.   3. The semiconductor device according to claim 1, wherein the special operation state is an operation state when power is turned on.   3. The semiconductor device according to claim 1, wherein the special operation state is a test mode.   5. The semiconductor device according to claim 1, wherein the second reference potential generation circuit is controlled to stop the operation in the normal operation state. 6.   6. The semiconductor device according to claim 1, wherein the second reference potential generation circuit has a characteristic that depends on an external input potential.   6. The semiconductor device according to claim 1, wherein the second reference potential generation circuit has power supply potential dependency.   The semiconductor device according to claim 1, wherein the first reference potential generation circuit includes a band-gap reference circuit. 8. The semiconductor according to claim 1, further comprising a program unit for setting an initial value of an output potential of the first reference potential generation circuit in the reference potential adjustment circuit. apparatus. 10. The semiconductor device according to claim 9, wherein the program means includes a fuse element having the same configuration as that of a fuse element used in a program process for relieving a defective memory element.   11. The plurality of first reference potential generation circuits are provided, and the reference potential adjustment circuit is provided corresponding to each of the plurality of first reference potential generation circuits. 2. The semiconductor device according to claim 1.   The reference potential adjustment circuit generates a plurality of reference potentials from the output potential of the first reference potential generation circuit, and is closest to the output potential of the second reference potential generation circuit among the plurality of reference potentials. 12. The semiconductor device according to claim 1, wherein a semiconductor device is selected and output. The first reference potential generating circuit that generates the first reference potential that is relatively less affected by the power supply potential and the ambient temperature, and is affected by the influence of the power supply potential and the ambient temperature, but is affected by variations in the elements used. A second reference potential generating circuit for generating a relatively small second reference potential, and a reference for adjusting the output potential of the first reference potential generating circuit and outputting it as a reference potential used inside the semiconductor device A potential adjustment circuit is provided inside the semiconductor device,
The second reference potential generating circuit is operated, the output potential of the first reference potential generating circuit is adjusted by the reference potential adjusting circuit with reference to the output potential, and the adjusted output potential is set in the semiconductor device. A method for adjusting a reference potential of a semiconductor device, wherein the reference potential is output as a reference potential used in a semiconductor device.   14. The reference potential adjustment method according to claim 13, wherein the second reference potential generation circuit is controlled to stop operation in a normal operation state.   15. The reference potential adjustment method according to claim 13, wherein the second reference potential generation circuit has a characteristic that depends on an external input potential.   The reference potential adjustment method according to claim 13, wherein the second reference potential generation circuit has power supply potential dependency.   17. The reference potential adjusting method according to claim 13, wherein the first reference potential generation circuit includes a band-gap reference circuit.

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