JP2015144348A - clock supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of the conventional occurrence of a phase jump at a changeover between a working system and a standby system.SOLUTION: A clock supply system, redundantly configured of the working system and the standby system, for supplying a clock from an upper-level device to a lower-level device of hierarchical disposition, includes: a conversion circuit for converting into a voltage a phase difference between a working system clock and a standby system clock; a changeover circuit for changing over between the voltage obtained by the conversion by the conversion circuit and a preset constant voltage, on the basis of operational system information indicating whether the self-system is the working system or the standby system; and a PLL circuit, including an adder circuit for adding a voltage output from the changeover circuit to a phase control value of the self-system, as a phase control value, for generating a clock synchronized with a clock received from the upper-level device to output to the lower-level device.

Description

  The present invention relates to a clock supply device.

  In general, a communication device that performs digital transmission is connected to a clock synchronization network in order to synchronize operation timing with other communication devices. The clock synchronization network includes a clock supply device for supplying a clock from a communication device of a main station having a generation source of a master clock to communication devices of subordinate stations connected hierarchically. In the clock synchronization network, the clock is transmitted from the higher-order clock supply device to the lower-order clock supply device in order and synchronized in accordance with the dependent synchronization method. In order to increase the reliability of the clock synchronous network, the clock path is made redundant in the active system and the standby system (see, for example, Patent Document 1).

JP 2011-124747 A

  The clock supply device switches to the standby system when a problem occurs in the active system clock, but there is no regulation of the phase difference between the active system clock and the standby system clock. There may be a large phase difference. However, when the phase difference between the clocks of both systems is large, there arises a problem that a phase jump occurs when switching from the active system to the standby system.

  An object of the clock supply device disclosed herein is to provide a technique for suppressing a phase jump that occurs when switching between an active system and a standby system.

  According to one aspect, the clock supply system includes a working system and a standby system that are made redundant, and in the clock supply apparatus that supplies a clock from a higher-level device to a lower-level device arranged in a hierarchy, The conversion circuit that converts the phase difference between the clock of the current system and the standby system clock into a voltage, and the voltage converted by the conversion circuit based on the operational system information indicating whether the local system is the active system or the standby system A switching circuit that switches between the set constant voltage and an adding circuit that adds the voltage output from the switching circuit as a phase control value to the phase control value of the own system, and a clock synchronized with the clock received from the host device And a PLL circuit that generates and outputs to a lower-level device.

  The clock supply device disclosed herein can suppress a phase jump that occurs when switching between the active system and the standby system.

It is a figure which shows an example of a clock supply system. It is a figure which shows an example of a clock supply apparatus. It is a figure which shows an example of a clock receiving part. As a comparative example of this embodiment, it is a figure which shows the circuit which matches an own system clock with the phase of another system clock. It is a figure which shows an example of the phase jump at the time of switching from an active system to a standby system. It is a figure which shows an example of the phase alignment circuit in the clock supply apparatus of this embodiment. It is a figure which shows the specific circuit example of a phase alignment circuit. It is a figure which shows an example of operation | movement of a D-FF circuit. It is a figure which shows the input-output characteristic of the signal in each part of a phase alignment circuit. It is a figure which shows operation | movement of a phase difference count circuit. It is a figure which shows the state of the phase alignment circuit when the own system is a backup system. It is a figure which shows the state of the phase alignment circuit when an own system switches from a standby system to an active system. It is a figure which shows an example of an oscillation part and an output part. It is a figure which shows the example by which a phase alignment circuit is mounted in an oscillation part.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a clock supply system 100. In FIG. 1, a clock supply system 100 includes a master clock generator 101 and clock supply devices 102a, 102b, 102c, 102d, 102e, and 102f. The clock supply devices 102a, 102b, and 102c supply clocks through the working path indicated by solid line arrows. Further, the clock supply devices 102d, 102e, and 102f supply a clock through a standby path drawn by a dotted arrow. In the example of FIG. 1, the clock supply device 102a and the clock supply device 102d are arranged in the same hierarchy, and both the active system and the standby system are routed to both the clock supply apparatus 102b and the clock supply apparatus 102e in the next hierarchy. Supply the clock. Similarly, the clock supply device 102c and the clock supply device 102f in the lowermost layer are supplied with clocks from both the active system and the standby system from the upper layer.

  Here, when a specific device is indicated among the plurality of clock supply devices 102a, 102b, 102c, 102d, 102e, and 102f, an alphabet is added to the reference symbol, for example, the clock supply device 102a. Further, when the contents common to the plurality of clock supply devices 102a, 102b, 102c, 102d, 102e, and 102f are described, the alphabet is omitted and the clock supply device 102 is described.

  Note that the clock supply device 102 generates a clock that cleans up jitter and wander of a clock input from a higher-order device (master clock generation device 101 or clock supply device 102), and outputs the generated clock to the lower-order device. Further, when a failure occurs in both the active system path and the standby system path, the clock supply apparatus 102 cannot receive the clock from the host apparatus. When the clock cannot be received from the higher-order device, the clock supply device has a function of supplying a clock to the lower-order device by running on its own oscillator (Holdover function).

  In FIG. 1, a clock supply device 102c and a clock supply device 102f arranged in the same hierarchy are, for example, two communication systems 103a, 103b, and 103c arranged in the same building. Supply the clock. The clock supplied from the clock supply device 102 to the communication device 103 is a clock synchronized with the master clock output from the master clock generation device 101. Similarly, the clock supply devices 102a and 102d and the clock supply devices 102b and 102e arranged in the same hierarchy supply the working and standby clocks to the communication devices of the respective layers. In FIG. 1, illustration of a communication device that receives a clock supply from the clock supply devices 102a, 102b, 102d, and 102e is omitted.

  Here, in FIG. 1, the route drawn by the solid line arrow is described as the active system, and the route drawn by the dotted line arrow is the standby system. However, when a failure occurs in the active system clock supply apparatus 102, the same hierarchy is used. The standby clock supply apparatus 102 functions as an active system. Therefore, it can be switched appropriately between the active system and the standby system. For example, in FIG. 1, when a failure occurs in the active clock supply apparatus 102b, the clock supply apparatus 102e in the same hierarchy is switched from the standby system to the active system.

As described above, the clock supply apparatus 102 according to the present embodiment is arranged in a hierarchical manner on the redundant paths of the master clock output from the master clock generation apparatus 101 in the active system and the standby system, and is synchronized with the master clock. Supply clocks in order.
[Example of clock supply apparatus 102]
FIG. 2 shows an example of the clock supply device 102. In FIG. 2, the clock supply apparatus 102 includes a clock receiving unit 201a, an oscillating unit 202a, and an output unit 203a on the working path. Similarly, the clock supply apparatus 102 includes a clock receiving unit 201b, an oscillating unit 202b, and an output unit 203b on a standby path. Here, the clock receiving unit 201a and the clock receiving unit 201b, the oscillation unit 202a and the oscillation unit 202b, the output unit 203a and the output unit 203b have the same basic functions. Therefore, in the following description, when the contents common to the clock receiving unit 201a and the clock receiving unit 201b are described, the alphabet of reference numerals is omitted and the clock receiving unit 201 is described. Similarly, when the contents common to the oscillating unit 202a and the oscillating unit 202b are described, the alphabet of the reference numerals is omitted and the oscillating unit 202 is described, and the contents common to the output unit 203a and the output unit 203b are described. In this case, the alphabet of the code is omitted and the output unit 203 is indicated.

  In FIG. 2, a clock receiving unit 201 inputs a clock from a higher-level device and outputs a clock to both the active and standby oscillation units 202. For example, the clock reception unit 201a and the clock reception unit 201b output clocks to the active oscillation unit 202a and the standby oscillation unit 202b, respectively.

  The oscillating unit 202 includes a PLL (Phase Locked Loop) circuit using, for example, a crystal oscillator in order to generate a clock synchronized with the clock input from the clock receiving unit 201.

  The output unit 203 selects the working clock or the standby clock input from the oscillation unit 202 and outputs the selected clock to the lower-level clock supply device 102. For example, the output unit 203 a selects a clock output from the active oscillation unit 202 a or a clock output from the standby oscillation unit 202 b and outputs the clock to the lower-level clock supply device 102.

  Here, the clock supply apparatus 102 includes a control unit 250 for controlling the entire apparatus. The control unit 250 controls switching from the active system to the standby system, or switching from the standby system to the active system, and the circuits of the clock reception unit 201, the oscillation unit 202, and the output unit 203 operate as the active system. Manage whether or not. Then, the control unit 250 outputs operational system information indicating whether it is an active system or a standby system to each circuit.

  As described above, the oscillating unit 202 can select the working or standby clock output from the clock receiving unit 201a or the clock receiving unit 201b. Similarly, the output unit 203 can select a working or standby clock output from the oscillation unit 202a or the oscillation unit 202b.

  FIG. 3 shows an example of the clock receiving unit 201. In FIG. 3, the clock receiving unit 201a includes a receiving circuit 301a, a frequency dividing circuit 302a, a phase matching circuit 303a, and a frequency dividing circuit 304a. Similarly, the clock receiving unit 201b includes a receiving circuit 301b, a frequency dividing circuit 302b, a phase matching circuit 303b, and a frequency dividing circuit 304b. Then, the clock receiving unit 201a and the clock receiving unit 201b feed back each output clock to another system and match the phases. For example, the output clock of the clock receiving unit 201a is fed back to the phase matching circuit 303b of the clock receiving unit 201b, and the output clock of the clock receiving unit 201b is fed back to the phase matching circuit 303a of the clock receiving unit 201a.

  Here, the receiving circuit 301a and the receiving circuit 301b, the frequency dividing circuit 302a and the frequency dividing circuit 302b, the phase adjusting circuit 303a and the phase adjusting circuit 303b, and the frequency dividing circuit 304a and the frequency dividing circuit 304b have the same functions. Therefore, when the contents common to the receiving circuit 301a and the receiving circuit 301b are described, the alphabet at the end of the code is omitted and the receiving circuit 301 is described. Similarly, when the contents common to the frequency dividing circuit 302a and the frequency dividing circuit 302b are described, they are expressed as the frequency dividing circuit 302, and the contents common to the phase adjusting circuit 303a and the phase adjusting circuit 303b are described. This is expressed as a phase matching circuit 303. In addition, when the contents common to the frequency dividing circuit 304 a and the frequency dividing circuit 304 b are described, they are referred to as the frequency dividing circuit 304.

  The reception circuit 301 includes circuits such as a buffer and an amplifier that input a clock from a higher-level device, and outputs the clock to the frequency dividing circuit 302.

  The frequency dividing circuit 302 divides the clock output from the receiving circuit 301 by a predetermined frequency dividing ratio. For example, the frequency dividing circuit 302 divides the clock output from the receiving circuit 301 into 1/10 frequency and outputs it to the phase matching circuit 303.

  The phase matching circuit 303 includes a phase difference conversion circuit 351 and a PLL circuit 352 as shown in the balloon portion of FIG.

  The phase difference conversion circuit 351 obtains the phase difference between the own system clock and the other system clock, and switches the output phase difference based on the operational system information given from the control unit 250. Here, as described above, the operational system information is information output from the control unit 250 and indicating whether the own system is the active system or the standby system. For example, when the own system is the active system, the other system is the standby system, and when the own system is the standby system, the other system is the active system. Therefore, in the following description, the own system is not necessarily the active system.

  The PLL circuit 352 operates to adjust the phase fluctuation of the own system clock and reduce the phase difference between the own system clock and the other system clock. For this purpose, the PLL circuit 352 has a circuit for adding the phase difference between the own clock and the other clock to the phase fluctuation of the own clock. The phase matching circuit 303 will be described in detail later.

  The frequency divider 304 is a circuit that divides the clock output from the phase matching circuit 303. The frequency divider circuit 304 is a circuit for outputting a clock having the same frequency as the clock output from the frequency divider circuit 302. The own frequency dividing circuit 304 outputs the divided clock to the own oscillating unit 202 and feeds it back to the other phase matching circuit 303. For example, the frequency dividing circuit 304a outputs the divided clock to the oscillation unit 202a and the phase matching circuit 303b, and the frequency dividing circuit 304b outputs the divided clock to the oscillation unit 202b and the phase matching circuit 303a. To do.

  As described above, the clock supply apparatus 102 according to the present embodiment adds the phase difference between the own system clock and the other system clock to the phase control value of the own system PLL circuit 352, so that the own system clock and the other system clock are added. And the phase can be adjusted. The working clock and the standby clock output from the frequency divider 304a and the frequency divider 304b are input to both the selection circuit 305a of the oscillation unit 202a and the selection circuit 305b of the oscillation unit 202b. As described above, the clock supply apparatus 102 according to the present embodiment performs control so that the phase difference between the active clock and the standby clock output from the frequency dividing circuit 304a and the frequency dividing circuit 304b is reduced. Thereby, the clock supply apparatus 102 according to the present embodiment can suppress the phase jump when the clock path is switched from the active system to the standby system.

  FIG. 4 shows, as a comparative example of the present embodiment, a circuit for matching the own system clock to the phase of the other system clock. In FIG. 4, clock receivers 400a and 400b correspond to the clock receivers 201a and 201b shown in FIG. In FIG. 4, the alphabet at the end of the code of each block is added when a specific block is described, and the alphabet is omitted when a description common to the same numbered blocks is given. For example, the clock receiver 400a and the clock receiver 400b are referred to as a clock receiver 400.

  In FIG. 4, the clock receiving unit 400 includes a receiving circuit 401, a frequency dividing circuit 402, a phase matching control circuit 403, and a differential pulse generating circuit 404. The clock output from the frequency dividing circuit 402 is input to the differential pulse generating circuit 404 of another system, and the frequency dividing circuit 402 of the other system is reset. For example, the clock output from the active frequency divider 402a is input to the differential pulse generator 404b of the standby clock receiver 400b. Then, the phase matching control circuit 403b outputs a reset signal (RST) to the frequency dividing circuit 402b to match the phase of the working clock. The operational information is the same information as the operational information described with reference to FIG. Based on the operation system information, the phase matching control circuit 403 outputs a reset signal to the frequency dividing circuit 402 when the own system is a standby system, and performs control to match the phase of the working clock.

  As described above, in the case of the comparative example shown in FIG. 4, the standby clock receiving unit 400 performs control to forcibly match the phase of the working clock, and thus the phase difference between the working clock and the standby clock is large. A phase jump occurs.

  FIG. 5 shows an example of a phase jump when switching from the active system to the standby system. In FIG. 5, the horizontal axis indicates the time axis t, and the difference between the timing t1 and the timing t2 is the phase difference between the active clock and the standby clock.

  In FIG. 5, the selection circuit 305 outputs a clock that rises at the same timing t1 as the active clock during a period from the active system to the standby system t3. On the other hand, in a period after timing t3 when the active system switches to the standby system, the selection circuit 305 selects the standby system clock. Then, the selection circuit 305 outputs a clock that rises at the same timing t5 as the standby clock, not the timing t4 when the active clock rises. At this time, the phase difference between the timing t4 and the timing t5 appears as a phase jump in the output clock of the selection circuit 305.

  Thus, the clock supply apparatus 102 according to the present embodiment controls the phase jump of the output clock of the selection circuit 305 by controlling the phase difference between the active clock and the standby clock input to the selection circuit 305 to be small. Suppress.

  FIG. 6 shows an example of the phase matching circuit 303 in the clock supply apparatus 102 of this embodiment. In FIG. 6, the phase matching circuit 303 includes a phase difference conversion circuit 351 and a PLL circuit 352 as described with reference to FIG. 3.

  The phase difference conversion circuit 351 includes a phase difference count circuit 501, a count voltage conversion circuit 502, a switch (SW: SWitch) 503, a low-pass filter (LPF) 504, a constant voltage circuit 505, and a switch. (SW) 506.

  The phase difference count circuit 501 counts the phase difference between the own system clock and the other system clock using the count clock output from the internal oscillator of the clock supply device 102 (for example, the oscillator of the control unit 250). For example, the phase difference count circuit 501 starts counting at the rising edge of the own system clock and ends counting at the rising edge of the other system clock. Then, the phase difference count circuit 501 outputs the count value by the next rising edge of the own clock and resets the counter. In this way, the phase difference count circuit 501 converts the phase difference between the own clock and the other clock into a count value and outputs it. For example, the count value increases as the phase difference increases, and decreases as the phase difference decreases.

  The count number voltage conversion circuit 502 includes a D / A (Digital / Analog) converter. The count number voltage conversion circuit 502 converts the count value output from the phase difference count circuit 501 into a voltage and outputs the voltage. Here, for example, the count value and the output voltage are in a proportional relationship, and the output voltage increases as the count value increases, and the output voltage decreases as the count value decreases.

  The SW 503 is a switch circuit that is turned on / off based on operational information provided from the control unit 250. The SW 503 is turned on when the own system is a standby system, and is turned off when the own system is the active system, based on the operational system information.

  The LPF 504 is a low-pass filter for smoothing the voltage output from the count voltage conversion circuit 502 when the SW 503 is on. Since the voltage output from the count number voltage conversion circuit 502 varies depending on the phase difference between the clocks of the own system and the other system, the LPF 504 smoothes the variation in the voltage output from the count number voltage conversion circuit 502. To do.

  The constant voltage circuit 505 is a circuit that has a constant voltage diode, a regulator circuit, and the like, for example, and outputs a preset constant voltage.

  The SW 506 is a switch circuit that is turned on / off based on operational information provided from the control unit 250. The SW 506 is turned on when the own system is the active system, and is turned off when the own system is the standby system, based on the operational system information. That is, the SW 506 is controlled exclusively so as to perform the reverse operation of the SW 503 described above.

  In this way, the phase difference conversion circuit 351 outputs a voltage based on the phase difference between the own system clock and the other system clock or a preset constant voltage to the PLL circuit 352 according to the operation system information. For example, the phase difference conversion circuit 351 outputs a preset constant voltage to the PLL circuit 352 when the own system is the active system, and when the own system is the standby system, A voltage based on the phase difference is output to the PLL circuit 352.

  On the other hand, in FIG. 6, the PLL circuit 352 includes a phase comparator 507, an LPF 508, an adder circuit 509, a VCO (Voltage Control Oscillator) 510, and a frequency divider 511.

  The phase comparator 507 compares the phase of the input own clock and the clock output from the PLL circuit 352, and outputs a voltage corresponding to the phase difference. The phase comparator 507 may use a digital circuit similar to the phase difference count circuit 501 or an analog circuit.

  The LPF 508 is a low-pass filter for smoothing the voltage output from the phase comparator 507.

  The adder circuit 509 adds the voltage output from the LPF 508 and the voltage output from the phase difference conversion circuit 351.

  The VCO 510 oscillates a clock having a frequency corresponding to the voltage output from the adder circuit 509.

  The frequency divider 511 outputs a clock obtained by dividing the frequency of the clock output from the VCO 510 into a frequency of 1 / N (N is a positive integer). In FIG. 6, the frequency divider 511 is represented by the symbol 1 / N.

  In this way, the PLL circuit 352 adjusts the phase of the clock output from the VCO 510 based on the phase variation of the own system clock and the phase difference between the own system clock and the other system clock output from the phase difference conversion circuit 351. .

  FIG. 7 shows a specific circuit example of the phase matching circuit 303. In FIG. 7, blocks having the same reference numerals as those in FIG. 6 have the same or similar functions as those in FIG. Hereinafter, a different part from FIG. 6 is demonstrated.

  In FIG. 7, a differential pulse generation circuit 521 is connected to a path for inputting the own system clock to the phase comparator 507 and the phase difference count circuit 501 shown in FIG. In FIG. 7, an inverter 522 is connected to a path for inputting another system clock to the phase difference count circuit 501 shown in FIG. Further, in FIG. 7, an inverter 523 is connected to a path for inputting operational system information to the SW 506 shown in FIG. In FIG. 7, a buffer 524 is connected between the LPF 504 and SW 506 shown in FIG.

  In FIG. 7, the LPF 504 shown in FIG. 6 has a resistor R7 and a capacitor C1, and the constant voltage circuit 505 shown in FIG. 6 has a power source for generating a constant voltage Vref and a resistor R6. The resistor R6 and the capacitor C1 operate as a time constant circuit.

  The differential pulse generation circuit 521 has a differential circuit that generates a negative pulse at the timing of the rising edge of the own system clock. Here, the pulse signal output from the differential pulse generation circuit 521 is denoted as REF_IN. The differential pulse generation circuit 521 outputs a pulse signal REF_IN to the phase comparator 507 and the phase difference count circuit 501.

  The inverter 522 is an inverting circuit for inverting the logic of the other system clock, and outputs the inverted other system clock to the phase difference count circuit 501. The inverter 522 is a circuit for shifting the phase of the own clock and the other clock by 1/2 to facilitate detection of the phase difference, and may be included in the phase difference count circuit 501.

  The inverter 523 is an inverting circuit for reversing the operations of the SW 503 and the SW 506 controlled by the operating system information, and outputs the inverted operating system information to the SW 506. Here, when the active system information of the operational system information is represented by logic “0” and the standby system is represented by logic “1”, SW503 and SW506 are respectively logic “0” and off, and logic “1” is on. The case of being controlled will be described. When the operation system information is the active system (logic “0”), the SW 503 is turned off and the SW 506 controlled via the inverter 523 is turned on. Conversely, when the operational system information is a standby system (logic “1”), the SW 503 is turned on and the SW 506 controlled via the inverter 523 is turned off.

  The buffer 524 is an amplifier that uses an operational amplifier and whose output is fed back to the negative input terminal (−) and has an amplification factor of 1. The buffer 524 outputs the voltage of the constant voltage circuit 506 or the LPF 504 to the addition circuit 509. Since the buffer 524 has a high input impedance, the influence on the circuit connected to the positive input terminal (+) is reduced.

  A D-FF (D-type FlipFlop) circuit 525 is an example of a circuit used as the phase comparator 507. The signal output from the inverting output terminal (Q￣) of the D-FF circuit 525 is fed back to the input terminal (D), and the signal output from the non-inverting output terminal (Q) is input to the LPF 508. The D-FF circuit 525 inputs a clock (FB) fed back from the VCO 510 via the frequency divider 511 to the clock input terminal (>). For example, the D-FF circuit 525 outputs the logic state of the input terminal (D) to the non-inverting output terminal (Q) at the rising edge of the clock (FB) output from the frequency divider 511. In the D-FF circuit 525, the REF_IN signal of the differential pulse generation circuit 521 is input to the set terminal (S), and the non-inverted output terminal (Q) is set to “1”.

  In FIG. 7, an adder circuit 509 is an example of the adder circuit 509 shown in FIG. 6, and includes an operational amplifier OP1 and an operational amplifier OP2. The reference voltage Vref (V) is applied to both the positive input terminals (+) of the operational amplifier OP1 and the operational amplifier OP2, and the addition circuit 509 is applied when the voltage of the negative input terminal (−) of the operational amplifier OP1 is Vref (V). The output voltage of becomes zero. The operational amplifier OP1 adds the output voltage of the LPF 508 input through the resistor R1 and the output voltage of the buffer 524 input through the resistor R2. The addition ratio between the output voltage of the LPF 508 and the output voltage of the buffer 524 is determined by the ratio of the resistor R1 on the LPF 508 side and the resistor R2 on the buffer 524 side. The operational amplifier OP2 is an amplifier for adjusting the level of the output voltage of the operational amplifier OP1. The amplification factor of the operational amplifier OP2 is determined by the ratio between the negative feedback resistor R5 of the operational amplifier OP2 and the input resistance R4 of the negative input terminal (−). The addition ratio of the operational amplifier OP1 and the amplification factor of the operational amplifier OP2 are set to predetermined values. For example, the addition ratio of the operational amplifier OP1 is 1 (R1 = R2), and the amplification factor of the operational amplifier OP2 is 1 (R4). = R5).

  FIG. 8 shows an example of the operation of the D-FF circuit 525. The differential pulse generation circuit 521 outputs a negative pulse (REF_IN) at the rising edge of its own clock, and the non-inverted output terminal (Q) of the D-FF circuit 525 is set to logic “1” by the REF_IN signal. (FIG. 8A). The non-inverting output terminal (Q) of the D-FF circuit 525 is reset to logic “0” by the rising edge of the output (FB) of the frequency divider 511 (FIG. 8B). In this way, the non-inverting output terminal (Q) of the D-FF circuit 525 repeats logic “1” and logic “0” by the REF_IN signal of the differential pulse generation circuit 521 and the FB signal of the frequency divider 511. Output clock.

  Here, the PLL circuit 352 using the phase comparator 507 establishes synchronization when the DUTY ratio of the non-inverting output terminal (Q) of the D-FF circuit 525 reaches about 50%. That is, the PLL circuit 352 is in a state in which synchronization is established at a position where the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511 are shifted by a half cycle. When the phase of the output (FB) of the frequency divider 511 is delayed from the output (REF_IN) of the differential pulse generation circuit 521, the DUTY ratio of the non-inverting output terminal (Q) of the D-FF circuit 525 increases. To change. On the contrary, when the phase of the output (FB) of the frequency divider 511 is advanced from the output (REF_IN) of the differential pulse generation circuit 521, the DUTY ratio of the non-inverting output terminal (Q) of the D-FF circuit 525 becomes small. Change direction.

  FIG. 9 shows the input / output characteristics of signals in each part of the phase matching circuit 303. 9A shows the phase difference [UI (Unit Interval)] between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511, and the output voltage [V (Volt)] of the LPF 508. FIG. It is a graph which shows the relationship. 9A, when the output voltage of the LPF 508 is the power supply voltage (Vcc), the phase difference between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511 is 1.0 [ UI]. Similarly, when the output voltage of the LPF 508 is ½ of the power supply voltage (Vcc), the phase difference between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511 is 0.5 [ UI]. That is, the phase difference between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511 is proportional to the output voltage of the LPF 508.

  FIG. 10 shows the operation of the phase difference count circuit 501. In FIG. 10, the relationship between the local clock and the output (REF_IN) of the differential pulse generation circuit 521 is the same as in FIG. Here, FIG. 10 shows a state in which synchronization between the own clock and the other system clock is established, or a state close to a state in which synchronization is established. In FIG. 10, the other system clock input to the phase difference count circuit 501 is inverted by the inverter 522 shown in FIG. Then, the phase difference count circuit 501 counts the number of counting clocks in the period from the rising edge of the own system clock to the rising edge of the other system clock. The count number counted by the phase difference count circuit 501 corresponds to the phase difference between the own system clock and the other system clock. Note that the own system clock and the other system clock are shifted by a half cycle by the inverter 522 shown in FIG. 7, and therefore, when the count number is ½ of the maximum count number, Will be in the correct state.

  FIG. 9B shows the relationship between the output voltage [V] of the phase difference conversion circuit 351 and the count number of the phase difference count circuit 501. In FIG. 9B, when the count number of the phase difference count circuit 501 is minimum (for example, 0), the output voltage of the phase difference conversion circuit 351 is maximum. Conversely, when the count number of the phase difference count circuit 501 is maximum (MAX), the output voltage of the phase difference conversion circuit 351 is minimum. Note that the slope of the graph in FIG. 9B changes according to the conversion magnification of the phase difference conversion circuit 351. When the count number (MID) is ½, the PLL circuit 352 is in a state where synchronization is established. When the own system is the active system, the voltage that the phase difference count circuit 501 gives to the PLL circuit 352 is Vref (V )

  FIG. 9C shows the relationship between the phase difference [UI] between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511 and the output voltage Vcont [V] of the adder circuit 509. It is a graph to show. In FIG. 9C, when the phase difference between the REF_IN signal and the FB signal is 1.0 [UI], the output voltage Vcont of the adder circuit 509 is the maximum voltage. Conversely, when the phase difference between the REF_IN signal and the FB signal is 0 [UI], the output voltage Vcont of the adder circuit 509 is the minimum voltage. Note that the slope of the graph in FIG. 9C changes according to the magnification of the adder circuit 509. Further, at the point of 0.5 [UI] where the REF_IN signal and the FB signal are shifted by a half cycle, the PLL circuit 352 is in a state where synchronization is established. As the phase difference between the REF_IN signal and the FB signal increases, the output voltage Vcont of the adder circuit 509 increases and the oscillation frequency of the VCO 510 increases, so the phase of the FB signal advances. Conversely, as the phase difference between the REF_IN signal and the FB signal decreases, the output voltage Vcont of the adder circuit 509 decreases and the oscillation frequency of the VCO 510 decreases, so the phase of the FB signal is delayed. In this way, the phase difference between REF_IN and FB converges to a point of 0.5 [UI], and the phase difference between the own system clock and the other system clock becomes 0 or close to 0.

  FIG. 11 shows the state of the phase matching circuit 303 when the own system is a standby system. In FIG. 11, blocks having the same reference numerals as those in FIG. 7 have the same or similar functions as those in FIG. FIG. 11 shows a case where the operational system information is a standby system, in which the SW 503 is turned on and the SW 506 is turned off.

  In FIG. 11, if the phase of the other system clock is delayed with respect to the REF_IN signal, as described in FIG. 10, the period from the rising edge of the own system clock to the rising edge of the inverted other system clock becomes longer. The count number of the phase difference count circuit 501 increases. As shown in FIG. 9B, since the count number and the output voltage are inversely proportional, the output voltage of the count number voltage conversion circuit 502 decreases and the output voltage of the buffer 524 also decreases. When the output voltage of the buffer 524 is lowered, the output voltage Vcont of the adder circuit 509 is also lowered, so that the oscillation frequency of the VCO 510 is lowered. Therefore, the PLL circuit 352 operates to increase the oscillation frequency of the VCO 510. For example, when the oscillation frequency of the VCO 510 is decreased, the frequency of the FB signal input to the D-FF circuit 525 is also decreased, and the period during which logic “1” is output from the non-inverting output terminal (Q) is increased. When the period during which logic “1” is output from the non-inverting output terminal (Q) becomes longer, the PLL circuit 352 increases the output voltage of the LPF 508 so as to cancel the decrease in the output voltage of the buffer 524. That is, the PLL circuit 352 operates so that the phase difference between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511 increases, and the phase of the own system clock is set to the phase of the other system clock. Can be combined.

  9D, similarly to FIG. 9C, the phase difference [UI] between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511, and the output of the addition circuit 509 It is a graph which shows the relationship with voltage Vcont [V]. In FIG. 9D, the characteristic indicated by the dotted line indicates the state of FIG. Then, due to the phenomenon described with reference to FIG. 11, the characteristic indicated by the dotted line in FIG. 9D slides to the left to become the characteristic indicated by the solid line, and the phase of the clock output from the VCO 510 changes.

  In this way, when the own system is a standby system, the phase matching circuit 303 controls the phase of the own system clock so that the phase difference from the clock of the other system (active system) is smaller than the current system. be able to.

  FIG. 12 shows a state of the phase matching circuit 303 when the own system is switched from the standby system to the active system. 12, blocks having the same reference numerals as those in FIG. 7 have the same or similar functions as those in FIG. Further, in FIG. 12, since the active system information is switched from the standby system to the active system, the SW 503 is switched from on to off, and the SW 506 is switched from off to on.

  In FIG. 12, in the phase matching circuit 303, when the SW 506 is switched from OFF to ON, a current flows from the constant voltage source to the capacitor C1 of the LPF 504 through the resistors R6 and SW 506. Since the SW 503 is in the off state, the resistor R7 of the LPF 504 can be ignored, and a time constant circuit is formed by the resistor R6 and the capacitor C1. The time of the time constant circuit becomes longer in proportion to the capacitance of the capacitor C1 and the resistor R6. However, since the capacitance of the capacitor C1 is determined according to the characteristics of the LPF 504, it is difficult to change it freely. Therefore, the resistor R6 is set to a resistance value such as several M [Ω] so that the time of the time constant circuit becomes longer. When the time of the time constant circuit is lengthened, the voltage of the capacitor C1 rises gradually until reaching the constant voltage Vref, and the output voltage of the buffer 524 also rises gently. Then, the PLL circuit 352 operates to cancel the increase in the output voltage of the buffer 524, and the output voltage of the LPF 508 gradually decreases. That is, the PLL circuit 352 operates so that the phase difference between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511 is smaller than that at present.

  FIG. 9E shows the phase difference [UI] between the output (REF_IN) of the differential pulse generation circuit 521 and the output (FB) of the frequency divider 511, as in FIGS. 9C and 9D. 4 is a graph showing the relationship with the output voltage Vcont [V] of the adder circuit 509. In FIG. 9 (e), the characteristic indicated by the dotted line corresponds to the characteristic indicated by the solid line in FIG. 9 (d). Then, due to the phenomenon described with reference to FIG. 12, the characteristic indicated by the dotted line in FIG. 9E slides to the right to become the characteristic indicated by the solid line, and the phase of the clock output from the VCO 510 changes.

  In this way, when the own system is switched from the standby system to the active system, the phase matching circuit 303 operates as the active system before switching (the original active system) and the output clock that has been synchronized with the other system clock. Control is performed to gradually change the phase to return to the phase of the own system clock.

As described above, the clock supply apparatus 102 according to the present embodiment obtains the phase difference between the active clock and the standby clock and controls the phase of the standby PLL circuit 352 when the own system is the standby system. Add to the value. Thereby, the standby phase matching circuit 303 can match the standby clock to the phase of the active clock, and can suppress a phase jump when switching from the standby to the active clock. In addition, when the own system is switched from the standby system to the working system, the phase matching circuit 303 gently returns the phase matched with the other system clock that was the original working system to the phase of the own system clock, thereby outputting the output phase. Can be prevented from changing suddenly.
[Application example]
FIG. 13 shows an example of the oscillation unit 202 and the output unit 203 as a comparative example. In FIG. 13, the oscillating unit 202a includes a selection circuit 305a, a PLL circuit 306a, and a frequency dividing circuit 307a. Similarly, the oscillation unit 202b includes a selection circuit 305b, a PLL circuit 306b, and a frequency dividing circuit 307b. Here, the selection circuit 305a and the selection circuit 305b, the PLL circuit 306a and the PLL circuit 306b, and the frequency dividing circuit 307a and the frequency dividing circuit 307b have the same functions. Therefore, when explaining the common contents, the alphabet at the end of the code is omitted, and it is expressed as, for example, a PLL circuit 306.

  In FIG. 13, a selection circuit 305 selects a working or standby clock output from the clock receiving unit 201. As the PLL circuit 306, for example, a rubidium oscillator having higher accuracy than a crystal oscillator is used, and the jitter and wander of the clock selected by the selection circuit 305 are suppressed. The frequency dividing circuit 307 divides the clock output from the PLL circuit 306 and outputs it to the output unit 203.

  On the other hand, the output unit 203a includes a selection circuit 308a and an output circuit 309a. Similarly, the output unit 203b includes a selection circuit 308b and an output circuit 309b. Here, the selection circuit 308a and the selection circuit 308b, and the output circuit 309a and the output circuit 309b have the same functions. Therefore, when explaining the common contents, the alphabet at the end of the code is omitted and, for example, the output circuit 309 is used.

  In FIG. 13, the selection circuit 308 selects an active or standby clock output from the oscillation unit 202. The output circuit 309 amplifies the clock selected by the selection circuit 308 and outputs the amplified clock to the lower-level device.

  Here, the clock supply apparatus 102 according to the present embodiment described with reference to FIG. 3 adjusts the phase to the clock reception unit 201 in order to suppress a phase jump when the selection circuit 305 of the oscillation unit 202 switches from the standby system to the active system. The circuit 303 was mounted. In the clock supply apparatus 102 in this application example, the selection circuit 308 of the output unit 203 shown in FIG. 13 includes a phase matching circuit 303 for suppressing a phase jump when switching the clock path from the standby system to the active system. 202.

  FIG. 14 shows an example in which the phase matching circuit 303 is mounted on the oscillation unit 212. 14, blocks having the same reference numerals as those in FIG. 13 have the same or similar functions as those in FIG. The phase matching circuit 303 has the same or similar function as the phase matching circuit 303 described in FIG.

  14, the oscillating unit 212 includes a phase matching circuit 303 and a frequency dividing circuit 310 after the frequency dividing circuit 307 of the oscillating unit 202 shown in FIG. As described with reference to FIG. 3, the phase matching circuit 303 includes a phase difference conversion circuit 351 and a PLL circuit 352. When the own system is a standby system, the phase matching circuit 303 adjusts the phase to the active system clock. Suppresses the phase jump when the system switches from the standby system to the active system. The frequency dividing circuit 310 outputs the output clock of the phase matching circuit 303 to the output unit 203 in accordance with the frequency of the clock output from the frequency dividing circuit 307.

  In this way, the clock supply apparatus 102 in this application example operates so that the phase difference between the active clock and the standby clock output from the oscillation unit 212 to the output unit 203 is eliminated. As a result, the clock supply apparatus 102 can suppress a phase jump when the selection circuit 308 of the output unit 203 switches the clock path from the standby system to the active system.

  In the previous embodiment, the phase matching circuit 303 is mounted on the clock reception unit 201, and in this application example, the phase matching circuit 303 is mounted on the oscillation unit 212. You may mount in both the clock receiving part 201 and the oscillation part 212. FIG.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

DESCRIPTION OF SYMBOLS 100 ... Clock supply system; 101 ... Master clock generator; 102, 102a, 102b, 102c, 102d, 102e, 102f ... Clock supply device; 103, 103a, 103b, 103c ... Communication device; 201, 201a, 201b ... clock receiving unit; 202, 202a, 202b, 212, 212a, 212b ... oscillating unit; 203, 203a, 203b ... output unit; 301, 301a, 301b ... receiving circuit 302, 302a, 302b ... frequency divider circuit; 303, 303a, 303b ... phase matching circuit; 304, 304a, 304b ... frequency divider circuit; 305, 305a, 305b ... selection circuit; 306a, 306b... PLL circuit; 307, 307a, 307b. 308, 308a, 308b ... selection circuit; 309, 309a, 309b ... output circuit; 310, 310a, 310b ... frequency dividing circuit; 351 ... phase difference conversion circuit; 352 ... PLL 400; 400a, 400b ... clock receiving unit; 401, 401a, 401b ... receiving circuit; 402, 402a, 402b ... frequency dividing circuit; 403, 403a, 403b ... phase matching control circuit; 404, 404a, 404b ... differential pulse generation circuit; 501 ... phase difference count circuit; 502 ... count number voltage conversion circuit; 503 ... SW; 504 ... LPF; 506... SW; 507... Phase comparator; 508... LPF; 509. Divider; 521 ... differential pulse generating circuit; 522 ... inverter; 523, 524 ... buffer; 525 ... D-FF circuit

Claims (5)

In a clock supply device that supplies a clock from a higher-order device arranged in a hierarchy to the active system and the standby system and arranged in a hierarchical manner to a lower-order device,
A conversion circuit that converts the phase difference between the active clock and the standby clock into a voltage;
A switching circuit for switching between a voltage converted by the conversion circuit and a preset constant voltage, based on operational system information indicating whether the own system is an active system or a standby system;
A PLL that includes an adder circuit that adds the voltage output from the switching circuit as a phase control value to the phase control value of the own system, generates a clock that is synchronized with the clock received from the higher-level device, and outputs the generated clock to the lower-level device A clock supply device comprising: a circuit. The clock supply device according to claim 1,
The switching circuit outputs a preset constant voltage to the adder circuit as a phase control value of the PLL circuit when the own system is an active system, and the conversion circuit converts the current when the own system is a standby system. The clock supply device, wherein the voltage is output to the adder circuit as a phase control value of the PLL circuit. The clock supply device according to claim 2,
The switching circuit further includes a time constant circuit that changes from a voltage converted by the conversion circuit to a constant voltage with a preset time constant when switching from a standby system to an active system. The clock supply device according to claim 3.
A filter circuit for suppressing a fluctuation in voltage indicating a phase difference between the active clock and the standby clock converted by the conversion circuit;
The clock supply apparatus, wherein the time constant circuit shares a part of the circuit with the filter circuit. The clock supply device according to claim 4,
The filter circuit is a low-pass filter in which a capacitor is disposed between the output of the first resistor connected in series and the ground,
The clock supply device, wherein the time constant circuit is formed by a second resistor connected to a constant voltage and a capacitor of the low-pass filter.

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