JP2000013220A - Phase locked loop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase locked loop circuit that is stable in operation over a wide frequency band. SOLUTION: A phase frequency comparator 12 compares a phase and a frequency of an input signal Si with those of a comparison signal S17 and provides an output of a phase lead signal S12u and a phase lag signal S12d. The phase lead signal S12u or the phase lag signal S12d is given to a charge pump 13, which provides an output of an output signal S13. A loop filter 14 smoothes the output signal S13 and provides an output of a control voltage S14. The control voltage S14 is given to a voltage controlled oscillator 15, which outputs an output signal S15. A frequency divider 17 frequency-divides the output signal S15, which gives a comparison signal S17 to the phase frequency comparator 12. Moreover, a control section 18 converts the control voltage S14 into a control signal S18. When the frequency of the input signal Si is low, the control voltage S14 is low, a current Ip of current sources 13-1, 13-4 is small, and when the frequency is high, the control signal S14 is high and the current Ip is high.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (hereinafter, referred to as "PLL") circuit that performs stable operation in a wide frequency band.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Literature; IEEE JOURNAL OF SOLID-STATE CIRCUITS.VOL.SC-
22 [NO.2] (APRIL1987), DEOG-KYOON JEONG, GAETANO BORRI
ELLO, DAVID A.HODGES, RANDY H.KATZ co-authored “Design of PL
L-Based Clock Generation Circuits "P.255-261

FIG. 2 shows a conventional PL described in the above document.
FIG. 2 is a configuration diagram illustrating an example of an L circuit. This PLL circuit,
It has an input terminal 1 for inputting an input signal Si, and a phase frequency comparator 2 is connected to the input terminal 1. The phase frequency comparator 2 has a function of comparing the phase and frequency of the input signal Si and the comparison signal S7 to generate and output a phase advance signal S2u or a phase delay signal S2d. Is connected. The charge pump 3 is a circuit that receives the phase advance signal S2u or the phase delay signal S2d and outputs an output signal S3.
And a current source 3-1 for flowing a current Ip from the DD, and the current Ip is turned on by the phase advance signal S2u to output the current Ip to the output node N.
Switch means 3-2 for outputting the phase delay signal S2d
Switch 3-3 which is turned on at the time of switching, and power supply voltage V from output node N when switch 3-3 is turned on.
And a current source 3-4 for flowing a current Ip into the SS. The output node N is connected to a loop filter 4 that smoothes the output signal S3 and outputs a control voltage S4. A control voltage S4 is input to the output side of the loop filter 4, and an output signal S of a frequency corresponding to the value of the control voltage S4 is output.
5 is connected. The output side of the voltage controlled oscillator 5 is connected to an output terminal 6 for outputting an output signal S5 and a frequency divider 7 for dividing the output signal S5 and outputting a comparison signal S7. The output side of the frequency divider 7 is connected to the phase frequency comparator 2.

Next, the operation of the PLL circuit shown in FIG. 2 will be described. In this PLL circuit, the phase and frequency of an input signal Si and a comparison signal S7 are compared in a phase frequency comparator 2, and a phase lead signal S2u and a phase delay signal S2d, which are asserted for a time proportional to the phase difference, are used. Is output. If the phase of the comparison signal S7 is behind the phase of the input signal Si, the phase advance signal S2u is asserted (activated). If the phase of the comparison signal S7 is ahead of the phase of the input signal Si, The phase delay signal S2d is asserted. When the phase advance signal S2u is asserted,
The switch means 3-2 of the charge pump 3 is turned on, and the current Ip flows into the loop filter 4. On the other hand, when the phase delay signal S2d is asserted, the switch means 3-3 of the charge pump 3 is turned on, and the current Ip flows out of the loop filter 4. If both the phase advance signal S2u and the phase delay signal S2d are not asserted, the switches 3-2 and 3-3 are both off, and the current Ip
No move.

[0005] The current Ip is smoothed by the loop filter 4, and a control voltage S4 is output. In this case, when the phase advance signal S2u is asserted, the voltage level of the control voltage S4 increases, and when the phase delay signal S2d is asserted, the voltage level of the control voltage S4 decreases. The control voltage S4 is input to the voltage controlled oscillator 5, and the voltage controlled oscillator 5 outputs an output signal S5 having a frequency corresponding to the control voltage S4.
When the voltage level of the control voltage S4 increases, the frequency of the output signal S5 increases, and when the voltage level decreases, the frequency decreases. The output signal S5 is frequency-divided by an arbitrary value in the frequency divider 7 and input to the phase frequency comparator 2 as a comparison signal S7. Thus, in the PLL circuit of FIG. 2, the loop filter 4 and the voltage controlled oscillator 5 operate as a continuous time system, and the phase frequency comparator 2 and the charge pump 3
Operates as a discrete-time system.

Therefore, as shown in the above-mentioned document, the loop gain K of this PLL circuit is expressed by the following equation (1). K = K0 × ΔVC = K0 × Ip × Z [Hz] (1) where K0: gain [Hz / V] of voltage controlled oscillator 5 ΔVC: control voltage change amount [V] Ip of voltage controlled oscillator 5 Current flowing through the charge pump 3 [A] Z; impedance of the loop filter 4 [Ω]

[0007]

However, the conventional PLL circuit of FIG. 2 has the following problems. FIG.
3 is a frequency characteristic diagram showing a relationship between a loop gain K and a stability limit in the PLL circuit of FIG. Loop gain K
Is represented by the equation (1), so that if the impedance Z of the loop filter 4 is constant independently of the frequency of the input signal Si, the value of the loop gain K is also constant independent of the frequency of the input signal Si. . In this case, as shown in FIG. 3, the loop gain K is indicated by a characteristic line RG, and the stability limit curve is indicated by a characteristic curve SC (however, indicated by an approximated line). The PLL circuit of FIG. 2 is composed of a negative feedback loop as a whole of the PLL circuit. In order to operate this negative feedback loop stably, the loop gain K needs to be smaller than a value of a stability limit. That is, the frequency of the input signal Si needs to be in a band higher than the frequency fa at the intersection of the characteristic line RG and the characteristic curve SC. Therefore, when the value of the loop gain K is large, the frequency fa
And it is difficult to secure a sufficient operable frequency band.

[0008]

According to a first aspect of the present invention, there is provided a PLL circuit for comparing the phase and frequency of an input signal and a comparison signal with each other, Phase frequency comparing means for generating and outputting a phase lead signal having a time width corresponding to the delay amount of the comparison signal with respect to the signal or a phase delay signal having a time width corresponding to the lead amount of the comparison signal with respect to the input signal And inputting the phase delay signal, the phase advance signal, and the control signal, and outputting a first signal whose current value or voltage value is controlled based on the control signal when the phase advance signal is input. And charge pump means for outputting a second signal whose current value or voltage value is controlled based on the control signal when the phase delay signal is input, and smoothing the first or second signal. Generates and outputs control voltage Smoothing means, a voltage-controlled oscillating means for receiving the control voltage and outputting an output signal having a frequency corresponding to the value of the control voltage, and a control voltage output from the smoothing means or an output from the voltage-controlled oscillating means. Control means for receiving the output signal thus generated, generating the control signal whose level increases or decreases in accordance with an increase or decrease in the value of the control voltage or the frequency of the output signal, and supplying the control signal to the charge pump means; Feedback means for generating the comparison signal by dividing or passing an output signal of the means, and feeding back to the phase frequency comparison means.

By adopting such a configuration, the phase and frequency of the input signal and the comparison signal are compared in the phase frequency comparison means, and a phase advance signal or a phase delay signal is generated. To the charge pump means, when a phase delay signal or a phase advance signal is input and a control signal is input from the control means, and when the phase advance signal is input,
A first signal whose current value or voltage value is controlled based on the control signal is output, and when the phase delay signal is input, a second signal whose current value or voltage value is controlled based on the control signal is output. Is output. The first or second signal is smoothed by the smoothing means to generate a control voltage. The control voltage is input to the voltage controlled oscillator, and an output signal having a frequency according to the value of the control voltage is output. The control voltage output from the smoothing means or the output signal output from the voltage control oscillating means is input to the control means, and the control signal whose level increases or decreases in accordance with an increase or a decrease in the value of the control voltage or the frequency of the output signal is generated. It is generated and supplied to the charge pump means. The output signal of the voltage controlled oscillator is divided or passed by the feedback unit, and the comparison signal is generated and fed back to the phase frequency comparison unit.

According to the invention of claim 2, the PL of claim 1
In the L circuit, the charge pump unit is supplied with a first power supply voltage, and outputs a first current whose current value is controlled based on the control signal; First switch means connected between a source and an output node, the first switch means being turned on based on the phase lead signal and outputting the first current to the output node;
A second power supply potential lower than the power supply potential of
A second current source that outputs a second current whose current value is controlled based on the control signal; and a second current source that is connected between the second current source and the output node, based on the phase delay signal. Second switch means for turning on to output the second current to the output node. By adopting such a configuration, when the phase advance signal is input, the first switch means is turned on, and the first current whose current value is controlled based on the control signal is changed to the first current. Output from the source to the output node. When the phase delay signal is input, the second switch is turned on, and the second current whose current value is controlled based on the control signal is equal to the second current.
From the current source to the output node.

In the invention according to claim 3, the PL of claim 1
In the L circuit, the charge pump unit is connected between a first voltage source that outputs a first voltage whose voltage value is controlled based on the control signal, and the first voltage source and an output node. A first switch unit that is turned on based on the phase advance signal and outputs the first voltage to the output node; and a second switch that has a lower potential than the first voltage based on the control signal. A second voltage source that outputs a second voltage, and is connected between the second voltage source and the output node, and is turned on based on the phase delay signal to output the second voltage. And second switch means for outputting to the node. By adopting such a configuration, when the phase advance signal is input, the first switch means is turned on, and the first voltage whose voltage value is controlled based on the control signal is changed to the first voltage. Output from the source to the output node. When the phase delay signal is input, the second switch is turned on, and the second voltage whose voltage value is controlled based on the control signal is output from the second voltage source to the output node.

[0012] In the invention according to claim 4, the PL according to claim 1 is provided.
In the L circuit, the charge pump means is connected between a first voltage source that outputs a first voltage, and the first voltage source and an output node, and is turned on based on the phase lead signal. First switch means for outputting the first voltage to the output node; a second voltage source for outputting a second voltage lower than the first voltage; and a second voltage source for outputting the second voltage. A second switch connected between a source and the output node, and turned on based on the phase delay signal to output the second voltage to the output node; and the output node and the smoothing unit. The first or second voltage output from the output node is changed and output to the input side of the smoothing means by changing the impedance based on the control signal. Variable impedance means It is provided. By adopting such a configuration, when a phase advance signal is input, the first
Is turned on, and the first voltage is changed by the impedance changing means and input to the smoothing means.
When the phase delay signal is input, the second switch is turned on, and the second voltage is changed by the impedance changing unit and input to the smoothing unit.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of a PLL circuit showing a first embodiment of the present invention. This PLL circuit has an input terminal 11 for inputting an input signal Si, and a phase frequency comparison means (for example, a phase frequency comparator) 12 is connected to the input terminal 11. The phase frequency comparator 12 compares the phase and frequency of the input signal Si with the comparison signal S17, and
, Or a phase lag signal S12d having a time width corresponding to the amount of advance of the comparison signal S17 with respect to the input signal Si, or a phase lag signal S12d having a time width corresponding to the amount of delay of the comparison signal S17 with respect to
Is generated and output, and a charge pump means (for example, a charge pump) 13 is connected to the output side. The charge pump 13 outputs the phase advance signal S12u
Or a circuit that receives the phase delay signal S12d and outputs the output signal S13, and outputs the control signal S1 from the power supply voltage VDD.
8 has a current source 13-1 for supplying a current Ip whose current value is controlled based on the current value Ip. Between the output side of the current source 13-1 and the output node N1, a switch 13-2 that is turned on by the phase advance signal S12u and outputs the current Ip to the output node N1 is connected. A switch 13-is provided between the output node N1 and the power supply voltage VSS.
3 and the current source 13-4 are connected in series. The switch means 13-3 is turned on when the phase delay signal S12d is asserted. The current source 13-4 is
Output node N when switch means 13-3 is on.
1 is a circuit for flowing a current Ip whose current value is controlled based on the control signal S18 from the power supply voltage VSS to the power supply voltage VSS. The current sources 13-1 and 13-4 are constituted by transistors or the like whose impedances are respectively changed based on the control signal S18.
12u and a transistor whose conduction state is controlled by the phase delay signal S12d.

The output node N1 has a smoothing means (for example, a smoothing means for smoothing the output signal S13 and outputting a control voltage S14).
Loop filter) 14 is connected. A voltage-controlled oscillating means (for example, a voltage-controlled oscillator) 15 that inputs a control voltage S14 and outputs an output signal S15 having a frequency corresponding to the value of the control voltage S14 to the output side of the loop filter 14.
Is connected. On the output side of the voltage controlled oscillator 15,
An output terminal 16 for outputting the output signal S15 and feedback means (for example, a frequency divider) 17 for dividing the output signal S15 and outputting a comparison signal S17 are connected. The phase frequency comparator 2 is connected to the output side of the frequency divider 7. Further, a control unit (for example, a control unit) 18 is connected to the output side of the loop filter 14. The control unit 18 includes, for example, an operational amplifier, and has a gain set so as to amplify the control voltage S14 and output a control signal S18 of an appropriate level. The output side of the control unit 18 is a current source 1
3-1 and 13-4.

FIG. 4 is a circuit diagram showing a configuration example of the loop filter 14 in FIG. This loop filter 14
A resistor 14c connected between the input terminal 14a and the output terminal 14b, a resistor 14d connected between the output terminal 14b and the node N14, and a capacitor 14e connected between the node N14 and the ground. It is composed of a lag lead (lag lead) filter provided.

Next, the operation of the PLL circuit of FIG. 1 will be described. In this PLL circuit, the phase and frequency of an input signal Si and a comparison signal S17 are compared in a phase frequency comparator 12, and a phase lead signal S12u and a phase delay signal S12d that are asserted for a time proportional to the phase difference are input.
Is output. If the phase of the comparison signal S17 is behind the phase of the input signal Si, the phase advance signal S12u is asserted, and the comparison signal S12
If the phase of 17 is advanced, the phase delay signal S12d is asserted. The phase advance signal S12u or the phase delay signal S12d is input to the charge pump 13. In the charge pump 13, the current source 13 is controlled based on the control voltage S14.
-1, 13-4 are controlled. That is, the control voltage S
14 is converted into a control signal S18 of an appropriate level by the control unit 18, and the current sources 13-1, 1 and 1 are controlled by the control signal S18.
The value of the current Ip flowing through 3-4 is controlled. Then, an output signal S13 is output from the charge pump 13. The output signal S13 is input to the loop filter 14, and the control voltage S14 is output from the loop filter 14. In this case, when the phase advance signal S12u is asserted, the voltage level of the control voltage S14 increases, and when the phase delay signal S12d is asserted, the voltage level of the control voltage S14 decreases. The control voltage S14 is input to the voltage controlled oscillator 15,
The voltage controlled oscillator 15 outputs an output signal S15 having a frequency corresponding to the control voltage S14. When the voltage level of the control voltage S14 increases, the frequency of the output signal S15 increases, and when the voltage level decreases, the frequency decreases. The output signal S15 is frequency-divided by the frequency divider 17 by an arbitrary value, and the frequency divider 17 sends a comparison signal S17 to the phase frequency comparator 12.

The control voltage S14 has a voltage level proportional to the frequency of the input signal Si. If the frequency is low, the voltage level of the control voltage S14 is low, and the control unit 18 controls the current sources 13-1 and 13-. 4 is kept small. On the other hand, if the frequency of the input signal Si is high, the voltage level of the control signal S14 is high, and the control unit 1
8, the value of the current Ip is kept large. Therefore, the current Ip is controlled based on the control voltage S14, and the loop gain K is expressed by the following equation (2). K = K0.times.Ip.times.Z = K0.times.A.VC.Ip.times.Z [Hz] (2) where: A; current control constant [1 / V] of control unit 18 VC; control of voltage controlled oscillator 15 Voltage [V] Ip; Current [A] flowing through charge pump 13 Z: Impedance [Ω] of loop filter 14

FIG. 5 is a frequency characteristic diagram showing the relationship between the loop gain K and the stability limit in the PLL circuit of FIG. Since the control voltage S14 has a voltage level proportional to the frequency of the input signal Si, the loop gain K is
It has a value that depends on the frequency of i. As a result, as shown in FIG. 5, the characteristic curve RG indicating the value of the loop gain K approaches the stability limit curve SC (however, both RG and SC are indicated by approximated straight lines), and the PLL circuit is more conventional than the conventional one. It operates stably in a wide frequency band. Further, since the loop gain K becomes as large as the stability limit, the input signal S
The stationary phase error between i and the comparison signal S17 is minimized. Further, a negative feedback loop that is strong against disturbances (for example, power supply voltage fluctuations and temperature changes) is formed, and the output signal S15
Is reduced.

As described above, in the first embodiment,
Based on the control voltage S14, the control unit 18 controls the current I flowing through the current sources 13-1 and 13-4 of the charge pump 13.
Since p is controlled, a PLL circuit capable of performing stable operation in a wider frequency band than before can be configured. Furthermore, the steady phase error between the input signal Si and the comparison signal S17 can be minimized, and the jitter of the output signal S15 can be reduced.

Second Embodiment FIG. 6 is a block diagram of a PLL circuit showing a second embodiment of the present invention. The common elements are the same as those in FIG. 1 showing the first embodiment. Reference numerals are given. In this PLL circuit, a charge pump 13A having a different configuration is provided instead of the charge pump 13 in FIG. In the charge pump 13A, the current source 13 in the charge pump 13
Instead of -1 and 13-4, voltage sources 13A-1 and 13A-4 for outputting voltages + Vp and -Vp whose voltage values are controlled based on the control signal S18 are provided. The voltage sources 13A-1 and 13A-4 are configured by transistors and the like whose output voltage is controlled based on the control signal S18. Other configurations are the same as those in FIG.

In the operation of the PLL circuit of FIG. 6, the values of the voltages + Vp and -Vp are controlled based on the control signal S18. Thereafter, the same operation as in FIG. 1 is performed. Therefore, the values of the voltages + Vp and -Vp are controlled based on the control voltage S14, and the loop gain K is expressed by the following equation (3). K = K0.times.Ip.times.Z = K0.times.B.Vc.Vp / Z.times.Z [Hz] (3) where: B; voltage control constant [1 / V] of control unit 18 Vc; voltage control oscillator 15 Control voltage [V] Vp; voltage [V] of voltage sources 13A-1 and 13A-4 [I]; current [A] flowing through charge pump 13A; Z; impedance [Ω] of loop filter 14 As in the first embodiment, FIG.
The middle characteristic curve RG approaches the stability limit curve SC, and the PLL circuit operates stably in a wider frequency band than before.

As described above, in the second embodiment,
Since the voltage Vp of the voltage sources 13A-1 and 13A-4 in the charge pump 13A is controlled by the control unit 18 based on the control voltage S14, as in the first embodiment, a wider frequency band Thus, a PLL circuit capable of performing a stable operation can be configured. Further, the steady phase error between the input signal Si and the comparison signal S17 is minimized, and the output signal S
15 jitter can be reduced.

Third Embodiment FIG. 7 is a block diagram of a PLL circuit showing a third embodiment of the present invention. Elements common to those in FIG. 1 are denoted by the same reference numerals. In this PLL circuit, a charge pump circuit 13B having a different configuration is provided instead of the charge pump circuit 13 in FIG. Charge pump circuit 1
3B, the current source 13- in the charge pump circuit 13
Fixed voltage + Vp, -Vp instead of 1,13-4
Are provided, respectively. Further, in the charge pump circuit 13B, between the output node N1 and the output node N2, there is provided an impedance varying unit 13B-5 whose impedance is controlled based on the control signal S18. The impedance varying means 13B-5 is configured by a transistor or the like whose impedance is varied based on the control signal S18. Other configurations are the same as those in FIG.

In the operation of the PLL circuit of FIG. 7, the impedance of the variable resistance means 13B-5 is controlled by the control signal S18. Thereafter, the same operation as in FIG. 1 is performed. Therefore, the variable resistance unit 1 is controlled based on the control voltage S14.
The resistance value of 3B-5 is controlled, and the loop gain K is expressed by the following equation (4). K = K0.times.Ip.times.Z = K0.times.Vp / (Zv / (C.Vc)). Times.Z [Hz] (4) where: C; resistance control constant of control unit 18 [1 / V] Vc; Control voltage [V] Zv of the voltage controlled oscillator 15; resistance value [Ω] of the impedance varying means 13B-5; Ip; current [A] flowing through the charge pump 13B; Z; impedance [Ω] of the loop filter 14 also in this embodiment. As in the first embodiment, FIG.
The middle characteristic curve RG approaches the stability limit curve SC, and the PLL circuit operates stably in a wider frequency band than before.

As described above, in the third embodiment,
Since the impedance of the impedance varying means 13B-5 in the charge pump 13B is controlled by the control unit 18 based on the control voltage S14, as in the first embodiment, stable operation in a wider frequency band than in the related art is achieved. A PLL circuit capable of the above can be configured. Further, the input signal S
minimize the steady phase error between i and the comparison signal S17,
The jitter of the output signal S15 can be reduced.

Fourth Embodiment FIG. 8 is a block diagram of a PLL circuit according to a fourth embodiment of the present invention, in which components common to those in FIG. 1 are denoted by common reference numerals. In this PLL circuit, a control means (for example, a bias voltage generation charge pump) 19 for outputting a bias voltage S19 proportional to the frequency of the output signal S15 is connected to the output side of the voltage controlled oscillator 15 in FIG. . The output side of the bias voltage generation charge pump 19 is connected to the input side of the control unit 18. Other configurations are the same as those in FIG.

FIG. 9 is an input / output characteristic diagram of the bias voltage generating charge pump 19 in FIG. This figure shows that the bias voltage S19 is proportional to the frequency of the output signal S15. In the operation of the PLL circuit in FIG. 8, the current source 13
-1, 13-4 are controlled. Thereafter, the same operation as in FIG. 1 is performed. Therefore, the current Ip is controlled based on the frequency of the output signal S15, and the loop gain K is expressed by the following equation (5). K = K0 × Ip × Z = K0 × A · Vb · Ip × Z [Hz] (5) where: A; current control constant [1 / V] of control unit 18 Vb; voltage of output signal S19 [ V] Ip; current [A] flowing through the charge pump 13 Z; impedance [Ω] of the loop filter 14 In this embodiment, as in the first embodiment, FIG.
The middle characteristic curve RG approaches the stability limit curve SC, and the PLL circuit operates stably in a wider frequency band than before.

As described above, in the fourth embodiment,
Based on the frequency of the output signal S15, the current Ip flowing through the current sources 13-1 and 13-4 of the charge pump 13 is controlled by the bias voltage generation charge pump 19 and the control unit 18.
, So that, as in the first embodiment,
PL that enables stable operation in a wider frequency band than before
An L circuit can be configured. Further, the input signal Si and the comparison signal S
17 is minimized, and the output signal S15
Jitter can be reduced.

Fifth Embodiment FIG. 10 is a block diagram of a PLL circuit showing a fifth embodiment of the present invention. FIG. 6 shows a second embodiment and FIG. 8 shows a fourth embodiment. The same reference numerals are given to the elements common to the elements described above. In this PLL circuit, the same charge pump 19 for generating a bias voltage as in FIG. 8 is connected to the output side of the voltage controlled oscillator 15 in FIG. The output side of the bias voltage generation charge pump 19 includes a control unit 18.
Input side is connected. Other configurations are the same as those in FIG.

In the operation of the PLL circuit of FIG. 10, the voltages + Vp, -Vp
Is controlled. Thereafter, the same operation as in FIG. 1 is performed. Therefore, based on the frequency of the output signal S15, the voltage +
The values of Vp and -Vp are controlled, and the loop gain K is expressed by the following equation (6). K = K0 × Ip × Z = K0 × B · Vb · Vp / Z × Z [Hz] (6) where B: voltage control constant [1 / V] of voltage control unit 18 Vb: output signal S19 Vp of the voltage sources 13A-1, 13A-4; Ip; the current [A] flowing through the charge pump 13A; Z; the impedance [Ω] of the loop filter 14 in the present embodiment. As in the embodiment of FIG.
The middle characteristic curve RG approaches the stability limit curve SC, and the PLL circuit operates stably in a wider frequency band.

As described above, in the fifth embodiment,
Based on the frequency of the output signal S15, the charge source 19 for bias voltage generation and the control unit 18 control the voltage source 13
Since the voltages Vp of A-1 and 13A-4 are controlled, a PLL circuit that can operate stably in a wider frequency band than in the related art can be configured as in the first embodiment. Furthermore, the steady phase error between the input signal Si and the comparison signal S17 can be minimized, and the jitter of the output signal S15 can be reduced.

Sixth Embodiment FIG. 11 is a block diagram of a PLL circuit showing a sixth embodiment of the present invention. FIG. 7 shows a third embodiment and FIG. 8 shows a fourth embodiment. The same reference numerals are given to the elements common to the elements described above. In this PLL circuit, the same charge pump 19 for generating a bias voltage as in FIG. 8 is connected to the output side of the voltage controlled oscillator 15 in FIG. The output side of the bias voltage generation charge pump 19 includes a control unit 18.
Input side is connected. Other configurations are the same as those in FIG.

In the operation of the PLL circuit of FIG. 11, the impedance of the impedance varying means 13B-5 is controlled according to the increase or decrease of the frequency of the output signal S15. Thereafter, the same operation as in FIG. 1 is performed. Therefore, the output signal S
Impedance variable means 13B based on the frequency of 15
The impedance of −5 is controlled, and the loop gain K is expressed by the following equation (7). K = K0.times.Ip.times.Z = K0.times.Vp / (Zv / (C.Vc)). Times.Z [Hz] (7) where: C; resistance control constant of control unit 18 [1 / V] Vb; Voltage [V] Zv of output signal S19; Resistance [Ω] of impedance varying means 13B-5 Ip; Current [A] flowing through charge pump 13B Z; Impedance [Ω] of loop filter 14 As in the first embodiment, FIG.
The middle characteristic curve RG approaches the stability limit curve SC, and the PLL circuit operates stably in a wider frequency band.

As described above, in the sixth embodiment,
Based on the frequency of the output signal S15, the impedance of the impedance varying means 13B-5 in the charge pump 13B is controlled by the bias voltage generation charge pump 19 and the control unit 18, so that, as in the first embodiment, A PLL circuit that can operate stably in a wider frequency band than before can be configured. Further, the input signal Si
And the comparison signal S17 can minimize the steady-state phase error and reduce the jitter of the output signal S15.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, there are the following modifications. (A) In each embodiment, when the frequency of the output signal S15 is the same as that of the input signal Si, the frequency divider 17 may be omitted. (B) In the fourth, fifth, and sixth embodiments, if the output signal S19 of the bias voltage generation charge pump 19 is at a level that can control the charge pumps 13, 13A, and 13B, the control unit 18 is deleted. Is also good. (C) The bias voltage generation charge pump 19 may be configured with a frequency-voltage converter (FV converter) that generates a DC voltage proportional to the frequency of the output signal S15.

[0036]

As described above in detail, according to the first aspect of the present invention, the current value of the charge pump means is determined based on the control voltage of the smoothing means or the frequency of the output signal output from the voltage controlled oscillation means. Alternatively, since the voltage value is controlled, a PLL circuit capable of performing stable operation in a wider frequency band than before can be configured. Further, the steady phase error between the input signal and the comparison signal can be minimized, and the jitter of the output signal of the PLL circuit can be reduced. According to the second aspect of the invention, the current of the current source of the charge pump means is controlled based on the control voltage of the smoothing means or the frequency of the output signal output from the voltage control oscillating means. A PLL circuit capable of performing stable operation in a wide frequency band can be configured. Further, the steady phase error between the input signal and the comparison signal can be minimized, and the jitter of the output signal of the PLL circuit can be reduced.

According to the third aspect of the present invention, the voltage of the voltage source of the charge pump means is controlled based on the control voltage of the smoothing means or the frequency of the output signal output from the voltage control oscillating means. A PLL circuit that can operate stably in a wider frequency band than before can be configured. Further, the steady phase error between the input signal and the comparison signal can be minimized, and the jitter of the output signal of the PLL circuit can be reduced. According to the invention according to claim 4, the resistance value of the variable resistance means of the charge pump means is controlled based on the control voltage of the smoothing means or the frequency of the output signal output from the voltage control oscillation means. A PLL circuit that can operate stably in a wider frequency band can be configured. Further, the steady phase error between the input signal and the comparison signal is minimized,
Jitter of the output signal of the L circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional PLL circuit.

FIG. 3 is a frequency characteristic diagram of a loop gain and a stability limit of FIG. 2;

FIG. 4 is a circuit diagram of a loop filter 14 in FIG.

FIG. 5 is a frequency characteristic diagram of a loop gain and a stability limit of FIG. 1;

FIG. 6 is a configuration diagram of a PLL circuit according to a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a PLL circuit according to a third embodiment of the present invention.

FIG. 8 is a configuration diagram of a PLL circuit according to a fourth embodiment of the present invention.

9 is a charge pump 1 for generating a bias voltage in FIG. 8;
9 is an input / output characteristic diagram of FIG.

FIG. 10 is a configuration diagram of a PLL circuit according to a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram of a PLL circuit according to a sixth embodiment of the present invention.

[Explanation of symbols]

12 Phase frequency comparator 13, 13A, 13B Charge pump 13-1, 13-4 Current source 13-2, 13-3 Switching means 13A-1, 13A-4, 13B-1, 13B-4 Voltage source 13B-5 Impedance variable means 15 Voltage controlled oscillator 17 Divider 18 Control unit 19 Charge pump for generating bias voltage VDD, VSS Power supply voltage

Claims (4)

[Claims] An input signal and a comparison signal are compared in phase and frequency, and a phase advance signal having a time width corresponding to a delay amount of the comparison signal with respect to the input signal, or advance of the comparison signal with respect to the input signal is provided. Phase frequency comparing means for generating and outputting a phase delay signal having a time width corresponding to the phase amount; and inputting the phase delay signal, the phase advance signal, and the control signal, and when the phase advance signal is input, Outputting a first signal whose current value or voltage value is controlled based on the control signal, and controlling the current value or voltage value based on the control signal when the phase delay signal is input; Charge pump means for outputting a control signal; smoothing means for smoothing the first or second signal to generate and output a control voltage; inputting the control voltage; and a frequency corresponding to the value of the control voltage. Voltage control output that outputs the output signal of And a control unit that receives a control voltage output from the smoothing unit or an output signal output from the voltage-controlled oscillating unit, and whose level increases or decreases according to an increase or decrease in the value of the control voltage or the frequency of the output signal. A control unit that generates a control signal and supplies the charge pump unit to the charge pump unit; a feedback unit that divides or passes an output signal of the voltage controlled oscillation unit to generate the comparison signal and that feeds back to the phase frequency comparison unit. And a phase-locked loop circuit. 2. The charge pump means, comprising: a first current source to which a first power supply voltage is supplied and which outputs a first current whose current value is controlled based on the control signal; A first switch connected between a current source and an output node, and turned on based on the phase lead signal to output the first current to the output node; A second current source that is supplied with a low-potential second power supply potential and outputs a second current whose current value is controlled based on the control signal; and the second current source and the output node. Connected between
The second state is turned on based on the phase delay signal.
2. A phase-locked loop according to claim 1, further comprising: a second switch for outputting said current to said output node. 3. The charge pump unit includes: a first voltage source that outputs a first voltage whose voltage value is controlled based on the control signal; and a first voltage source between the first voltage source and an output node. A first switch unit that is connected and is turned on based on the phase advance signal to output the first voltage to the output node; and a lower switch having a lower potential than the first voltage based on the control signal. A second voltage source that outputs a second voltage, connected between the second voltage source and the output node,
The second state is turned on based on the phase delay signal.
2. A phase-locked loop according to claim 1, further comprising: a second switch for outputting said voltage to said output node. 4. The charge pump means is connected between a first voltage source for outputting a first voltage, and the first voltage source and an output node, and is turned on based on the phase lead signal. A first switch means for outputting the first voltage to the output node, a second voltage source for outputting a second voltage lower in potential than the first voltage, Connected between a voltage source and the output node;
The second state is turned on based on the phase delay signal.
A second switch means for outputting the voltage of the output node to the output node, and connected between the output node and the input side of the smoothing means, and varying the impedance based on the control signal, from the output node. 2. The phase-locked loop according to claim 1, further comprising: impedance varying means for varying the output first or second voltage and outputting the same to the input side of the smoothing means.