JP2015143713A - semiconductor pressure sensor - Google Patents

semiconductor pressure sensor Download PDF

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JP2015143713A
JP2015143713A JP2015090063A JP2015090063A JP2015143713A JP 2015143713 A JP2015143713 A JP 2015143713A JP 2015090063 A JP2015090063 A JP 2015090063A JP 2015090063 A JP2015090063 A JP 2015090063A JP 2015143713 A JP2015143713 A JP 2015143713A
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detection unit
pressure sensor
semiconductor pressure
parallel
diaphragm
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JP5866496B2 (en
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新村　雄一
Yuichi Niimura
雄一 新村
西川　英男
Hideo Nishikawa
英男 西川
史仁 加藤
Fumihito Kato
史仁 加藤
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Panasonic Intellectual Property Management Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor pressure sensor capable of suppressing reduction in detection accuracy.SOLUTION: A semiconductor pressure sensor includes: a semiconductor substrate; a diaphragm part that is part of the semiconductor substrate and is obtained by thinning the semiconductor substrate; and first, second, third, and fourth detection units. Each of the first, second, third, and fourth detection units includes: a first end; a second end; a first part that extends in a first direction from the first end; a second part that extends in a second direction perpendicular to the first direction from the first part; a third part that extends in the first direction from the second part and has a part facing the first part in the first direction; a fourth part that extends in the second direction from the third part and has a part facing the second part in the first direction; and a fifth part that extends in the first direction from the fourth part to the second end in the first direction and has a part facing the first part in the second direction.

Description

本発明は、ダイヤフラム上に検出部を形成し、この検出部によりダイヤフラムに加えられた圧力を検出する半導体圧力センサに関する。   The present invention relates to a semiconductor pressure sensor in which a detection unit is formed on a diaphragm and the pressure applied to the diaphragm is detected by the detection unit.

従来より、ダイヤフラム上に形成された検出部によりダイヤフラムに加えられた圧力を検出する半導体圧力センサが知られている（例えば、特許文献１参照）。   2. Description of the Related Art Conventionally, a semiconductor pressure sensor that detects a pressure applied to a diaphragm by a detection unit formed on the diaphragm is known (see, for example, Patent Document 1).

特公平２−４１１８３号公報Japanese Examined Patent Publication No. 2-41183

このような半導体圧力センサにおいては、検出精度が低下してしまうのを抑制できるようにするのが好ましい。   In such a semiconductor pressure sensor, it is preferable to be able to suppress a decrease in detection accuracy.

そこで、本発明は、検出精度が低下してしまうのを抑制することのできる半導体圧力センサを得ることを目的とする。   Then, an object of this invention is to obtain the semiconductor pressure sensor which can suppress that detection accuracy falls.

本発明は、半導体基板と、前記半導体基板の一部であって、前記半導体基板が薄肉化されたダイヤフラム部と、第１，第２，第３，第４の検出部と、を備える半導体圧力センサにおいて、前記第１，第２，第３，第４の検出部はそれぞれ、第１の端と、第２の端と、前記第１の端から第１の方向に延びる第１の部分と、前記第１の部分から前記第１の方向と垂直な第２の方向に延びる第２の部分と、前記第２の部分から前記第１の方向に延び、前記第１の部分と前記第２の方向に対向する部分を有する第３の部分と、前記第３の部分から前記第２の方向に延び、前記第２の部分と前記第１の方向に対向する部分を有する第４の部分と、前記第４の部分から前記第２の端まで前記第１の方向に延び、前記第１の部分と前記第２の方向に対向する部分を含む第５の部分と、を有する。   The present invention relates to a semiconductor pressure comprising: a semiconductor substrate; a diaphragm portion which is a part of the semiconductor substrate and in which the semiconductor substrate is thinned; and first, second, third and fourth detection portions. In the sensor, each of the first, second, third, and fourth detection units includes a first end, a second end, and a first portion that extends in the first direction from the first end. , A second portion extending in a second direction perpendicular to the first direction from the first portion, and extending in the first direction from the second portion, the first portion and the second A third portion having a portion facing the first direction, a fourth portion extending from the third portion in the second direction, and having a portion facing the second portion and the first direction; , Extending from the fourth portion to the second end in the first direction and facing the first portion in the second direction Has a fifth portion which includes the minutes, the.

また、前記ダイヤフラム部の上面視において、前記第２の部分は前記第４の部分より幅の広い部分を有し、前記幅の広い部分は前記第１の部分に接続してもよい。   Further, in the top view of the diaphragm part, the second part may have a part wider than the fourth part, and the wide part may be connected to the first part.

また、前記第１の検出部の第１の端と、前記第２の検出部の第２の端とを接続する第１の配線と、前記第２の検出部の第１の端と、前記第３の検出部の第２の端とを接続する第２の配線と、前記第３の検出部の第１の端と、前記第４の検出部の第２の端とを接続する第３の配線と、前記第４の検出部の第１の端と、前記第１の検出部の第２の端とを接続する第４の配線と、を更に備え、前記ダイヤフラム部は、上面視において、第１，第２，第３，第４の辺を有する四角形であり、前記第１の配線は、前記第１の辺に並行な部分と、前記第２の辺に並行な部分とを有し、前記第２の配線は、前記第２の辺に並行な部分と、前記第３の辺に並行な部分とを有し、前記第３の配線は、前記第３の辺に並行な部分と、前記第４の辺に並行な部分とを有し、前記第４の配線は、前記第４の辺に並行な部分と、前記第１の辺に並行な部分とを有してもよい。   A first wiring connecting a first end of the first detection unit and a second end of the second detection unit; a first end of the second detection unit; A third wiring connecting the second wiring connecting the second end of the third detection unit, the first end of the third detection unit, and the second end of the fourth detection unit. And a fourth wiring that connects a first end of the fourth detection unit and a second end of the first detection unit, and the diaphragm unit is a top view. , A quadrilateral having first, second, third, and fourth sides, and the first wiring has a portion parallel to the first side and a portion parallel to the second side. The second wiring has a portion parallel to the second side and a portion parallel to the third side, and the third wiring is a portion parallel to the third side. And a portion parallel to the fourth side And the fourth wiring, and parallel portion to the fourth side may have a parallel portion to the first side.

また、前記半導体基板と前記ダイヤフラム部とは上面視において四角形であってもよい。   Further, the semiconductor substrate and the diaphragm portion may be quadrangular in a top view.

また、前記第１，第２，第３，第４の検出部はそれぞれ、前記ダイヤフラム部の上に設けられていてもよい。   Further, each of the first, second, third, and fourth detection units may be provided on the diaphragm unit.

また、前記第１，第２，第３，第４の検出部はピエゾ抵抗であってもよい。   The first, second, third, and fourth detection units may be piezoresistors.

また、前記第１，第２，第３，第４の検出部がホイートストンブリッジ回路を構成してもよい。   The first, second, third and fourth detection units may constitute a Wheatstone bridge circuit.

また、前記ダイヤフラム部は、上面視において、第１，第２，第３，第４の辺を有する四角形であり、前記第１の検出部は前記第１の辺の近傍に設けられ、前記第１の検出部の第１の部分は前記第１の辺と垂直に伸び、前記第１の検出部の第５の部分は前記第１の辺と垂直に伸び、前記第２の検出部は前記第２の辺の近傍に設けられ、前記第２の検出部の第１の部分は前記第１の辺と平行に伸び、前記第２の検出部の第５の部分は前記第１の辺と平行に伸び、前記第３の検出部は前記第３の辺の近傍に設けられ、前記第３の検出部の第１の部分は前記第１の辺と垂直に伸び、前記第３の検出部の第５の部分は前記第１の辺と垂直に伸び、前記第４の検出部は前記第４の辺の近傍に設けられ、前記第４の検出部の第１の部分は前記第１の辺と垂直に伸び、前記第４の検出部の第５の部分は前記第１の辺と垂直に伸びていてもよい。   The diaphragm portion is a quadrangle having first, second, third, and fourth sides in a top view, and the first detection unit is provided in the vicinity of the first side. The first part of the first detection unit extends perpendicular to the first side, the fifth part of the first detection unit extends perpendicular to the first side, and the second detection unit Provided in the vicinity of the second side, the first part of the second detection unit extends parallel to the first side, and the fifth part of the second detection unit is connected to the first side. Extending in parallel, the third detection unit is provided in the vicinity of the third side, the first part of the third detection unit extends perpendicular to the first side, and the third detection unit The fifth part extends perpendicularly to the first side, the fourth detection part is provided in the vicinity of the fourth side, and the first part of the fourth detection part is the first part. Side and droop Elongation, fifth portion of the fourth detector may extend perpendicular to the first side.

本発明によれば、検出精度が低下してしまうのを抑制することのできる半導体圧力センサを得ることができる。   ADVANTAGE OF THE INVENTION According to this invention, the semiconductor pressure sensor which can suppress that detection accuracy falls can be obtained.

本発明の実施形態１に係る半導体圧力センサの構成を示す図である。It is a figure which shows the structure of the semiconductor pressure sensor which concerns on Embodiment 1 of this invention. 半導体圧力センサのピエゾ抵抗素子が形成された部分の構成を示す図である。It is a figure which shows the structure of the part in which the piezoresistive element of the semiconductor pressure sensor was formed. ピエゾ抵抗素子で構成されたホイートストンブリッジ回路の構成を示す図である。It is a figure which shows the structure of the Wheatstone bridge circuit comprised by the piezoresistive element. 本発明の実施形態２に係る半導体圧力センサにおけるホイートストンブリッジ回路の構成を示す図である。It is a figure which shows the structure of the Wheatstone bridge circuit in the semiconductor pressure sensor which concerns on Embodiment 2 of this invention. 本発明の実施形態３に係る半導体圧力センサにおけるホイートストンブリッジ回路の構成を示す図である。It is a figure which shows the structure of the Wheatstone bridge circuit in the semiconductor pressure sensor which concerns on Embodiment 3 of this invention.

以下、図面を用いて本発明を実施するための実施形態を説明する。
（実施形態１）
図１は本発明の実施形態１に係る半導体圧力センサの構成を示す図であり、同図（ａ）は平面図、同図（ｂ）は同図（ａ）のＡ−Ａ線に沿った断面図である。図１において、本発明の実施形態１となる半導体圧力センサ１１は、図１（ａ），（ｂ）に示すように、矩形形状の薄肉化されたダイヤフラム部１２が形成された、例えば単結晶のシリコン基板からなる半導体基板１３と、ダイヤフラム部１２の各辺内側の半導体基板１３の表面領域に形成されたピエゾ抵抗素子Ｒ１〜Ｒ４とを備える。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
(Embodiment 1)
1A and 1B are diagrams showing a configuration of a semiconductor pressure sensor according to Embodiment 1 of the present invention, where FIG. 1A is a plan view, and FIG. 1B is taken along line AA in FIG. It is sectional drawing. In FIG. 1, a semiconductor pressure sensor 11 according to Embodiment 1 of the present invention includes, for example, a single crystal in which a thin diaphragm portion 12 having a rectangular shape is formed, as shown in FIGS. 1 (a) and 1 (b). And a piezoresistive element R <b> 1 to R <b> 4 formed in the surface region of the semiconductor substrate 13 inside each side of the diaphragm portion 12.

ピエゾ抵抗素子Ｒ１とピエゾ抵抗素子Ｒ２のそれぞれの一端は、例えば拡散配線を介して接続され、接続点は後述するホイートストンブリッジ回路の出力端子Ｖｏｕｔ１に接続されている。ピエゾ抵抗素子Ｒ１の他端は、ホイートストンブリッジ回路に印加するバイアス電圧を供給する高位電源Ｖｄｄに接続されている。ピエゾ抵抗素子Ｒ２の他端は、低位電源となる接地電位（グランド電位）ＧＮＤに接続されている。   One end of each of the piezoresistive element R1 and the piezoresistive element R2 is connected through, for example, a diffusion wiring, and the connection point is connected to an output terminal Vout1 of a Wheatstone bridge circuit described later. The other end of the piezoresistive element R1 is connected to a high level power supply Vdd that supplies a bias voltage to be applied to the Wheatstone bridge circuit. The other end of the piezoresistive element R2 is connected to a ground potential (ground potential) GND serving as a low potential power source.

ピエゾ抵抗素子Ｒ３とピエゾ抵抗素子Ｒ４のそれぞれの一端は、例えば拡散配線を介して接続され、接続点は後述するホイートストンブリッジ回路の出力端子Ｖｏｕｔ２に接続されている。ピエゾ抵抗素子Ｒ３の他端は、高位電源Ｖｄｄに接続されている。ピエゾ抵抗素子Ｒ４の他端は、接地電位ＧＮＤに接続されている。   One end of each of the piezoresistive element R3 and the piezoresistive element R4 is connected through, for example, a diffusion wiring, and the connection point is connected to an output terminal Vout2 of a Wheatstone bridge circuit described later. The other end of the piezoresistive element R3 is connected to the high level power supply Vdd. The other end of the piezoresistive element R4 is connected to the ground potential GND.

図２（ａ）は各ピエゾ抵抗素子Ｒ１〜Ｒ４が形成された部分（図１（ａ）の符号ａで示す部分）を拡大した平面図であり、同図（ｂ）は同図（ａ）のＢ−Ｂ線に沿った断面図である。図２において、ダイヤフラム部１２の半導体基板１３には、その表層部に例えば不純物を低濃度に選択的に拡散させて各ピエゾ抵抗素子Ｒ１〜Ｒ４が形成されている。各ピエゾ抵抗素子Ｒ１〜Ｒ４の上部には、例えば酸化膜などの絶縁体薄膜層２１を介してそれぞれ独立して個別に導電性のシールド薄膜層２２が形成されている。このシールド薄膜層２２は、絶縁体薄膜層２１によって各ピエゾ抵抗素子Ｒ１〜Ｒ４と絶縁されている。シールド薄膜層２２は、ダイヤフラム部１２と線膨張係数が近い例えば多結晶シリコンなどで構成される。   FIG. 2A is an enlarged plan view of a portion where each of the piezoresistive elements R1 to R4 is formed (portion indicated by reference numeral a in FIG. 1A), and FIG. It is sectional drawing along line BB. In FIG. 2, the semiconductor substrate 13 of the diaphragm portion 12 is formed with respective piezoresistive elements R1 to R4 in the surface layer portion by selectively diffusing impurities, for example, at a low concentration. On each of the piezoresistive elements R <b> 1 to R <b> 4, a conductive shield thin film layer 22 is independently formed via an insulating thin film layer 21 such as an oxide film. The shield thin film layer 22 is insulated from the piezoresistive elements R1 to R4 by the insulator thin film layer 21. The shield thin film layer 22 is made of, for example, polycrystalline silicon having a linear expansion coefficient close to that of the diaphragm portion 12.

各ピエゾ抵抗素子Ｒ１〜Ｒ４に対応した各シールド薄膜層２２は、予め設定した所定の電位、例えば高位電源Ｖｄｄや高位電源Ｖｄｄと接地電位ＧＮＤとの間の中間電位を与えることで、電気シールドとして機能する。   Each shield thin film layer 22 corresponding to each of the piezoresistive elements R1 to R4 provides a predetermined potential, for example, a high potential power supply Vdd or an intermediate potential between the high potential power supply Vdd and the ground potential GND as an electric shield. Function.

このような構成を有する半導体圧力センサ１１では、ピエゾ抵抗素子Ｒ１〜Ｒ４は図３に示すようなホイートストンブリッジ回路を構成している。ピエゾ抵抗素子Ｒ１は、その一端が高位電源Ｖｄｄに接続され、他端がホイートストンブリッジ回路の出力端子Ｖｏｕｔ１に接続されている。ピエゾ抵抗素子Ｒ２は、その一端が接地電位ＧＮＤに接続され、他端がホイートストンブリッジ回路の出力端子Ｖｏｕｔ１に接続されている。ピエゾ抵抗素子Ｒ３は、その一端が高位電源Ｖｄｄに接続され、他端がホイートストンブリッジ回路の出力端子Ｖｏｕｔ２に接続されている。ピエゾ抵抗素子Ｒ４は、その一端が接地電位ＧＮＤに接続され、他端がホイートストンブリッジ回路の出力端子Ｖｏｕｔ２に接続されている。   In the semiconductor pressure sensor 11 having such a configuration, the piezoresistive elements R1 to R4 form a Wheatstone bridge circuit as shown in FIG. One end of the piezoresistive element R1 is connected to the high level power supply Vdd, and the other end is connected to the output terminal Vout1 of the Wheatstone bridge circuit. One end of the piezoresistive element R2 is connected to the ground potential GND, and the other end is connected to the output terminal Vout1 of the Wheatstone bridge circuit. One end of the piezoresistive element R3 is connected to the high-level power supply Vdd, and the other end is connected to the output terminal Vout2 of the Wheatstone bridge circuit. The piezoresistive element R4 has one end connected to the ground potential GND and the other end connected to the output terminal Vout2 of the Wheatstone bridge circuit.

また、ピエゾ抵抗素子Ｒ１上に形成されたシールド薄膜層２２と、ピエゾ抵抗素子Ｒ３上に形成されたシールド薄膜層２２とは、拡散層もしくは金属などで構成された配線３１により電気的に接続され、両者を予め設定した同一の電位に固定することが可能に構成されている。ピエゾ抵抗素子Ｒ２上に形成されたシールド薄膜層２２と、ピエゾ抵抗素子Ｒ４上に形成されたシールド薄膜層２２とは、拡散層もしくは金属などで構成された配線３２により電気的に接続され、両者を予め設定した同一の電位に固定することが可能に構成されている。したがって、高位電源Ｖｄｄ側に接続されたピエゾ抵抗素子Ｒ１，Ｒ３上に形成されたシールド薄膜層２２に与えられる電位と、接地電位ＧＮＤ側に接続されたピエゾ抵抗素子Ｒ２，Ｒ４上に形成されたシールド薄膜層２２に与えられる電位とが、異なる電位に設定できるように構成されている。なお、シールド薄膜層２２に与える電位は、ピエゾ抵抗素子Ｒ１〜Ｒ４が受ける電気的な影響の度合いが概ね同程度になるように実機による実験などによって定めることができる。   The shield thin film layer 22 formed on the piezoresistive element R1 and the shield thin film layer 22 formed on the piezoresistive element R3 are electrically connected by a wiring 31 made of a diffusion layer or metal. Both can be fixed at the same potential set in advance. The shield thin film layer 22 formed on the piezoresistive element R2 and the shield thin film layer 22 formed on the piezoresistive element R4 are electrically connected by a wiring 32 made of a diffusion layer or metal, etc. Can be fixed at the same potential set in advance. Therefore, the potential applied to the shield thin film layer 22 formed on the piezoresistive elements R1 and R3 connected to the high potential power supply Vdd side and the piezoresistive elements R2 and R4 connected to the ground potential GND side are formed. The potential applied to the shield thin film layer 22 can be set to a different potential. Note that the potential applied to the shield thin film layer 22 can be determined by an experiment using an actual machine so that the degree of electrical influence received by the piezoresistive elements R1 to R4 is approximately the same.

このような構成を有する半導体圧力センサ１１では、ダイヤフラム部１２の一方の表面に圧力が加わると、ダイヤフラム部１２の上面と下面との間に差圧が生じることによってダイヤフラム部１２に撓みが生じ、この撓みによってピエゾ抵抗素子Ｒ１〜Ｒ４を形成する結晶が歪んで抵抗値が変化する。そして、ピエゾ抵抗素子Ｒ１〜Ｒ４の抵抗値の変化をホイートストンブリッジ回路を利用して高位電源Ｖｄｄに対する電圧変化として出力端子Ｖｏｕｔ１，Ｖｏｕｔ２から検出する。これにより、半導体圧力センサ１１に印加された圧力を電気信号に変換して取り出し、取り出した電気信号に基づいて圧力を検出する。   In the semiconductor pressure sensor 11 having such a configuration, when pressure is applied to one surface of the diaphragm portion 12, a differential pressure is generated between the upper surface and the lower surface of the diaphragm portion 12, thereby causing the diaphragm portion 12 to bend, Due to this bending, the crystals forming the piezoresistive elements R1 to R4 are distorted and the resistance value changes. And the change of the resistance value of piezoresistive element R1-R4 is detected from output terminal Vout1, Vout2 as a voltage change with respect to high level power supply Vdd using a Wheatstone bridge circuit. Thereby, the pressure applied to the semiconductor pressure sensor 11 is converted into an electric signal and taken out, and the pressure is detected based on the taken out electric signal.

このように、上記実施形態１では、高位電源Ｖｄｄ側に接続されたピエゾ抵抗素子Ｒ１，Ｒ３上に形成されたシールド薄膜層２２に与えられる電位と、接地電位ＧＮＤ側に接続されたピエゾ抵抗素子Ｒ２，Ｒ４上に形成されたシールド薄膜層２２に与えられる電位とを、異なる電位に設定することが可能である。これにより、それぞれの電位を適切に設定することが可能となり、各ピエゾ抵抗素子Ｒ１〜Ｒ４は、対応したシールド薄膜層２２から受ける電気的な影響の度合いを概ね同程度にすることが可能となる。この結果、ホイートストンブリッジ回路のオフセット電圧、ならびにオフセットドリフトを改善することができる。
（実施形態２）
図４は本発明の実施形態２に係る半導体圧力センサの構成を示す図であり、先の実施形態１の図３に対応した図である。なお、各ピエゾ抵抗素子Ｒ１〜Ｒ４の構造や配置は先の実施形態１の図１、図２と同様であるので、その説明は省略する。 As described above, in the first embodiment, the potential applied to the shield thin film layer 22 formed on the piezoresistive elements R1 and R3 connected to the high power supply Vdd side and the piezoresistive element connected to the ground potential GND side. The potential applied to the shield thin film layer 22 formed on R2 and R4 can be set to a different potential. Thereby, it becomes possible to set each electric potential appropriately, and it becomes possible for each piezoresistive element R1-R4 to make the degree of the electrical influence received from the corresponding shield thin film layer 22 substantially the same. . As a result, the offset voltage and offset drift of the Wheatstone bridge circuit can be improved.
(Embodiment 2)
FIG. 4 is a diagram showing the configuration of the semiconductor pressure sensor according to the second embodiment of the present invention, and corresponds to FIG. 3 of the first embodiment. The structure and arrangement of the piezoresistive elements R1 to R4 are the same as those shown in FIGS.

この実施形態２の特徴とするところは、先の実施形態１と対比して、高位電源Ｖｄｄ側に接続されたピエゾ抵抗素子Ｒ１，Ｒ３上に形成された各シールド薄膜層２２を高位電源Ｖｄｄに共通接続し、接地電位ＧＮＤ側に接続されたピエゾ抵抗素子Ｒ２，Ｒ４上に形成された各シールド薄膜層２２を出力端子Ｖｏｕｔ１に共通接続したことにある。   The feature of the second embodiment is that, in contrast to the first embodiment, each shield thin film layer 22 formed on the piezoresistive elements R1 and R3 connected to the higher power supply Vdd side is used as the higher power supply Vdd. Each shield thin film layer 22 formed on the piezoresistive elements R2 and R4 connected in common and connected to the ground potential GND side is commonly connected to the output terminal Vout1.

このような特徴を備えたことで、この実施形態２では、高位電源Ｖｄｄ側に接続されたピエゾ抵抗素子Ｒ１，Ｒ３上に形成された各シールド薄膜層２２に高位電源電位を与えて両者を同一電位に固定することができる。かつ、接地電位ＧＮＤ側に接続されたピエゾ抵抗素子Ｒ２，Ｒ４上に形成された各シールド薄膜層２２に出力端子Ｖｏｕｔ１に出力される電位、すなわち高位電源Ｖｄｄと接地電位ＧＮＤとの間の中間電位を与えて、両者を同一電位に固定することができる。これにより、各ピエゾ抵抗素子Ｒ１〜Ｒ４は、対応したシールド薄膜層２２から受ける電気的な影響の度合いを概ね同程度にすることが可能となる。この結果、ホイートストンブリッジ回路のオフセット電圧、ならびにオフセットドリフトを改善することができる。
（実施形態３）
図５は本発明の実施形態３に係る半導体圧力センサの構成を示す図であり、先の実施形態１の図３に対応した図である。なお、各ピエゾ抵抗素子Ｒ１〜Ｒ４の構造や配置は先の実施形態１の図１、図２と同様であるので、その説明は省略する。 With this feature, in the second embodiment, a high power supply potential is applied to each shield thin film layer 22 formed on the piezoresistive elements R1 and R3 connected to the high power supply Vdd side so that they are the same. The potential can be fixed. In addition, the potential output to the output terminal Vout1 on each shield thin film layer 22 formed on the piezoresistive elements R2 and R4 connected to the ground potential GND side, that is, the intermediate potential between the high potential power supply Vdd and the ground potential GND. Can be fixed at the same potential. As a result, each of the piezoresistive elements R1 to R4 can have substantially the same degree of electrical influence received from the corresponding shield thin film layer 22. As a result, the offset voltage and offset drift of the Wheatstone bridge circuit can be improved.
(Embodiment 3)
FIG. 5 is a diagram showing a configuration of a semiconductor pressure sensor according to the third embodiment of the present invention, and corresponds to FIG. 3 of the first embodiment. The structure and arrangement of the piezoresistive elements R1 to R4 are the same as those shown in FIGS.

この実施形態３の特徴とするところは、先の実施形態２と対比して、出力端子Ｖｏｕｔ１で得られる中間電位に代えて、抵抗ｒ１，ｒ２によって得られる中間電位を接地電位ＧＮＤ側に接続されたピエゾ抵抗素子Ｒ２，Ｒ４上に形成された各シールド薄膜層２２に与えたことにある。なお、高位電源Ｖｄｄ側に接続されたピエゾ抵抗素子Ｒ１，Ｒ３上に形成された各シールド薄膜層２２は、先の実施形態２と同様に高位電源Ｖｄｄに接続されて、高位電源電位が与えられている。   In contrast to the second embodiment, the third embodiment is characterized in that the intermediate potential obtained by the resistors r1 and r2 is connected to the ground potential GND side instead of the intermediate potential obtained at the output terminal Vout1. In other words, the shield thin film layers 22 formed on the piezoresistive elements R2 and R4 are provided. Each shield thin film layer 22 formed on the piezoresistive elements R1 and R3 connected to the high-level power supply Vdd side is connected to the high-level power supply Vdd and given a high-level power supply potential as in the second embodiment. ing.

抵抗ｒ１と抵抗ｒ２とは、高位電源Ｖｄｄと接地電位ＧＮＤとの間で直列接続され、その直列接続点Ｓ１は、接地電位ＧＮＤ側に接続されたピエゾ抵抗素子Ｒ２，Ｒ４上に形成されたシールド薄膜層２２に接続されている。抵抗ｒ１、ｒ２の抵抗値は、それぞれ個別に独立して設定され、直列接続点Ｓ１で得られる電位は、高位電源Ｖｄｄと接地電位ＧＮＤとの間の任意の中間電位に設定される。この中間電位は、ピエゾ抵抗素子Ｒ１〜Ｒ４が受ける電気的な影響の度合いが概ね同程度になるように実機による実験などによって定めることができる。   The resistors r1 and r2 are connected in series between the high-level power supply Vdd and the ground potential GND, and the series connection point S1 is a shield formed on the piezoresistive elements R2 and R4 connected to the ground potential GND side. Connected to the thin film layer 22. The resistance values of the resistors r1 and r2 are individually set independently, and the potential obtained at the series connection point S1 is set to an arbitrary intermediate potential between the high-level power supply Vdd and the ground potential GND. This intermediate potential can be determined by an experiment using an actual machine so that the degree of electrical influence received by the piezoresistive elements R1 to R4 is approximately the same.

このような特徴を備えたことで、この実施形態３では、高位電源Ｖｄｄ側に接続されたピエゾ抵抗素子Ｒ１，Ｒ３上に形成された各シールド薄膜層２２に高位電源電位を与えて両者を同一電位に固定することができる。かつ、接地電位ＧＮＤ側に接続されたピエゾ抵抗素子Ｒ２，Ｒ４上に形成された各シールド薄膜層２２に、高位電源Ｖｄｄと接地電位ＧＮＤとの間の中間電位を与えて、両者を同一電位に固定することができる。これにより、各ピエゾ抵抗素子Ｒ１〜Ｒ４は、対応したシールド薄膜層２２から受ける電気的な影響の度合いを概ね同程度にすることが可能となる。この結果、ホイートストンブリッジ回路のオフセット電圧、ならびにオフセットドリフトを改善することができる。   With this feature, in the third embodiment, a high power supply potential is applied to each shield thin film layer 22 formed on the piezoresistive elements R1 and R3 connected to the high power supply Vdd side so that they are the same. The potential can be fixed. In addition, an intermediate potential between the high-level power supply Vdd and the ground potential GND is applied to each shield thin film layer 22 formed on the piezoresistive elements R2 and R4 connected to the ground potential GND side, so that both are made the same potential. Can be fixed. As a result, each of the piezoresistive elements R1 to R4 can have substantially the same degree of electrical influence received from the corresponding shield thin film layer 22. As a result, the offset voltage and offset drift of the Wheatstone bridge circuit can be improved.

１１…半導体圧力センサ
１２…ダイヤフラム部
１３…半導体基板
２１…絶縁体薄膜層
２２…シールド薄膜層
３１，３２…配線
Ｒ１〜Ｒ４…ピエゾ抵抗素子
ｒ１，ｒ２…抵抗 DESCRIPTION OF SYMBOLS 11 ... Semiconductor pressure sensor 12 ... Diaphragm part 13 ... Semiconductor substrate 21 ... Insulator thin film layer 22 ... Shield thin film layer 31, 32 ... Wiring R1-R4 ... Piezoresistive element r1, r2 ... Resistance

Claims (8)

半導体基板と、
前記半導体基板の一部であって、前記半導体基板が薄肉化されたダイヤフラム部と、
第１，第２，第３，第４の検出部と、
を備える半導体圧力センサにおいて、
前記第１，第２，第３，第４の検出部はそれぞれ、
第１の端と、
第２の端と、
前記第１の端から第１の方向に延びる第１の部分と、
前記第１の部分から前記第１の方向と垂直な第２の方向に延びる第２の部分と、
前記第２の部分から前記第１の方向に延び、前記第１の部分と前記第２の方向に対向する部分を有する第３の部分と、
前記第３の部分から前記第２の方向に延び、前記第２の部分と前記第１の方向に対向する部分を有する第４の部分と、
前記第４の部分から前記第２の端まで前記第１の方向に延び、前記第１の部分と前記第２の方向に対向する部分を含む第５の部分と、
を有する半導体圧力センサ。 A semiconductor substrate;
A part of the semiconductor substrate, wherein the semiconductor substrate is thinned; and
First, second, third and fourth detectors;
In a semiconductor pressure sensor comprising:
The first, second, third and fourth detection units are respectively
A first end;
A second end;
A first portion extending in a first direction from the first end;
A second portion extending from the first portion in a second direction perpendicular to the first direction;
A third portion extending from the second portion in the first direction and having a portion facing the first portion and the second direction;
A fourth portion having a portion extending from the third portion in the second direction and facing the second portion in the first direction;
A fifth portion including a portion extending from the fourth portion to the second end in the first direction and facing the first portion in the second direction;
A semiconductor pressure sensor. 前記ダイヤフラム部の上面視において、前記第２の部分は前記第４の部分より幅の広い部分を有し、
前記幅の広い部分は前記第１の部分に接続する請求項１に記載の半導体圧力センサ。 In the top view of the diaphragm portion, the second portion has a portion wider than the fourth portion,
The semiconductor pressure sensor according to claim 1, wherein the wide portion is connected to the first portion. 前記第１の検出部の第１の端と、前記第２の検出部の第２の端とを接続する第１の配線と、
前記第２の検出部の第１の端と、前記第３の検出部の第２の端とを接続する第２の配線と、
前記第３の検出部の第１の端と、前記第４の検出部の第２の端とを接続する第３の配線と、
前記第４の検出部の第１の端と、前記第１の検出部の第２の端とを接続する第４の配線と、を更に備え、
前記ダイヤフラム部は、上面視において、第１，第２，第３，第４の辺を有する四角形であり、
前記第１の配線は、前記第１の辺に並行な部分と、前記第２の辺に並行な部分とを有し、
前記第２の配線は、前記第２の辺に並行な部分と、前記第３の辺に並行な部分とを有し、
前記第３の配線は、前記第３の辺に並行な部分と、前記第４の辺に並行な部分とを有し、
前記第４の配線は、前記第４の辺に並行な部分と、前記第１の辺に並行な部分とを有する請求項１または請求項２に記載の半導体圧力センサ。 A first wiring connecting a first end of the first detection unit and a second end of the second detection unit;
A second wiring connecting the first end of the second detection unit and the second end of the third detection unit;
A third wiring connecting the first end of the third detection unit and the second end of the fourth detection unit;
A fourth wiring connecting the first end of the fourth detection unit and the second end of the first detection unit;
The diaphragm portion is a quadrangle having first, second, third, and fourth sides in a top view,
The first wiring has a portion parallel to the first side and a portion parallel to the second side,
The second wiring has a portion parallel to the second side and a portion parallel to the third side,
The third wiring has a portion parallel to the third side and a portion parallel to the fourth side,
3. The semiconductor pressure sensor according to claim 1, wherein the fourth wiring includes a portion parallel to the fourth side and a portion parallel to the first side. 前記半導体基板と前記ダイヤフラム部とは上面視において四角形である請求項１〜３のうちいずれか１項に記載の半導体圧力センサ。   The semiconductor pressure sensor according to claim 1, wherein the semiconductor substrate and the diaphragm portion are quadrangular in a top view. 前記第１，第２，第３，第４の検出部はそれぞれ、前記ダイヤフラム部の上に設けられる請求項１〜４のうちいずれか１項に記載の半導体圧力センサ。   5. The semiconductor pressure sensor according to claim 1, wherein each of the first, second, third, and fourth detection units is provided on the diaphragm unit. 前記第１，第２，第３，第４の検出部はピエゾ抵抗である請求項１〜５のうちいずれか１項に記載の半導体圧力センサ。   The semiconductor pressure sensor according to claim 1, wherein the first, second, third, and fourth detection units are piezoresistors. 前記第１，第２，第３，第４の検出部がホイートストンブリッジ回路を構成する請求項１〜６のうちいずれか１項に記載の半導体圧力センサ。   The semiconductor pressure sensor according to any one of claims 1 to 6, wherein the first, second, third, and fourth detection units constitute a Wheatstone bridge circuit. 前記ダイヤフラム部は、上面視において、第１，第２，第３，第４の辺を有する四角形であり、
前記第１の検出部は前記第１の辺の近傍に設けられ、
前記第１の検出部の第１の部分は前記第１の辺と垂直に延び、
前記第１の検出部の第５の部分は前記第１の辺と垂直に延び、
前記第２の検出部は前記第２の辺の近傍に設けられ、
前記第２の検出部の第１の部分は前記第１の辺と平行に延び、
前記第２の検出部の第５の部分は前記第１の辺と平行に延び、
前記第３の検出部は前記第３の辺の近傍に設けられ、
前記第３の検出部の第１の部分は前記第１の辺と垂直に延び、
前記第３の検出部の第５の部分は前記第１の辺と垂直に延び、
前記第４の検出部は前記第４の辺の近傍に設けられ、
前記第４の検出部の第１の部分は前記第１の辺と垂直に延び、
前記第４の検出部の第５の部分は前記第１の辺と垂直に延びる請求項１に記載の半導体圧力センサ。 The diaphragm portion is a quadrangle having first, second, third, and fourth sides in a top view,
The first detection unit is provided in the vicinity of the first side,
A first portion of the first detector extending perpendicular to the first side;
A fifth portion of the first detection unit extends perpendicular to the first side;
The second detection unit is provided in the vicinity of the second side,
A first portion of the second detector extending parallel to the first side;
A fifth portion of the second detection unit extending in parallel with the first side;
The third detection unit is provided in the vicinity of the third side,
A first portion of the third detector extending perpendicular to the first side;
A fifth portion of the third detection unit extends perpendicular to the first side;
The fourth detection unit is provided in the vicinity of the fourth side,
A first portion of the fourth detection unit extending perpendicular to the first side;
The semiconductor pressure sensor according to claim 1, wherein the fifth portion of the fourth detection unit extends perpendicularly to the first side.
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