JP2018021796A - Semiconductor strain gauge - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor strain gauge which can suppress changes and variations in the sensitivity or the offset of a bridge circuit.SOLUTION: A semiconductor strain gauge 1 includes: a first n-type well layer 11 and a second n-type well layer 21 formed on a p-type semiconductor substrate 2; a first p-type piezo-resistor 12 and a second p-type piezo-resistor 22 formed on the first well layer 11 and the second well layer 21, respectively; a first wire 31 connecting one terminal 12A of the first piezo-resistor 12 and the first well layer 11 together, the first wire being clamped to a predetermined first potential V1; a second wire 32 connecting the other terminal 12B of the first piezo-resistor 12 and one terminal 22A of the second piezo-resistor 22 together; a third wire 33 connected to the other terminal 22B of the second piezo-resistor 22, the third wire being clamped to a second potential V2; and a voltage source 40 for outputting, to the second well layer 21, a potential associated with the potential of the one terminal 22A of the second piezo-resistor 22.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor strain gauge having two piezoresistors connected in series.

  Conventionally, a sensor that converts pressure into an electric signal by using a piezoresistive effect of a semiconductor has been used. Examples of this type of sensor include those described in Patent Documents 1 and 2.

  The pressure sensor described in Patent Document 1 is configured using a gauge resistor (corresponding to “piezoresistor” in the present application) made of p-type silicon. In this pressure sensor, the pn junction is reverse-biased in order to isolate and isolate each of the plurality of gauge resistors formed on the p-type silicon substrate. On the other hand, in the pn junction, it is known that the leak current at the time of reverse bias is relatively large, and the output of the sensor drifts greatly due to this leak current. In the pressure sensor described in Patent Document 1, in order to reduce the leakage current and reduce the drift of the sensor output, an independent n-type well region corresponding to the piezoresistor is formed on the p-type substrate (in this application “well layer”). Equivalent), p-type piezoresistors are formed in each of the n-type well regions, and each piezoresistor is incorporated in a bridge circuit. At this time, each n-type well region is electrically connected to the high potential side of the p-type piezoresistor formed in the region, and is fixed at that potential.

  The self-detecting SPM probe described in Patent Document 2 includes a cantilever using a piezoresistor made of p-type silicon. This self-sensing SPM probe eliminates the influence of leakage current between piezoresistors and carriers generated by light irradiation, so that the amount of bending of the cantilever can be detected properly. An element diffusion layer is formed by forming an impurity diffusion layer having a conductivity type (ie, “p-type”) of the silicon substrate and a conductivity type (ie, “n-type”) different from the conductivity type on the surface in contact with the substrate. It is carried out.

JP-A-6-207871 Japanese Patent Laid-Open No. 11-211736

In the technique described in Patent Document 1, when forming an n-type well region on a p-type silicon substrate, a group V element is implanted as an impurity into the p-type silicon substrate. In contrast, the impurity concentration of the n-type well region is increased. Similarly, the impurity concentration of the p-type gauge resistor formed by impurity diffusion in the n-type well region is higher than the impurity concentration of the n-type well region. On the other hand, the impurity concentration of the p-type gauge resistor is often designed to be as low as 2 × 10 ¹⁸ / cm ³ with good temperature characteristics of sensitivity (Kazuji Yamada et al. “Piezoresistance effect in P-type silicon diffusion layer”). Temperature characteristics of the Institute of Electrical Engineers of Japan A 103, No. 10, p. 31). Further, the p-type silicon substrate is connected to a potential that is in a reverse bias state with respect to the n-type well region, and is normally at a ground level, and the high-potential side electrode of the gauge resistor and the n-type well region are positive. A potential is applied. As described above, when energized, the n-type well layer and the p-type silicon substrate are in a reverse bias state, and at the same time, a large depletion layer region is formed, via a hole-electron leak current and crystal defects caused by thermal excitation. Leakage current easily flows. When the output impedance of the wiring connected to the high potential side electrode is high, such as the piezo resistance on the low potential side in the bridge circuit by the piezo resistance, the leakage current is supplied from the wiring connected to the high potential side electrode of the piezo resistance. As a result, the current flowing through the piezoresistor fluctuates, causing the bridge circuit sensitivity, offset fluctuation, and variation.

  The technique described in Patent Document 2 applies a piezoresistor to detection of deformation of a cantilever, and the relationship between a p-type silicon substrate, a well region, and a piezoresistor is the relationship between an electrode on the high potential side of the piezoresistor and a well region. However, it is the same as the technique described in Patent Document 1 except that it is not directly connected by metal wiring. Therefore, a forward current flows through the n-type well region via the pn junction between the well region and the piezoresistor. However, when the potential of the n-type well region becomes sufficiently high, the forward current stops flowing, An insulation state is established with the piezoresistor. However, similar to the technique described in Patent Document 1, the pn junction between the p-type silicon substrate and the well region is in a reverse bias state, and the depletion layer expands, so that the leakage current tends to increase. As a result, the current flowing from the well region to the silicon substrate flows from the high potential side of the p-type piezoresistor to the well region via the pn junction, and the output impedance of the wiring connected to the high potential side electrode of the piezoresistor is If it is high, the sensitivity of the bridge circuit, the fluctuation of the offset, and the variation are generated similarly to the problem with the technique described in Patent Document 1.

  Therefore, a semiconductor strain gauge that can suppress the fluctuation of the sensitivity and offset of the bridge circuit and the occurrence of variations is required.

  A characteristic configuration of a semiconductor strain gauge according to the present invention includes a first well layer formed on a first conductivity type semiconductor substrate having a second conductivity type different from the first conductivity type, and the semiconductor substrate including the first well layer. A second well layer spaced apart from the first well layer and having the second conductivity type; a first piezoresistor formed in the first well layer having the first conductivity type; A second piezoresistor formed on the second well layer having the first conductivity type, and electrically connecting one terminal of the first piezoresistor and the first well layer; A first wiring that is clamped at one potential; a second wiring that electrically connects the other terminal of the first piezoresistor and one terminal of the second piezoresistor; and the other of the second piezoresistor. A third wiring connected to the terminal and clamped at a second potential different from the first potential; A pn junction formed by the well layer and the second piezoresistor and a pn junction formed by the second well layer and the semiconductor substrate are in at least one of the same potential state and the reverse bias state. And a voltage source that outputs a potential linked to the potential of one terminal of the second piezoresistor to the second well layer.

  The semiconductor strain gauge is highly sensitive, and it is possible to reduce the size of the gauge and the object or sensor to which the semiconductor strain gauge is bonded. Moreover, since a plurality of piezoresistors that are gauge resistors can be formed on the same chip in the same process, the relative positional accuracy is high and the relative accuracy specific to the gauge can be increased. However, the p-type piezoresistor is formed in the n-type well region to electrically isolate the piezoresistors, the high-potential side electrode of the piezoresistor and the well region are electrically connected, and the p-type semiconductor substrate is grounded. The pn junction is used in a reverse bias state by setting the potential lower than that of the well region. For this reason, the output impedance of the wiring connected to the high-potential side electrode of the piezoresistor is high, the leakage current between the well region and the semiconductor substrate increases, and if the current drop through the piezoresistor cannot be ignored, the sensitivity fluctuations cause. Furthermore, offset due to variations in leakage current occurs, and the temperature characteristics of the leakage current cause deterioration of the temperature characteristics of the gauge characteristics.

  Therefore, in a semiconductor strain gauge comprising a first well layer and a second well layer formed on a semiconductor substrate so as to be separated from each other, and a first piezoresistor and a second piezoresistor formed in each well layer, The voltage source is at least one of a pn junction formed by the second well layer and the second piezoresistor and a pn junction formed by the second well layer and the semiconductor substrate in the same potential state and the reverse bias state. By outputting a potential linked to the potential of one terminal of the second piezoresistor to the second well layer, insulation between the second well layer and the second piezoresistor is possible, and Since the influence of the leakage current between the second well layer and the semiconductor substrate on the amount of current flowing through the second piezoresistor can be suppressed, a semiconductor strain gauge with little sensitivity and offset variation can be realized. Note that the potential difference between the second well layer and the second piezoresistor is sufficiently smaller than the threshold voltage in the forward direction of the pn junction formed between the second well layer and the second piezoresistor, for example, the threshold voltage. The leakage current between the second well layer and the second piezoresistor can be reduced so that the reverse bias state is not necessarily required between the second piezoresistor and the second well layer.

  The voltage source is preferably a buffer that outputs the same potential as the potential of one terminal of the second piezoresistor.

  By setting the voltage source as a buffer (voltage buffer circuit), the potential of the upstream electrode in the flow of carriers in the second piezoresistor and the second well layer can be set to substantially the same potential, so the second well layer and the semiconductor substrate The influence of the leakage current between the second piezoresistor and the current flowing through the second piezoresistor can be suppressed, and the spread of the depletion layer between the second well layer and the second piezoresistance can be suppressed. As a result, since the leakage current between the second well region and the piezoresistor can be reduced, the influence of the leakage current on the current flowing through the second piezoresistor can be suppressed, and a semiconductor strain gauge with less sensitivity and offset variation can be realized. .

  The first conductivity type is p-type, the second conductivity type is n-type, the potential of the first piezoresistor and the second piezoresistor is equal to or higher than the potential of the semiconductor substrate, and the voltage source Is composed of a p-type MOS-FET and a resistor, and the resistor has one terminal clamped at a potential higher than the potential of one terminal of the second piezoresistor, and the other terminal The p-type MOS-FET is connected to the source terminal of the p-type MOS-FET and the second well layer, and the p-type MOS-FET has a drain terminal clamped at a potential lower than the potential of one terminal of the second piezoresistor. It is preferable that the terminal is connected to one terminal of the second piezoresistor.

  A voltage source whose output is connected to the second well layer when the first piezoresistor, the second piezoresistor, and the semiconductor substrate are p-type semiconductors and the first well layer and the second well layer are n-type semiconductors, The source follower is composed of a resistor and a p-type MOS-FET, the source terminal of the p-type MOS-FET is connected to the second well layer, and the gate terminal of the p-type MOS-FET is the high potential side electrode of the second piezoresistor. Connected to. Accordingly, the second well layer is held at a potential higher than the threshold voltage of the p-type MOS-FET with respect to the high potential side electrode of the second piezoresistor, and a pn junction between the second well layer and the semiconductor substrate, and Since the pn junction between the second well layer and the second piezoresistor is in a reverse bias state, element isolation of the second piezoresistor becomes possible, and at the same time, leakage current between the second well layer and the semiconductor substrate is reduced. The influence on the current flowing through the piezoresistor can be suppressed. Therefore, a semiconductor strain gauge with little sensitivity and offset fluctuation can be realized.

  Further, the first conductivity type is n-type, the second conductivity type is p-type, the potential of the first piezoresistor and the second piezoresistor is equal to or lower than the potential of the semiconductor substrate, and the voltage source Is composed of an n-type MOS-FET and a resistor, and the resistor has one terminal clamped at a potential higher than the potential of one terminal of the second piezoresistor, and the other terminal The n-type MOS-FET is connected to the source terminal of the n-type MOS-FET and the second well layer, and the n-type MOS-FET has a drain terminal clamped at a potential lower than the potential of one terminal of the second piezoresistor, It is preferable that the terminal is connected to one terminal of the second piezoresistor.

  When the first piezoresistor, the second piezoresistor, and the semiconductor substrate are n-type semiconductors and the first well layer and the second well layer are p-type semiconductors, the voltage source whose output is connected to the second well layer is The buffer circuit is composed of a resistor and an n-type MOS-FET, the source terminal of the n-type MOS-FET is connected to the second well layer, and the gate terminal of the n-type MOS-FET is the low potential side electrode of the second piezoresistor. Connected to. Thus, the second well layer is held at a potential lower than the threshold voltage of the n-type MOS-FET with respect to the low potential side electrode of the second piezoresistor, and a pn junction between the second well layer and the semiconductor substrate, and Since the pn junction between the second well layer and the second piezoresistor is in a reverse bias state, element isolation of the second piezoresistor becomes possible, and at the same time, leakage current between the second well layer and the semiconductor substrate is reduced. The influence on the current flowing through the piezoresistor can be suppressed. Therefore, a semiconductor strain gauge with little sensitivity and offset fluctuation can be realized.

It is the figure which showed typically the circuit structure of the half bridge by the semiconductor strain gauge which concerns on 1st Embodiment. It is the figure which showed typically the circuit structure of the half bridge by the semiconductor strain gauge which concerns on 2nd Embodiment. It is the figure which showed typically the circuit structure of the half bridge by the semiconductor strain gauge which concerns on 3rd Embodiment.

  The semiconductor strain gauge according to the present invention is configured to suppress the fluctuation of the sensitivity and offset of the bridge circuit and the occurrence of variations. Hereinafter, embodiments of a semiconductor strain gauge will be described with reference to the drawings.

1. First Embodiment FIG. 1 is a diagram schematically showing a circuit configuration of a half bridge by a semiconductor strain gauge 1 according to a first embodiment. As shown in FIG. 1, the semiconductor strain gauge 1 includes a first well layer 11, a first piezoresistor 12, a second well layer 21, a second piezoresistor 22, a first wiring 31, a second wiring 32, a third The wiring 33 and the voltage source 40 are provided.

  The first well layer 11 is formed on the first conductivity type semiconductor substrate 2 having a second conductivity type different from the first conductivity type. The semiconductor strain gauge 1 of this embodiment is configured using a p-type semiconductor substrate 2. Therefore, in this embodiment, the “first conductivity type” corresponds to the p-type, and the “second conductivity type different from the first conductivity type” corresponds to the n-type. Therefore, the first well layer 11 is formed on the p-type semiconductor substrate 2 so as to have an n-type. In the present embodiment, the p-type semiconductor substrate 2 is grounded (shown as a potential V3 in FIG. 1).

  The second well layer 21 is formed on the semiconductor substrate 2 so as to be separated from the first well layer 11 and to have the second conductivity type. The semiconductor substrate 2 is a p-type semiconductor substrate. “Separate from the first well layer 11” means a portion at least between the first well layer 11 and the second well layer 21 that is different from both the first well layer 11 and the second well layer 21 (this embodiment). Is equivalent to “semiconductor substrate 2”, and the first well layer 11 and the second well layer 21 are formed independently of each other. The second well layer 21 is formed to have the same n-type as the first well layer 11.

  The first piezoresistor 12 is formed in the first well layer 11 having the first conductivity type. The second piezoresistor 22 is formed in the second well layer 21 having the first conductivity type. As described above, the “first conductivity type” is p-type. The first well layer 11 and the second well layer 21 are each formed to have an n-type. Therefore, the first piezoresistor 12 is formed with the p-type in the n-type first well layer 11, and the second piezoresistor 22 is formed with the p-type in the n-type second well layer 21. .

  The first wiring 31 electrically connects one terminal 12A of the first piezoresistor 12 and the first well layer 11, and is clamped to a predetermined first potential V1. In the present embodiment, “one terminal 12 </ b> A of the first piezoresistor 12” is an electrode to which a positive power supply is connected when the semiconductor strain gauge 1 constitutes a half-bridge circuit. The positive power supply is a power supply that outputs a voltage higher than 0 V, and outputs a predetermined potential V1 in this embodiment. Since the first wiring 31 is connected to both the one terminal 12A of the first piezoresistor 12 and the first well layer 11, the one terminal 12A of the first piezoresistor 12 and the first well layer 11 are predetermined. The potential V1 is applied. Note that the connection between the first wiring 31 and the first well layer 11 is on the one terminal 12A side (preferably in the vicinity of the one terminal 12A) with respect to the other terminal 12B of the first piezoresistor 12 in the first well layer 11. ).

  The second wiring 32 electrically connects the other terminal 12 </ b> B of the first piezoresistor 12 and one terminal 22 </ b> A of the second piezoresistor 22. “The other terminal 12B of the first piezoresistor 12” is a terminal from which a current flows out from the first piezoresistor 12 to which a predetermined potential V1 is applied to the terminal 12A, and “one terminal 22A of the second piezoresistor 22”. "Corresponds to a terminal into which a current from the first piezoresistor 12 flows. The second wiring 32 electrically connects these terminals and corresponds to the output terminal of the half bridge circuit.

  The third wiring 33 is connected to the other terminal 22B of the second piezoresistor 22 and is clamped at a second potential V2 different from the first potential V1. In the present embodiment, “the other terminal 22 </ b> B of the second piezoresistor 22” is an electrode to which a reference potential is connected when the semiconductor strain gauge 1 constitutes a half-bridge circuit. In the present embodiment, the reference potential is the second potential V2, which corresponds to 0V. Therefore, in the present embodiment, the third wiring 33 is grounded. By connecting as described above, the potential of the first piezoresistor 12 and the second piezoresistor 22 becomes equal to or higher than the potential of the semiconductor substrate 2.

  The first wiring 31, the second wiring 32, and the third wiring 33 are respectively connected to the first well layer 11, the second well layer 21, the first piezoresistor 12, the second piezoresistor 22, and the semiconductor substrate 2. Insulation is performed by the insulating layer 50 except for the electrically connected portions described above.

  The voltage source 40 has a pn junction formed by the second well layer 21 and the second piezoresistor 22 and a pn junction formed by the second well layer 21 and the semiconductor substrate 2 in the same potential state and the reverse bias state. Thus, a potential interlocked with the potential of one terminal 22A of the second piezoresistor 22 is output to the second well layer 21 so that at least one of the states is established.

  As described above, in the present embodiment, the second well layer 21 is formed with an n-type, and the second piezoresistor 22 is formed with a p-type. The semiconductor substrate 2 is p-type. Therefore, a pn junction is formed by the second well layer 21 and the second piezoresistor 22, and a pn junction is formed by the second well layer 21 and the semiconductor substrate 2.

  In the present embodiment, the voltage source 40 is configured using a buffer 41 (voltage buffer circuit). An input terminal (non-inverting terminal) of the buffer 41 is connected to the second wiring 32, and an output terminal is connected to the second well layer 21. Accordingly, the buffer 41 outputs the same potential as the one terminal 22A of the second piezoresistor 22 to the second well layer 21.

  By connecting as described above, the first well layer 11 is connected to a positive power supply, and the interface with the first piezoresistor 12 and the interface with the p-type semiconductor substrate 2 are in a reverse bias state. On the other hand, the second well layer 21 is connected to the output of the buffer 41 so that the interface with the second piezoresistor 22 and the interface with the p-type semiconductor substrate 2 are in a reverse bias state.

  Usually, the impurity concentration is p-type piezoresistance> n-type well layer> p-type semiconductor substrate. For this reason, the depletion layer between the first well layer 11 and the first piezoresistor 12 and the depletion layer between the second well layer 21 and the second piezoresistor 22 are narrow, and the leakage current due to the depletion layer is small. The leakage current caused by the depletion layer between the first well layer 11 and the p-type semiconductor substrate 2 is negligible and is supplied from a positive power source, and is between the second well layer 21 and the p-type semiconductor substrate 2. Since the leakage current caused by the depletion layer is supplied from the buffer 41, the influence of the leakage current on the current flowing through the first piezoresistor 12 and the second piezoresistor 22 can be suppressed.

2. Second Embodiment Next, a second embodiment of the semiconductor strain gauge 1 will be described. FIG. 2 is a diagram schematically showing a circuit configuration of a half bridge by the semiconductor strain gauge 1 according to the second embodiment. In the semiconductor strain gauge 1 of the first embodiment, the voltage source 40 is described as being configured by the buffer 41. However, in the present embodiment, the voltage source 40 is configured by including a p-type MOS-FET 42 and a resistor 43. This is different from the first embodiment. Since other configurations are the same as those in the first embodiment, description thereof will be omitted, and description will be made mainly on different points.

  As shown in FIG. 2, the semiconductor strain gauge 1 of this embodiment also includes the first well layer 11, the first piezoresistor 12, the second well layer 21, the second piezoresistor 22, the first wiring 31, and the second wiring. 32, a third wiring 33, and a voltage source 40. The first well layer 11, the first piezoresistor 12, the second well layer 21, the second piezoresistor 22, the first wiring 31, the second wiring 32, and the third wiring 33 are the same as in the first embodiment. Since it exists, description is abbreviate | omitted.

  In the present embodiment, the voltage source 40 includes a p-type MOS-FET 42 and a resistor 43. In the resistor 43, one terminal 43A is clamped to a potential higher than the potential of one terminal 22A of the second piezoresistor 22, and the other terminal 43B is connected to the source terminal of the p-type MOS-FET 42 and the second well layer 21. Connected. The “potential higher than the potential of one terminal 22A of the second piezoresistor 22” is a potential higher than the threshold voltage of the p-type MOS-FET 42 with respect to the potential of one terminal 22A of the second piezoresistor 22. . In the present embodiment, the same potential as the first potential V1 applied to one terminal 12A of the first piezoresistor 12 is used. Thereby, the first potential V <b> 1 is applied to one terminal 43 </ b> A of the resistor 43. The other terminal 43B of the resistor 43 is electrically connected to the source terminal of the p-type MOS-FET 42 and the second well layer 21 using a conductor.

  The p-type MOS-FET 42 has a drain terminal clamped at a potential lower than the potential of one terminal 22A of the second piezoresistor 22, and a gate terminal connected to the one terminal 22A of the second piezoresistor 22. In the present embodiment, the “potential lower than the potential of one terminal 22A of the second piezoresistor 22” is the same potential as the second potential V2 applied to the other terminal 22B of the second piezoresistor 22. The second potential V2 is 0 V as in the first embodiment. Therefore, the drain terminal of the p-type MOS-FET 42 is grounded. The gate terminal is electrically connected to one terminal 22 </ b> A of the second piezoresistor 22 through the second wiring 32.

  By connecting as described above, the first well layer 11 is connected to a positive power supply, and the interface with the first piezoresistor 12 and the interface with the p-type semiconductor substrate 2 are in a reverse bias state. On the other hand, since the second well layer 21 has a potential higher than the output of the half bridge circuit by the threshold voltage of the p-type MOS-FET 42, the second well layer 21 is in a reverse bias state with respect to the second piezoresistor 22 and the p-type semiconductor substrate 2. At the same time, the voltage source 40 (source follower) composed of the p-type MOS-FET 42 and the resistor 43 can be regarded as a voltage source below the current value limited by the resistor 43. Therefore, the second well layer 21 and the p-type semiconductor are used. Leakage current due to the depletion layer between the substrate 2 is supplied from the voltage source 40. Further, since the voltage source 40 can be configured only by the p-type MOS-FET 42 and the resistor 43, a process of forming a half bridge circuit by the first piezoresistor 12 and the second piezoresistor 22 on the p-type semiconductor substrate 2 is performed. It is possible to form without making a big change.

3. Third Embodiment Next, a third embodiment of the semiconductor strain gauge 1 will be described. FIG. 3 is a diagram schematically illustrating a circuit configuration of a half bridge by the semiconductor strain gauge 1 according to the third embodiment. In the semiconductor strain gauge 1 of the second embodiment, it has been described that the voltage source 40 includes the p-type MOS-FET 42 and the resistor 43. However, in this embodiment, the voltage source 40 is the n-type MOS-FET 52. And the resistor 53 is different from the second embodiment in that it is configured. The conductivity types of the first well layer 11, the first piezoresistor 12, the second well layer 21, and the second piezoresistor 22 are also different from those of the second embodiment.

  In the present embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. Therefore, the n-type semiconductor substrate 2 is used. A p-type first well layer 11 and a p-type second well layer 21 are formed on the n-type semiconductor substrate 2. Further, the first piezoresistor 12 and the second piezoresistor 22 are formed to have n-type in the first well layer 11 and the second well layer 21, respectively.

  One terminal 12A of the first piezoresistor 12 and the first well layer 11 are electrically connected by a first wiring 31, and a negative power source is connected to the first wiring 31. Therefore, in the present embodiment, the first potential V1 is a negative potential. One terminal 12 </ b> A of the first piezoresistor 12 and the first well layer 11 are connected to a negative potential via the first wiring 31.

  The other terminal 12B of the first piezoresistor 12 and one terminal 22A of the second piezoresistor 22 are connected by a second wiring 32. The other terminal 22B of the second piezoresistor 22 is clamped to the second potential via the third wiring 33. In the present embodiment, the second potential corresponds to 0V. Therefore, the other terminal 22B of the second piezoresistor 22 is grounded. The n-type semiconductor substrate 2 is connected to a predetermined third potential V3. In the present embodiment, the n-type semiconductor substrate 2 is grounded. By connecting as described above, the potential of the first piezoresistor 12 and the second piezoresistor 22 becomes equal to or lower than the potential of the semiconductor substrate 2.

  In the present embodiment, the voltage source 40 includes an n-type MOS-FET 52 and a resistor 53. In the resistor 53, one terminal 53A is clamped to a potential higher than the potential of one terminal 22A of the second piezoresistor 22, and the other terminal 53B is connected to the source terminal of the n-type MOS-FET 52 and the second well layer 21. Connected. The “potential higher than the potential of one terminal 22A of the second piezoresistor 22” is a potential lower than the threshold voltage of the n-type MOS-FET 52 with respect to the potential of one terminal 22A of the second piezoresistor 22. . In the present embodiment, it is set to the same potential as the second potential V2 applied to the other terminal 22B of the second piezoresistor 22. Thereby, the second potential V <b> 2 is applied to one terminal 53 </ b> A of the resistor 53. The other terminal 53B of the resistor 53 is electrically connected to the source terminal of the n-type MOS-FET 52 and the second well layer 21 using a conductor.

  The n-type MOS-FET 52 has a drain terminal clamped at a potential lower than the potential of one terminal 22A of the second piezoresistor 22, and a gate terminal connected to the one terminal 22A of the second piezoresistor 22. In the present embodiment, the “potential lower than the potential of one terminal 22A of the second piezoresistor 22” is the same potential as the first potential V1 connected to one terminal 12A of the first piezoresistor 12. The gate terminal is electrically connected to one terminal 22 </ b> A of the second piezoresistor 22 through the second wiring 32.

  By connecting as described above, the first well layer 11 is connected to a negative power source, and the interface with the first piezoresistor 12 and the interface with the n-type semiconductor substrate 2 are in a reverse bias state. On the other hand, since the second well layer 21 has a potential lower than the output of the half-bridge circuit by the threshold voltage of the n-type MOS-FET 52, the second well layer 21 is in a reverse bias state with respect to the second piezoresistor 22 and the n-type semiconductor substrate 2. At the same time, the voltage source 40 composed of the n-type MOS-FET 52 and the resistor 53 can be regarded as a voltage source below the current value limited by the resistor 53, so that the second well layer 21 and the n-type semiconductor substrate 2 Leakage current due to the depletion layer therebetween is supplied from the voltage source 40. Further, since the voltage source 40 can be configured only by the n-type MOS-FET 52 and the resistor 53, a process of forming a half bridge circuit by the first piezoresistor 12 and the second piezoresistor 22 on the n-type semiconductor substrate 2 is performed. It is possible to form without making a big change.

  The present invention can be used for a semiconductor strain gauge having two piezoresistors connected in series.

1: Semiconductor strain gauge 2: Semiconductor substrate 11: First well layer 12: First piezoresistor 12A: One terminal (one terminal of the first piezoresistor)
12B: the other terminal (the other terminal of the first piezoresistor)
21: second well layer 22: second piezoresistor 22A: one terminal (one terminal of the second piezoresistor)
22B: the other terminal (the other terminal of the second piezoresistor)
31: First wiring 32: Second wiring 33: Third wiring 40: Voltage source 41: Buffer 42: p-type MOS-FET
43: Resistor 43A: One terminal (one terminal of the resistor)
43B: the other terminal (the other terminal of the resistor)
52: n-type MOS-FET
53: Resistor 53A: One terminal (one terminal of the resistor)
53B: the other terminal (the other terminal of the resistor)
V1: first potential V2: second potential

Claims (4)

A first well layer formed on a first conductivity type semiconductor substrate having a second conductivity type different from the first conductivity type;
A second well layer formed on the semiconductor substrate and spaced apart from the first well layer and having the second conductivity type;
A first piezoresistor formed in the first well layer with the first conductivity type;
A second piezoresistor formed in the second well layer with the first conductivity type;
A first wiring that electrically connects one terminal of the first piezoresistor and the first well layer and is clamped to a predetermined first potential;
A second wiring that electrically connects the other terminal of the first piezoresistor and one terminal of the second piezoresistor;
A third wiring connected to the other terminal of the second piezoresistor and clamped at a second potential different from the first potential;
A pn junction formed by the second well layer and the second piezoresistor and a pn junction formed by the second well layer and the semiconductor substrate are in at least one of the same potential state and the reverse bias state. A voltage source that outputs a potential linked to the potential of one terminal of the second piezoresistor to the second well layer;
A semiconductor strain gauge.   The semiconductor strain gauge according to claim 1, wherein the voltage source is a buffer that outputs the same potential as the potential of one terminal of the second piezoresistor. The first conductivity type is p-type;
The second conductivity type is n-type;
The potential of the first piezoresistor and the second piezoresistor is greater than or equal to the potential of the semiconductor substrate;
The voltage source includes a p-type MOS-FET and a resistor,
The resistor has one terminal clamped at a potential higher than the potential of one terminal of the second piezoresistor, and the other terminal connected to the source terminal of the p-type MOS-FET and the second well layer. ,
The drain terminal of the p-type MOS-FET is clamped to a potential lower than the potential of one terminal of the second piezoresistor, and the gate terminal is connected to one terminal of the second piezoresistor. The semiconductor strain gauge described. The first conductivity type is n-type;
The second conductivity type is p-type;
The potential of the first piezoresistor and the second piezoresistor is less than or equal to the potential of the semiconductor substrate;
The voltage source includes an n-type MOS-FET and a resistor,
The resistor has one terminal clamped to a potential higher than the potential of one terminal of the second piezoresistor, and the other terminal connected to the source terminal of the n-type MOS-FET and the second well layer. ,
The n-type MOS-FET has a drain terminal clamped at a potential lower than a potential of one terminal of the second piezoresistor and a gate terminal connected to one terminal of the second piezoresistor. The semiconductor strain gauge described.

Images