JP2015140270A - silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a silicon wafer from cracking or having more dislocation to warp large when a nitride semiconductor layer is epitaxially grown on the silicon wafer.SOLUTION: A first projection length in a direction along a top surface 3 between the intersection of an end face 5 and a first inclined plane 6 and the intersection of the top surface 3 and the first inclined plane 6 is denoted as a1 μm, and a second projection length in a direction along a reverse surface 4 between the intersection of the end face 5 and a second inclined plane 7 and the intersection of the reverse surface 4 and the second inclined plane 7 is denoted as a2 μm; and the first angle of inclination of the first inclined plane 6 from the top surface 3 is denoted as θ1, the second angle of inclination of the second inclined plane 7 from the reverse surface 4 is denoted as θ2, and the surface interval between the top surface 3 and reverse surface 4 is denoted as T μm. Then the shape value of a bevel defined by a1 tanθ1-a2 tanθ2 is calculated from values of the respective parameters, and the shape of the bevel is defined so that the shape value is within a predetermined range.

Description

  The present invention relates to a silicon wafer, and more particularly, to a silicon wafer suitable as a substrate for epitaxial growth of a nitride semiconductor (for example, a gallium nitride based semiconductor).

  Gallium nitride (GaN) -based semiconductor materials have excellent characteristics such as a band gap that is about three times that of silicon (Si), a breakdown electric field that is about ten times that of Si, and a large saturation electron velocity. Research and development has been actively conducted as a material for high-frequency and high-power devices in the communication field, and mobile phone base station devices have already entered the stage of practical use. Recently, it is expected to achieve both high breakdown voltage and low loss, that is, low on-resistance, which is difficult with conventional Si power devices, and therefore, attention is focused on application to power devices for electric power. Since the theoretical value of the on-resistance is inversely proportional to the cube of the dielectric breakdown electric field, a power device using GaN may have an ultra-low on-resistance of about 1/1000 of Si.

  A GaN-based semiconductor material used for an optical device such as an LED or an electronic device such as a transistor is generally formed by epitaxial growth (hereinafter referred to as epi growth) on a heterogeneous substrate such as sapphire or silicon carbide (SiC). . However, in recent years, Si, which has been widely used in the past, has been widely used as a substrate for GaN epi growth from the viewpoint of increasing the substrate diameter, improving the substrate quality itself, and cost.

However, regarding the crystal growth of a nitride semiconductor layer on a Si wafer (hereinafter referred to as a wafer as appropriate), there are differences in the crystal structure of the nitride semiconductor with respect to Si, lattice mismatch, and thermal expansion coefficient differences, so , Wafer warpage and dislocation occur. These cause manufacturing problems such as wafer handling errors and junction leaks. For example, the lattice constant of Si used as an epitaxial growth substrate is 5.43 angstroms, whereas the lattice constant of GaN, which is one of nitride semiconductors, is 3.189 angstroms. Further, the thermal expansion coefficient of Si is 3.59 × 10 ⁻⁶ / K, whereas the thermal expansion coefficient of GaN is 5.59 × 10 ⁻⁶ / K. Thus, since the lattice constant and the thermal expansion coefficient of the two are greatly different, when GaN is epitaxially grown as it is on Si, there arises a problem that large strains, cracks and the like are generated.

  In order to solve this problem, for example, in Patent Document 1, after epitaxially growing aluminum nitride (AlN) and gallium aluminum nitride (AlGaN) (see paragraphs 0025 to 0026 of this document) on Si, A technique for epi-growing a GaN layer (see paragraph 0021 of this document) is disclosed. This is because by causing AlN or AlGaN to act as a buffer layer, the lattice mismatch ratio between the respective layers is reduced and the strain is gradually relaxed, so that it is possible to expect a reduction in wafer warpage and dislocation.

JP 2012-79952 A

In the configuration of Patent Document 1, it is necessary to perform high-temperature heat treatment at about 1000 to 1200 ° C. for a long time (usually several hours or more) in order to form an epi layer having a thickness of several μm. Even if the buffer layer is formed as in the configuration, there are still problems that slip (dislocation) occurs at a high density of 10 ⁹ / cm ² and the wafer is cracked. Although the strain can be alleviated to some extent by forming a buffer layer, the bevel on the wafer end surface comes into contact with the surrounding jig, and new defects that cause slipping or cracking are introduced, or during the heat treatment It is presumed that slips and the like extend from defects (such as crushing marks and scratches at the time of polishing) originally existing in the wafer due to the stress applied.

  Therefore, an object of the present invention is to suppress the occurrence of a large warp due to cracking of a wafer or dislocation extension when a nitride semiconductor layer is epitaxially grown on a silicon wafer.

  In order to solve the above problems, in the present invention, a (111) plane disk-shaped silicon wafer for epitaxially growing a nitride semiconductor layer, the surface on which the nitride semiconductor layer is formed, A first surface that has a back surface parallel to the surface, a surface normal perpendicular to the surface normal of the surface, an end surface constituting a wafer outer peripheral portion, the surface and the end surface, and an inclination with the surface. An inclined surface, and a second inclined surface that is continuous with the back surface and the end surface and is inclined with the back surface, and an intersection of the end surface and the first inclined surface, and an intersection of the surface and the first inclined surface The first projection length in the direction along the front surface is a1 μm, the first projection length in the direction along the back surface between the intersection of the end surface and the second inclined surface, and the intersection of the back surface and the second inclined surface. Two projection lengths a2 μm, the first inclined surface When the first inclination angle from the front surface is θ1, the second inclination angle from the back surface of the second inclined surface is θ2, and the surface interval between the front surface and the back surface is T μm, the following equation −0 before and after epitaxial growth: 0.048T ≦ a1 · tan θ1−a2 · tan θ2 ≦ 0.048T was satisfied, thereby forming a silicon wafer.

  Alternatively, a silicon wafer having a (111) orientation disk for epitaxial growth of a nitride semiconductor layer, the surface on which the nitride semiconductor layer is formed, the back surface parallel to the surface, and the surface normal of the surface A curved end surface having a surface normal that continuously changes with respect to the surface, a curved end surface constituting a wafer outer peripheral portion, a first inclined surface that is continuous with the surface and the curved end surface, and is inclined with respect to the surface, the back surface, and A second inclined surface that is continuous with the curved end surface and is inclined with respect to the back surface, and a direction along the surface between the outermost end of the curved end surface and the intersection of the surface and the first inclined surface The first projection length is a1 μm, the second projection length in the direction along the back surface between the outermost end of the curved end surface and the intersection of the back surface and the second inclined surface is a2 μm, The first inclination angle from the surface is θ1, and the back side of the second inclined surface When the second inclination angle from θ is θ2, and the surface interval between the front surface and the back surface is Tμm, the following expression −0.064T ≦ a1 · tan θ1−a2 · tan θ2 ≦ 0.064T is satisfied before and after epitaxial growth. A silicon wafer was constructed.

  The wafer thickness of the bevel before and after forming the nitride semiconductor layer by keeping the value calculated from the end face shape of the wafer using the above formula (hereinafter referred to as the shape value) within the range of the left side and the right side of the above formula. The longitudinal cross section is maintained in a substantially symmetrical shape. For this reason, when the wafer is placed on the susceptor of the epi-growth apparatus for epi-growth, when the wafer end surface and the susceptor come into contact with each other, defects such as cracks that cause the wafer to crack are newly added to this end surface. Can be prevented as much as possible.

  During this epi growth, the wafer surface is in free contact with the source gas flowing in the epi growth apparatus, while the back surface of the wafer faces the susceptor and therefore hardly contacts the source gas. As a result, a shape change accompanying epi growth occurs only on the wafer surface side. Therefore, considering the shape change on the wafer surface side before and after the epi, the absolute value of the numerical value on the right side of the above equation can be made smaller than the absolute value of the numerical value on the left side by the amount corresponding to the epi thickness.

  In each of the configurations, the first projection length and the second projection length are both 50 μm or more and 1000 μm or less, and the absolute value of the difference between the first projection length and the second projection length is 50 μm or less. Is preferred.

  This is because if the first projection length and the second projection length are 50 μm or less, the bevel becomes angular and defects such as cracks are easily introduced by contact with a jig such as a susceptor. In addition, if the first projection length and the second projection length are 1000 μm or more, the surface area of the wafer that can be used for manufacturing the device is substantially reduced, and the number of devices that can be manufactured from one wafer is reduced. This is because the yield decreases. In addition, when the absolute value of the difference between the first projection length and the second projection length exceeds 50 μm, the asymmetry of the bevel-shaped wafer surface side and the back surface side becomes conspicuous. This is because defects such as cracks are likely to be introduced by contact with.

  The first projection length and the second projection length are more preferably in the range of 50 μm to 250 μm. This is because the occurrence of defects in the bevel can be further suppressed and the device manufacturing yield can be further increased.

  Further, in order to solve the above-mentioned problem, a silicon wafer having a (111) plane orientation for epitaxial growth of a nitride semiconductor layer, which is present in a region within 30% of the radius from the center of the back surface of the substrate A silicon wafer characterized in that the number of defects having a size of 1 μm or more is 5 or less.

  As described above, since the lattice constant of a nitride semiconductor (for example, GaN) is significantly smaller than that of Si used as a wafer for epi growth, the nitride semiconductor is epitaxially formed on the Si surface (upper surface). When grown, the wafer warps in a downward convex shape. At this time, according to the stress distribution calculation in the wafer surface, it can be seen that particularly large stress (tensile stress on the back side of the wafer) is generated in the vicinity of the center of the wafer, particularly in a region within 30% of the radius from the center. Since this tensile stress acts to expand defects such as cracks, it causes warpage due to dislocation extension due to the defects and cracking of the wafer. Therefore, by controlling the size and number of defects in this region to be equal to or less than a predetermined value, it is possible to significantly reduce wafer warpage and the like.

  There is a correlation between the size of the defect and the ease of occurrence of warpage or the like due to the defect. If the size of the defect is smaller than 1 μm, the warp or the like even when stress is applied to the defect. The risk of causing this is low. Further, as the number of defects increases, the amount of warpage tends to increase, but when the number is 5 or less, the amount of warpage can be kept sufficiently low. For the evaluation of the size of the defect, an apparatus that can accurately measure the size of the defect, such as a scanning electron microscope or an optical microscope, is usually used.

  In addition, the size and number of defects at the position where the orientation flat or orientation notch is likely to cause problems such as cracks and slips due to defects due to the crystal orientation are less than a predetermined value (for example, 5 defects having a size of 1 μm or more). In the same manner as described above, warpage due to dislocation extension due to this defect and induction of wafer cracking can be prevented. Similarly to the above, an apparatus that can accurately measure the size of the defect, such as a scanning electron microscope or an optical microscope, is usually used.

  A wafer having a diameter of 12 inches is generally mirror-finished on both the front and back surfaces, but a wafer having a smaller diameter (for example, 6 inches or 8 inches) has a mirror-finished surface. On the other hand, the back surface is often in an etching finish state or subjected to backside damage. The surface subjected to the etching finish or the backside damage tends to be disadvantageous in terms of strength such as crack resistance as compared with the surface subjected to the mirror finish. Therefore, this small diameter wafer, especially 6 inch and 8 inch wafers, are mirror-finished on both the front and back surfaces, and by applying the above-mentioned defect size, number and area criteria, And cracks can be greatly reduced. Further, by applying a mirror finish to the end face, it is possible to greatly reduce the warpage and cracking of the wafer as described above.

  In this invention, the first projection length along the surface of the first inclined surface in the bevel of the silicon wafer, the second projection length along the back surface of the second inclined surface, the first inclination angle from the surface of the first inclined surface, and The silicon wafer was configured such that the second inclination angle of the second inclined surface from the back surface was within the range of a predetermined relational expression. By using a wafer that satisfies this relational expression, it is possible to suppress the occurrence of slips caused by defects such as cracking, warping, and cracking of the wafer throughout the entire epi-growth process, thereby ensuring a high manufacturing yield. be able to.

  Alternatively, in the present invention, a wafer is configured in which the size and number of defects in a predetermined region (region near the center of the wafer) are controlled to a predetermined value or less. By using the wafer configured as described above, the occurrence of slips due to defects such as warpage, cracking, and cracking of the wafer can be suppressed throughout the entire epitaxial growth process, as described above, and high manufacturing is possible. Yield can be secured.

The longitudinal cross-sectional view of the edge part of the wafer which concerns on this invention is shown, (a) when a taper process is given, (b) when a round process is given The figure which shows the relationship between the bevel shape value at the time of forming a gallium nitride semiconductor layer in the wafer shown in FIG. 1, and a crack rate Diagram showing the relationship between the number of defects on the backside of the wafer and the amount of warpage after epi It is sectional drawing which shows extension of the slip from a defect, (a) before epi, (b) during epi film formation, (c) after epi Perspective view showing the relationship between crystal orientation, sliding direction and stress direction Diagram showing the relationship between notch formation position and warpage after epi

(1) About influence of bevel shape Embodiment of the wafer which changed the bevel shape is described using drawing.

  FIGS. 1A and 1B are longitudinal sectional views of an end portion (bevel 1) of a wafer grown by Czochralski method (CZ method). The bevel 1a in FIG. 1 (a) has a tapered shape composed of a plurality of continuous planes, and the bevel 1b in FIG. 1 (b) has a round shape having a curved surface at its end.

  A tapered bevel 1a shown in FIG. 1A includes a surface 3 on which a nitride semiconductor layer 2 such as GaN (hereinafter referred to as an epi layer as appropriate) is formed, a back surface 4 parallel to the surface 3, and a surface 3 The first inclined surface 6, the rear surface 4 and the end surface which have a surface normal perpendicular to the surface normal and which are continuous with the end surface 5 constituting the outer peripheral portion of the wafer, the front surface 3 and the end surface 5, and are inclined with the front surface 3. 5 and a second inclined surface 7 that is inclined with respect to the back surface 4. The first projection length in the direction along the surface 3 between the intersection of the end surface 5 and the first inclined surface 6 and the intersection of the surface 3 and the first inclined surface 6 is a1 μm, and the intersection of the end surface 5 and the second inclined surface 7 , The second projection length in the direction along the back surface 4 between the intersection of the back surface 4 and the second inclined surface 7 is a2 μm, the first inclination angle from the surface 3 of the first inclined surface 6 is θ1, and the second inclined surface 7 The second inclination angle from the back surface 4 is θ2, the surface interval between the front surface 3 and the back surface 4 (hereinafter referred to as wafer thickness) is T μm, and is defined by the equation a1 · tan θ1−a2 · tan θ2 from the values of each parameter. The shape value of the bevel is calculated.

  A round bevel 1b shown in FIG. 1B is continuous with a surface 3 on which a nitride semiconductor layer 2 such as GaN is formed, a back surface 4 parallel to the surface 3, and a surface normal of the surface 3. The first inclined surface 6, the rear surface 4, and the curved end surface 8 are continuous with the curved end surface 8, the surface 3 and the curved end surface 8. And a back surface 4 and a second inclined surface 7 that is inclined. The first projection length in the direction along the surface 3 between the outermost end of the curved end surface 8 and the intersection of the surface 3 and the first inclined surface 6 is a1 μm, the outermost end of the curved end surface 8, the rear surface 4 and the second The second projection length in the direction along the back surface 4 with the intersection of the inclined surface 7 is a2 μm, the first inclination angle from the surface of the first inclined surface 6 is θ1, and the second projection surface from the back surface 4 of the second inclined surface 7 is second. The inclination angle is θ2, the wafer thickness is T μm, and the shape value of the bevel defined by the equation a1 · tan θ1−a2 · tan θ2 is calculated from the values of the parameters.

  The shape value calculated here is an index of symmetry in the longitudinal section of the bevel 1 (1a, 1b). That is, in the longitudinal section of the bevel 1 (1a, 1b), if the shape on the front and back surfaces 3 and 4 side is completely symmetrical, the shape value becomes 0, and the shape increases as the asymmetry of the shape on the front and back surfaces 3 and 4 increases. The absolute value of the value increases.

  In FIGS. 1A and 1B, the thickness of the epi layer 2 is exaggerated in order to make the epi layer 2 formed on the surface 3 side of the wafer easier to see. The thickness is about several μm to several tens of μm, which is sufficiently smaller than the wafer thickness T (about 600 to 800 μm). For this reason, before and after the formation of the epi layer 2, the first projection length a1 and the first inclination angle θ1 are treated as hardly changing.

  The wafer is placed on a susceptor (not shown) of a MOCVD (Metal Organic Chemical Deposition) apparatus with the back surface 4 facing downward. Both the front surface 3 and the back surface 4 of this wafer are mirror-finished. A counterbore is formed in the susceptor, and the wafer just fits into the counterbore. With the wafer placed on the susceptor, a source gas is introduced into the apparatus, and the epi layer 2 is grown while heating the wafer to 1000 to 1200 ° C. At this time, as shown in FIGS. 1 (a) and 1 (b), the epitaxial layer 2 grows on the front surface 3 side where the source gas is sufficiently supplied, while the back surface 4 side is in contact with the susceptor and the source gas is difficult to flow around. Then, the epi layer 2 hardly grows.

  An epitaxial layer made of a gallium nitride semiconductor (GaN) on a silicon wafer having a (111) plane orientation of 6 inches (about 150 mm) in diameter and 625 μm in thickness formed with the bevels 1a and 1b shown in FIGS. The occurrence of cracks in the wafer when 2 was formed to 5 μm was evaluated. The evaluation results are shown in FIG. The horizontal axis represents the shape value (a1 · tan θ1−a2 · tan θ2) (μm) calculated from the bevel shape before GaN film formation, and the vertical axis represents the wafer cracking rate (%) after GaN film formation. Regardless of whether the bevel shape is a taper shape or a round shape, by reducing the shape value, that is, by bringing the longitudinal cross-sectional shapes of the bevels 1a and 1b closer to the front and back surfaces 3 and 4 symmetrically, a low crack rate (0. 1% or less). On the other hand, when the shape value exceeds 30 in the case of the taper shape, and the shape value exceeds 40 in the case of the round shape, the cracking rate is clearly increased. This is because, as the shape value approaches 0, the contact stress with the susceptor acting on the bevels 1a and 1b is evenly distributed on the front and back surfaces 3 and 4 of the bevels 1a and 1b, and the stress can be relaxed. On the other hand, as the absolute value of the shape value increases, the contact stress is likely to be concentrated on either the front surface 3 side or the back surface 4 side of the bevels 1a and 1b.

  From the results shown in FIG. 2, when the crack rate management value in the production line is 0.1% or less, for example, the shape value is 30 or less when the bevels 1a and 1b are tapered, and the shape value is 40 when the bevel is round. It can be said that it is necessary to: Since the wafer strength against cracking is proportional to its thickness, the shape value threshold (30 for the taper shape, 40 for the round shape) obtained using a 625 μm thick wafer is set to an arbitrary wafer thickness T. Can be extended. That is, the threshold value of the shape value for achieving the above crack rate management value (0.1% or less) is 30/625 × T = 0.048T in the case of the taper shape, and 40/625 × T = in the case of the round shape. 0.064T. From this, the threshold value of the shape value of a wafer having a (111) plane orientation with a diameter of 8 inches and a thickness of 725 μm is calculated to be 34.8 for the taper shape and 46.4 for the round shape. If the crack rate management value is changed, the threshold values of the shape values of the bevels 1a and 1b also change according to the result shown in FIG. In addition, by further increasing the wafer thickness T while keeping the wafer diameter the same, the threshold value can be increased and the crack resistance of the wafer can be further improved.

  Bevel shape values (before and after epi) when the first and second projection lengths a1 and a2, the first and second tilt angles θ1 and θ2 are changed, and when GaN is epitaxially grown on these wafers Table 1 (Taper shape, diameter 6 inches), Table 2 (Round shape, diameter 6 inches), Table 3 (Taper shape, diameter 8 inches (about 200 mm)), and Table 4 (Round shape, diameter) 8 inches). The bevel shape value before epi is calculated using the above formula a1 · tan θ1−a2 · tan θ2, and the bevel shape value after epi is expressed using the equation (a1 · tan θ1 + t) −a2 · tan θ2 (t is epi thickness). Respectively.

  Thus, for a wafer having an arbitrary first and second projection length, first and second tilt angles, wafer diameter, and epi thickness, by comparing the bevel shape value with the above threshold, the occurrence of cracks It can be predicted. Moreover, as shown in the comparative examples of Tables 1 to 4, if the first and second projection lengths a1 and a2 are not within the range of 50 μm or more and 1000 μm or less even if the bevel shape value is less than or equal to the threshold value, cracking occurs. It can be seen that the rate exceeds 0.1% of the crack rate management value.

  When the purpose of use after the epi (type of device to be manufactured) is clear and the approximate epi thickness t is known, the threshold corresponding to the epi thickness t is subtracted in advance from the right side of the above formula, The absolute value of the left side and the right side of the above formula may be different. For example, when the maximum thickness of the epitaxial layer to be formed is 10 μm and the bevel is tapered, the right side (maximum value of the shape value) of the above equation is 0.032T from 0.048T × (10/30). When the bevel is round, the right side of the above equation is 0.048T from 0.064T × (10/40). By determining the right side in this way, it is possible to prevent the shape value from exceeding the threshold value after the formation of the epi layer, and to reliably prevent the problem that the wafer breaks after the formation of the epi layer.

(2) Influence of the size, number, and defect position of defects on the backside of the wafer A GaN layer is formed on the surface of a wafer having a different size, number, and position of defects on the backside of the wafer. The amount of warpage was evaluated. The conditions for forming the GaN layer are the same as those described in item (1) above.

  Prior to the formation of the GaN layer, defects on the back side of the wafer were evaluated. For defect evaluation, Surfscan SP1 or Surfscan SP2 (both manufactured by KLA-Tencor) (hereinafter referred to as SP1 and SP2, respectively), a scanning electron microscope (hereinafter referred to as SEM) or an optical microscope. It was used. The position of the defect in the wafer surface was specified by SP1 or SP2, and the specified position was observed with an SEM or an optical microscope, and the size of the defect was measured. The size of this defect is very small, about several μm to several tens of μm, and the number is as small as several to several tens on the wafer surface. Therefore, SP1 or the like does not specify the position of the defect. Direct observation with an SEM or the like is almost impossible, and it is essential to specify the position of a defect in advance with SP1 or SP2 prior to direct observation.

  SP1 and SP2 are the normal surface of the wafer out of the two incident optical systems in which the laser is perpendicularly incident or obliquely incident on the wafer and the scattered light of the incident light irregularly reflected by the defects present on the surface of the wafer. There are provided two types of condensing optical systems for condensing near scattered light (narrow channel side) and scattered light on a wider angle side (wide channel side) than the narrow channel side. SP1 is used to measure 6 inch and 8 inch diameter wafers, and SP2 is used to measure 8 inch and 12 inch diameter wafers.

  SP1 and SP2 differ in terms of the wavelength of the laser to be used, but the measurement principle is the same. The position of the defect in the wafer surface is specified, and the magnitude of the defect is determined from the intensity of the detected scattered light. Can be evaluated. The size of this defect is not the actual size of the defect, but a standard curve of PSL (Polystyrene Latex) with a different diameter is used to create a calibration curve between the scattered light intensity and the diameter of the standard particle in advance. It is the apparent size derived by converting the calibration curve into the diameter of the PSL standard particles. By moving the wafer in the plane while rotating the wafer and scanning the laser, it is possible to perform in-wafer mapping of the defect position and size.

  A relatively small defect is mainly detected in the wide channel, and a relatively large defect is mainly detected in the narrow channel. In this defect evaluation, as shown in Table 5 (for SP1) and Table 6 (for SP2), the wide channel range was set to 0.1-1.0 μm and the narrow channel range was set to 0.295-50 μm. . Of the two incident optical systems, the incident optical system perpendicularly incident on the wafer was selected. Note that the measurement conditions of SP1 and SP2 shown in Tables 5 and 6 are merely examples, and may be appropriately changed in consideration of various factors such as the surface state of the wafer and the size of the defect to be measured. it can. Further, an incident optical system that is obliquely incident can be employed instead of the incident optical system that is vertically incident.

  On the surface of the wafer, not only concave defects such as cracks and crushing layer traces but also convex deposits such as particles are present. Since the defect and the deposit are different in size and shape (concave or convex), they can be clearly distinguished in the measurement of SP1 or SP2.

  For example, as shown in Table 7, defects on the wafer surface that directly cause wafer cracking are often detected relatively large compared to the deposits. On both sides of the wide channel where a relatively small defect is detected, a saturation state (Saturated) where the size is determined to have exceeded the upper limit of 1.0 μm is likely to occur. At this time, as indicated by defect numbers 1 and 3, while being saturated on the wide channel side, it may be determined to be smaller than 1.0 μm on the narrow channel side. This may be due to the fact that the crushing layer mark, which is the actual state of this defect, has a concave shape, and it is difficult to detect scattered light in the narrow channel as compared to the wide channel on the wide angle side.

  On the other hand, as shown in Table 8, wafer surface deposits that are not likely to cause direct cracking are often detected relatively small compared to defects such as cracks, and only on the wide channel side. It is often detected and not detected (ND) on the narrow channel side. When the size of this deposit increases to some extent, as shown in defect numbers 5 and 6, it is detected on both the narrow channel side and the wide channel side. In this case, the size on the narrow channel side tends to be detected larger than the size on the wide channel side. This can be attributed to the fact that the actual particle of this defect has a convex shape, and contrary to the concave defect, it is easier to detect scattered light in the narrow channel than in the wide channel on the wide angle side. There is sex. As shown in the defect number 4, in the case of an extra large deposit that extends over a plurality of measurement areas, it may be determined that the defect channel is clustered on the wide channel side and saturated on the narrow channel side.

  Thus, in the measurement of SP1 and SP2, there is a difference in the size detected by the narrow channel and the wide channel between the concave defect and the convex deposit, so that both are detected separately. Can do. However, the size of the defect measured by SP1 or SP2 is only used for distinguishing the concave defect or the convex deposit, and when evaluating the relationship with the warp or crack of the wafer, the SEM Or measured values using an optical microscope.

  FIG. 3 shows the measurement results of the amount of warpage of the wafer when GaN is formed on the wafer having defects on the back surface of the wafer. The size of the defect shown below is an actual measurement value measured with an SEM or an optical microscope. The diameter of the wafer used in this measurement is 6 inches, the thickness is 625 μm, and both the front and back surfaces are mirror-finished. The horizontal axis represents the number of defects having a size of 1 μm or more in an area 22.5 mm (30% of the wafer radius) from the center on the back side of the wafer, and the vertical axis represents the amount of warpage of the wafer after epitaxy. The measurement conditions of SP1 performed prior to the measurement with the SEM or the optical microscope are as shown in Table 5. Defects measured by SEM or optical microscope were distributed within a size range of 2 μm to 30 μm.

  From this measurement result, it can be seen that the amount of warpage increases as the number of defects increases. As shown in FIGS. 4A to 4C, when a tensile stress acts during the formation of the epi layer on the defect 9 (see FIG. 4A) existing on the back surface of the wafer, this defect It is considered that this is because a slip is extended from 9 (see this figure (b)), and this slip is pulled out to the surface side of the wafer (see this figure (c)) to cause a large warp. For example, when the management value of the warp amount is 20 μm or less, it can be seen that the warp amount after epi can be within the control value range by setting the number of defects to 5 or less.

  Although not shown in the figure, it was confirmed that even if a defect of 1 μm or more exists outside the range of 22.5 mm from the center, the amount of warpage of the wafer is hardly affected. This is because a large tensile stress acts within a range of 22.5 mm from the center of the wafer, but the tensile stress becomes relatively small outside the range, and even if a defect exists, it does not become a slip source. is there. It was also confirmed that even if a defect smaller than 1 μm exists within a range of 22.5 mm from the center, the amount of warpage of the wafer was hardly affected. This is presumed to be because there is a minimum threshold of defect size that can become a slip source when stress is applied.

  Thus, by controlling the size of the defect, it is possible to suppress the cracking of the wafer. This is because it has been found that cracks are more likely to occur as the size of the defect is larger (30 μm or more as a guideline), and the above-mentioned guideline is well below the above-mentioned guideline if the size of the defect is 1 μm.

  Further, although not shown in the figure, it was also confirmed that when there are almost the same number of defects in the wafer surface, the amount of warpage increases as the size of the defects increases.

  FIG. 3 shows the results for wafers with a diameter of 6 inches, but for wafers with diameters of 8 inches and 12 inches, an area of 30 mm from the center (for 8 inches) or 45 mm from the center (for 12 inches) In this, the number of defects having a size of 1 μm or more was set to 5 or less, so that the amount of warpage after epi was within the control value range. If the management value of the warpage amount is changed, the number of defects that are allowed to exist within an area of 30% from the center also changes according to the result shown in FIG.

  In the above description, the defect size reference is set to 1 μm or more. However, when the optical microscope is used and the resolution does not reach 1 μm, the defect size reference is set to 2 μm or more, 3 μm or more, 5 μm or more. While changing to 10 μm or more, etc., it is also allowed to change the number of defects allowed to exist within 30% of the center. The amount of warpage can be further reduced by controlling the size and number of defects as described above and further increasing the wafer thickness while maintaining the same wafer diameter.

(3) Effect of interstitial oxygen and additive concentration In the wafer, interstitial oxygen introduced from the quartz crucible during crystal growth, boron as a dopant of p-type semiconductor, and Si oxide precipitation promotion in the wafer In order to achieve this, additional elements such as nitrogen and carbon are included. These additive elements aggregate in the vicinity of dislocations, which are a kind of crystal defects, to prevent the movement of dislocations, or by acting on the dislocations that the Si oxide moves to prevent the movement of dislocations. It has the effect of suppressing the occurrence of slips caused by the movement of the wafer and the cracking of the wafer.

The dislocation migration inhibiting action basically works more effectively as the concentration of the added element is higher, but interstitial oxygen is 1-12 × 10 ¹⁷ / cm ³ , boron is 1-100 × 10 ¹⁸ / cm ³ , nitrogen Is preferably in the range of 1-10 × 10 ¹⁴ / cm ³ , and carbon is preferably in the range of 1-10 × 10 ¹⁶ / cm ³ . The lower limit of the concentration range of each additive element is that when the additive concentration is lower than this, the dislocation migration inhibiting action is not sufficiently exhibited. The upper limit of the interstitial oxygen concentration range is that if the concentration is higher than this, the Si oxide is excessively precipitated and grows, and dislocations are generated from the Si oxide itself, which may cause a decrease in strength. . This is because the upper limit of the boron concentration range is outside the predetermined resistivity range normally required for a wafer if the additive concentration is higher than this. The upper limit of the concentration range of nitrogen and carbon is that if the concentration is higher than this, precipitation of Si oxide is promoted excessively, which may cause adverse effects on device characteristics.

In consideration of the required wafer characteristics, the concentration of each additive element can be appropriately determined within the above concentration range. In particular, interstitial oxygen is 10 × 10 ¹⁷ / cm ³ , and boron is 10 × 10 6. ^It is preferable that ¹⁸ / cm ³ , carbon be 0.8 × 10 ¹⁶ / cm ³ , and nitrogen be 5 × 10 ¹⁴ / cm ³ . From the viewpoint of improving the strength of the wafer, it is preferable that each additive element has the above concentration (within the concentration range) over the entire wafer. However, as described in the above item (2), the tensile strength is high near the center of the wafer back surface. Since stress occurs, it is particularly preferable that the concentration is within the above-described concentration range at least in a region within 30% of the radius from the center of the back surface of the substrate.

(4) Effect of mirror finish on the end face The back face of the wafer is mirror finished, and the end face is also mirror finished to remove defects on the end face, thereby further reducing the amount of wafer cracking and warping. Can do. An example of a process related to this series of mirror finish will be described. First, a wafer obtained by slicing an ingot is roughly polished (lapped) to remove mechanical damage on the wafer surface. The end face (bevel) is chamfered either before or after the rough polishing step. Next, mirror polishing (Double Side Polish: DSP) of the front and back surfaces of the wafer is performed, followed by end surface polishing (Polishing Corner Rounding: PCR), and this end surface is used as a mirror surface. Finally, mirror polishing of the wafer surface is performed with a single-wafer polishing machine as a finish, and a series of processes is completed through cleaning and inspection.

(5) Effect of notch creation position A notch is formed on the edge of the wafer to indicate the crystal orientation, but this notch is concave toward the center of the wafer, causing stress concentration during the process. May become the starting point of slip. The extension of the slip causes warping of the wafer after epitaxy. As shown in FIG. 5, the slip starting point is likely to have an angle formed between the direction of the stress F acting on the wafer and the direction n of the sliding surface ((111) plane) of the Si crystal, θ, and the stress F and the sliding. When the angle formed by the direction (<110> direction) b is Φ, it is determined by the size of the Schmid factor S defined by cos θ · cos Φ, and the larger the Schmit factor S, the more slippage of dislocation occurs on the sliding surface. It is judged that it is easy (slip is likely to occur).

  The Schmitt factor S is the smallest when the notch is formed in the <110> direction, and increases as it deviates from the <110> direction. FIG. 6 shows the amount of warpage of the wafer after epitaxy when GaN is formed under the same film formation conditions as in the above item (1) on a wafer in which the notch formation position is displaced from the <110> direction around the outer periphery of the wafer. . In both cases where the bevel is round or tapered, the amount of warpage increased as the notch formation position shifted from the <110> direction. For example, when the management value of the warp amount is 20 μm, it is understood that a notch needs to be formed within 20 degrees from the <110> direction in the round shape and almost in the just <110> direction in the taper shape.

  Each of the above-described embodiments is merely an example, and when the nitride semiconductor layer of the present invention is epitaxially grown on a silicon wafer, it is possible to prevent the wafer from cracking or dislocations from extending and causing large warpage. As long as the problem of “Yes” can be solved, it is allowed to change the configuration as appropriate.

1 (1a, 1b) Bevel 2 Nitride semiconductor layer (epi layer)
3 Front surface 4 Back surface 5 End surface 6 First inclined surface 7 Second inclined surface 8 Curved end surface 9 Defect

Claims (6)

A (111) plane disk-shaped silicon wafer for epitaxially growing a nitride semiconductor layer,
A surface (3) forming the nitride semiconductor layer (2), a back surface (4) parallel to the surface (3), and a surface normal perpendicular to the surface normal of the surface (3); A first inclined surface (6) that is continuous with the end surface (5) constituting the outer peripheral portion of the wafer, the front surface (3), and the end surface (5) and is inclined with respect to the front surface (3), and the back surface (4). And a second inclined surface (7) that is continuous with the end surface (5) and is inclined with respect to the back surface (4),
First projection in a direction along the surface (3) between the intersection of the end surface (5) and the first inclined surface (6) and the intersection of the surface (3) and the first inclined surface (6). The length is a1μm,
Second projection in a direction along the back surface (4) between the intersection of the end surface (5) and the second inclined surface (7) and the intersection of the back surface (4) and the second inclined surface (7). The length is a2μm,
A first inclination angle of the first inclined surface (6) from the surface (3) is θ1,
The second inclined angle from the back surface (4) of the second inclined surface (7) is θ2,
The surface interval between the front surface (3) and the back surface (4) is Tμm,
The following formula −0.048T ≦ a1 · tan θ1−a2 · tan θ2 ≦ 0.048T before and after epitaxial growth.
A silicon wafer characterized by satisfying A (111) plane disk silicon wafer for epitaxially growing a nitride semiconductor layer,
The surface (3) forming the nitride semiconductor layer (2), the back surface (4) parallel to the surface (3), and the surface normal changing continuously with respect to the surface normal of the surface (3) A curved end surface (8) that constitutes the outer periphery of the wafer, a first inclined surface (6) that is continuous with the surface (3) and the curved end surface (8) and is inclined with respect to the surface (3); A second inclined surface (7) that is continuous with the back surface (4) and the curved end surface (8) and is inclined with the back surface (4),
The first projection length in the direction along the surface (3) between the outermost end of the curved end surface (8) and the intersection of the surface (3) and the first inclined surface (6) is a1 μm,
The second projection length in the direction along the back surface (4) between the outermost end of the curved end surface (8) and the intersection of the back surface (4) and the second inclined surface (7) is a2 μm,
A first inclination angle of the first inclined surface (6) from the surface (3) is θ1,
The second inclined angle from the back surface (4) of the second inclined surface (7) is θ2,
The surface interval between the front surface (3) and the back surface (4) is Tμm,
The following formula −0.064T ≦ a1 · tan θ1−a2 · tan θ2 ≦ 0.064T before and after epitaxial growth.
A silicon wafer characterized by satisfying   The first projection length and the second projection length are both 50 μm or more and 1000 μm or less, and the absolute value of the difference between the first projection length and the second projection length is 50 μm or less. Item 3. The silicon wafer according to Item 1 or 2. A (111) plane disk silicon wafer for epitaxially growing a nitride semiconductor layer,
A silicon wafer, wherein the number of defects (9) having a size of 1 μm or more existing in a region within 30% of the radius from the center of the back surface (4) of the substrate is 5 or less.   5. The silicon wafer according to claim 4, wherein the front surface (3) and the back surface (4) are mirror-finished and have a diameter of 6 inches or 8 inches.   The silicon wafer according to claim 4 or 5, wherein the end surface is mirror-finished.

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