JP4583060B2 - Method for manufacturing single crystal sapphire substrate and method for manufacturing nitride semiconductor light emitting device - Google Patents

Method for manufacturing single crystal sapphire substrate and method for manufacturing nitride semiconductor light emitting device Download PDF

Info

Publication number
JP4583060B2
JP4583060B2 JP2004092239A JP2004092239A JP4583060B2 JP 4583060 B2 JP4583060 B2 JP 4583060B2 JP 2004092239 A JP2004092239 A JP 2004092239A JP 2004092239 A JP2004092239 A JP 2004092239A JP 4583060 B2 JP4583060 B2 JP 4583060B2
Authority
JP
Japan
Prior art keywords
single crystal
sapphire substrate
crystal sapphire
nitride semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004092239A
Other languages
Japanese (ja)
Other versions
JP2005277334A (en
Inventor
隆司 宇都
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2004092239A priority Critical patent/JP4583060B2/en
Publication of JP2005277334A publication Critical patent/JP2005277334A/en
Application granted granted Critical
Publication of JP4583060B2 publication Critical patent/JP4583060B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Led Devices (AREA)

Description

本発明は、単結晶サファイア基板およびそれを用いた窒化物半導体に関し、特に発光ダイオード等の光デバイス用途の結晶成長に適した単結晶サファイア基板に関する。   The present invention relates to a single crystal sapphire substrate and a nitride semiconductor using the same, and more particularly to a single crystal sapphire substrate suitable for crystal growth for use in an optical device such as a light emitting diode.

窒化物半導体はLED(Light Emittiing Diode)等の発光デバイスや耐熱性や耐環境性に優れた特徴を活かした電子デバイス用途として実用化されている。この窒化物半導体層は単結晶サファイア基板上に成長させることが多く、また、この単結晶サファイア基板の主面は鏡面加工されていることが多い。以下、一方の主面のみ鏡面加工されている単結晶サファイア基板を片面鏡面であると言う。   Nitride semiconductors have been put into practical use as light-emitting devices such as LEDs (Light Emitting Diode), and electronic device applications that make use of features excellent in heat resistance and environmental resistance. The nitride semiconductor layer is often grown on a single crystal sapphire substrate, and the main surface of the single crystal sapphire substrate is often mirror-finished. Hereinafter, a single crystal sapphire substrate in which only one main surface is mirror-finished is referred to as a single-sided mirror surface.

窒化物半導体層の成長用としての単結晶サファイア基板は、成膜後の窒化物半導体層の発光波長・輝度を安定させる意味から、形状、表面状態、結晶性等に安定した品質を求められる。この品質の中で片面鏡面の単結晶サファイア基板の裏面の状態については、成膜中の基板間および基板面内の温度分布のバラツキ、成膜後の基板検査時の光取り出し効率のバラツキの原因とされ、安定性を求められる。   A single crystal sapphire substrate for growing a nitride semiconductor layer is required to have a stable quality in terms of shape, surface state, crystallinity, and the like in order to stabilize the emission wavelength and luminance of the nitride semiconductor layer after film formation. Within this quality, the condition of the back surface of a single-crystal sapphire substrate with a single-sided mirror is the cause of variations in temperature distribution between the substrates during film formation and in the substrate surface, and variations in light extraction efficiency during substrate inspection after film formation. Therefore, stability is required.

図6に窒化物半導体を用いた発光素子の一例を示す。図6に示すように、この発光素子は単結晶サファイア基板61上にバッファ層62を備え、該バッファ層62の上に発光素子を成す3−5族半導体の多重層63を備えている。この多重層63は、バッファ層62の全面に備えたSiドープn型GaN層からなるn層64と、このn層64上に備えた電極65と、該電極65以外の部分に備えたSiドープAl0.1Ga0.9N層からなるn層66と、シリコンドープGaN層からなる活性層67と、マグネシウムドープAl0.1Ga0.9N層からなるp層68と、これを覆うSiO層79とSiO層69の窓部に備えた電極70から構成されている。 FIG. 6 shows an example of a light-emitting element using a nitride semiconductor. As shown in FIG. 6, this light emitting device includes a buffer layer 62 on a single crystal sapphire substrate 61, and a group 3-5 semiconductor multi-layer 63 constituting the light emitting device on the buffer layer 62. The multi-layer 63 includes an n + layer 64 made of a Si-doped n-type GaN layer provided on the entire surface of the buffer layer 62, an electrode 65 provided on the n + layer 64, and a portion other than the electrode 65. N layer 66 made of Si-doped Al 0.1 Ga 0.9 N layer, active layer 67 made of silicon-doped GaN layer, p-layer 68 made of magnesium-doped Al 0.1 Ga 0.9 N layer, and and a electrode 70 including the window portion of the SiO 2 layer 79 and the SiO 2 layer 69 for covering the.

窒化物半導体を用いた発光素子は単結晶サファイア基板上に図6に示すような層を構成した後に、発光波長および輝度によりランク分けを実施する。その後、単結晶サファイア基板61を裏面側より、砥石及びダイヤモンド砥粒等を用いてバックグラインドを実施し、単結晶サファイア基板61を薄化した後、スクライバーを用いて素子毎にチップとして切り分ける工程をとるのが一般的である。   In a light-emitting element using a nitride semiconductor, a layer as shown in FIG. 6 is formed on a single crystal sapphire substrate, and then ranking is performed according to the emission wavelength and luminance. Thereafter, the single crystal sapphire substrate 61 is back-grinded from the back side using a grindstone, diamond abrasive grains, etc., and after the single crystal sapphire substrate 61 is thinned, a step of cutting the single crystal sapphire substrate 61 into chips for each element using a scriber. It is common to take.

ところが、単結晶サファイア基板61は透明体であるので光透過性を有しており、上記にあるランク分け時における発光層からの光が単結晶サファイア基板61側から漏れる可能性がある(特許文献1参照)。   However, since the single crystal sapphire substrate 61 is a transparent body, it has light transmittance, and light from the light emitting layer at the time of the above rank classification may leak from the single crystal sapphire substrate 61 side (Patent Literature). 1).

そこで、発光層からの光が単結晶サファイア基板側から漏れることを防止するために窒化物半導体層を形成した後に、単結晶サファイア基板の裏面側に凹凸を設けることが提案されている(特許文献2参照)。   In order to prevent light from the light emitting layer from leaking from the single crystal sapphire substrate side, it has been proposed to provide irregularities on the back side of the single crystal sapphire substrate after forming the nitride semiconductor layer (Patent Document). 2).

また、単結晶サファイア基板にチタン、バナジウム、クロム、マンガン、鉄、コバルト、ニッケルなどの金属元素のうち少なくとも一種を含有することにより、特定波長に対する光吸収性もたせることによる対策が提案されている(特許文献3参照)。
特開平9−237934号公報 特開2002−368261号公報 特開2000−332420号公報
In addition, a measure has been proposed in which the single crystal sapphire substrate is provided with at least one of metallic elements such as titanium, vanadium, chromium, manganese, iron, cobalt, and nickel, thereby providing light absorption for a specific wavelength ( (See Patent Document 3).
Japanese Patent Laid-Open No. 9-237934 JP 2002-368261 A JP 2000-332420 A

窒化物半導体を用いた発光素子は単結晶サファイア基板上に発光層を形成後、輝度によりランク分けを実施するが、従来、窒化物半導体発光素子の成膜後の評価時に輝度の低下を生じる課題があった。また、窒化物半導体発光素子形成時に輝度のバラツキを生じる課題があった。   Light emitting devices using nitride semiconductors are ranked according to luminance after forming a light emitting layer on a single crystal sapphire substrate, but the conventional problem is that the luminance decreases when evaluation is performed after deposition of nitride semiconductor light emitting devices. was there. In addition, there is a problem in that the luminance varies when the nitride semiconductor light emitting element is formed.

図7は単結晶サファイア基板71上に窒化物半導体発光素子を形成した際の光の漏れについて示す図である。窒化物半導体層より発生した光は基板全面に発光する。これは単結晶サファイア基板71側についても同様であり、この時の単結晶サファイア基板71の透過率が大きいと、基板裏面側即ち、単結晶サファイア基板71側からの光の漏れ74を生じてしまう
特許文献2による基板の裏面に凹凸を形成する方法は、発光層形成後の基板について輝度を向上させることが目的であり、窒化物半導体層を単結晶サファイア基板に形成した後のバックグラインディング時の面状態を規定するものである。そのため、窒化物半導体を用いた発光素子を形成後の基板の評価時には、従来の単結晶サファイア基板の状態がそのまま反映されるためランク分けの判断が困難となる。また新たな凹凸形成のための応力の発生がさけられず、基板のそり精度に影響をあたえ、スクライビング等に問題を生じさせる危険性が懸念される。
FIG. 7 is a diagram showing light leakage when a nitride semiconductor light emitting element is formed on a single crystal sapphire substrate 71. Light generated from the nitride semiconductor layer is emitted over the entire surface of the substrate. This also applies to the single crystal sapphire substrate 71 side. If the transmittance of the single crystal sapphire substrate 71 at this time is large, light leakage 74 from the back side of the substrate, that is, from the single crystal sapphire substrate 71 side occurs. The method of forming irregularities on the back surface of the substrate according to Patent Document 2 is intended to improve the luminance of the substrate after the light emitting layer is formed, and at the time of backgrinding after the nitride semiconductor layer is formed on the single crystal sapphire substrate. This defines the surface state. Therefore, when evaluating a substrate after forming a light emitting element using a nitride semiconductor, the state of the conventional single crystal sapphire substrate is reflected as it is, so that it is difficult to determine the ranking. In addition, the generation of stress for the formation of new irregularities cannot be avoided, and there is concern about the risk of affecting the warpage accuracy of the substrate and causing problems in scribing and the like.

また、特許文献3の金属元素を含有させる方法であれば、窒化物半導体を用いた発光素子より発生した光の単結晶サファイア基板側からの漏れは無くなるものの、単結晶サファイア基板自体が、発光層より発生した光を吸収してしまい、発光輝度の低下に繋がる可能性がある。   In addition, the method including the metal element of Patent Document 3 eliminates leakage of light generated from a light emitting element using a nitride semiconductor from the single crystal sapphire substrate side, but the single crystal sapphire substrate itself has a light emitting layer. The generated light may be absorbed, leading to a decrease in light emission luminance.

従って、本発明の目的は、窒化物半導体発光素子の成膜後の評価時に輝度の低下を防止し、また、窒化物半導体発光素子形成時に輝度のバラツキを抑えることを目的とした単結晶サファイア基板を提供することであり、且つそれを用いた窒化物半導体発光素子を提供することにある。   Accordingly, an object of the present invention is to prevent a decrease in luminance at the time of evaluation after the formation of a nitride semiconductor light emitting device, and to suppress variation in luminance at the time of forming a nitride semiconductor light emitting device. And to provide a nitride semiconductor light emitting device using the same.

本発明者は、上記問題を解決すべく研究を行った結果、透過率を抑え且つバラツキを低減した単結晶サファイア基板が、成膜後の評価時の輝度の低下を防止するとともに、窒化物半導体発光素子形成時の輝度のバラツキを抑えることが可能であることを見出した。   As a result of researches to solve the above problems, the present inventor has a single crystal sapphire substrate that suppresses transmittance and reduces variation, and prevents a decrease in luminance at the time of evaluation after film formation. It has been found that it is possible to suppress variations in luminance when forming a light emitting element.

本発明の単結晶サファイア基板は、200〜600nmの波長域の光に対する透過率が10%以下であることを特徴としている。   The single crystal sapphire substrate of the present invention is characterized by having a transmittance of 10% or less with respect to light in the wavelength region of 200 to 600 nm.

また、各波長における基板面内の透過率バラツキが5%以下であることを特徴としている。   In addition, the transmittance variation within the substrate surface at each wavelength is 5% or less.

また、一方の主面が鏡面であることを特徴とし、さらに他方の主面の算術平均粗さRaが0.4〜1.5μmであることを特徴としている。   Moreover, one main surface is a mirror surface, and the arithmetic mean roughness Ra of the other main surface is 0.4 to 1.5 μm.

また、基板面内の算術平均粗さのバラツキが0.4μm以下であることを特徴としている。   Further, the variation in arithmetic average roughness within the substrate surface is 0.4 μm or less.

さらに、上記単結晶サファイア基板の主面上に、AlGaN(X+Y=1,X≧0,Y≧0)のバッファ層を形成した後、その上に窒化物半導体結晶層を成長させ、その中に発光層を含む半導体結晶層が積層された素子構造を有する窒化物半導体発光素子であることを特徴としている。 Furthermore, after forming a buffer layer of Al X Ga Y N (X + Y = 1, X ≧ 0, Y ≧ 0) on the main surface of the single crystal sapphire substrate, a nitride semiconductor crystal layer is grown thereon. A nitride semiconductor light emitting device having an element structure in which a semiconductor crystal layer including a light emitting layer is stacked therein.

本発明の単結晶サファイア基板は、200〜600nmの波長域において透過率が10%以下であるため、窒化物半導体を用いた発光層を、単結晶サファイア基板上に形成した後、発光層より発光される光の単結晶サファイア基板側への漏れが減少し、発光素子輝度の安定化が図れる。   Since the single crystal sapphire substrate of the present invention has a transmittance of 10% or less in a wavelength region of 200 to 600 nm, a light emitting layer using a nitride semiconductor is formed on the single crystal sapphire substrate, and then light is emitted from the light emitting layer. Leakage of light to the single crystal sapphire substrate side is reduced, and the luminance of the light emitting element can be stabilized.

さらに、単結晶サファイア基板の上記波長領域におけるバラツキを5%以下とするため、窒化物半導体を用いた発光層よりの光の単結晶サファイア基板側への漏れのバラツキの低減が可能であり、発光素子の輝度バラツキを低減することができる。   Furthermore, since the variation in the wavelength region of the single crystal sapphire substrate is 5% or less, it is possible to reduce the variation in leakage of light from the light emitting layer using the nitride semiconductor to the single crystal sapphire substrate side. It is possible to reduce the luminance variation of the element.

また、本発明の単結晶サファイア基板は片面鏡面加工されており、鏡面側に窒化物半導体層を形成する。また、裏面側については、算術平均粗さRaが0.4〜1.5μmであり、算術平均面粗さRaのバラツキが0.4μm以下であることにより、200〜600nmの波長域にあって透過率が10%以下に制御することが容易になり、また上記波長域に対する透過率のバラツキを5%以下とすることが可能となる。   Further, the single crystal sapphire substrate of the present invention is single-sided mirror-finished, and a nitride semiconductor layer is formed on the mirror side. On the back surface side, the arithmetic average roughness Ra is 0.4 to 1.5 μm, and the variation of the arithmetic average surface roughness Ra is 0.4 μm or less, so that it is in the wavelength range of 200 to 600 nm. It becomes easy to control the transmittance to 10% or less, and the variation in the transmittance with respect to the wavelength range can be set to 5% or less.

さらに、本発明の単結晶サファイア基板を用いて、AlGaN(X+Y=1,X≧0,Y≧0)のバッファ層を形成した後、その上に窒化物半導体結晶層を成長させ、その中に発光層を含む半導体結晶層が積層された素子構造を形成した場合に、輝度特性に優れる窒化物半導体発光素子を得ることができる。 Furthermore, after forming a buffer layer of Al X Ga Y N (X + Y = 1, X ≧ 0, Y ≧ 0) using the single crystal sapphire substrate of the present invention, a nitride semiconductor crystal layer is grown thereon. When a device structure in which a semiconductor crystal layer including a light emitting layer is laminated is formed, a nitride semiconductor light emitting device having excellent luminance characteristics can be obtained.

次に本発明の実施の形態について図面を参照し詳述する。   Next, embodiments of the present invention will be described in detail with reference to the drawings.

図1は本発明により得られた単結晶サファイア基板11の主面12上に窒化物半導体発光素子を形成した図である。単結晶サファイア基板11の一方の主面12は鏡面加工がなされており、他方の主面13は、算術平均面粗さRaが0.4〜1.5μmであり、基板面内の算術平均粗さRaのバラツキが0.4μm以下である。このように他方の主面13を適度に粗くすることにより、単結晶サファイア基板11は200〜600nmの波長域の光に対する透過率が10%以下であって、各波長に対する透過率の基板面内におけるバラツキが5%以下となっている。   FIG. 1 is a diagram in which a nitride semiconductor light emitting element is formed on a main surface 12 of a single crystal sapphire substrate 11 obtained by the present invention. One main surface 12 of the single crystal sapphire substrate 11 is mirror-finished, and the other main surface 13 has an arithmetic average surface roughness Ra of 0.4 to 1.5 μm, and an arithmetic average roughness within the substrate surface. The variation in thickness Ra is 0.4 μm or less. Thus, by making the other main surface 13 moderately rough, the single crystal sapphire substrate 11 has a transmittance of 10% or less for light in the wavelength region of 200 to 600 nm, and the transmittance for each wavelength is within the substrate surface. The variation in is less than 5%.

また、単結晶サファイア基板11の主面12上に、AlGaN(X+Y=1,X≧0,Y≧0)のバッファ層14を形成した後、その上に窒化物半導体結晶層15を成長させ、その中に発光層16を含む半導体結晶層が積層された素子構造を有する。 Further, after forming a buffer layer 14 of Al X Ga Y N (X + Y = 1, X ≧ 0, Y ≧ 0) on the main surface 12 of the single crystal sapphire substrate 11, a nitride semiconductor crystal layer 15 is formed thereon. And an element structure in which a semiconductor crystal layer including the light emitting layer 16 is stacked.

発光層16より発生した光は基板全面に発光する。これは単結晶サファイア基板11側についても同様であり、この時の単結晶サファイア基板11の透過率が大きいと、単結晶サファイア基板の他方の主面13側からの光の漏れを生じてしまうため、単結晶サファイア基板11においては、透過率が200〜600nmの波長領域において、透過率10%以下が必要となる。透過率が10%より大きくなると、発光層16から発光した光の単結晶サファイア基板の他方の主面13側からの漏れが大きくなり、発光層16形成後の評価と実際の素子形成後の評価に相違が生じてしまい、正当な評価ができない。特に、窒化物半導体における単結晶サファイア基板上のLEDにおいては380〜450nm領域の紫外〜青色領域の波長域での透過率が低いことが望まれる。   Light generated from the light emitting layer 16 is emitted to the entire surface of the substrate. The same applies to the single crystal sapphire substrate 11 side. If the transmittance of the single crystal sapphire substrate 11 at this time is large, light leaks from the other main surface 13 side of the single crystal sapphire substrate. In the single crystal sapphire substrate 11, the transmittance of 10% or less is required in the wavelength region of the transmittance of 200 to 600 nm. When the transmittance is greater than 10%, leakage of light emitted from the light emitting layer 16 from the other main surface 13 side of the single crystal sapphire substrate increases, and evaluation after the light emitting layer 16 is formed and evaluation after actual device formation is performed. This makes a difference and cannot be evaluated properly. In particular, an LED on a single crystal sapphire substrate in a nitride semiconductor is desired to have a low transmittance in the wavelength range from 380 to 450 nm in the ultraviolet to blue region.

また、単結晶サファイア基板11の透過率は、分光光度計を用いて測定し、片面鏡面のサファイア基板の主面12側より光を入射し、他方の主面13側より光を取り出した際の光の強度の割合にて規定する。波長200〜600nmを測定することにより、単結晶サファイア基板成膜後の赤〜紫外光域までの波長の発光素子波長での状態のバラツキの評価が可能である。   The transmittance of the single crystal sapphire substrate 11 is measured using a spectrophotometer, and light is incident from the main surface 12 side of the single-sided mirror surface of the sapphire substrate, and light is extracted from the other main surface 13 side. It is defined by the ratio of light intensity. By measuring the wavelength of 200 to 600 nm, it is possible to evaluate the variation of the state at the light emitting element wavelength of the red to ultraviolet light region after the single crystal sapphire substrate is formed.

また、基板面内の透過率のバラツキに関しては極力少ない方が好ましく、基板面内で5%以下であることが必要であり、特に好ましくは3%以下である。このバラツキが大きいと、特に5%より大きくなると、発光層16から発生した光の他方の主面13への透過するバラツキが大きくなり、発光素子輝度のバラツキを生じてしまう。また、3%以下であると、発光層16形成時の発光素子輝度のバラツキをより低減化することが可能である。   Further, it is preferable that the transmittance variation in the substrate surface is as small as possible, and it is necessary that the transmittance is 5% or less in the substrate surface, and particularly preferably 3% or less. When this variation is large, particularly when it is greater than 5%, the variation in which light generated from the light emitting layer 16 is transmitted to the other main surface 13 becomes large, resulting in variation in light emitting element luminance. Further, if it is 3% or less, it is possible to further reduce variations in the luminance of the light emitting element when the light emitting layer 16 is formed.

ここで、基板面内の透過率バラツキとは、基板の中央部と外周部を2点以上測定したときの最大値と最小値の差をバラツキとして表す。   Here, the transmittance variation in the substrate plane represents the difference between the maximum value and the minimum value when the central portion and the outer peripheral portion of the substrate are measured at two or more points as the variation.

また、単結晶サファイア基板11の一方の主面12は鏡面加工を実施し、窒化物半導体層が成膜可能な表面状態とする必要があるが、他方の主面13についてはラッピング加工面状態とし、光の透過を抑える必要がある。   In addition, one main surface 12 of the single crystal sapphire substrate 11 needs to be mirror-finished to be in a surface state where a nitride semiconductor layer can be formed, but the other main surface 13 is in a lapping processed surface state. It is necessary to suppress the transmission of light.

単結晶サファイア基板11の他方の主面13の算術平均粗さRaについては0.4μmより小さくなると、光の漏れが大きくなり、透過率が10%を超えてしまうため好ましくない。1.5μmより大きくなると、他方の主面13の粗さが鏡面加工時に基板表面の鏡面状態に影響を及ぼし、基板精度が著しく悪化してしまう。また基板面内の算術平均粗さRaのバラツキに関しては、0.4μmより大きくなると単結晶サファイア基板11の透過率にバラツキを生じてしまい好ましくない。   If the arithmetic mean roughness Ra of the other principal surface 13 of the single crystal sapphire substrate 11 is smaller than 0.4 μm, light leakage increases and the transmittance exceeds 10%, which is not preferable. When it is larger than 1.5 μm, the roughness of the other main surface 13 affects the mirror surface state of the substrate surface during mirror processing, and the substrate accuracy is significantly deteriorated. Further, regarding the variation of the arithmetic mean roughness Ra in the substrate surface, if it exceeds 0.4 μm, the transmittance of the single crystal sapphire substrate 11 varies, which is not preferable.

なお、単結晶サファイア基板11の算術平均粗さRaの測定条件としては、接触式のR2μmの触針にて、測定長4mm、カットオフ値0.8mm、スキャンスピード0.1mmである。また、バラツキに関しては透過率と同様に基板の中央部と外周部を2点以上測定したときの最大値と最小値の差で表す。   The measurement conditions for the arithmetic average roughness Ra of the single crystal sapphire substrate 11 are a measurement length of 4 mm, a cut-off value of 0.8 mm, and a scan speed of 0.1 mm with a contact-type R2 μm stylus. Further, the variation is represented by the difference between the maximum value and the minimum value when the central portion and the outer peripheral portion of the substrate are measured at two or more points, similarly to the transmittance.

以上のような単結晶サファイア基板11上に窒化物半導体発光素子を形成することができる。   A nitride semiconductor light emitting device can be formed on the single crystal sapphire substrate 11 as described above.

図2に本単結晶サファイア基板11を用いて作成した青色LED構造を示す。先ず、本発明による単結晶サファイア基板11をMOVPE装置に装着し、窒素ガス主成分雰囲気下で1100℃まで昇温し、サーマルクリーニングを行った。その後、温度を500℃まで下げ、周期律表第3族原料として、トリメチルガリウム(以下TMG)を、N原料としてアンモニアを流し、厚さ30nmのAlGaN低温バッファ層21を成長させた。続いて温度を1000℃に昇温し原料としてTMG、アンモニアを、ドーパントとしてシランを流しn型GaNコンタクト層22を成長させた。続いて、n型AlGaNクラッド層24、GaN系半導体層25、p型AlGaNクラッド層26、p型GaNコンタクト層27を順に形成し、さらに、n型コンタクト層を表出させるためのエッチング加工、n電極23とp型電極28を形成した。   FIG. 2 shows a blue LED structure formed using the single crystal sapphire substrate 11. First, the single crystal sapphire substrate 11 according to the present invention was mounted on a MOVPE apparatus, and heated to 1100 ° C. in a nitrogen gas main component atmosphere to perform thermal cleaning. Thereafter, the temperature was lowered to 500 ° C., trimethylgallium (hereinafter referred to as TMG) was flown as a Group 3 raw material of the periodic table, and ammonia was flowed as an N raw material to grow an AlGaN low temperature buffer layer 21 having a thickness of 30 nm. Subsequently, the temperature was raised to 1000 ° C., and TMG and ammonia were flown as raw materials, and silane was flown as a dopant to grow the n-type GaN contact layer 22. Subsequently, an n-type AlGaN cladding layer 24, a GaN-based semiconductor layer 25, a p-type AlGaN cladding layer 26, and a p-type GaN contact layer 27 are formed in this order, and an etching process for exposing the n-type contact layer, n Electrode 23 and p-type electrode 28 were formed.

上記形成後にサファイア基板11上の窒化物半導体発光素子の輝度は、基板裏面よりの光漏れが少ないため輝度の低下が見られず、その後裏面をバックグラインドし、素子分離した後の青色LEDの各素子間の輝度のバラツキも見られない。   The luminance of the nitride semiconductor light emitting device on the sapphire substrate 11 after the above formation is not reduced because the light leakage from the back surface of the substrate is small. Thereafter, each of the blue LEDs after the back surface is ground and the device is separated. There is no variation in luminance between elements.

ここで、本発明の単結晶サファイア基板11の製造方法に関して説明する。   Here, the manufacturing method of the single crystal sapphire substrate 11 of the present invention will be described.

単結晶サファイア基板11は、インゴットもしくは平板の単結晶サファイアより、所望の形状に切り出し、その後所定の厚みとなるように、バンドソー、ワイヤーソー等を用いて切断を実施する。その後、基板の裏面の粗さを規定するラッピングの工程を実施する。 The single crystal sapphire substrate 11 is cut into a desired shape from an ingot or a flat single crystal sapphire, and then cut using a band saw, a wire saw, or the like so as to have a predetermined thickness. Thereafter, a lapping process for defining the roughness of the back surface of the substrate is performed.

図3は本発明の単結晶サファイア基板11の両面ラッピング工程の模式的に示す図であり、単結晶サファイア基板11の両面から遊離砥粒31を介して、ラッピング定盤32を押し当てて、回転させながらラッピングする。遊離砥粒31に関してはサファイア基板が高硬度であることから、なるべく硬度の高い材料を用いることが必要である。具体的にはSiC、BC、ガラスビーズ、アルミナおよびダイヤモンド砥粒の少なくとも一種を用いる。遊離砥粒の粒径により、ラッピングで得られる面の算術平均粗さRaは規定されるため、本発明における片面鏡面の単結晶サファイア基板の裏面の算術平均粗さRa0.4〜1.5μm、基板面内の算術平均粗さRaのバラツキ0.4μm以下を得るためには、平均粒径1〜80μmの砥粒を用いることが必要であり、砥粒粒径のバラツキが30μm以下の砥粒を用いる必要がある。砥粒粒径にバラツキを生じると両面ラッピング工程にて得られる表面すなわち、片面鏡面単結晶サファイア基板の裏面の算術平均粗さRaにバラツキを生じることになる。 FIG. 3 is a diagram schematically showing a double-sided lapping process of the single crystal sapphire substrate 11 of the present invention. Wrapping while letting. Regarding the loose abrasive grains 31, since the sapphire substrate has a high hardness, it is necessary to use a material having a hardness as high as possible. Specifically, at least one of SiC, B 4 C, glass beads, alumina, and diamond abrasive grains is used. Since the arithmetic average roughness Ra of the surface obtained by lapping is defined by the particle size of the free abrasive grains, the arithmetic average roughness Ra of the single-sided mirror single crystal sapphire substrate in the present invention is 0.4 to 1.5 μm, In order to obtain an arithmetic average roughness Ra variation of 0.4 μm or less in the substrate surface, it is necessary to use abrasive grains having an average particle diameter of 1 to 80 μm, and abrasive grains having an abrasive grain diameter variation of 30 μm or less. Must be used. When the abrasive grain size varies, the arithmetic average roughness Ra of the surface obtained by the double-sided lapping process, that is, the back surface of the single-sided mirror single crystal sapphire substrate, varies.

上記両面ラッピング加工実施後、基板表面に付着した砥粒、加工屑、定盤成分等を洗浄にて除去した後、加工歪除去の目的で熱処理を実施する。この熱処理は酸化、還元、真空いずれの雰囲気下でも可能であるが、各処理雰囲気により、裏面の面状態に差が生じ、それが透過率に影響を及ぼす。同一の熱処理条件であっても熱処理の雰囲気条件により、基板裏面状態に差が生じ透過率に影響する。また、同一雰囲気下であっても処理条件により面状態に差が生じ、同様に透過率に差を生じさせる。このため、透過率を低く且つバラツキを低減させるためには、ラッピング加工後の熱処理雰囲気および条件を適切に設定する必要がある。   After carrying out the above double-sided lapping processing, after removing abrasive grains, processing chips, surface plate components, etc. adhering to the substrate surface by washing, heat treatment is carried out for the purpose of removing processing strain. This heat treatment can be performed in any atmosphere of oxidation, reduction, and vacuum, but depending on each treatment atmosphere, a difference occurs in the surface state of the back surface, which affects the transmittance. Even under the same heat treatment conditions, a difference occurs in the back surface state of the substrate due to the atmospheric conditions of the heat treatment, which affects the transmittance. Further, even under the same atmosphere, a difference occurs in the surface state depending on the processing conditions, and similarly, a difference occurs in the transmittance. For this reason, in order to reduce the transmittance and reduce variations, it is necessary to appropriately set the heat treatment atmosphere and conditions after lapping.

上記の熱処理工程後、一方の主面に対してコロイダルシリカ等の研磨材を用いて鏡面加工を実施し、表面への汚染を除去する目的で精密洗浄を実施することにより、本発明の単結晶サファイア基板11を得ることができる。   After the above heat treatment step, one main surface is mirror-finished using an abrasive such as colloidal silica and precision cleaning is performed for the purpose of removing contamination on the surface. A sapphire substrate 11 can be obtained.

本発明の実施例として、直径φ2インチ、厚み0.430mmの片面鏡面の単結晶サファイア基板であって、透過率が200〜600nmの領域で、6%±0.5%の単結晶サファイア基板11を以下に作製した。   As an example of the present invention, a single-crystal sapphire substrate having a diameter of 2 inches and a thickness of 0.430 mm and having a single-sided mirror surface and having a transmittance of 200 to 600 nm is 6% ± 0.5%. Was prepared as follows.

まず、所定の面方位に切り出し外形を整えた単結晶サファイア基板を遊離砥粒にて両面ラッピング加工を実施した。この時、砥粒は平均粒径65μmのBC砥粒を使用し、60μmの加工を実施した。 First, a single crystal sapphire substrate cut into a predetermined plane orientation and trimmed in outer shape was subjected to double-sided lapping with free abrasive grains. At this time, B 4 C abrasive grains having an average particle diameter of 65 μm were used as the abrasive grains, and processing of 60 μm was performed.

ラッピング加工後、単結晶サファイア基板をアルカリ洗剤・純水にて洗浄を実施し、真空炉にて熱処理を実施した。その後、主面をダイヤ等を用いて粗研磨加工を実施した後、コロイダルシリカを用いた機械化学研磨を実施した。   After the lapping process, the single crystal sapphire substrate was washed with an alkaline detergent / pure water and heat-treated in a vacuum furnace. Thereafter, the main surface was subjected to rough polishing using a diamond or the like, and then subjected to mechanical chemical polishing using colloidal silica.

このようにして得られた片面鏡面の単結晶サファイア基板11の他方の主面13の算術平均粗さRaは、基板間および基板面内ともにRa0.8±0.15μmの範囲内であり、透過率においては200〜600nmにおいて6%前後となっており、面内のバラツキに関しては±0.5%以下となった。   The arithmetic average roughness Ra of the other principal surface 13 of the single-sided mirror single-crystal sapphire substrate 11 thus obtained is within a range of Ra 0.8 ± 0.15 μm between the substrates and within the substrate surface. The rate was around 6% at 200 to 600 nm, and the in-plane variation was ± 0.5% or less.

本加工方法によって得られた単結晶サファイア基板11と比較例として他の方法により作成した透過率が15%で透過率の面内バラツキが12%の単結晶サファイア基板71を用い、それぞれに、図2で示した一般的なLED構造を形成し、輝度の評価を実施した。   A single crystal sapphire substrate 11 obtained by this processing method and a single crystal sapphire substrate 71 having a transmittance of 15% and an in-plane variation of transmittance of 12%, which are produced by another method as a comparative example, are used. The general LED structure shown in 2 was formed, and the luminance was evaluated.

図4(a)に発明実施例の単結晶サファイア基板11上のLEDの輝度の分布を示すように、平均48.3mcdの輝度となり、面内バラツキにおいても3%以内となっていた。一方、図4(b)に比較例の単結晶サファイア基板71上に作成したLEDの輝度の分布を示すように、平均で30.3mcdの輝度となり、面内バラツキにおいても15%を超える結果となった。次に、発光層を形成した単結晶サファイア基板11,71をバックグラインディングし、チップ化して再度輝度と輝度のバラツキの評価を実施した。   As shown in FIG. 4A, the luminance distribution of the LEDs on the single crystal sapphire substrate 11 of the inventive example, the average luminance was 48.3 mcd, and the in-plane variation was within 3%. On the other hand, as shown in FIG. 4B, the luminance distribution of the LED formed on the single crystal sapphire substrate 71 of the comparative example is 30.3 mcd on average, and the result is that the in-plane variation exceeds 15%. became. Next, the single crystal sapphire substrates 11 and 71 on which the light emitting layer was formed were back-ground, formed into chips, and evaluation of luminance and luminance variation was performed again.

図5(a)に本発明実施例のサファイア基板11上のLEDの輝度の分布を示すように、平均45.4mcdの輝度となり、面内バラツキにおいても3%以内となっていた。一方、図5(b)に比較例の他の方法により作成した透過率が15%で透過率の面内バラツキが12%の単結晶サファイア基板71上に作成したLEDの輝度を示すように平均で40.1mcdの輝度となり、面内バラツキにおいても15%を超える結果となった。   As shown in FIG. 5 (a), the luminance distribution of the LEDs on the sapphire substrate 11 of the embodiment of the present invention has an average luminance of 45.4 mcd, and the in-plane variation is within 3%. On the other hand, FIG. 5B shows an average so as to indicate the luminance of the LED prepared on the single crystal sapphire substrate 71 having a transmittance of 15% and an in-plane variation of the transmittance of 12%, which is created by another method of the comparative example. The luminance was 40.1 mcd, and the in-plane variation was more than 15%.

以上のように本発明の単結晶サファイア基板を用いることにより、成膜後輝度判定時に輝度低下を生じることを防止でき、窒化物半導体発光層形成時に輝度のバラツキの低減を図ることができる。   As described above, by using the single crystal sapphire substrate of the present invention, it is possible to prevent a decrease in luminance when determining luminance after film formation, and to reduce variation in luminance when forming a nitride semiconductor light emitting layer.

窒化物半導体発光素子に適した単結晶サファイア基板を提供することができる。   A single crystal sapphire substrate suitable for a nitride semiconductor light emitting device can be provided.

本発明の単結晶サファイア基板を用いた窒化物半導体素子を示す断面図である。It is sectional drawing which shows the nitride semiconductor element using the single crystal sapphire substrate of this invention. 本発明の窒化物半導体発光素子の一例である青色LED素子の構成を示す断面図である。It is sectional drawing which shows the structure of the blue LED element which is an example of the nitride semiconductor light-emitting element of this invention. 単結晶サファイア基板の両面ラッピング工程を示す模式図である。It is a schematic diagram which shows the double-sided lapping process of a single crystal sapphire substrate. (a)(b)は単結晶サファイア基板に窒化物半導体発光素子を形成したときの輝度を示す図である。(A) (b) is a figure which shows the brightness | luminance when a nitride semiconductor light-emitting device is formed in a single crystal sapphire substrate. (a)(b)は単結晶サファイア基板に窒化物半導体発光素子を形成し、素子化した後の輝度を示す図である。(A) and (b) are the figures which show the brightness | luminance after forming the nitride semiconductor light-emitting device in a single crystal sapphire substrate, and making it into a device. 従来の窒化物半導体発光素子の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional nitride semiconductor light-emitting device. 単結晶サファイア基板上に形成した窒化物半導体発光素子の光漏れを示す断面図である。It is sectional drawing which shows the light leakage of the nitride semiconductor light-emitting device formed on the single crystal sapphire substrate.

符号の説明Explanation of symbols

11:単結晶サファイア基板
12:一方の主面
13:他方の主面
14:バッファ層
15:窒化物半導体結晶層
16:発光層
21:低温バッファ層
22:n型GaNコンタクト層
23:n型電極
24:n型AlGaNクラッド層
25:GaN系半導体層
26:p型AlGaNクラッド層
27:p型GaNコンタクト層
28:p型電極
31:遊離砥粒
32:ラッピング定盤
61:単結晶サファイア基板
62:低温バッファ層
63:多重層
64:n型GaN層
65:n型電極
66:SiドープAl0.1Ga0.9Nn層
67:活性層
68:マグネシウムドープAl0.1Ga0.9Np層
69:SiO
70:p型電極
71:単結晶サファイア基板
72:低温バッファ層
73:窒化物半導体結晶層
74:光の漏れ
11: single crystal sapphire substrate 12: one main surface 13: the other main surface 14: buffer layer 15: nitride semiconductor crystal layer 16: light emitting layer 21: low temperature buffer layer 22: n-type GaN contact layer 23: n-type electrode 24: n-type AlGaN cladding layer 25: GaN-based semiconductor layer 26: p-type AlGaN cladding layer 27: p-type GaN contact layer 28: p-type electrode 31: loose abrasive 32: lapping platen 61: single crystal sapphire substrate 62: Low temperature buffer layer 63: Multiple layer 64: n-type GaN layer 65: n-type electrode 66: Si-doped Al 0.1 Ga 0.9 Nn layer 67: active layer 68: magnesium-doped Al 0.1 Ga 0.9 Np layer 69: SiO 2 layer 70: p-type electrode 71: single crystal sapphire substrate 72: low-temperature buffer layer 73: nitride semiconductor crystal layer 74: light leakage

Claims (3)

一方の主面の算術平均粗さRaが0.4〜1.5μmであり、該一方の主面における算術平均粗さの面内バラツキが0.4μm以下であって、200〜600nmの波長域の光に対する透過率が10%以下である単結晶サファイア基板の製造方法であって、
単結晶サファイア基板の両主面を、砥粒を用いてラッピングするラッピング工程と、
前記単結晶サファイア基板の前記両主面から砥粒を除去する除去工程と、
前記単結晶サファイア基板を熱処理する熱処理工程と、
前記単結晶サファイア基板の他方の主面を鏡面研磨する研磨工程と
を有し、
前記砥粒の平均粒径が1〜80μmであり、前記砥粒の平均粒径のバラツキが、30μm以下であることを特徴とする単結晶サファイア基板の製造方法。
The arithmetic average roughness Ra of one main surface is 0.4 to 1.5 μm, the in-plane variation of the arithmetic average roughness of the one main surface is 0.4 μm or less, and a wavelength region of 200 to 600 nm A method for producing a single crystal sapphire substrate having a light transmittance of 10% or less,
A lapping step of lapping both main surfaces of the single crystal sapphire substrate using abrasive grains;
A removal step of removing abrasive grains from the two main surfaces of the single crystal sapphire substrate;
A heat treatment step of heat treating the single crystal sapphire substrate;
A polishing step of mirror-polishing the other main surface of the single crystal sapphire substrate;
Have
The method for producing a single crystal sapphire substrate, wherein the average grain size of the abrasive grains is 1 to 80 μm, and the variation of the average grain diameter of the abrasive grains is 30 μm or less.
前記砥粒は、SiC又はBThe abrasive grains are SiC or B 4 Cである請求項1に記載の単結晶サファイア基板の製造方法。The method for producing a single crystal sapphire substrate according to claim 1, which is C. 窒化物半導体発光素子の製造方法であって、A method for manufacturing a nitride semiconductor light emitting device, comprising:
一方の主面の算術平均粗さRaが0.4〜1.5μmであり、該一方の主面における算術平均粗さの面内バラツキが0.4μm以下であって、200〜600nmの波長域の光に対する透過率が10%以下である単結晶サファイア基板を製造する基板製造工程と、The arithmetic average roughness Ra of one main surface is 0.4 to 1.5 μm, the in-plane variation of the arithmetic average roughness of the one main surface is 0.4 μm or less, and a wavelength region of 200 to 600 nm A substrate manufacturing process for manufacturing a single crystal sapphire substrate having a light transmittance of 10% or less;
前記単結晶サファイア基板の他方の主面にAlGaNのバッファ層を形成するバッファ層形成工程とA buffer layer forming step of forming an AlGaN buffer layer on the other main surface of the single crystal sapphire substrate;
前記バッファ層上に窒化物半導体結晶層を形成する結晶層形成工程とA crystal layer forming step of forming a nitride semiconductor crystal layer on the buffer layer;
を有し、Have
前記基板製造工程は、The substrate manufacturing process includes
前記単結晶サファイア基板の両主面を、砥粒を用いてラッピングするラッピング工程と、A lapping step of lapping both main surfaces of the single crystal sapphire substrate using abrasive grains;
前記単結晶サファイア基板の前記両主面から砥粒を除去する除去工程と、A removal step of removing abrasive grains from the two main surfaces of the single crystal sapphire substrate;
前記単結晶サファイア基板を熱処理する熱処理工程と、A heat treatment step of heat treating the single crystal sapphire substrate;
前記単結晶サファイア基板の前記他方の主面を鏡面研磨する研磨工程とA polishing step of mirror-polishing the other main surface of the single crystal sapphire substrate;
を有し、前記砥粒の平均粒径が1〜80μmであり、前記砥粒の平均粒径のバラツキが、30μm以下であることを特徴とする窒化物半導体発光素子の製造方法。The average particle size of the abrasive grains is 1 to 80 μm, and the variation of the average particle size of the abrasive grains is 30 μm or less.
JP2004092239A 2004-03-26 2004-03-26 Method for manufacturing single crystal sapphire substrate and method for manufacturing nitride semiconductor light emitting device Expired - Fee Related JP4583060B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004092239A JP4583060B2 (en) 2004-03-26 2004-03-26 Method for manufacturing single crystal sapphire substrate and method for manufacturing nitride semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004092239A JP4583060B2 (en) 2004-03-26 2004-03-26 Method for manufacturing single crystal sapphire substrate and method for manufacturing nitride semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JP2005277334A JP2005277334A (en) 2005-10-06
JP4583060B2 true JP4583060B2 (en) 2010-11-17

Family

ID=35176625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004092239A Expired - Fee Related JP4583060B2 (en) 2004-03-26 2004-03-26 Method for manufacturing single crystal sapphire substrate and method for manufacturing nitride semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JP4583060B2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2673662C (en) 2006-12-28 2012-07-24 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US8740670B2 (en) 2006-12-28 2014-06-03 Saint-Gobain Ceramics & Plastics, Inc. Sapphire substrates and methods of making same
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129928A (en) * 1995-08-31 1997-05-16 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2002305323A (en) * 2000-07-03 2002-10-18 Nichia Chem Ind Ltd n-TYPE NITRIDE SEMICONDUCTOR LAMINATE AND SEMICONDUCTOR DEVICE USING IT

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129928A (en) * 1995-08-31 1997-05-16 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2002305323A (en) * 2000-07-03 2002-10-18 Nichia Chem Ind Ltd n-TYPE NITRIDE SEMICONDUCTOR LAMINATE AND SEMICONDUCTOR DEVICE USING IT

Also Published As

Publication number Publication date
JP2005277334A (en) 2005-10-06

Similar Documents

Publication Publication Date Title
JP4849296B2 (en) GaN substrate
US8062960B2 (en) Compound semiconductor device and method of manufacturing compound semiconductor device
JP5552627B2 (en) Internally modified substrate for epitaxial growth, crystal film formed by using the same, device, bulk substrate, and manufacturing method thereof
CN100517583C (en) Production method of compound semiconductor device wafer, wafer produced thereby and device
JP4862442B2 (en) Method for manufacturing group III-V nitride semiconductor substrate and method for manufacturing group III-V nitride device
US9431489B2 (en) β-Ga2O3-based single crystal substrate
US9105472B2 (en) Single-crystal substrate,single-crystal substrate having crystalline film,crystalline film,method for producing single-crystal substrate having crystalline film,method for producing crystalline substrate,and method for producing element
WO2018198718A1 (en) Semiconductor wafer, and method for polishing semiconductor wafer
US9349915B2 (en) β-Ga2O3-based single crystal substrate
KR20060127752A (en) Damage evaluation method of compound semiconductor member, production method of compound semiconductor member, gallium nitride compound semiconductor member, and gallium nitride compound semiconductor membrane
TW201638378A (en) Group iii nitride laminate and light emitting element comprising said laminate
JP4583060B2 (en) Method for manufacturing single crystal sapphire substrate and method for manufacturing nitride semiconductor light emitting device
JP2006179898A (en) Gallium nitride semiconductor and method for manufacturing same
JP2008211040A (en) Single crystal sapphire substrate, its manufacturing method, and semiconductor light emitting element using them
JP5828993B1 (en) Composite substrate and functional element
KR101172364B1 (en) GaN SINGLE-CRYSTAL SUBSTRATE AND METHOD FOR PROCESSING SURFACES OF GaN SINGLE-CRYSTAL SUBSTRATE
JP4899911B2 (en) Group III nitride semiconductor substrate
WO2022004046A1 (en) Free-standing substrate for epitaxial crystal growth, and functional element
JP6856356B2 (en) Aluminum nitride single crystal substrate and method for manufacturing the single crystal substrate
JP2002329665A (en) Method for manufacturing unit substrate composed of nitride semiconductor
WO2017216997A1 (en) Nitride semiconductor template, method for producing nitride semiconductor template, and method for producing nitride semiconductor freestanding substrate
CN106536794B (en) Gallium nitride substrate
JP2013010681A (en) Gallium nitride substrate, light emitting element, field effect transistor, and method for producing epitaxial film
JP4964430B2 (en) Semiconductor element forming substrate, epitaxial wafer, and semiconductor element and semiconductor device using them
JP5624317B2 (en) AlN member for compound semiconductor vapor phase growth apparatus and compound semiconductor manufacturing method using the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070213

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090724

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090804

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091005

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100803

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100831

R150 Certificate of patent or registration of utility model

Ref document number: 4583060

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130910

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees