JP2015130587A - A/d converter and a/d conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter and an A/D conversion method, which can obtain output data derived from compensation of data even when an erroneous decision occurs in the data due to redundancy while suppressing an increase in a circuit size and an increase in power consumption.SOLUTION: An A/D converter which receives an analog input voltage Vi and repeats A/D conversion by at least 2 bits a plurality of times to perform a plurality of times of A/D conversion with successively increasing density to output digital data comprises: a plurality of comparators CMP1, CMP2, CMP3 for determining the analog input voltage; and redundancy control parts 4, 5 for detecting determination completion of the analog input voltage by the plurality of comparators in first determination of performing A/D conversion of the analog input voltage on a high-order bit side and performing redundancy control by specifying the first comparator CMP1 which provides redundancy in second determination subsequent to the first determination.

Description

  The embodiment referred to in this application relates to an A / D converter (Analog-to-Digital Converter) and an A / D conversion method.

  In recent years, A / D converters are widely used in various fields. As an A / D conversion method, for example, a method of completing A / D conversion at a time, such as a flash type (parallel comparison type). In addition, there is a method of gradually specifying a range by repeating small bit A / D conversion.

  A sub-ranging type A / D converter is known as an A / D converter that repeats such a small bit A / D conversion and gradually specifies a range. This sub-ranging A / D converter performs, for example, 4-bit A / D conversion in a stepwise manner, firstly using the upper 2 bits as a rough decision and then using the lower 2 bits as a fine decision.

  A successive approximation register (SAR) type A / D converter that repeatedly performs A / D conversion of 1 bit or small bit from the most significant bit side to the least significant bit side, and gradually specifies the range. Has also been proposed.

  This SAR type A / D converter can be realized with a relatively simple circuit configuration, has high compatibility with the CMOS process, and can be manufactured at a relatively low cost.

  By the way, conventionally, various A / D converters have been proposed.

Japanese Patent Laid-Open No. 10-209870 JP 2009-302716 A Japanese Patent Laid-Open No. 06-085677 JP 2010-045579 A JP 2005-136540 A

Hyeok-Ki Hong et al., "A 7b 1GS / s 7.2mW Nonbinary 2b / cycle SAR ADC with Register-to-DAC Direct Control," 978-1-4673-1556-2 / 12, IEEE, September 2012 (Custom Integrated Circuits Conference (CICC), 2012 IEEE) Kentaro Yoshioka et al., "An 8bit 0.35-0.8V 0.5-30MS / s 2bit / step SAR ADC with Wide Range Threshold Configuring Comparator," ESSCIRC, pp.381-384, IEEE, September 2012 Joshua J. Kang et al., "A 12b 11MS / s Successive Approximation ADC with two comparators in 0.13μm CMOS," Symposium on VLSI Circuits Digest of Technical Papers, pp.240-241, June 2009

  As described above, in the sub-ranging A / D converter, for example, in the coarse determination of the upper 2 bits, if there is a determination error (offset) in the comparator that compares the analog input voltage and the reference voltage, an erroneous determination is made. There is a risk of doing it.

  Specifically, for example, if it is determined that the upper 2 bits of the digital data by the coarse determination obtained by performing A / D conversion of the input voltage is correctly “01” as “00” due to the offset of the comparator, etc. It is difficult to correct the digital data of the lower 2 bits in the determination. That is, even if the low-order 2-bit digital data by the fine determination becomes “11”, the high-order 2-bit digital data by the rough determination is not corrected to “01”.

  For this reason, it is conceivable to set the redundancy range in consideration of the offset of the comparator. However, since a comparator for the redundancy range is additionally provided, the circuit scale and power consumption of the A / D converter are reduced. Since it increases, it is not preferable.

  According to one embodiment, an A / D converter that receives an analog input voltage, repeats A / D conversion of at least 2 bits a plurality of times, gradually performs A / D conversion, and outputs digital data. An A / D converter having a plurality of comparators and a redundancy control unit is provided.

  The plurality of comparators determine the analog input voltage. In the first determination for performing A / D conversion on the higher-order bit side of the analog input voltage, the redundancy control unit detects completion of determination of the analog input voltage by the plurality of comparators. Further, in the second determination performed after the first determination, the redundancy control unit performs redundancy control by specifying a first comparator having redundancy.

  The disclosed A / D converter and A / D conversion method can suppress the increase in circuit scale and power consumption, and can provide output data that compensates for the data even if there is an erroneous determination by providing redundancy. There is an effect.

FIG. 1 is a diagram for explaining an example of an A / D converter. FIG. 2 is a block diagram showing a first embodiment of the A / D converter. FIG. 3 is a diagram for explaining the operation of the A / D converter shown in FIG. FIG. 4 is a diagram illustrating an example of a comparator in the A / D converter illustrated in FIG. FIG. 5 is a diagram for explaining the determination operation of the comparator shown in FIG. FIG. 6 is a diagram (part 1) for explaining the operation of the A / D converter when the comparator has an offset. FIG. 7 is a diagram (part 2) for explaining the operation of the A / D converter when the comparator has an offset. FIG. 8 is a block diagram showing a second embodiment of the A / D converter. FIG. 9 is a diagram illustrating an example of a comparator in the A / D converter illustrated in FIG. FIG. 10 is a diagram (No. 1) for explaining the operation of the CDAC in the A / D converter shown in FIG. FIG. 11 is a diagram (No. 2) for explaining the operation of the CDAC in the A / D converter shown in FIG.

  First, before describing embodiments of the A / D converter and the A / D conversion method in detail, an example of the A / D converter and a problem in the A / D converter will be described with reference to FIG. .

  FIG. 1 is a diagram for explaining an example of an A / D converter. Here, FIG. 1A is for explaining the operation of a general sub-ranging type A / D converter, and converts the analog input voltage Vi into 4-bit digital data. Show the case. FIG. 1B is for explaining the operation of the A / D converter provided with a redundancy range (having redundancy).

  As shown in FIG. 1A, when the analog input voltage Vi is converted into 4-bit digital data, the input voltage Vi is first sampled. Further, rough judgment is performed using three comparators CMP1, CMP2, and CMP3 which receive different reference voltages (for example, voltages obtained by dividing the full scale VREF0 to VREF4 into four equal parts) VREF1, VREF2, and VREF3.

  By this rough determination, the upper 2 bits of digital data obtained by A / D converting the analog input voltage Vi are obtained. In the example of FIG. 1A, the upper 2 bits of digital data are obtained as “01”.

  That is, in FIG. 1A, since the input voltage Vi is between the reference voltages VREF1 and VREF2, the comparators CMP2 and CMP3 output “0” (the input voltage Vi is lower than the reference voltages VREF2 and VREF3). The comparator CMP1 outputs “1” (the input voltage Vi is higher than the reference voltage VREF1).

  Next, a reference voltage is selected, and finer (higher resolution) dense determination is performed. For example, the reference voltages VREF11, VREF12, and VREF13 obtained by dividing the voltage range from the reference voltages VREF1 to VREF2 into four equal parts are selected, and three comparators CMP1, CMP2, and CMP3 that receive the reference voltages VREF11, VREF12, and VREF13 are used. Finer A / D conversion (fine determination) is performed.

  In FIG. 1A, since the input voltage Vi is between the reference voltages VREF12 and VREF13, the comparator CMP3 outputs “0” and the comparators CMP2 and CMP1 output “1” in the fine determination. Therefore, the lower 2 bits are “10”, and the analog input voltage Vi is converted to 4-bit digital data “0110”. Note that after the dense determination is performed, the next sampling is performed.

  In this way, in the sub-ranging A / D converter, for example, the range (the reference voltage range of two comparators including Vi) in which the determination result is switched by 0/1 due to the upper determination (coarse determination) is narrowed down. Within the narrowed down range, a lower level determination (fine determination) is performed to obtain finer digital data. That is, A / D conversion of upper 2 bits is performed as a rough determination in the first step, and then A / D conversion of lower 2 bits is performed as a fine determination in the second step.

  However, in the A / D converter described with reference to FIG. 1A, for example, when the potential difference between the input voltage Vi and the determination voltage of the comparator is small, if the comparator has an offset, an erroneous determination is caused. It will be.

  Specifically, when the input voltage Vi is higher than the reference voltage VREF1 of the comparator CMP1 in the rough determination (when the determination is “1”), for example, it is determined that it is erroneously lower than the reference voltage VREF1 due to the offset of the comparator CMP1 ( If the determination is “0”), it is difficult to correct by the determination based on the dense determination. In particular, if the upper bit is erroneously determined due to a comparator offset or the like and the lower A / D conversion range is wrong, the linearity of the A / D conversion result near the input voltage Vi is deteriorated.

  FIG. 1B shows a redundant range for such a problem. That is, in FIG. 1B, in the dense determination, for example, a comparison is made to provide a redundant range (to provide redundancy) for each of the reference voltages VREF1 (low potential side) and VREF2 (high potential side). The devices CMP0 and CMP4 have been added.

  That is, for example, in the determination of the low-order bits (fine determination), the offset is set to the size of the redundancy range by determining the voltage levels VREF1 and VREF2 so that the reference voltages of the two comparators CMP0 and CMP4 overlap outward. It is possible to allow it.

  However, in the A / D converter shown in FIG. 1B, for example, a redundant range that always overlaps the outside of the two comparators CMP1 and CMP3 is set, and the input voltage Vi is within the redundant range. Comparators CMP0 and CMP4 for determining whether or not are added. This leads to an increase in circuit and power consumption.

  Further, for example, when the input voltage Vi and the reference voltage VREF1 are Vi≈VREF1, the redundancy on the reference voltage VREF1 side is very significant in order to reduce the influence of the offset of the comparator CMP1. However, regarding the redundancy on the reference voltage VREF2 side, Vi <VREF2 is sufficiently satisfied, and there is no influence of the offset of the comparator CMP2, which is wasted.

  Hereinafter, embodiments of an A / D converter and an A / D conversion method will be described in detail with reference to the accompanying drawings. In this specification, in order to simplify the description, a 2-bit / step-successive comparison (SAR) type A / D converter will be described as an example. The present invention can also be applied to a SAR type A / D converter.

  FIG. 2 is a block diagram showing a first embodiment of the A / D converter, and shows a 2-bit / step SAR type A / D converter. In FIG. 2, reference numeral 1 is a switch, 2 is a capacitive D / A converter (CDAC), 3 is a SAR control logic, 4 is a determination time detection circuit, and 5 is a reference voltage control circuit. Here, the determination time detection circuit 4 and the reference voltage control circuit 5 form a redundancy control unit.

  The switch 1 controls whether or not the analog input voltage Vi is input to the CDAC 2, and the CDAC 2 has a sample and hold function for the input voltage Vi by a plurality of capacitors and switches, and redistributes the charge to voltage Va. Is output.

  That is, the SAR control logic 3 receives the outputs of the comparators CMP1, CMP2, and CMP3, and outputs a control signal based on the determination result (digital data) to the CDAC2. Based on the control signal from the SAR control logic 3, the CDAC 2 outputs a voltage Va suitable for the next step (A / D conversion process).

  Here, the CDAC 2 and the SAR control logic 3 can be applied in various known configurations, and have a single-ended configuration, as will be described in detail later with reference to FIGS. However, a differential configuration can also be applied.

  Further, since the A / D converter shown in FIG. 2 performs 2-bit A / D conversion simultaneously in one A / D conversion process (1 step), the CDAC 2 and the SAR control logic 3 are 2 bits / step. A voltage Va suitable for A / D conversion is output.

  Here, as described above, the A / D converter of the first embodiment is not limited to the one of 2 bits / step and can be applied to an A / D converter of 3 bits / step or more. For example, when applied to a 3-bit / step A / D converter, the three comparators CMP1 to CMP3 shown in FIG. 2 are further provided (for example, seven).

  The output voltage Va (Vi) of CDAC2 is given to one input of three comparators CMP1 to CMP3, and the reference voltage from the reference voltage control circuit 5 is given to the other input of each comparator CMP1 to CMP3. It is done.

  Here, the reference voltage control circuit 5 generates a reference voltage based on the determination times of the comparators CMP1 to CMP3 determined by the determination time detection circuit 4, and supplies the reference voltages to the other inputs of the comparators CMP1 to CMP3. give.

  FIG. 3 is a diagram for explaining the operation of the A / D converter shown in FIG. 2. The operation of the 2-bit / step SAR type A / D converter of the first embodiment is expressed as analog input voltage Vi. This is for explanation based on the relationship between the reference voltages VREF1 and VREF2.

  Here, FIGS. 3A to 3C show the input voltage Vi and the reference voltage in the first determination operation (first determination: equivalent to the rough determination in FIGS. 1A and 1B). Based on the relationship between VREF1 and VREF2, the second determination operation (second determination: equivalent to fine determination) will be described. That is, FIG. 3A shows the case of Vi≈VREF1, FIG. 3B shows the case where Vi is in the middle of VREF1 and VREF2, and FIG. 3C shows that Vi≈VREF2. Show the case.

  First, in the first determination (first determination) in which the analog input voltage Vi is A / D converted to obtain upper 2 bits of digital data, when Vi is in the middle of VREF1 and VREF2, it is shown in FIG. As shown, reference voltages VREF11 to VREF13 similar to those in FIG.

  That is, if it is detected (recognized) that Vi is near the middle of VREF1 and VREF2 by the first determination (second determination), for example, an erroneous determination is made by the determination error (offset) of the comparators CMP1 and CMP2. It is determined that there is no risk of incurring and it is not necessary to provide redundancy.

  Here, the relationship between the input voltage Vi (the output voltage Va of CDAC2) and the voltage levels of the reference voltages VREF1 and VREF2 can be recognized from the determination times of the comparators CMP1 and CMP2 detected by the determination time detection circuit 4, for example. it can. The relationship between Vi (Va) and the voltage levels of VREF1 and VREF2 will be described in detail later with reference to FIGS.

  Therefore, as shown in FIG. 3B, in the second determination, for example, reference voltages VREF11, VREF12, and VREF13 obtained by dividing the voltage range from the reference voltages VREF1 to VREF2 into four equal parts are generated, and the comparators CMP1, Comparison (determination) processing is performed by giving the other input of CMP2 and CMP3.

  Next, as shown in FIG. 3A, when the determination time detection circuit 4 recognizes that Vi≈VREF1 by the first determination, the comparator CMP1 that makes the determination based on the reference voltage VREF1 is used. Set the redundancy range.

  That is, when Vi≈VREF1 is determined by the first determination, the reference voltages VREF11, VREF12, and VREF13 in FIG. 3B are shifted to the low potential side by Vr / k, and the reference voltages VREF11a, VREF12a, and VREF13a are compared. Judgment processing is given to the other inputs of the devices CMP1, CMP2, and CMP3. Here, Vr represents the absolute value of the difference between VREF1 and VREF2. When Vi≈VREF1, it is not necessary to set a redundancy range for the comparator CMP2 that performs determination based on the reference voltage VREF2.

Therefore, as shown in FIG. 3A, the reference voltages VREF11a to VREF13a given to the other inputs of the comparators CMP1 to CMP3 when Vi≈VREF1 can be expressed as follows. Here, k changes according to the number of determination operations, that is, according to the fineness (resolution) of A / D conversion, for example, 4, 16, 64,... In the case of 2 bits / step.
VREF11a = VREF11-Vr / k
VREF12a = VREF12-Vr / k
VREF13a = VREF13-Vr / k

  Thus, in the case of Vi≈VREF1, the reference voltage VREF11, VREF12, VREF13 used in the normal second determination is shifted to the low potential side by Vr / k, so that the redundancy in the vicinity of VREF1 by the comparator CMP1 is obtained. It becomes possible to have.

  On the contrary, as shown in FIG. 3C, when the determination time detection circuit 4 recognizes that Vi≈VREF2 by the first determination, the comparator CMP2 that performs the determination based on the reference voltage VREF2 Set the redundancy range. When Vi≈VREF2, it is not necessary to set a redundancy range for the comparator CMP1 that makes a determination based on the reference voltage VREF1.

  That is, when Vi≈VREF2 is determined by the first determination, the reference voltages VREF11, VREF12, and VREF13 in FIG. 3B are shifted to the high potential side by Vr / k, and the reference voltages VREF11c, VREF12c, and VREF13c are compared. Judgment processing is given to the other inputs of the devices CMP1, CMP2, and CMP3.

Therefore, as shown in FIG. 3C, the reference voltages VREF11c to VREF13c given to the other inputs of the comparators CMP1 to CMP3 when Vi≈VREF2 can be expressed as follows.
VREF11c = VREF11 + Vr / k
VREF12c = VREF12 + Vr / k
VREF13c = VREF13 + Vr / k

  As described above, when Vi≈VREF2, the reference voltage VREF11, VREF12, VREF13 used in the normal second determination is shifted to the high potential side by Vr / k, so that the redundancy in the vicinity of VREF2 by the comparator CMP2 is obtained. It becomes possible to have.

  In the above, when the analog input voltage Vi is Vi≈VREF1 in FIG. 3A or Vi≈VREF2 in FIG. 3C, the reference voltages VREF11 to VREF13 in FIG. 3B are shifted. The voltage level (width) is not limited to Vr / k.

  That is, the voltage level for shifting the reference voltages VREF11 to VREF13 is set to the width (Vr / k) of one bit of the least significant bit (LSB) for A / D conversion in the determination process (each A / D conversion step). It is not limited and can be set to an optimum size.

  Thus, according to the A / D converter of the first embodiment, for example, without adding a comparator for providing redundancy as described with reference to FIG. Redundancy can be provided to a comparator that may cause an erroneous determination due to the offset of the comparator.

  In other words, according to the A / D converter of the first embodiment, even if there is a misjudgment with redundancy while suppressing an increase in circuit scale and power consumption without providing an additional comparator, the data Can be obtained.

  FIG. 4 is a diagram illustrating an example of a comparator in the A / D converter illustrated in FIG. As shown in FIG. 4, the comparators CMP1, CMP2, and CMP3 in the A / D converter of FIG. 2 have the same circuit configuration, pMOS transistors TP1, TP2, nMOS transistors TN1 to TN4, and switches SW1 to SW1, respectively. SW3 is included. Here, the reference symbol Vdd indicates a high potential power supply line, and Vss indicates a low potential power supply line (ground).

  Here, the transistors TP1, TN1 and TP2, TN2 are latches in which the input and output of the two inverters are cross-connected, and are latched together with the differential pair transistors TN3, TN4 whose input voltage Vi and reference voltage VREFx are input to the gate A differential amplifier having a function is formed.

  The switches SW1 and SW2 are connected in parallel between the source and drain of the transistors TP1 and TP2, respectively, and are turned off when determining (comparing) the input voltage Vi and the reference voltage VREFx. On the other hand, the switch SW3 is provided between the commonly connected source of the differential pair transistors TN3 and TN4 and the low-potential power line Vss, and is turned on when determining the input voltage Vi and the reference voltage VREFx.

  For example, in the comparator CMP1, the reference sign VREFx indicates the reference voltage VREF1 at the first determination, indicates the reference voltage VREF11 (VREF11a, VREF11c) at the second determination, and also the reference voltage after the third determination. Show.

  In the determination operation in which SW1 and SW2 are turned off and SW3 is turned on, if Vi has a voltage level higher than VREFx, the current flowing through TN3 becomes larger than the current flowing through TN4, and as a result, VQM becomes “0”. VQP becomes “1” and the state is maintained.

  Further, in the determination operation, if VREFx is higher than Vi, the current flowing through TN4 becomes larger than the current flowing through TN3. As a result, VQP becomes “0” and VQM becomes “1”. , Hold that state.

  FIG. 5 is a diagram for explaining the determination operation of the comparator shown in FIG. 4, and FIG. 5 (a) shows an example of the determination time detection circuit 4 (determination completion timing detection circuit 40). FIG. 5B shows the operation when | Vi−VREFx |> 0 by the circuit of FIG. 5A, and FIG. 5C shows | Vi−VREFx by the circuit of FIG. The operation when | ≈0 is shown.

  As shown in FIG. 5A, the determination time detection circuit 4 includes, for example, an exclusive OR (EXOR) circuit 400, and the differential outputs VQP and VQM of the comparators CMP1, CMP2, and CMP3 are different. At the level (“1”, “0”), the determination completion signal Sc is output.

  Note that the circuit shown in FIG. 5 (a) outputs a high level “1” determination completion signal Sc at the timing when the determinations are completed in the comparators CMP1, CMP2, and CMP3. Therefore, for example, in order to output the determination time itself as the determination time detection circuit 4 in FIG. 2, for example, a timer (counter) that continues counting from the timing when the switch SW3 is turned on until the timing when the determination completion signal Sc is output is also included. Will be provided.

Here, as is clear from the comparison between FIG. 5B and FIG. 5C, the determination time Δt ₁ when | Vi−VREFx |> 0 is the determination time when | Vi−VREFx | ≈0. It can be seen that it is shorter than Δt ₂ .

  That is, when | Vi−VREFx | ≈0, for example, when Vi≈VREF1 shown in FIG. 3 (a) and Vi≈VREF2 shown in FIG. 3 (c), currents flowing through the differential pair transistors TN3 and TN4 Is smaller than when | Vi−VREFx |> 0. Note that | Vi−VREFx |> 0 corresponds to, for example, when Vi shown in FIG. 3B is in the vicinity of the middle between VREF1 and VREF2.

Therefore, regarding the time (judgment time) until the differential outputs VQP and VQM (VQM and VQP) of the comparators are determined at different levels (“1” and “0”), when | Vi−VREFx | ≈0 The determination time Δt ₂ is longer than the determination time Δt _{1 of} | Vi−VREFx |> 0. That is, the determination time Δt ₁ when | Vi−VREFx |> 0 is shorter than the determination time Δt ₂ when | Vi−VREFx | ≈0.

Thus, in the A / D converter of the first embodiment shown in FIG. 2, the analog input voltage Vi of each comparator is determined from the determination time (Δt ₁ , Δt ₂ ) obtained by the determination time detection circuit 4 in the first determination. And the voltage level difference (| Vi−VREFx |) between the reference voltage VREFx and the reference voltage VREFx.

  The reference voltage control circuit 5 controls the reference voltage in the second determination based on the output of the determination time detection circuit 4, that is, the second time described with reference to FIGS. 3 (a) to 3 (c). A reference voltage is generated (shifted) in the determination.

  In the A / D converter of the first embodiment described above, the reference voltage supplied to each comparator is generated by the reference voltage control circuit 5, but this reference voltage shifts the voltage level relative to the input voltage. Can also be generated.

  FIGS. 6 and 7 are diagrams for explaining the operation of the A / D converter when the comparator has an offset, and shows an example in which A / D conversion is performed with a resolution of 6 bits. Here, FIG. 6 shows an operation when the determination time detection circuit 4 and the reference voltage control circuit 5 are stopped in the A / D converter shown in FIG. 2, and the first determination and the second determination in FIG. This corresponds to the rough judgment and fine judgment operations described with reference to FIG.

  7 shows the operation of the A / D converter shown in FIG. 2 (when the determination time detection circuit 4 and the reference voltage control circuit 5 are functioned). The first determination and the second determination in FIG. This corresponds to the rough judgment and fine judgment operations described with reference to FIG.

  6 (a) and 7 (a) show the outputs and binary results of the comparators CMP1 to CMP3 in the first to third determinations (A / D conversion processing), and FIG. 6 (b) and FIG. (b) shows the reference voltages of the comparators CMP1 to CMP3 in the first to third determinations.

  As shown in FIG. 6A and FIG. 6B, for example, in the first determination, the analog input voltage Vi is close to the reference voltage −Vr / 2 (VREF1) of the comparator CMP1, and the offset of the comparator CMP1. If it is erroneously determined by, for example, it is difficult to correct after the second determination.

  That is, when the digital data (binary result) that is correctly determined as “01” is determined as “00” in the first determination in which A / D conversion of the upper 2 bits is performed, the second determination and the third determination respectively. It determines with "11" and outputs the data of "001111".

  As described with reference to FIG. 1A, in the second determination (fine determination), the reference voltages of the comparators CMP1, CMP2, and CMP3 are -Vr and the comparator CMP1 of the first determination. The reference voltage -Vr / 2 is divided into four equal voltages -7Vr / 8, -6Vr / 8, and -5Vr / 8, and is determined to be "11".

  Further, in the third determination, the reference voltages of the comparators CMP1, CMP2, and CMP3 are the reference voltage -Vr / 2 of the comparator CMP1 for the first determination and the reference voltage -5Vr / 8 of the comparator CMP3 for the second determination. The divided voltages are -19Vr / 32, -18Vr / 32, and -17Vr / 32, and are judged as "11". That is, even if the digital data when correctly A / D converted is “0100001”, if it is erroneously determined as “00” in the first determination, data “001111” is output.

  On the other hand, according to the A / D converter of the first embodiment, as shown in FIGS. 7A and 7B, for example, in the first determination, the offset of the comparator CMP1 is used. Even if “01” is correctly determined to be “00”, it can be corrected by the second determination with redundancy.

  That is, in the second determination, the reference voltages of the comparators CMP1, CMP2, and CMP3 are equal to −Vr and the reference voltage −Vr / 2 of the comparator CMP1 of the first determination, divided into four equal voltages −7Vr / 8, −6Vr / To provide redundancy for 8 and -5Vr / 8, shift by Vr / 8.

  That is, in the first determination, the level of the input voltage Vi and the reference voltage −Vr / 2 is close (Vi≈−Vr / 2) in the comparator CMP1, for example, the determination time of the comparator CMP1 is the other comparators CMP2 and CMP3. If it is longer than this determination time, a redundant range is provided on the reference voltage side of the comparator CMP1 for the first determination.

  Specifically, for example, the voltage level Vr / 8 corresponding to the second determination LSB is shifted, and the reference voltages of the comparators CMP1, CMP2, CMP3 are set to -6Vr / 8, -5Vr / 8, -4Vr / 8. Perform the second determination. If an output of “100” (binary result) is obtained by this second determination, “00” of the first determination is changed to “01” according to the result of the lower bit determination (in this case, the second determination). And make a third determination.

  That is, a digital output “0100” is obtained by the second determination. Regarding the reference voltages of the comparators CMP1 to CMP3 in the third determination, for example, when the determination time of each comparator is short in the second determination, that is, the input voltage Vi is referred to each comparator in the second determination. In the case of a voltage level between voltages, the reference voltage is not shifted.

  Therefore, the reference voltages of the comparators CMP1, CMP2, and CMP3 in the third determination are not shifted, and the third determination is performed using -15Vr / 32, -14Vr / 32, and -13Vr / 32 as they are. .

  As described above, according to the A / D converter of the first embodiment, even when “01” is erroneously determined as “00” in the first determination, correction is performed by the second determination with redundancy. Therefore, it becomes possible to perform A / D conversion correctly as “0100001”. The effects of the A / D converter of the first embodiment are also exhibited in the A / D converter of the second embodiment described below.

  FIG. 8 is a block diagram showing a second embodiment of the A / D converter, in which the control of the reference voltage in the A / D converter of the first embodiment described above is performed as processing of the analog input voltage Vi in CDAC2. Is shown. In the A / D converter of the second embodiment, the reference voltages of the comparators CMP1, CMP2, and CMP3 are fixed to the potential of the low potential power supply line Vss (ground potential: 0V).

  As shown in FIG. 8, the A / D converter of the second embodiment includes a switch 1, a CDAC 2, a SAR control logic 3, a determination completion timing detection circuit 40 and a redundant range control circuit 6. Here, the determination completion timing detection circuit 40, the redundancy range control circuit 6, and the CDAC2 form a redundancy control unit.

  The determination completion timing detection circuit 40 detects the determination completion timing from the outputs of the comparators CMP1, CMP2, and CMP3, and outputs a determination completion signal Sc to the redundancy range control circuit 6. For example, the redundancy range control circuit 6 determines Vi≈VREF1 (FIG. 3 (a)) and Vi≈VREF2 (depending on which of the determination completion signals Sc of the comparators CMP1 and CMP2 first changes from “0” to “1”. 3 (c)) or Vi near the middle of VREF1 and VREF2 (FIG. 3 (b)), and the redundant range is selected.

  That is, if Vi≈VREF1, the input voltage Vi (input voltage Va considering the reference voltage VREFx) is shifted by Vr / k, and if Vi≈VREF2, the input voltage Vi is shifted by −Vr / k. As in the first embodiment described above, the CDAC 2 and the SAR control logic 3 can be applied to various configurations in the A / D converter of the second embodiment.

  As described above, according to the A / D converter of the second embodiment, similarly to the A / D converter of the first embodiment, an increase in circuit scale and power consumption can be achieved without providing an additional comparator. It is possible to obtain output data that compensates for misjudgment while providing redundancy.

  FIG. 9 is a diagram illustrating an example of a comparator in the A / D converter illustrated in FIG. As is clear from the comparison between FIG. 9 and FIG. 4 described above, the comparators CMP1 and CMP3 (CMP2) in the A / D converter shown in FIG. 8 are compared with the comparator shown in FIG. An A / D converter (ADC) 10 that receives the output control codes CC1 and CC3 is added.

  Here, in the three comparators CMP1, CMP2, and CMP3, for example, the circuit of FIG. 4 is applied as the comparator CMP2 that uses the reference voltage (0 V) as a reference as it is, and a predetermined voltage level (width) is used as the reference voltage. 9 can be applied as the comparators CMP1 and CMP3. Of course, the circuit of FIG. 9 may be applied to all three comparators CMP1, CMP2, and CMP3.

  The comparator shown in FIG. 9 adjusts the back gate voltages of the differential pair transistors TN3 and TN4 by the DAC 10 that receives the control codes CC1 and CC3, and controls the threshold voltages of these transistors TN3 and TN4. ing.

  That is, as described with reference to FIG. 3, for example, in the second determination, the reference voltage VREF11 (VREF11a, VREF11b) applied to the comparator CMP1 is higher than the reference voltage VREF12 (VREF12a, VREF12b) applied to the comparator CMP2. The voltage is lowered by Vr / k.

  Therefore, in the comparator CMP1, the threshold voltage of the transistor TN3 is set low by adjusting the back gate voltage VBP of the transistor TN3 output from the DAC 10 to the high potential side based on the control code CC1 from the SAR control logic 3. be able to. Further, the threshold voltage of the transistor TN4 can be set high by adjusting the back gate voltage VBM of the transistor TN4 to the low potential side.

  As a result, the comparator CMP1 receives a reference voltage having a voltage level lower than that of the comparator CMP2 in a state where the input voltage Va (Vi) having the same voltage level as that of the comparator CMP2 is applied to the gate of the transistor TN3. The same judgment (comparison) operation is performed.

  Further, in the comparator CMP3, the threshold voltage of the transistor TN3 is set high by adjusting the back gate voltage VBP of the transistor TN3 output from the DAC 10 to the low potential side based on the control code CC3 from the SAR control logic 3. be able to. Further, the threshold voltage of the transistor TN4 can be set low by adjusting the back gate voltage VBM of the transistor TN4 to the high potential side.

  As a result, the comparator CMP1 receives a reference voltage having a voltage level higher than that of the comparator CMP2 in a state where the input voltage Va (Vi) having the same voltage level as that of the comparator CMP2 is applied to the gate of the transistor TN3. The same judgment (comparison) operation is performed.

  Note that a reference voltage VREFx fixed to the ground potential (Vss) is applied to the gates of the transistors TN4 in the comparators CMP1 to CMP3. For example, regarding the shift (Vr / k, −Vr / k) of the reference voltages VREF11a to VREF13a and VREF11c to VREF13c described with reference to FIGS. This is realized by shifting (Vi) in the reverse direction. Hereinafter, the operation of the CDAC 2 will be described in detail with reference to FIGS. 10 and 11.

  10 and 11 are diagrams for explaining the operation of the CDAC in the A / D converter shown in FIG. Here, FIG. 10A shows a state where the analog input voltage Vi is sampled by turning on the switch 1 in the A / D converter shown in FIG. 8, and FIG. 10B shows the first determination. The state which is performing (1st determination) is shown. FIG. 11 (a) shows a state in which the second determination (second determination) is performed in the A / D converter shown in FIG. 8, and FIG. 11 (b) performs the third determination. Indicates the state.

  First, as shown in FIGS. 10 (a) and 10 (b) and FIGS. 11 (a) and 11 (b), the CDAC 2 in the A / D converter shown in FIG. It includes a capacitor group and a switch group whose weights are 1C, 1C, 2C, 4C, 8C, 16C, and 32C. That is, the capacitor group has a capacity of 64C (32C × 2) due to the capacitors 20-30.

  Here, the capacitance weight of each capacitor and the connection control of the fixed voltage + Vr, −Vr for covering each capacitor and the input voltage Vi and the full scale range by a plurality of switches are general. The CDACs having various configurations are also applicable.

  However, in CDAC2 applied to the A / D converter of the second embodiment, the reference voltages of the subsequent comparators CMP1 to CMP3 are fixed to the ground potential (0V), and the input voltage Va ( The reference voltage shift described above is performed on the Vi) side.

  Therefore, for example, a capacitor of weight 2C is formed by the capacitors 22 and 23 of weight 1C, and a capacitor of weight 4C is formed by the capacitor 24 of weight 1C and the capacitor 25 of weight 3C.

  Further, for example, a capacitor of weight 8C is formed by capacitors 26 and 27 of weight 4C, and a capacitor of weight 16C is formed by capacitor 28 of weight 4C and capacitor 29 of weight 12C.

  Thus, for example, when performing A / D conversion of 2 bits / step, the reference voltage VREFx applied to the comparators CMP1, CMP2, and CMP3 is shifted by + Vr / k and −Vr / k according to each step. Similar functions can be provided.

  That is, in the case of A / D conversion of 2 bits / step, k changes as 2, 8, 32, 128,..., So that a shift voltage corresponding to the k can be generated to shift the input voltage Va (Vi). In addition, the control is performed separately for a plurality of capacitors.

  Note that the shift voltage is not limited to + Vr / k and −Vr / k, and therefore the configuration of each capacitor can be variously changed. Further, the CDAC 2 may have a single-ended configuration, but may also have a differential configuration as described above.

  First, in the sample mode for sampling the analog input voltage Vi, for example, the switch 1 in FIG. 8 is turned on. Further, as shown in FIG. 10 (a), the output node N0 of CDAC2 is grounded (Vss), and all the switches SW20 to SW30 are connected to the input voltage Vi side, whereby the capacitors 20 to 30 are connected to the input. Charges due to the voltage Vi are stored.

  In the first determination of the upper 2 bits including the most significant bit (MSB), as shown in FIG. 10B, the output node N0 is removed from the ground, and the switches SW20 to SW29 are set to the positive fixed voltage + Vr side. Connect the switch SW30 to the negative fixed voltage -Vr side. As a result, the output voltage Va of CDAC2 input to the comparators CMP1 to CMP3 from the output node N0 is Va = −Vi.

  That is, in the first determination, for example, −Vi is input to the inverting input of the comparator CMP2 (CMP1, CMP3) (for example, the gate input of the transistor TN3 in FIG. 9). At this time, the non-inverting input of the comparator CMP2 (CMP1, CMP3) (for example, the gate input of the transistor TN4 in FIG. 9) is fixed to the ground (Vss: 0 V).

  However, in the comparator CMP1, for example, the reference voltage is −Vr / 2 by the output voltages VBP and VBM (back gate voltages of the transistors TN3 and TN4) of the DAC 10 according to the control code CC1 described with reference to FIG. A determination (comparison) operation equivalent to the time is performed. Further, in the comparator CMP3, for example, a determination operation equivalent to that when the reference voltage is + Vr / 2 is performed by the output voltages VBP and VBM of the DAC 10 based on the control code CC3.

  Here, the first determination is the same as that generally performed. In this first determination, for example, it is correctly determined as “01” by the offset of the comparator or the like as described above. A case where the digital data to be processed is determined to be “00” will be described.

  This is because when the input voltage Vi is close to the reference voltage VREF1 of the comparator CMP1 (| Vi−VREF1 | ≈0), that is, in this embodiment in which the input on the reference voltage side of the comparator CMP1 is grounded. This corresponds to the case of ≈−Vr / 2.

  At this time, in the A / D converter shown in FIG. 8, for example, the redundancy range control circuit 6 recognizes that the comparator that sets the redundancy range by the determination completion signal Sc from the determination completion timing detection circuit 40 is CMP1. Then, the shift voltage is controlled for CDAC2.

  That is, as shown in FIG. 11A, in the second determination, the switches SW20 to SW30 reflecting the determination results for the upper 2 bits including the most significant bit are controlled. At this time, a process for providing redundancy to the comparator CMP1 that may have made an erroneous determination is also performed.

  Specifically, when the result of A / D conversion of the upper 2 bits is “00”, the switch SW30 of the capacitor 30 with the weight 32C is switched from the −Vr side to the + Vr side, and the switches of the capacitors 26 and 27 with the weight 8C are switched. SW26 and SW27 are switched from the + Vr side to the -Vr side. As a result, the output voltage Va of the CDAC at the node N0 becomes Va = − (Vi−6Vr / 8).

  Further, in order to provide redundancy to the comparator CMP1, the switch SW28 of the capacitor 28 having the weight 4C at the weight 16C is switched from the + Vr side to the −Vr side. As a result, the output voltage Va is shifted by + Vr / 8, and Va = − (Vi−5Vr / 8). This voltage is given to the comparator CMP2 in the second determination, and compared with the ground potential (0V). Is done.

  In the second determination, the comparator CMP1 performs a determination operation equivalent to that when the reference voltage is −6 Vr / 8, for example, based on the output voltages VBP and VBM of the DAC 10 based on the control code CC1. Further, in the comparator CMP3, for example, a determination operation equivalent to that when the reference voltage is −4 Vr / 8 is performed by the output voltages VBP and VBM of the DAC 10 based on the control code CC3, for example.

  Then, for example, when “100” digital data (binary result) is obtained by the second determination, “00” by the first determination is corrected to “01”, and “0100” is obtained as the digital data until the second determination. ] Will be obtained.

  In the third determination shown in FIG. 11B, for example, in the second determination, the determination completion signal Sc of the comparators CMP1 to CMP3 is used and the determination time is approximately equal and short, that is, the comparison is erroneous. The case where there is no vessel is shown.

  That is, the switches SW24 and SW25 of the capacitors 24 and 25 at the weight 4C and the switches SW22 and SW23 of the capacitors 22 and 23 at the weight 2C are switched from the + Vr side to the −Vr side. As a result, the output voltage Va of the CDAC at the node N0 becomes Va = − (Vi−14Vr / 32).

  In the second determination, the connection of the switch SW28 of the capacitor 28 at the weight 16C connected to the −Vr side is maintained at the −Vr side. Further, in the third determination, the comparators CMP1 and CMP3 control the back gate voltage by the control codes CC1, CC3 and DAC 10 described above, and perform the determination equivalent to the determination with the reference voltage having a predetermined voltage width.

  In the above description, the A / D converter of each embodiment can be modified in various ways. For example, the CDAC can be applied in a single-ended configuration or a differential configuration, and also has redundancy. The direction can be changed in various ways.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
An A / D converter that receives an analog input voltage, repeats at least 2-bit A / D conversion a plurality of times, gradually performs fine A / D conversion, and outputs digital data,
A plurality of comparators for determining the analog input voltage;
In the first determination for performing A / D conversion on the higher bit side of the analog input voltage, the completion of determination of the analog input voltage by the plurality of comparators is detected, and in the second determination performed after the first determination, A redundancy control unit that performs redundancy control by specifying the first comparator that has redundancy, and
An A / D converter characterized by the above.

(Appendix 2)
The second determination is a determination to perform A / D conversion on the lower bit side with respect to the A / D conversion range defined by the first determination.
2. The A / D converter according to appendix 1, wherein

(Appendix 3)
The first determination is a first determination for performing A / D conversion on the upper bit side including the most significant bit,
The second determination is a second determination performed after the first determination.
The A / D converter according to Supplementary Note 1 or Supplementary Note 2, wherein

(Appendix 4)
The first determination and the second determination are 2-bit / step determinations in which the analog input voltage is A / D converted simultaneously by 2 bits.
The A / D converter according to any one of Supplementary Note 1 to Supplementary Note 3, wherein:

(Appendix 5)
A capacitive DAC having a plurality of capacitors and a plurality of switches for receiving the analog input voltage and performing charge redistribution;
SAR control logic for controlling charge redistribution in the capacitive DAC based on outputs of the plurality of comparators.
The A / D converter according to any one of Supplementary Note 1 to Supplementary Note 4, wherein:

(Appendix 6)
The redundancy control by the redundancy control unit is
In order to set the redundancy range of the first comparator, the analog input voltage and the reference voltage applied to the plurality of comparators are relatively shifted,
The A / D converter according to any one of Supplementary Note 1 to Supplementary Note 5, wherein:

(Appendix 7)
The redundancy control unit
A determination time detection circuit for detecting a determination time of the analog input voltage by the plurality of comparators;
A reference voltage control circuit for controlling a reference voltage applied to the plurality of comparators based on an output of the determination time detection circuit;
The reference voltage control circuit includes:
Controlling a reference voltage applied to the plurality of comparators so as to provide redundancy to the first comparator having the longest determination time in the first determination among the plurality of comparators;
The A / D converter according to supplementary note 6, wherein:

(Appendix 8)
The reference voltage control circuit includes:
A reference voltage applied to the plurality of comparators is shifted by a predetermined voltage level;
The A / D converter according to appendix 7, characterized by:

(Appendix 9)
The predetermined voltage level for shifting the reference voltage applied to the plurality of comparators is a voltage level for one bit of the least significant bit in the second determination.
9. The A / D converter according to appendix 8, wherein

(Appendix 10)
The redundancy control unit
A determination completion timing detection circuit for detecting a determination completion timing of the analog input voltage by the plurality of comparators;
A redundant range control circuit that controls a redundant range via the capacitor DAC based on the output of the determination completion timing detection circuit,
The redundant range control circuit includes:
Controlling the output voltage of the capacitor DAC so as to provide redundancy to the first comparator having the earliest determination completion timing in the first determination among the plurality of comparators;
The A / D converter according to supplementary note 6, wherein:

(Appendix 11)
The redundant range control circuit includes:
Shifting the output voltage of the capacitor DAC by a predetermined voltage level;
The A / D converter according to appendix 10, which is characterized in that.

(Appendix 12)
The predetermined voltage level for shifting the output voltage of the capacitor DAC is a voltage level for one bit of the least significant bit in the second determination.
The A / D converter according to appendix 11, characterized by that.

(Appendix 13)
An A / D conversion method for receiving an analog input voltage, repeating A / D conversion of at least 2 bits a plurality of times, gradually performing A / D conversion and outputting digital data,
In the first determination for performing A / D conversion on the higher bit side of the analog input voltage by a plurality of comparators, the completion of determination of the analog input voltage by the plurality of comparators is detected,
In the second determination performed after the first determination, a first comparator that provides redundancy is specified,
In order to set a redundancy range of the first comparator, the analog input voltage and a reference voltage applied to the plurality of comparators are relatively shifted.
A / D conversion method characterized by the above.

(Appendix 14)
The first comparator for providing redundancy in the second determination;
Among the plurality of comparators, specify by the comparator having the longest determination time in the first determination,
14. The A / D conversion method according to appendix 13, wherein

(Appendix 15)
The first comparator for providing redundancy in the second determination;
Among the plurality of comparators, the comparator is identified by the comparator having the earliest determination completion timing in the first determination.
14. The A / D conversion method according to appendix 13, wherein

1 Switch 2 Capacitance DAC (CDAC)
3 SAR control logic 4 Judgment time detection circuit 5 Reference voltage control circuit 6 Redundant range control circuit 10 DAC
40 Judgment completion timing detection circuit
CMP1, CMP2, CMP3 comparator

Claims (11)

An A / D converter that receives an analog input voltage, repeats at least 2-bit A / D conversion a plurality of times, gradually performs fine A / D conversion, and outputs digital data,
A plurality of comparators for determining the analog input voltage;
In the first determination for performing A / D conversion on the higher bit side of the analog input voltage, the completion of determination of the analog input voltage by the plurality of comparators is detected, and in the second determination performed after the first determination, A redundancy control unit that performs redundancy control by specifying the first comparator that has redundancy, and
An A / D converter characterized by the above. The first determination is a first determination for performing A / D conversion on the upper bit side including the most significant bit,
The second determination is a second determination performed after the first determination.
The A / D converter according to claim 1. A capacitive DAC having a plurality of capacitors and a plurality of switches for receiving the analog input voltage and performing charge redistribution;
SAR control logic for controlling charge redistribution in the capacitive DAC based on outputs of the plurality of comparators.
The A / D converter according to claim 1 or 2, characterized by the above. The redundancy control by the redundancy control unit is
In order to set the redundancy range of the first comparator, the analog input voltage and the reference voltage applied to the plurality of comparators are relatively shifted,
The A / D converter according to any one of claims 1 to 3, wherein the A / D converter is provided. The redundancy control unit
A determination time detection circuit for detecting a determination time of the analog input voltage by the plurality of comparators;
A reference voltage control circuit for controlling a reference voltage applied to the plurality of comparators based on an output of the determination time detection circuit;
The reference voltage control circuit includes:
Controlling a reference voltage applied to the plurality of comparators so as to provide redundancy to the first comparator having the longest determination time in the first determination among the plurality of comparators;
The A / D converter according to claim 4. The reference voltage control circuit includes:
A reference voltage applied to the plurality of comparators is shifted by a predetermined voltage level;
The A / D converter according to claim 5. The predetermined voltage level for shifting the reference voltage applied to the plurality of comparators is a voltage level for one bit of the least significant bit in the second determination.
The A / D converter according to claim 6. The redundancy control unit
A determination completion timing detection circuit for detecting a determination completion timing of the analog input voltage by the plurality of comparators;
A redundant range control circuit that controls a redundant range via the capacitor DAC based on the output of the determination completion timing detection circuit,
The redundant range control circuit includes:
Controlling the output voltage of the capacitor DAC so as to provide redundancy to the first comparator having the earliest determination completion timing in the first determination among the plurality of comparators;
The A / D converter according to claim 4. The redundant range control circuit includes:
Shifting the output voltage of the capacitor DAC by a predetermined voltage level;
The A / D converter according to claim 8. The predetermined voltage level for shifting the output voltage of the capacitor DAC is a voltage level for one bit of the least significant bit in the second determination.
The A / D converter according to claim 9. An A / D conversion method for receiving an analog input voltage, repeating A / D conversion of at least 2 bits a plurality of times, gradually performing A / D conversion and outputting digital data,
In the first determination for performing A / D conversion on the higher bit side of the analog input voltage by a plurality of comparators, the completion of determination of the analog input voltage by the plurality of comparators is detected,
In the second determination performed after the first determination, a first comparator that provides redundancy is specified,
In order to set a redundancy range of the first comparator, the analog input voltage and a reference voltage applied to the plurality of comparators are relatively shifted.
A / D conversion method characterized by the above.

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