JP2015126154A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which has a thick insulation layer in order to transmit a high-frequency radio signal with high efficiency and which can stably form a via conductor.SOLUTION: A wiring board A comprises: an insulation layer 1; a lower surface side conductor 2 which is arranged on a lower surface of the insulation layer 1 and includes a via land 2a and a lower surface side wiring conductor 2b connected to the via land 2a; a via hole 4 which is formed in the insulation layer 1 and makes a top face of the via land 2a be a bottom face; a via conductor 5 which is deposited in the via hole 4 so as to be connected with the via land 2a; and an upper surface side wiring conductor 2 which is deposited on a top face of the insulation layer 1 so as to be connected with the via conductor 5. The via land 2a has a thickness larger than a thickness of the lower surface side wiring conductor 2b and the via land 2a is buried in the insulation layer 1 so as to make a thickness from the top face of the via land 2a to the top face of the insulation layer 1 be smaller than a thickness from a top face of the lower surface side wiring conductor 2b to the top face of the insulation layer 1.

Description

  The present invention relates to a wiring board having high-density wiring.

FIG. 5 shows an example of a conventional wiring board B having high density wiring. As shown in FIG. 5, for example, four insulating layers 11 are laminated on the wiring board B, and a conductor layer 12 is formed on the surface of each insulating layer 11. Furthermore, a solder resist layer 13 is formed on the surfaces of the outermost insulating layer 11 and the conductor layer 12.
Each insulating layer 11 is formed with a plurality of via holes 14 whose bottom surface is the upper surface of a conductor layer 12 on the lower surface side of each insulating layer 11 (hereinafter referred to as a lower surface side conductor 12). A via conductor 15 connected to the lower conductor 12 is formed. The conductor layer 12 on the upper surface side of each insulating layer 11 (hereinafter referred to as the upper surface conductor 12) is formed integrally with the via conductor 15, whereby the upper surface conductor 12 and the lower surface of each insulating layer 11 are formed. The side conductors 12 are electrically connected to each other through via conductors 15. In addition, the part which forms the bottom face of the via hole 14 in the lower surface side conductor 12 forms a substantially circular via land 12 a having a slightly larger diameter than the via hole 14. The upper surface side conductor 12 and the lower surface side conductor 12 have an upper surface side wiring conductor 12c and a lower surface side wiring conductor 12b, respectively. The upper surface side wiring conductor 12c and the lower surface side wiring conductor 12b are integrally connected to at least one of the via land 12a and the via conductor 15, respectively. Such a conductor layer 12 is formed by, for example, an electrolytic plating method.
A part of the uppermost conductor 12 on the uppermost layer is exposed from an opening 13 a provided in the solder resist layer 13 to form a semiconductor element connection pad 16. Further, a part of the lowermost conductor 12 on the lowermost layer is exposed from an opening 13 b provided in the solder resist layer 13 to form a circuit board connection pad 17.
An electrode of a semiconductor element such as a semiconductor integrated circuit element is connected to the semiconductor element connection pad 16 via solder. The circuit board connection pads 17 are connected to the electrodes of the circuit board on which the wiring board B is mounted via solder. Thereby, the semiconductor element and the circuit board are electrically connected, and the semiconductor element is operated by transmitting a signal between the semiconductor element and the circuit board.

  By the way, in recent years, radio signals with a high frequency of 30 to 300 GHz are often used for purposes such as in-vehicle collision prevention sensors and indoor wireless LANs. For this reason, it is required to efficiently transmit a high-frequency radio signal also to a wiring board mounted on an electronic device intended for such an application. Furthermore, with the miniaturization of electronic devices, higher density of wiring is also required.

It is known that it is effective to increase the thickness of the insulating layer covering the wiring in the wiring board in order to meet the demand for efficiently transmitting the high frequency radio signal as described above. Yes.
However, when the thickness of the insulating layer 11 is increased in the conventional wiring board B, the depth of the via hole 14 also increases. Moreover, since the wiring is formed with high density, the diameter of the via hole 14 cannot be increased. Therefore, when the via conductor 15 is formed in the via hole 14 by the electrolytic plating method as described above, it is difficult to supply the plating solution into the via hole 14 having a small diameter and a large depth, thereby stabilizing the via conductor 15. In some cases.

Japanese Patent No. 5203108

  It is an object of the present invention to provide a wiring board that has a thick insulating layer for efficiently transmitting a high-frequency radio signal and that can stably form a via conductor. .

  The wiring board of the present invention is formed on the insulating layer, the lower surface side conductor including the lower surface side wiring conductor connected to the via land and the via land, and the upper surface of the via land as the bottom surface. And a via conductor deposited in the via hole so as to be connected to the via land, and a top-side wiring conductor deposited on the upper surface of the insulating layer so as to be connected to the via conductor. The via land is thicker than the thickness of the lower surface side wiring conductor, and the thickness from the upper surface of the via land to the upper surface of the insulating layer is smaller than the thickness from the upper surface of the lower surface side wiring conductor to the upper surface of the insulating layer. It is characterized by being embedded in an insulating layer.

  In the wiring board of the present invention, the via land disposed below the insulating layer is thicker than the lower surface wiring disposed below the insulating layer, and from the upper surface of the via land to the upper surface of the insulating layer. Is embedded in the insulating layer so as to be thinner than the thickness from the upper surface of the lower surface side wiring to the upper surface of the insulating layer. For this reason, the thickness of the insulating layer covering the lower surface side wiring can be increased to efficiently transmit high-frequency radio signals, and the thickness of the insulating layer on the upper surface of the via land can be decreased to reduce the depth of the via hole. Thus, for example, since it becomes easy to supply the plating solution in the electrolytic plating method into the via hole, it is possible to provide a wiring board capable of stably forming the via conductor.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is an enlarged cross-sectional view of a main part of the wiring board shown in FIG. 3A to 3F are schematic cross-sectional views showing an example of an embodiment for each process in the method for manufacturing a wiring board of the present invention. 4G to 4J are schematic cross-sectional views showing an example of the embodiment for each process in the method for manufacturing a wiring board of the present invention. FIG. 5 is a schematic cross-sectional view showing an example of an embodiment of a conventional wiring board.

  Next, an example of an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, in the wiring board A of this example, for example, four insulating layers 1 are laminated and a conductor layer 2 is formed on the surface of each insulating layer 1. Further, a solder resist layer 3 is formed on the surfaces of the outermost insulating layer 1 and the conductor layer 2.

Each insulating layer 1 is formed with a plurality of via holes 4 whose bottom surface is the upper surface of a conductor layer 2 on the lower surface side of each insulating layer 1 (hereinafter referred to as a lower surface side conductor 2). Via conductors 5 are formed. Further, the conductor layer 2 on the upper surface side of each insulating layer 1 (hereinafter referred to as the upper surface side conductor 2) is formed integrally with the here conductor 5, so that the upper surface side conductor 2 of each insulating layer 1 and The lower surface side conductor 2 is electrically connected to each other through the via conductor 5. In addition, the part which forms the bottom face of the via hole 4 in the lower surface side conductor 2 forms a substantially circular via land 2 a having a slightly larger diameter than the via hole 4. The upper surface side conductor 2 and the lower surface side conductor 2 have an upper surface side wiring conductor 2c and a lower surface side wiring conductor 2b, respectively. The upper surface side wiring conductor 2c and the lower surface side wiring conductor 2b are integrally connected to at least one of the via land 2a and the via conductor 5, respectively.
A part of the uppermost conductor 2 on the uppermost layer is exposed in an opening 3 a provided in the solder resist layer 3 to form a semiconductor element connection pad 6. Further, a part of the lowermost lower surface side conductor 2 is exposed in an opening 3 b provided in the solder resist layer 3 to form a circuit board connection pad 7.
An electrode of a semiconductor element such as a semiconductor integrated circuit element is connected to the semiconductor element connection pad 6 via solder. The circuit board connection pads 7 are connected to the electrodes of the circuit board on which the wiring board A is mounted via solder. Thereby, the semiconductor element and the circuit board are electrically connected, and the semiconductor element is operated by transmitting a signal between the semiconductor element and the circuit board.

The insulating layer 1 is made of, for example, an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. In this example, a multi-layer structure in which insulating layers are stacked in multiple layers is shown, but a single-layer structure may be used.
The insulating layer 1 has a thickness of about 40 to 100 μm.

  The conductor layer 2 is made of a highly conductive metal such as copper, and is formed by a known semi-additive method.

  The solder resist layer 3 is made of an electrically insulating material obtained by applying a paste or film made of a thermosetting resin having photosensitivity such as an acrylic-modified epoxy resin to the surface of the insulating layer 1 and curing it.

  The via hole 4 is formed by, for example, drilling, laser processing, or blasting. The diameter of the via hole is about 50 to 100 μm.

  By the way, in the wiring board A of this example, as shown in FIG. 2, the lower surface side conductor 2 includes a first conductor layer 2A and a second conductor layer 2B laminated on the first conductor layer 2A. Embedded in the lower surface of the insulating layer 1 thereon. The thickness of the first conductor layer 2A is about 10 to 20 μm, and the thickness of the second conductor layer 2B is about 10 μm. The via land 2a is composed of the first conductor layer 2A and the second conductor layer 2B, and the lower surface side wiring conductor 2b is composed only of the first conductor layer 2A. Therefore, the via land 2a is approximately 10 μm thicker than the lower surface side wiring conductor 2b, and the thickness from the upper surface of the via land 2a to the upper surface of the insulating layer 1 is lower surface side wiring conductor 2b. And about 10 μm thinner than the thickness from the top to the upper surface of the insulating layer 1.

  Thus, in the present invention, the via land 2a is thicker than the lower surface side wiring conductor 2b. Further, the via land 2 a is embedded in the insulating layer 1 so that the thickness from the upper surface of the via land 2 a to the upper surface of the insulating layer 1 is thinner than the thickness from the upper surface of the lower surface side wiring conductor 2 b to the upper surface of the insulating layer 1. For this reason, the thickness of the insulating layer 1 covering the lower surface side wiring conductor 2b can be increased to efficiently transmit high-frequency radio signals, and the thickness of the insulating layer 1 on the upper surface of the via land 2a can be decreased to reduce the via hole 4. By reducing the depth of the wiring board A, for example, it is possible to provide the wiring board A capable of stably forming the via conductor 5 by making it easy to supply the plating solution in the electrolytic plating method into the via hole 4.

Here, the manufacturing method of the wiring board A will be described with reference to FIGS.
3 and 4 show schematic cross-sectional views during the production of the wiring board A in each step.
The same parts as those in FIGS. 1 and 2 described above are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, as shown in FIG. 3A, a support plate is prepared in which a copper foil 9 composed of a first copper foil 9 a and a second copper foil 9 b is pressed on the upper surface of the support substrate 8. The copper foil 9 is obtained by holding a first copper foil 9a and a second copper foil 9b so as to be separable from each other via an adhesive layer (not shown). The thicknesses of the first copper foil 9a and the second copper foil 9b are about 1 to 30 μm, respectively.

  Next, as shown in FIG. 3B, a first plating resist R1 having a predetermined pattern exposing a portion corresponding to the first conductor layer 2A is formed on the second copper foil 9b.

  Next, as shown in FIG. 3C, the first plated metal that becomes the first conductor layer 2A is formed on the surface of the second copper foil 9b exposed from the first plating resist R1 by, for example, a known semi-additive method. 2AP is precipitated.

  Next, as shown in FIG. 3D, a second plating resist R2 having a predetermined pattern exposing a portion corresponding to the second conductor layer 2B is formed on the first plating resist R1 and the first plating metal 2AP. To form.

  Next, as shown in FIG. 3E, on the surface of the first plating metal 2AP exposed from the second plating resist R2, for example, a second plating metal 2BP that becomes the second conductor layer 2B by a known semi-additive method. To precipitate.

  Next, as shown in FIG. 3F, the first conductor layer 2A and the second conductor layer 2B are formed by removing the first and second plating resists R1 and R2.

  Next, as shown in FIG. 4G, the insulating layer 1 is laminated on the second copper foil 9b and the first and second conductor layers 2A and 2B.

  Next, as shown in FIG. 4H, a via hole 4 is formed in the insulating layer 1 to expose the upper surface of the second conductor layer 2B.

  Next, as shown in FIG. 4 (i), a third plating resist R 3 having a predetermined pattern exposing a portion corresponding to the conductor layer 2 on the upper surface side is formed on the upper surface of the insulating layer 1.

  Next, as shown in FIG. 4 (j), for example, electroless plating (not shown) is deposited on the insulating layer 1 and the via hole 4 exposed from the third plating resist R3, and then a well-known semi-additive. The third plating metal 2P that becomes the conductor layer 2 on the upper surface side and the via conductor 5 is integrally deposited by the method.

Thereafter, by repeating the steps shown in FIGS. 3d to 4j, a predetermined number of insulating layers 1 are laminated, and the solder resist layer 3 is formed on the surface of the outermost insulating layer 1, and then the first copper foil 9a. 1 is formed by separating the interface between the first copper foil 9b and the second copper foil 9b deposited on the lower surface of the lowermost insulating layer 1 by etching.

DESCRIPTION OF SYMBOLS 1 Insulation layer 2a Via land 2b Lower surface side wiring conductor 2c Upper surface side wiring conductor 4 Via hole 5 Via conductor A Wiring board

Claims (2)

  An insulating layer, a lower surface side conductor including a via land and a lower surface side wiring conductor connected to the via land, and a via hole formed in the insulating layer with the upper surface of the via land as a bottom surface And a via conductor deposited in the via hole so as to be connected to the via land, and an upper surface side wiring conductor deposited on the upper surface of the insulating layer so as to be connected to the via conductor. The via land is thicker than the thickness of the lower surface side wiring conductor, and the thickness from the upper surface of the via land to the upper surface of the insulating layer is from the upper surface of the lower surface side wiring conductor to the upper surface of the insulating layer. The wiring board is embedded in the insulating layer so as to be thinner than the thickness of the wiring board.   The lower surface-side conductor includes a first conductor layer and a second conductor layer laminated on the first conductor layer, and the via land includes the first and second conductor layers, and the lower surface side. The wiring board according to claim 1, wherein the wiring is made of the first conductor layer.