JP2015119583A - Control circuit for inverter circuit, inverter device with the control circuit, induction heating device with the inverter device, and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control circuit which performs control in such a manner that an advanced phase is prevented in an inverter device.SOLUTION: A control circuit 7 for controlling an inverter circuit 2 includes: a first pulse signal generation part 734 for generating a pulse signal Pa that becomes a source of a drive signal Pa' to be inputted to a switching element 2a of one arm of the inverter circuit 2; a second pulse signal generation part 735 for generating a pulse signal Pc that becomes a source of a drive signal Pc' to be inputted to a switching element 2c of the other arm; and a phase difference detection part 76 for detecting a smaller voltage/current phase difference φ between a phase difference between a phase of an output current signal I and a phase of the pulse signal Pa and a phase difference between a phase of an inverse signal of the output current signal I and a phase of the pulse signal Pc. By preventing the voltage/current phase difference φ from becoming smaller than a predetermined phase difference φ, control can be performed in such a manner that the advanced phase can be prevented for both the phase differences.

Description

  The present invention relates to a control circuit that performs control by inputting drive signals to switching elements of two arms of a single-phase full-bridge type inverter circuit, an inverter device that includes this control circuit, and an induction that includes this inverter device. The present invention relates to a heating device and a control method.

  An induction heating apparatus that performs heating using electromagnetic induction has been developed. The induction heating device supplies a high-frequency current to the heating coil using an inverter device, and changes the magnetic field. And an eddy current is generated in the metal heating object arrange | positioned in this magnetic field. Joule heat due to electrical resistance is generated in the object to be heated due to the flow of eddy current, and the object to be heated is heated by self-heating.

  When the inverter device operates in a state in which the phase of the output current is advanced from the phase of the output voltage (hereinafter referred to as “advanced phase”), a steep reverse recovery current flows to generate EMI noise or an inverter circuit There is a concern that the switching element of this may break down. Therefore, in the inverter device, a technique for detecting the phase difference between the output current and the output voltage and controlling the phase difference so as not to be a lead phase is generally well known (for example, see Patent Document 1). As a method for detecting the phase difference between the output current and the output voltage, a method for converting the time difference between the zero-cross point of the output voltage signal and the zero-cross point of the output current signal into a phase difference is known (for example, patent document). 2). Note that the phase of the drive signal is used as the phase of the output voltage.

  In addition, in the control of the inverter device, phase shift control has been developed in which the output is controlled by changing the phase difference of the drive signal input to each switching element of the inverter device. For example, Patent Document 3 describes an induction heating device including an inverter device that performs phase shift control. The induction heating device delays the phase of the drive signal output to the switching element of one arm from the phase of the drive signal output to the switching element of the other arm. By changing this phase difference, output control is performed. I do.

Patent No. 4084615 JP 2007-157345 A JP 2009-259851 A JP 2004-74258 A

  In an inverter device that performs phase shift control, a problem arises when a phase difference between an output current and an output voltage is detected. In other words, in the case of phase shift control, the drive signal output to the switching element of one arm and the drive signal output to the switching element of the other arm have different phases, and the phase difference changes. The problem is whether to use the phase as a reference for the phase of the output voltage. For example, even if the phase difference between the phase of one drive signal and the phase of the output current is detected and controlled so that it does not become a lead phase, the phase of the output current will lead ahead of the phase of the other drive signal There is.

  Moreover, in the inverter apparatus described in Patent Document 4, the phase of one drive signal is switched between a state advanced and a phase delayed from the phase of the other drive signal. Therefore, when the phase of one drive signal is advanced from the phase of the other drive signal, the output current is controlled relative to the other drive signal by controlling so that the output current does not become the advance phase with respect to one drive signal. However, if the phase of one drive signal is switched to a state delayed from the phase of the other drive signal, the phase of the output current is higher than the phase of the other drive signal even if the phase is not advanced. There is a case to go forward.

  The present invention has been conceived under the circumstances described above, and an object of the present invention is to provide a control circuit for an inverter circuit that controls an inverter device so as not to be in a lead phase.

  In order to solve the above problems, the present invention takes the following technical means.

  A control circuit provided by the first aspect of the present invention is a control circuit that inputs a drive signal to an inverter circuit and controls the inverter circuit, and is a switching circuit disposed on one arm of the inverter circuit. A first drive signal generating means for generating a first drive signal to be input to the element; a second drive signal generating means for generating a second drive signal to be input to the switching element disposed on the other arm of the inverter circuit; , A first voltage-current phase difference that is a difference between the phase of the output current signal of the inverter circuit and the phase of the first drive signal, and the phase of the inverted signal of the output current signal and the phase of the second drive signal. A phase difference detecting means for detecting a smaller one of the differences in the second voltage / current phase difference as a difference is provided.

  In a preferred embodiment of the present invention, the phase of the first drive signal and the second drive signal are such that the smaller voltage-current phase difference detected by the phase difference detection means does not become smaller than a predetermined phase difference. The output of the inverter circuit is controlled by changing the phase difference, which is the difference from the phase of.

  In a preferred embodiment of the present invention, the frequency of the first drive signal and the second drive signal is such that the smaller voltage-current phase difference detected by the phase difference detection means does not become smaller than a predetermined phase difference. Is changed to control the output of the inverter circuit.

  In a preferred embodiment of the present invention, the phase of the first drive signal is advanced from the phase of the second drive signal, and the phase of the first drive signal is delayed from the phase of the second drive signal. Further, switching means for switching between and is provided.

  In a preferred embodiment of the present invention, the phase difference detection means smoothes a logical product of the binarized signal of the output current signal and the first drive signal to cope with the first voltage / current phase difference. A signal corresponding to the second voltage-current phase difference is generated by smoothing a logical product of the inverted signal of the binarized signal and the second drive signal, and the first voltage-current level is generated. The larger one of the signal corresponding to the phase difference and the signal corresponding to the second voltage / current phase difference is output as a signal corresponding to the smaller voltage / current phase difference.

  In a preferred embodiment of the present invention, when the phase of the first drive signal is ahead of the phase of the second drive signal, the phase difference detecting means includes the binarized signal of the output current signal and the first drive signal. When the signal obtained by smoothing the logical product with the drive signal is output as a signal corresponding to the smaller voltage-current phase difference, and the phase of the second drive signal is more advanced than the first drive signal, the output current A signal obtained by smoothing the logical product of the inverted signal of the binarized signal and the second drive signal is output as a signal corresponding to the smaller voltage-current phase difference.

  In a preferred embodiment of the present invention, the phase difference detecting means corresponds to a time difference from a rising zero cross of the first drive signal to a zero cross from the negative to the positive of the output current signal to the first voltage / current phase difference. A time difference from the rising zero cross of the second drive signal to the zero cross from the negative to the positive of the output current signal is generated as a signal corresponding to the second voltage current phase difference, and the first voltage current The smaller one of the signal corresponding to the phase difference and the signal corresponding to the second voltage / current phase difference is output as a signal corresponding to the smaller voltage / current phase difference.

  The inverter device provided by the second aspect of the present invention includes an inverter circuit and a control circuit provided by the first aspect of the present invention.

  An induction heating device provided by the third aspect of the present invention includes a direct current power source, an inverter device provided by the second aspect of the present invention, and a coil that generates a magnetic field by an alternating current input from the inverter device. It is characterized by having.

  A control method provided by a fourth aspect of the present invention is a control method for controlling an inverter circuit, and generates a first drive signal to be input to a switching element arranged in one arm of the inverter circuit. A first step, a second step of generating a second drive signal to be input to a switching element arranged on the other arm, and a switching element corresponding to the generated first drive signal and second drive signal, respectively. A first voltage current phase difference that is a difference between the phase of the output current signal of the inverter circuit and the phase of the first drive signal, the phase of the inverted signal of the output current signal, and A fourth step of detecting a smaller one of the second voltage and current phase differences, which is a difference from the phase of the second drive signal, and the smaller voltage and current phase detected in the fourth step. So it does not become smaller than a predetermined phase difference, and wherein the changing the phase difference which is a difference between the phase of the phase and the second driving signal of the first driving signal.

  According to the present invention, the phase difference detecting means detects the smaller voltage-current phase difference between the first voltage-current phase difference and the second voltage-current phase difference. If the smaller voltage-current phase difference detected by the phase-difference detecting means is not made smaller than the predetermined phase difference, the larger voltage-current phase difference will not become smaller than the predetermined phase difference. Therefore, both can be controlled so as not to reach the leading phase.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a figure for demonstrating the whole structure of the induction heating apparatus which concerns on 1st Embodiment. It is a figure which shows the waveform of the drive signal of the inverter apparatus which performs phase shift control. It is a figure for demonstrating the internal structure of the phase difference detection part which concerns on 1st Embodiment. It is a wave form diagram for demonstrating the input-output signal of the phase difference detection part which concerns on 1st Embodiment. It is a figure for demonstrating the other Example of the phase difference detection part which concerns on 1st Embodiment. It is a figure which shows the waveform of the drive signal of the inverter apparatus which performs frequency control. It is a figure for demonstrating the induction heating apparatus which concerns on 2nd Embodiment. It is a figure for demonstrating the induction heating apparatus which concerns on 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings, taking as an example the case where a control circuit according to the present invention is used in an inverter apparatus of an induction heating apparatus.

  Drawing 1 is a figure for explaining the whole composition of induction heating device A concerning a 1st embodiment.

  The induction heating device A includes a DC power source 1, an inverter device, a coil 5, and a resonance capacitor 6. The induction heating device A heats the heating object B using electromagnetic induction.

  The DC power source 1 outputs a DC current, and includes, for example, a rectifier circuit that rectifies an AC current input from the power system, and a smoothing capacitor that smoothes the AC current. Note that the DC power source 1 is not limited to the one that converts an alternating current into a direct current and outputs it, and may be one that outputs a direct current such as a fuel cell, a storage battery, or a solar cell.

  The inverter device converts a direct current input from the direct current power source 1 into a high frequency current and outputs it to the coil 5. The inverter device includes an inverter circuit 2 and a control circuit 7, and is hereinafter referred to as “inverter device 8”. Details of the inverter device 8 will be described later.

  The coil 5 is for generating a magnetic field, and is a conductor wire wound in a spiral shape. In the present embodiment, the induction heating apparatus A is for cooking, and a pan or the like is disposed on the upper part of the coil 5, so that the coil 5 is spirally wound in a planar shape. I can't. The shape of the coil 5 may be in accordance with the shape of the heating object B and the state of arrangement. For example, the heating object B may be arranged in the center as a so-called coil shape in which the coil 5 is wound in a cylindrical shape. The coil 5 changes a magnetic field by the high frequency current input from the inverter apparatus 8 flowing. And an eddy current generate | occur | produces in the heating target B, such as a pan, arrange | positioned at this magnetic field. Joule heat due to electric resistance is generated in the heating object B due to an eddy current flowing, and the heating object B is heated by self-heating.

  The resonant capacitor 6 is for canceling the impedance due to the coil 5 and is connected in series to the coil 5 to constitute a series resonant circuit.

  Since the coil 5 and the heating target B are magnetically coupled, the coil 5, the resonance capacitor 6 and the heating target B can be collectively considered as a load connected to the inverter device 8. That is, in the induction heating device A, the inverter device 8 converts the direct current output from the direct current power source 1 into an alternating current and supplies the alternating current to the load. The inverter device 8 can control the power supplied to the load. In the present embodiment, the inverter device 8 controls the output power by phase shift control.

  The inverter device 8 includes a single-phase full-bridge type inverter circuit 2 and a control circuit 7. The inverter circuit 2 includes four switching elements 2a to 2d, flywheel diodes 3a to 3d, and snubber capacitors 4a to 4d. In the present embodiment, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used as the switching elements 2a to 2d. The switching elements 2a to 2d are not limited to MOSFETs, and may be bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), or the like. Further, the types of flywheel diodes 3a to 3d and snubber capacitors 4a to 4d are not limited.

  The switching elements 2a and 2b are connected in series by connecting the source terminal of the switching element 2a and the drain terminal of the switching element 2b. The drain terminal of the switching element 2a is connected to the positive electrode side of the DC power source 1, and the source terminal of the switching element 2b is connected to the negative electrode side of the DC power source 1 to form a bridge structure. Similarly, the switching elements 2c and 2d are connected in series to form a bridge structure. A bridge structure formed by the switching elements 2a and 2b is a first arm, and a bridge structure formed by the switching elements 2c and 2d is a second arm. An output line is connected to a connection point between the switching elements 2a and 2b of the first arm, and an output line is also connected to a connection point between the switching elements 2c and 2d of the second arm. A coil 5 and a resonant capacitor 6 are connected in series between these two output lines. Drive signals Pa 'to Pd' (described later) output from the control circuit 7 are input to the gate terminals of the switching elements 2a to 2d.

  Each of the switching elements 2a to 2d can be switched between an on state and an off state based on the drive signals Pa 'to Pd', respectively. Since both ends of each arm are respectively connected to the positive electrode and the negative electrode of the DC power source 1, when the positive switching element is on and the negative switching element is off, the potential of the output line of the arm is DC The potential is on the positive side of the power supply 1. On the other hand, when the positive-side switching element is off and the negative-side switching element is on, the potential of the output line of the arm is the negative-side potential of the DC power supply 1. As a result, a pulsed voltage signal in which the positive potential and the negative potential of the DC power supply 1 are switched is output from each output line, and the line voltage that is the voltage between the two output lines is changed to the AC voltage. Become.

  The flywheel diodes 3a to 3d are connected in antiparallel between the drain terminals and the source terminals of the switching elements 2a to 2d, respectively. That is, the anode terminals of the flywheel diodes 3a to 3d are connected to the source terminals of the switching elements 2a to 2d, respectively, and the cathode terminals of the flywheel diodes 3a to 3d are connected to the drain terminals of the switching elements 2a to 2d, respectively. The flywheel diodes 3a to 3d are for preventing a high reverse voltage due to the counter electromotive force generated by switching the switching elements 2a to 2d from being applied to the switching elements 2a to 2d, respectively.

  The snubber capacitors 4a to 4d are connected between the drain terminals and the source terminals of the switching elements 2a to 2d, respectively. The snubber capacitors 4a to 4d absorb a surge voltage applied between the drain terminal and the source terminal by switching the switching elements 2a to 2d. In addition, it is good also as a snubber circuit by connecting resistance to the snubber capacitor 4a-4d in series, respectively.

  Note that the flywheel diodes 3a to 3d and the snubber capacitors 4a to 4d may be provided with only one of them, or may not be provided with any of them.

  The control circuit 7 controls the inverter circuit 2 and controls the output power of the inverter circuit 2 by controlling the AC power input to the DC power supply 1 to be the target power. The control circuit 7 controls the inverter circuit 2 by phase shift control. That is, the phase of the drive signal output to the switching element (eg, 2c (2d)) of one arm is delayed from the phase of the drive signal output to the switching element (eg, 2a (2b)) of the other arm. The output power is controlled by changing the phase difference.

  FIG. 2 is a diagram illustrating a waveform of a drive signal of an inverter device that performs phase shift control, and is a diagram for explaining that output power changes due to a change in phase difference.

  In the figure, the frequency of the drive signal is fixed at 25 kHz, and the phase difference θ between the two drive signals is changed. FIG. 11A shows the case where the phase difference θ is larger than that in FIG. FIG. 4C shows the case where the phase difference θ is smaller than that in FIG.

  2 (a), 2 (b), and 2 (c), the top shows the waveform of the drive signal Pa ′ input to the switching element 2a of the first arm, and the bottom is the switching element 2c of the second arm. 2 shows the waveform of the drive signal Pc ′ inputted to the bottom, the current signal I of the current flowing through the coil 5 is shown below, and the bottom is the voltage signal V of the voltage applied to the load.

  As shown in FIG. 2, when the phase difference θ is reduced, the time during which a voltage is applied to the load is shortened (see voltage signal V), the amplitude of the current signal I is reduced, and the output power of the inverter circuit 2 is reduced. Become. Conversely, when the phase difference θ is increased, the time during which the voltage is applied to the load is increased, the amplitude of the current signal I is increased, and the output power of the inverter circuit 2 is increased. The phase difference θ can vary from 0 to π. When the phase difference θ = π, the output power becomes maximum, and when the phase difference θ = 0, the output power becomes minimum.

  In addition, the control circuit 7 has a function of switching the arm (following arm) on the phase delay side. That is, the phase of the drive signal output to the switching element 2c (2d) of the second arm is delayed from the phase of the drive signal output to the switching element 2a (2b) of the first arm (the second arm is the follower arm and the first A state in which the arm is a leading arm) and a state in which the phase of the drive signal output to the switching element 2a (2b) of the first arm is delayed from the phase of the drive signal output to the switching element 2c (2d) of the second arm (first 1 arm is a follower arm and the second arm is a preceding arm). The time during which the current flows through the switching element on the preceding arm side (the phase is advanced) is longer than the time during which the current flows through the switching element on the following arm side (the phase is delayed). This generates more heat and causes a large difference in the heat loss of the switching element. In the present embodiment, by alternately switching the leading arm and the follower arm, the time during which the current flows through each switching element is leveled, and the difference in heat loss is reduced.

  Further, the control circuit 7 provides a total stop period in which all drive signals are set to the low level before switching between the preceding arm and the follower arm. The reason for providing the total stop period is to prevent the drive circuit from malfunctioning and the inverter device from being unstable because the duty ratio of each drive signal (the high level period divided by the pulse period) exceeds 50%. .

Further, the control circuit 7 performs control so that the phase difference between the voltage and the current (hereinafter referred to as “voltage-current phase difference”) does not become a predetermined phase difference or less. The control circuit 7 compares the voltage / current phase difference φ with a predetermined value φ ^* in order to maintain a delayed phase state in which the phase of the current signal is delayed from the phase of the voltage signal. ^{* I} try not to make it smaller. The predetermined value φ ^* is set to zero or a value slightly larger than zero. It is necessary to prevent the current signal from being in the leading phase in the first arm, and it is also necessary to prevent the current signal from being in the leading phase in the second arm.

As shown in FIG. 2, the phase difference φ ₁ between the phase of the drive signal Pa ′ and the phase of the current signal I is different from the phase difference φ ₂ between the phase of the drive signal Pc ′ and the phase of the current signal I. . In the current signal I shown in FIG. 2, the direction from the first arm to the second arm is indicated as positive. Therefore, the phase difference φ ₁ is a phase difference from the rising edge of the drive signal Pa ′ to the zero crossing of the current signal I from negative to positive, and the phase difference φ ₂ is the positive edge of the current signal I from the rising edge of the drive signal Pc ′. The phase difference is up to zero cross. Since the phase of the drive signal Pa ′ matches the phase of the voltage signal of the first arm and the phase of the drive signal Pc ′ matches the phase of the voltage signal of the second arm, the phase difference φ ₁ and the phase difference φ ₂ It means the voltage-current phase difference at the arm. Therefore, hereinafter, they are referred to as “voltage / current phase difference φ ₁ ” and “voltage / current phase difference φ ₂ ”, respectively.

Further, as shown in FIG. 2, when the phase difference θ is reduced, the voltage / current phase difference φ ₁ is reduced and the voltage / current phase difference φ ₂ is increased. Conversely, when the phase difference θ is increased, the voltage / current phase difference φ ₁ increases and the voltage / current phase difference φ ₂ decreases. When the phase difference θ reaches the maximum π, the voltage / current phase difference φ ₁ matches the voltage / current phase difference φ ₂ . Therefore, the voltage / current phase difference φ ₁ is always equal to or smaller than the voltage / current phase difference φ ₂ . That is, when the first arm is the preceding arm, if the voltage / current phase difference φ ₁ is detected so as not to be less than or equal to the predetermined value φ ^* , the voltage / current phase difference φ ₂ will not be less than or equal to the predetermined value φ ^* . However, in this embodiment, since the leading arm and the follower arm are switched, the smaller voltage current phase difference φ of the two voltage current phase differences is detected, and the voltage current phase difference φ is equal to or less than the predetermined value φ ^*. Control so that it does not become.

  The control circuit 7 includes a power calculation unit 71, a power setting unit 72, a current detection unit 75, a phase difference detection unit 76, a pulse signal generation unit 73, and a driver 74.

  The power calculation unit 71 calculates the power value of AC power input to the DC power supply 1 from the power system. Although not shown in FIG. 1, the DC power supply 1 is provided with a current sensor and a voltage sensor between the power system and the rectifier circuit. The current sensor detects an alternating current input from the power system to the DC power source 1 and outputs the detected alternating current to the power calculation unit 71. In addition, the voltage sensor detects an AC voltage input from the power system to the DC power supply 1 and outputs the AC voltage to the power calculation unit 71. The power calculation unit 71 calculates a power value P of AC power input to the DC power source 1 based on inputs from the current sensor and the voltage sensor, and outputs the power value P to the pulse signal generation unit 73. Note that the power calculation unit 71 may be provided in the DC power supply 1 and the power value P may be input from the DC power supply 1 to the control circuit 7.

The power setting unit 72 sets a target value P ^* of the power value P, and outputs the set target value P ^* to the pulse signal generation unit 73. The power setting unit 72 sets the target value P ^* according to the operation of an operating means (not shown). For example, the operating means changes the heating power by rotating the knob. When the knob is rotated in one direction (for example, counterclockwise), the target value P ^* is set to a small value, and the other direction (for example, clockwise). When the knob is rotated, the target value P ^* is set to a large value.

  The current detector 75 detects the output current of the first arm by a current sensor provided in the output line of the first arm of the inverter circuit 2 and outputs the detected current signal I to the phase difference detector 76. is there.

The phase difference detector 76 detects the smaller voltage / current phase difference φ. That is, the voltage-current phase difference at the first arm phi ₁ and of the voltage-current phase difference phi ₂ of the second arm, to detect a person smaller as the voltage current phase difference phi. The phase difference detection unit 76 outputs a pulse signal Pa output from a first pulse signal generation unit 734 (described later), a pulse signal Pc output from a second pulse signal generation unit 735 (described later), and a current detection unit 75. Current signal I to be input. The pulse signal Pa (Pc) is a signal that is the basis of the drive signal Pa ′ (Pc ′), and has a phase match. Further, the phase of the drive signal Pa ′ (Pc ′) matches the phase of the voltage signal of the first arm (second arm). Therefore, the pulse signal Pa (Pc) is used instead of detecting the voltage signal of each arm. The phase difference detector 76 detects the voltage / current phase difference φ ₁ in the first arm from the pulse signal Pa and the current signal I, and determines the voltage / current phase difference φ ₂ in the second arm from the pulse signal Pc and the current signal I. The smaller one of the voltage / current phase difference φ ₁ and the voltage / current phase difference φ ₂ is detected as the voltage / current phase difference φ.

  FIG. 3A is a diagram for explaining the internal configuration of the phase difference detection unit 76.

  The phase difference detection unit 76 includes a binarization circuit 761, a negation circuit 762, logical product circuits 763a and 763b, smoothing circuits 764a and 764b, and diodes 765a and 765b.

  The binarization circuit 761 generates a current binarization signal which is a digital signal binarized according to the positive / negative of the current signal I input from the current detection unit 75. The negation circuit 762 is a logic circuit and inverts the current binarization signal input from the binarization circuit 761. Since the output current signal of the second arm is obtained by inverting the output current signal of the first arm, the signal output from the negation circuit 762 corresponds to a signal obtained by binarizing the output current signal of the second arm.

  The AND circuit 763a is a logic circuit, and outputs a logical product of the pulse signal Pa input from the first pulse signal generation unit 734 and the current binarization signal input from the binarization circuit 761. The output of the AND circuit 763a becomes high level only when both the pulse signal Pa and the current binarization signal are high level, and otherwise becomes low level. When the phase difference between the pulse signal Pa and the current binarization signal is small, the time over which the high level period overlaps becomes long, so the time during which the output of the AND circuit 763a becomes high level becomes long. On the other hand, when the phase difference between the pulse signal Pa and the current binarization signal is large, the time over which the high level period overlaps is shortened, so the time during which the output of the AND circuit 763a is at the high level is shortened.

The smoothing circuit 764a is an integrating circuit, and smoothes the signal output from the logical product circuit 763a and outputs it as an analog voltage signal. The longer the time that the output of the AND circuit 763a becomes high level, that is, the smaller the phase difference between the pulse signal Pa and the current binarized signal, the greater the output of the smoothing circuit 764a. The waveform of the pulse signal Pa matches the waveform of the voltage signal of the first arm, and the current signal I is the current signal of the first arm. Therefore, the smaller the voltage / current phase difference φ ₁ in the first arm, the larger the output voltage of the smoothing circuit 764a.

  The AND circuit 763b is a logic circuit, and is a signal obtained by inverting the pulse signal Pc input from the second pulse signal generation unit 735 and the current binarization signal input from the negation circuit 762 (hereinafter referred to as “inversion”). Signal ") is output. The output of the AND circuit 763b becomes high level only when both the pulse signal Pc and the inverted signal are high level, and otherwise becomes low level. When the phase difference between the pulse signal Pc and the inverted signal is small, the time over which the high level period overlaps becomes long, so the time during which the output of the AND circuit 763b becomes high level becomes long. On the other hand, when the phase difference between the pulse signal Pc and the inverted signal is large, the time for which the high level period overlaps is shortened, so the time for the output of the AND circuit 763b to be high level is shortened.

The smoothing circuit 764b is an integration circuit, and smoothes the signal output from the logical product circuit 763b and outputs it as an analog voltage signal. The longer the time that the output of the logical product circuit 763b becomes high level, that is, the smaller the phase difference between the pulse signal Pc and the inverted signal, the larger the output of the smoothing circuit 764b. The waveform of the pulse signal Pc matches the waveform of the voltage signal of the second arm, and the signal obtained by inverting the current signal I is the current signal of the second arm. Therefore, the smaller the voltage-current phase difference φ ₂ in the second arm, the larger the output voltage of the smoothing circuit 764b.

The output voltage of the smoothing circuit 764a is input to the anode terminal of the diode 765a, and the output voltage of the smoothing circuit 764b is input to the anode terminal of the diode 765b. The cathode terminal of the diode 765a and the cathode terminal of the diode 765b are connected to serve as the output of the phase difference detector 76. The larger of the output voltage of the smoothing circuit 764a and the output voltage of the smoothing circuit 764b is the output voltage of the phase difference detector 76. Therefore, the phase difference detector 76 outputs a voltage corresponding to the smaller voltage current phase difference φ of the voltage current phase difference φ ₁ and the voltage current phase difference φ ₂ . The output voltage of the phase difference detector 76 increases as the voltage / current phase difference φ decreases.

  FIG. 4 is a waveform diagram for explaining input / output signals of the phase difference detector 76.

  2A shows the pulse signal Pa, FIG. 2B shows the pulse signal Pc, and FIG. 1C shows the current signal I. FIG. FIG. 6D shows a current binarized signal obtained by binarizing the current signal I by the binarizing circuit 761. FIG. 8E shows the binarized signal inverted by the negating circuit 762. An inversion signal is shown.

  FIG. 5F shows the output of the logical product circuit 763a, which is the logical product of the pulse signal Pa (see FIG. 11A) and the current binarized signal (see FIG. 14D). Both the pulse signal Pa and the current binarization signal are high level only during a high level period. FIG. 5G shows the output voltage of the smoothing circuit 764a, which is obtained by smoothing the output of the AND circuit 763a (see FIG. 5F).

  FIG. 11H shows the output of the logical product circuit 763b, which is the logical product of the pulse signal Pc (see FIG. 14B) and the inverted signal (see FIG. 19E). Both the pulse signal Pc and the inverted signal are high level only during a high level period. FIG. 6 (i) shows the output voltage of the smoothing circuit 764b, which is obtained by smoothing the output of the AND circuit 763b (see FIG. 11 (h)).

  The phase difference between the pulse signal Pa (see (a) in the figure) and the current binarized signal (see (d) in the figure) is equal to the pulse signal Pc (see (b) in the figure) and the inverted signal (see (e) in the figure). )), The output waveform of the AND circuit 763a (see (f) of the figure) is higher than the output waveform of the AND circuit 763b (see (h) of the figure). Is long. Therefore, the output voltage of the smoothing circuit 764a (see (g) in the figure) is larger than the output voltage of the smoothing circuit 764b (see (i) in the figure).

  The phase difference detector 76 outputs the larger output voltage of the smoothing circuit 764a (see (g) in the figure).

  FIG. 3A only shows an example of the internal configuration of the phase difference detection unit 76, and the internal configuration of the phase difference detection unit 76 is not limited to this. In addition, the diodes 765a and 765b are preferably a circuit combining an ideal diode circuit and an inverting amplifier circuit as shown in FIG.

A difference Δφ between the voltage / current phase difference φ detected by the phase difference detector 76 and the predetermined value φ ^* is output to the pulse signal generator 73. Specifically, the differential voltage between the voltage corresponding to the voltage / current phase difference φ output from the phase difference detector 76 and the voltage corresponding to the predetermined value φ ^* is converted into a digital value, and the pulse signal generator 73 Is output.

The pulse signal generation unit 73 generates the pulse signals Pa to Pd, and is realized by, for example, a microcomputer. The pulse signal generation unit 73 generates pulse signals Pa to Pd based on the power value P input from the power calculation unit 71 and the target value P ^* input from the power setting unit 72 and outputs the pulse signals Pa to Pd to the driver 74. . Further, the pulse signal generation unit 73 prevents the voltage / current phase difference φ detected by the phase difference detection unit 76 from becoming smaller than the predetermined value φ ^* . The pulse signal generation unit 73 includes a power control unit 731, a timer unit 732, a switching unit 733, a first pulse signal generation unit 734, and a second pulse signal generation unit 735.

The power control unit 731 is for controlling the power input to the inverter circuit 2. The power control unit 731 receives the power deviation ΔP (= P ^* −P) between the power value P output from the power calculation unit 71 and the target value P ^* output from the power setting unit 72, and the power The power compensation value X for making the deviation ΔP zero is output to the switching unit 733. For example, the power control unit 731 performs PI control. Further, the power control unit 731 has a power compensation value so that the phase difference of the drive signal is not further reduced when the voltage / current phase difference φ detected by the phase difference detection unit 76 becomes a predetermined value φ ^*. Adjust X. Specifically, while the difference Δφ between the voltage / current phase difference φ and the predetermined value φ ^* is a positive value (while the voltage corresponding to the voltage / current phase difference φ is smaller than the voltage corresponding to the predetermined value φ ^* ), The power compensation value X is output as it is, but when the difference Δφ becomes zero (when the voltage corresponding to the voltage-current phase difference φ matches the voltage corresponding to the predetermined value φ ^* ), the power compensation value X is not set to a negative value. Like that.

  The timer unit 732 generates a timer signal for providing a total stop period in which all drive signals are set to a low level. The timer signal is a pulse signal that repeats a low level period of a predetermined time (for example, several hours) and a high level period of another predetermined time (for example, several hundred milliseconds). In the present embodiment, the high level period is set as the entire stop period. Note that the lengths of the low level period and the high level period are not limited. The low level period is set to a time that does not cause a problem even if the leading arm and the tracking arm are not switched. Also, during the high level period, the time when the oscillating current attenuates after the switching of the inverter circuit 2 stops and the effective value of the output current becomes zero is set. The timer signal is also a timing signal for switching between the preceding arm and the follower arm. The timer unit 732 outputs the generated timer signal to the switching unit 733.

  The switching unit 733 switches the output destination of the power compensation value X input from the power control unit 731. The switching unit 733 switches the signal to be output to the first pulse signal generation unit 734 and the second pulse signal generation unit 735 based on the timer signal input from the timer unit 732. That is, the switching unit 733 outputs the power compensation value X to either the first pulse signal generation unit 734 or the second pulse signal generation unit 735 while the timer signal is at a low level (timer OFF), During the high level (timer ON), all stop signals are output to the first pulse signal generation unit 734 and the second pulse signal generation unit 735. In addition, the switching unit 733 switches the output destination of the power compensation value X between the first pulse signal generation unit 734 and the second pulse signal generation unit 735 when the timer signal switches from the high level to the low level. . That is, while the timer signal continues to be high level (until it becomes low level), the output of all stop signals continues, and when the timer signal becomes low level, the power compensation value X output destination Switching takes place. Note that the switching process performed by the switching unit 733 is not limited to the one described above.

  The first pulse signal generation unit 734 generates the pulse signals Pa and Pb that are the basis of the drive signals Pa ′ and Pb ′ input to the switching elements 2 a and 2 b of the first arm, and outputs them to the driver 74. The first pulse signal generation unit 734 generates and outputs a pulse signal Pa having a duty ratio of 50% at a predetermined period during a period when the power compensation value X and the total stop signal are not input from the switching unit 733. Further, during the period when the power compensation value X is input from the switching unit 733, the phase of the pulse signal Pa is delayed and output according to the power compensation value X. Further, the first pulse signal generation unit 734 outputs a signal obtained by inverting the pulse signal Pa during these periods as the pulse signal Pb. On the other hand, the pulse signals Pa and Pb are output as low level signals during the period when the all stop signal is input from the switching unit 733.

  The second pulse signal generation unit 735 generates pulse signals Pc and Pd that are the basis of the drive signals Pc ′ and Pd ′ input to the switching elements 2 c and 2 d of the second arm, and outputs them to the driver 74. The second pulse signal generation unit 735 generates and outputs a pulse signal Pc having a duty ratio of 50% at a predetermined period during a period when the power compensation value X and the total stop signal are not input from the switching unit 733. Further, during the period in which the power compensation value X is input from the switching unit 733, the phase of the pulse signal Pc is delayed and output according to the power compensation value X. Further, the second pulse signal generation unit 735 outputs a signal obtained by inverting the pulse signal Pc during these periods as the pulse signal Pd. On the other hand, the pulse signals Pc and Pd are output as low level signals during the period when the entire stop signal is input from the switching unit 733.

When the inverter device 8 is started, the phases of the pulse signals Pa and Pc (Pb and Pd) match. By the operation of the operation unit, the power setting unit 72 increases the target value P ^* from zero, and the first pulse signal generation unit 734 or the second pulse signal generation unit 735 delays the phase of the pulse signal, so that the inverter circuit 2 outputs power.

  For example, when the power compensation value X is input to the first pulse signal generation unit 734, the pulse signal Pa (Pb) output from the first pulse signal generation unit 734 is the pulse output from the second pulse signal generation unit 735. The phase is delayed from the signal Pc (Pd). As a result, the second arm is a leading arm and the first arm is a follower arm. Conversely, when the power compensation value X is input to the second pulse signal generation unit 735, the first pulse signal generation unit 734 outputs the pulse signal Pc (Pd) output from the second pulse signal generation unit 735. The phase is delayed from the pulse signal Pa (Pb). As a result, the first arm is a leading arm and the second arm is a follower arm.

  When all stop signals are input to the first pulse signal generation unit 734 and the second pulse signal generation unit 735, the pulse signals Pa, Pb, Pc, and Pd are all low level signals. When the input of all stop signals is completed (when the timer signal is switched from high level to low level), the output destination of the power compensation value X is switched, and the preceding arm and the follower arm are switched.

  Note that the pulse signal generation method by the pulse signal generation unit 73 is not limited to the above. The phase of the pulse signals Pa and Pb or the pulse signals Pc and Pd can be delayed according to the power compensation value X output from the power control unit 731, and the entire stop period (the pulse signals Pa, Pb, Pc, and Pd can be It is only necessary to be able to switch between a state in which the phases of the pulse signals Pa and Pb are delayed and a state in which the phases of the pulse signals Pc and Pd are delayed, with a period during which the signal is also at a low level.

  In the present embodiment, the case where the pulse signal generation unit 73 is realized as a digital circuit has been described, but it may be realized as an analog circuit. Further, the processing performed by each unit may be designed by a program, and the computer may function as the pulse signal generation unit 73 by executing the program. The program may be recorded on a recording medium and read by a computer.

  The driver 74 amplifies the pulse signals Pa to Pd input from the pulse signal generation unit 73, and outputs the amplified signals as drive signals Pa 'to Pd' that can drive the switching elements 2a to 2d. In this embodiment, the driver 74 is a pulse transformer type gate drive circuit. Note that the driver 74 is not limited to a pulse transformer type gate drive circuit, and may be another type of gate drive circuit such as a photocoupler type. The driver 74 is designed on the assumption that the duty ratio of the input pulse signals Pa to Pd is 50%. That is, the most economical design capable of operating without a problem when the duty ratio is 50% is made. In order to prevent both of the switching elements 2a and 2b (2c and 2d) from being instantaneously turned on, a dead time may be provided in the drive signals Pa 'to Pd'.

  Next, the operation and effect of the induction heating apparatus A will be described.

The induction heating device A is feedback-controlled so that the power value P calculated by the power calculation unit 71 becomes the target value P ^* set by the power setting unit 72. When the AC power input to the DC power supply 1 fluctuates and the power value P becomes larger than the target value P ^*, or when the target value P ^* is changed to a smaller value by operating the operation unit, the power deviation ΔP is Negative value. In this case, the power compensation value X output from the power control unit 731 becomes a negative value, and the first pulse signal generation unit 734 or the second pulse signal generation unit 735 to which the power compensation value X is input from the switching unit 733 The phase of the output pulse signal advances and the phase difference decreases. As a result, the output power of the inverter circuit 2 decreases, the power input to the DC power supply 1 decreases, and the power value P matches the target value P ^* . Conversely, when the AC power input to the DC power source 1 fluctuates and the power value P becomes smaller than the target value P ^*, or when the target value P ^* is changed to a larger value by operating the operation unit, The deviation ΔP becomes a positive value. In this case, the power compensation value X output from the power control unit 731 becomes a positive value, and the first pulse signal generation unit 734 or the second pulse signal generation unit 735 to which the power compensation value X is input from the switching unit 733 The phase of the output pulse signal is delayed and the phase difference increases. As a result, the output power of the inverter circuit 2 increases, the power input to the DC power source 1 increases, and the power value P matches the target value P ^* .

  The control circuit 7 has a function of providing a full stop period and switching between the preceding arm and the follower arm before and after that. Based on the timer signal input from the timer unit 732, the switching unit 733 of the pulse signal generation unit 73 outputs a power compensation value X to the first pulse signal generation unit 734, and outputs to the second pulse signal generation unit 735. The state in which the power compensation value X is output and the state in which all stop signals are output to the first pulse signal generation unit 734 and the second pulse signal generation unit 735 are switched. While the first pulse signal generation unit 734 receives the power compensation value X, the phase of the pulse signal Pa (Pb) is delayed from the phase of the pulse signal Pc (Pd). Two arms become the leading arm. Conversely, while the second pulse signal generation unit 735 receives the power compensation value X, the phase of the pulse signal Pc (Pd) lags behind the phase of the pulse signal Pa (Pb), so the second arm becomes the follower arm. Thus, the first arm becomes the leading arm. Further, the first pulse signal generation unit 734 and the second pulse signal generation unit 735 are all low level signals while the all stop signals are input, and the inverter circuit 2 The switching operation is stopped.

The phase difference detector 76 detects the smaller one of the voltage / current phase difference φ ₁ in the first arm and the voltage / current phase difference φ ₂ in the second arm as the voltage / current phase difference φ. Then, the pulse signal generation unit 73 performs control so that the voltage / current phase difference φ detected by the phase difference detection unit 76 does not become smaller than the predetermined value φ ^* .

In the present embodiment, control is performed so that the voltage / current phase difference φ detected by the phase difference detector 76 does not become smaller than the predetermined value φ ^*, so that the larger voltage / current phase difference does not become smaller than the predetermined value φ ^* . Therefore, it is possible to control so that the leading phase is not reached in both the first arm and the second arm.

The internal configuration of the phase difference detector 76 is not limited to that shown in FIG. Among the voltage-current phase difference phi ₂ voltage-current phase difference at the first arm phi ₁ and the second arm, as long as it can detect the person smaller as the voltage current phase difference phi.

  FIG. 5A is a diagram for explaining another example of the phase difference detection unit 76 according to the first embodiment.

As shown in FIG. 2, when the first arm is the preceding arm, the voltage / current phase difference φ ₁ is always equal to or smaller than the voltage / current phase difference φ ₂ . Conversely, when the second arm is the preceding arm, the voltage / current phase difference φ ₂ is always equal to or less than the voltage / current phase difference φ ₁ . That is, the voltage / current phase difference of the leading arm is always the smaller voltage / current phase difference. The phase difference detector 76 ′ shown in FIG. 5 uses this to detect the smaller voltage / current phase difference φ.

  A switching signal is input from the switching unit 733 to the phase difference detection unit 76 ′. The switching signal is a signal that is at a high level while the first arm is a preceding arm and that is at a low level while the first arm is a follower arm. The negation circuit 766 is a logic circuit and inverts the switching signal output from the switching unit 733. That is, the signal output from the negation circuit 766 becomes a high level while the second arm is the preceding arm, and becomes a low level while the second arm is the follower arm.

  The logical product circuit 767a is a logical circuit, and outputs a logical product of the pulse signal Pa input from the first pulse signal generation unit 734 and the switching signal input from the switching unit 733. That is, the AND circuit 767a outputs the pulse signal Pa while the first arm is the preceding arm, and outputs the low level signal while the first arm is the follower arm. The logical product circuit 763a is the same as the logical product circuit 763a shown in FIG. 3A, and the logical product of the signal input from the logical product circuit 767a and the current binarized signal output from the binarization circuit 761. Is output. Therefore, the overlap of the high level period of the pulse signal Pa and the current binarization signal is detected only while the first arm is the preceding arm.

  The AND circuit 767b is a logic circuit, and outputs a logical product of the pulse signal Pc input from the second pulse signal generation unit 735 and the signal input from the negation circuit 766. That is, the AND circuit 767b outputs the pulse signal Pc while the second arm is the preceding arm, and outputs the low level signal while the second arm is the follower arm. The AND circuit 763b is similar to the AND circuit 763b shown in FIG. 3A, and outputs a logical product of the signal input from the AND circuit 767b and the inverted signal output from the negation circuit 762. Therefore, the overlap between the high level period of the pulse signal Pc and the inverted signal is detected only while the second arm is the preceding arm.

The logical sum circuit 768 is a logical circuit and outputs a logical sum of the output of the logical product circuit 763a and the output of the logical product circuit 763b. Therefore, the OR circuit 768 detects an overlap of the high level period of the pulse signal Pa and the current binarization signal while the first arm is the leading arm, and the pulse signal Pc while the second arm is the leading arm. And the overlap of the high level period of the inverted signal is detected. The smoothing circuit 764 is the same as the smoothing circuits 764a and 764b shown in FIG. 3A, smoothes the signal output from the OR circuit 768, and outputs it as an analog voltage signal. Therefore, the phase difference detection unit 76 ′ outputs a voltage corresponding to the voltage / current phase difference φ ₁ while the first arm is the leading arm (the voltage / current phase difference φ ₁ is equal to or less than the voltage / current phase difference φ ₂ ). While the second arm is the leading arm (the voltage / current phase difference φ ₂ is equal to or less than the voltage / current phase difference φ ₁ ), the voltage corresponding to the voltage / current phase difference φ ₂ is output. That is, the phase difference detector 76 ′ can detect the smaller voltage / current phase difference φ of the voltage / current phase difference φ ₁ and the voltage / current phase difference φ ₂ .

  FIG. 5B is a diagram for explaining still another example of the phase difference detection unit 76 according to the first embodiment.

  The phase difference detection unit 76 ″ is replaced with timing circuits 769a and 769b and a selection circuit instead of the AND circuits 763a and 763b, the smoothing circuits 764a and 764b, and the diodes 765a and 765b of the phase difference detection unit 76 shown in FIG. The circuit 770 is provided. The phase difference detector 76 ″ detects the time difference between the zero cross points of the voltage signal and the current signal instead of detecting the overlap of the high level period of the voltage signal and the current signal. Current phase difference is detected.

The time measuring circuit 769a detects a time difference from the rising zero cross point of the pulse signal Pa input from the first pulse signal generation unit 734 to the rising zero cross point of the current binarized signal input from the binarization circuit 761. And output. That is, the timer circuit 769a outputs a time difference corresponding to the voltage / current phase difference φ ₁ .

The time measuring circuit 769b detects and outputs a time difference from the rising zero cross point of the pulse signal Pc input from the second pulse signal generation unit 735 to the rising zero cross point of the inverted signal input from the negation circuit 762. In other words, the timer circuit 769b outputs a time difference corresponding to the voltage-current phase difference phi _2.

The selection circuit 770 selects and outputs the smaller time difference between the time difference input from the time measuring circuit 769a and the time difference input from the time measuring circuit 769b. Therefore, the phase difference detector 76 ″ outputs a time difference corresponding to the smaller voltage current phase difference φ of the voltage / current phase difference φ ₁ and the voltage / current phase difference φ _2. The output value of the phase difference detector 76 ″ Is smaller as the voltage-current phase difference φ is smaller. The power control unit 731 (see FIG. 1) adjusts the power compensation value X so that the time difference corresponding to the voltage / current phase difference φ is not smaller than the time difference corresponding to the predetermined value φ ^* .

  In the present embodiment, the case where the duty ratio is 50% has been described, but the present invention is not limited to this. 50% is merely an example, and may be a predetermined value other than 50%.

  In the present embodiment, the inverter circuit is controlled by controlling the AC power input to the DC power source 1 by utilizing the fact that the AC power input to the DC power source 1 is substantially the same as the output power of the inverter circuit 2. Although the output power of 2 is controlled, it is not limited to this. For example, the output power of the inverter circuit 2 may be directly controlled. That is, the power calculation unit 71 may calculate the output power from the output current and output voltage of the inverter circuit 2, and the power setting unit 72 may set the target value of the output power. Further, the DC power input from the DC power source 1 to the inverter circuit 2 may be controlled. Moreover, you may make it control the alternating current input into the direct-current power supply 1, and you may make it control the alternating current power estimated from the said alternating current.

  In the present embodiment, the case of switching between the preceding arm and the follower arm every predetermined time has been described, but the present invention is not limited to this. Even if switching between the preceding arm and the follower arm is performed every predetermined time, in some cases, the heat loss of the switching element on one arm side may increase. In order to suppress this, the temperature of the switching element may be monitored, and switching between the preceding arm and the follower arm may be performed based on this. In addition, when the continuous use time is limited, for example, when the continuous use is performed only for several hours, it is not necessary to perform switching during use, and switching may be performed at the start of use.

  Further, it is possible not to provide a total stop period before switching the arms. Further, the arm may not be switched. Even in these cases, the smaller voltage-current phase difference of the voltage-current phase differences of the two arms can be detected.

  In the first embodiment, the case of performing the phase shift control has been described, but the present invention is not limited to this. The present invention is effective in the case where the phase of the drive signal input to the switching elements of the two arms is shifted and controlled even when performing frequency control. A case where frequency control is performed will be described below as a second embodiment.

  FIG. 6 is a diagram illustrating a waveform of a drive signal of an inverter device that performs frequency control, and is a diagram for explaining that output power changes due to a change in frequency.

  In the figure, the phase difference between the two drive signals is fixed to (3/4) π, and the frequency f (period T) of these drive signals is changed. FIG. ) Is a case where the frequency f is larger (the period T is smaller), and FIG. 9C shows a case where the frequency f is smaller than the period (b) (the period T is larger).

  6 (a), 6 (b), and 6 (c), the top shows the waveform of the drive signal Pa ′ input to the switching element 2a of the first arm, and the bottom is the switching element 2c of the second arm. 2 shows the waveform of the drive signal Pc ′ inputted to the bottom, the current signal I of the current flowing through the coil 5 is shown below, and the bottom is the voltage signal V of the voltage applied to the load.

  As shown in FIG. 6, when the frequency f is decreased (the period T is increased), the time during which a voltage is applied to the load is increased (see voltage signal V), the amplitude of the current signal I is increased, and the inverter circuit 2 Output power increases. Conversely, when the frequency f is increased (the period T is decreased), the time during which the voltage is applied to the load is shortened, the amplitude of the current signal I is decreased, and the output power of the inverter circuit 2 is decreased.

As shown in FIG. 6, when the frequency f is decreased (the period T is increased), the voltage / current phase difference φ ₁ is decreased and the voltage / current phase difference φ ₂ is increased. Conversely, when the frequency f is increased (the period T is decreased), the voltage / current phase difference φ ₁ increases and the voltage / current phase difference φ ₂ decreases.

  FIG. 7 is a diagram for explaining the induction heating device A2 according to the second embodiment. In the same figure, description of the part which is common with the induction heating apparatus A (refer FIG. 1) which concerns on 1st Embodiment is abbreviate | omitted, and it has described focusing on the pulse signal generation part 73 ', and the induction heating apparatus A and The same or similar elements are given the same reference numerals.

  The induction heating device A2 shown in FIG. 7 is different from the induction heating device A according to the first embodiment in that frequency control is performed.

The power control unit 731 ′ receives the power deviation ΔP (= P ^* −P) between the power value P and the target value P ^*, and sets the power compensation value X for making the power deviation ΔP zero as a frequency command unit. 736. In addition, the power control unit 731 ′ uses the power compensation value so that the frequency of the drive signal is not further reduced when the voltage-current phase difference φ detected by the phase difference detection unit 76 reaches the predetermined value φ ^*. Adjust X. Specifically, while the difference Δφ between the voltage / current phase difference φ and the predetermined value φ ^* is a positive value (while the voltage corresponding to the voltage / current phase difference φ is smaller than the voltage corresponding to the predetermined value φ ^* ), The power compensation value X is output as it is, but when the difference Δφ becomes zero (when the voltage corresponding to the voltage-current phase difference φ matches the voltage corresponding to the predetermined value φ ^* ), the power compensation value X is not set to a positive value. Like that.

  The frequency command unit 736 commands the frequency of the pulse signals Pa to Pd. The frequency command unit 736 outputs the frequency changed according to the power compensation value X input from the power control unit 731 ′ to the first pulse signal generation unit 734 and the second pulse signal generation unit 735. When the power compensation value X is a positive value, the frequency command unit 736 decreases the frequency according to the value, and when the power compensation value X is a negative value, the frequency command unit 736 increases the frequency according to the absolute value.

  The switching unit 733 differs from the switching unit 733 according to the first embodiment in that instead of outputting the power compensation value X, a delay signal that instructs to become a follow-up arm is output. The switching unit 733 outputs a delay signal to either the first pulse signal generation unit 734 or the second pulse signal generation unit 735 while the timer signal input from the timer unit 732 is at a low level (timer OFF), While the timer signal is at a high level (timer ON), a full stop signal is output to the first pulse signal generation unit 734 and the second pulse signal generation unit 735. Further, the switching unit 733 switches the destination of the delay signal between the first pulse signal generation unit 734 and the second pulse signal generation unit 735 when the timer signal is switched from the high level to the low level. In other words, while the timer signal continues to be high level (until it becomes low level), the output of all stop signals continues, and when the timer signal becomes low level, the destination to which the delay signal is output is switched. Done. Note that the switching process performed by the switching unit 733 is not limited to the one described above.

  The first pulse signal generation unit 734 generates the pulse signals Pa and Pb at the frequency commanded by the frequency command unit 736 and outputs the pulse signals Pa and Pb to the driver 74. The first pulse signal generation unit 734 generates and outputs a pulse signal Pa during a period when the delay signal and the all stop signal are not input from the switching unit 733. Further, during the period when the delay signal is input from the switching unit 733, the phase of the pulse signal Pa is delayed by a predetermined phase and output. Further, the first pulse signal generation unit 734 outputs a signal obtained by inverting the pulse signal Pa during these periods as the pulse signal Pb. On the other hand, the pulse signals Pa and Pb are output as low level signals during the period when the all stop signal is input from the switching unit 733.

  The second pulse signal generation unit 735 generates pulse signals Pc and Pd at the frequency commanded by the frequency command unit 736 and outputs the pulse signals Pc and Pd to the driver 74. The second pulse signal generation unit 735 generates and outputs the pulse signal Pc during a period when the delay signal and the all stop signal are not input from the switching unit 733. Further, during the period in which the delay signal is input from the switching unit 733, the phase of the pulse signal Pc is delayed by a predetermined phase and output. Further, the second pulse signal generation unit 735 outputs a signal obtained by inverting the pulse signal Pc during these periods as the pulse signal Pd. On the other hand, the pulse signals Pc and Pd are output as low level signals during the period when the entire stop signal is input from the switching unit 733.

The induction heating device A2 is feedback-controlled so that the power value P calculated by the power calculation unit 71 becomes the target value P ^* set by the power setting unit 72. When the AC power input to the DC power supply 1 fluctuates and the power value P becomes larger than the target value P ^*, or when the target value P ^* is changed to a smaller value by operating the operation unit, the power deviation ΔP is Negative value. In this case, the power compensation value X output from the power control unit 731 ′ becomes a negative value, the frequency commanded by the frequency command unit 736 increases, and the first pulse signal generation unit 734 and the second pulse signal generation unit 735 The frequency of the pulse signal output from becomes larger. As a result, the output power of the inverter circuit 2 decreases, the power input to the DC power supply 1 decreases, and the power value P matches the target value P ^* . Conversely, when the AC power input to the DC power source 1 fluctuates and the power value P becomes smaller than the target value P ^*, or when the target value P ^* is changed to a larger value by operating the operation unit, The deviation ΔP becomes a positive value. In this case, the power compensation value X output from the power control unit 731 ′ becomes a positive value, the frequency commanded by the frequency command unit 736 becomes small, and the first pulse signal generation unit 734 and the second pulse signal generation unit 735 The frequency of the pulse signal output from becomes smaller. As a result, the output power of the inverter circuit 2 increases, the power input to the DC power source 1 increases, and the power value P matches the target value P ^* .

  The control circuit 7 has a function of providing a full stop period and switching between the preceding arm and the follower arm before and after that. Based on the timer signal input from the timer unit 732, the switching unit 733 of the pulse signal generation unit 73 ′ outputs a delay signal to the first pulse signal generation unit 734, and delays to the second pulse signal generation unit 735. A state of outputting a signal and a state of outputting a full stop signal to the first pulse signal generation unit 734 and the second pulse signal generation unit 735 are switched. While the delay signal is input to the first pulse signal generator 734, the phase of the pulse signal Pa (Pb) is delayed from the phase of the pulse signal Pc (Pd), so the first arm becomes the follower arm and the second arm Becomes the leading arm. Conversely, while the second pulse signal generation unit 735 receives the delay signal, the phase of the pulse signal Pc (Pd) lags behind the phase of the pulse signal Pa (Pb), so the second arm becomes the tracking arm, The first arm becomes the leading arm. Further, the first pulse signal generation unit 734 and the second pulse signal generation unit 735 are all low level signals while the all stop signals are input, and the inverter circuit 2 The switching operation is stopped.

The phase difference detector 76 detects the smaller one of the voltage / current phase difference φ ₁ in the first arm and the voltage / current phase difference φ ₂ in the second arm as the voltage / current phase difference φ. Then, the pulse signal generation unit 73 ′ performs control so that the voltage / current phase difference φ detected by the phase difference detection unit 76 does not become smaller than the predetermined value φ ^* .

Also in the second embodiment, since the voltage / current phase difference φ detected by the phase difference detection unit 76 is controlled not to be smaller than the predetermined value φ ^* , the larger voltage / current phase difference does not become smaller than the predetermined value φ ^* . Therefore, it is possible to control so that the leading phase is not reached in both the first arm and the second arm.

In the first embodiment, in order to prevent the voltage / current phase difference φ detected by the phase difference detector 76 from becoming smaller than the predetermined value φ ^* , when the difference Δφ becomes zero, the power compensation value X is set to a negative value. The phase difference between the pulse signal on the preceding arm side and the pulse signal on the following arm side is not further reduced. In this case, since the phase difference cannot be reduced, the output power cannot be reduced. Conversely, in the second embodiment, in order to prevent the voltage / current phase difference φ detected by the phase difference detector 76 from becoming smaller than the predetermined value φ ^* , when the difference Δφ becomes zero, the power compensation value X is set to the positive value. The frequency of each pulse signal is not further reduced. In this case, since the frequency cannot be reduced, the output power cannot be increased.

  Normally, phase shift control is performed, and when the output power is reduced in a state where the difference Δφ is zero, switching to frequency control may be performed. The case where this control is switched will be described below as a third embodiment.

  FIG. 8 is a diagram for explaining the induction heating device A3 according to the third embodiment. In the figure, the description of the parts common to the induction heating device A (see FIG. 1) according to the first embodiment is omitted, and the pulse signal generation unit 73 ″ is mainly described, and the induction heating device A and The same or similar elements are given the same reference numerals.

  The induction heating device A3 shown in FIG. 8 is different from the induction heating device A according to the first embodiment in that the phase shift control and the frequency control are switched.

The power control unit 731 ″ receives the power deviation ΔP (= P ^* −P) between the power value P and the target value P ^*, and controls the power compensation value X for making the power deviation ΔP zero. Output to 737.

The control switching unit 737 switches between the phase shift control and the frequency control by switching the output destination of the power compensation value X. The control switching unit 737 normally outputs the power compensation value X to the switching unit 733 so as to perform phase shift control in the same manner as the pulse signal generation unit 73 according to the first embodiment. However, when the voltage / current phase difference φ detected by the phase difference detection unit 76 becomes the predetermined value φ ^* and the power compensation value X is a negative value, the power compensation value X is output to the frequency command unit 736. The frequency control is performed similarly to the pulse signal generation unit 73 ′ according to the second embodiment. As a result, the frequency of the pulse signal can be increased to reduce the output.

When the phase shift control is switched to the frequency control, the phase difference between the pulse signal on the preceding arm side and the pulse signal on the following arm side is fixed, and the frequency control is performed with the phase difference unchanged. Further, the preceding arm and the follower arm are switched by the switching unit 733. However, the phase difference detection unit 76 can detect the smaller one of the voltage / current phase difference φ ₁ in the first arm and the voltage / current phase difference φ ₂ in the second arm as the voltage / current phase difference φ. Therefore, also in the third embodiment, the pulse signal generation unit 73 ″ controls the voltage / current phase difference φ so as not to be smaller than the predetermined value φ ^* , so that the advance can be performed in both the first arm and the second arm. It can control so that it may not become a phase.

  In 1st thru | or 3rd Embodiment, although the case where this invention was used for the inverter apparatus 8 of the induction heating apparatus was demonstrated, it is not restricted to this. The present invention can be used for all inverter devices that perform phase shift control. For example, you may make it use this invention for the inverter apparatus of a power supply device (a high frequency power supply device, a welding power supply device, a non-contact electric power feeder, etc.) or a drive device. That is, the present invention can also be used when the inverter device 8 supplies power to another load instead of the load (the coil 5, the resonance capacitor 6 and the heating object B) in FIG.

  The control circuit of the inverter circuit according to the present invention, the inverter device provided with the control circuit, the induction heating device provided with the inverter device, and the control method are not limited to the above-described embodiments. The specific configuration of each part of the control circuit of the inverter circuit according to the present invention, the inverter device provided with the control circuit, the induction heating device provided with the inverter device, and the control method can be varied in various ways.

A, A2, A3 Induction heating device 1 DC power supply 2 Inverter circuit 2a, 2b, 2c, 2d Switching element 3a, 3b, 3c, 3d Flywheel diode 4a, 4b, 4c, 4d Snubber capacitor 5 Coil 6 Resonant capacitor 7 Control circuit 71 power calculation unit 72 power setting unit 73, 73 ′, 73 ″ pulse signal generation unit 731, 731 ′ power control unit 732 timer unit 733 switching unit (switching means)
734 First pulse signal generator (first drive signal generator)
735 Second pulse signal generator (second drive signal generator)
736 Frequency command unit 737 Control switching unit 74 Driver (first drive signal generation unit, second drive signal generation unit)
75 Current detector 76, 76 ', 76 "Phase difference detector (phase difference detector)
761 Binary circuit 762,766 Negative circuit 763a, 763b, 767a, 767b AND circuit 764a, 764b, 764 Smoothing circuit 765a, 765b Diode 768 OR circuit 769a, 769b Timing circuit 770 Select circuit 8 Inverter device B Heating object

Claims (10)

A control circuit that inputs a drive signal to the inverter circuit and controls the inverter circuit,
First drive signal generating means for generating a first drive signal to be input to a switching element disposed on one arm of the inverter circuit;
Second drive signal generation means for generating a second drive signal to be input to a switching element disposed on the other arm of the inverter circuit;
A first voltage / current phase difference, which is the difference between the phase of the output current signal of the inverter circuit and the phase of the first drive signal, and the difference between the phase of the inverted signal of the output current signal and the phase of the second drive signal Phase difference detection means for detecting the smaller one of the second voltage and current phase differences,
A control circuit characterized by that. A phase difference that is a difference between the phase of the first drive signal and the phase of the second drive signal is set so that the smaller voltage-current phase difference detected by the phase difference detection means does not become smaller than a predetermined phase difference. By controlling the output of the inverter circuit,
The control circuit according to claim 1. By changing the frequencies of the first drive signal and the second drive signal so that the smaller voltage-current phase difference detected by the phase difference detection means does not become smaller than a predetermined phase difference, the inverter circuit Control the output,
The control circuit according to claim 1 or 2. There is further provided switching means for switching between a state in which the phase of the first drive signal is advanced from the phase of the second drive signal and a state in which the phase of the first drive signal is delayed from the phase of the second drive signal. ,
The control circuit according to claim 1. The phase difference detecting means includes
Smoothing a logical product of the binarized signal of the output current signal and the first drive signal to generate a signal corresponding to the first voltage-current phase difference;
Smoothing the logical product of the inverted signal of the binarized signal and the second drive signal to generate a signal corresponding to the second voltage-current phase difference;
The larger signal of the signal corresponding to the first voltage / current phase difference and the signal corresponding to the second voltage / current phase difference is output as a signal corresponding to the smaller voltage / current phase difference,
The control circuit according to claim 1. The phase difference detecting means includes
When the phase of the first drive signal is ahead of that of the second drive signal, a signal obtained by smoothing the logical product of the binarized signal of the output current signal and the first drive signal is set to a smaller voltage. Output as a signal corresponding to the current phase difference,
When the phase of the second drive signal is ahead of that of the first drive signal, a signal obtained by smoothing the logical product of the inverted signal of the binary signal of the output current signal and the second drive signal is small. Output as a signal corresponding to the voltage-current phase difference of
The control circuit according to claim 1. The phase difference detecting means includes
Generating a time difference from a rising zero cross of the first drive signal to a negative zero cross of the output current signal as a signal corresponding to the first voltage-current phase difference;
Generating a time difference from a rising zero cross of the second drive signal to a negative zero cross of the output current signal as a signal corresponding to the second voltage current phase difference;
A smaller one of the signal corresponding to the first voltage-current phase difference and the signal corresponding to the second voltage-current phase difference is output as a signal corresponding to the smaller voltage-current phase difference;
The control circuit according to claim 1. An inverter circuit; and a control circuit according to any one of claims 1 to 7;
An inverter device comprising: A DC power supply, the inverter device according to claim 8, a coil that generates a magnetic field by an alternating current input from the inverter device,
An induction heating apparatus comprising: A control method for controlling an inverter circuit,
A first step of generating a first drive signal to be input to a switching element disposed on one arm of the inverter circuit;
A second step of generating a second drive signal to be input to the switching element disposed on the other arm;
A third step of inputting the generated first drive signal and second drive signal to the corresponding switching elements;
A first voltage / current phase difference, which is the difference between the phase of the output current signal of the inverter circuit and the phase of the first drive signal, and the difference between the phase of the inverted signal of the output current signal and the phase of the second drive signal A fourth step of detecting the smaller one of the second voltage and current phase differences,
With
A phase difference that is a difference between the phase of the first drive signal and the phase of the second drive signal is set so that the smaller voltage-current phase difference detected in the fourth step is not smaller than a predetermined phase difference. Change,
A control method characterized by that.