JP2015119163A - Mounting substrate for surface-mounting semiconductor sensor and mounting method of the same - Google Patents
Mounting substrate for surface-mounting semiconductor sensor and mounting method of the same Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 135
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 238000002844 melting Methods 0.000 claims abstract description 6
- 230000008018 melting Effects 0.000 claims abstract description 6
- 239000000919 ceramic Substances 0.000 claims description 20
- 239000003112 inhibitor Substances 0.000 claims description 12
- 229910052738 indium Inorganic materials 0.000 claims description 8
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000004080 punching Methods 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 description 12
- -1 CdZnTe compound Chemical class 0.000 description 6
- 239000010931 gold Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 4
- QWUZMTJBRUASOW-UHFFFAOYSA-N cadmium tellanylidenezinc Chemical compound [Zn].[Cd].[Te] QWUZMTJBRUASOW-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000155 melt Substances 0.000 description 4
- 238000003825 pressing Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- QKEOZZYXWAIQFO-UHFFFAOYSA-M mercury(1+);iodide Chemical compound [Hg]I QKEOZZYXWAIQFO-UHFFFAOYSA-M 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- UBZYKBZMAMTNKW-UHFFFAOYSA-J titanium tetrabromide Chemical compound Br[Ti](Br)(Br)Br UBZYKBZMAMTNKW-UHFFFAOYSA-J 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 101001045744 Sus scrofa Hepatocyte nuclear factor 1-beta Proteins 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910001338 liquidmetal Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000010345 tape casting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Measurement Of Radiation (AREA)
- Die Bonding (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
本発明は、表面実装する実装基板に関するもので、より詳細には、半導体センサーを表面実装する実装基板およびその実装方法に関するものである。 The present invention relates to a mounting substrate that is surface-mounted, and more particularly, to a mounting substrate that surface-mounts a semiconductor sensor and a mounting method thereof.
半導体のチップの小型化、多機能化、高性能化、大容量化が急速に行われるにしたがってパッケージング(packaging)技術は、最終的に、デバイスの電気的性能、信頼性、生産性、および電子システムの小型化を決定づける重要な技術として、その重要性が増している。パッケージング技術というのは、ウェハ工程で作られた個々のチップを最終的に製品化する一連の工程を意味する。最近では、単位体積当たりの実装効率をさらに高めるために、ＢＧＡ(Ball Grid Array)、チップサイズとほぼ同じサイズのＣＳＰ(Chip Scale Pakage)、チップ上に別のチップを積層(stack)させて積み上げたり、機能が異なる複数の半導体チップを一つのパッケージの中に配列するマルチチップモジュール(Multi Chip Module, MCM)などの技術が登場している。 As semiconductor chips become smaller, multifunctional, higher performance, and larger in capacity, packaging technology will ultimately lead to device electrical performance, reliability, productivity, and As an important technology that determines the miniaturization of electronic systems, its importance is increasing. The packaging technology means a series of processes for finally commercializing individual chips produced in the wafer process. Recently, in order to further increase the mounting efficiency per unit volume, BGA (Ball Grid Array), CSP (Chip Scale Pakage) of almost the same size as the chip size, and another chip stacked on the chip are stacked. In addition, a technology such as a multi-chip module (MCM) in which a plurality of semiconductor chips having different functions are arranged in one package has appeared.
半導体やＬＥＤチップは、プリント回路基板（ＰＣＢ、ＦＰＣＢ）上にチップとパッケージ部分を接合する工程を経て、ここで、一般的に、ボンディング方法として、ソルダーボールをリフロー(reflow)させる方式を用いることになる。つまり、個々のパッケージをプリント基板に接続するためのはんだ付け工程を実行することになる。特に、従来のストリップ型あるいはピクセル型半導体センサは、金属膜が粘着する粘性溶液を用いるリフロー方式で単層または多層セラミックにボンディングされる。 Semiconductors and LED chips go through a process of bonding the chip and package part on a printed circuit board (PCB, FPCB). Here, generally, a method of reflowing solder balls is used as a bonding method. become. That is, a soldering process for connecting individual packages to the printed circuit board is executed. In particular, a conventional strip type or pixel type semiconductor sensor is bonded to a single layer or multilayer ceramic by a reflow method using a viscous solution to which a metal film adheres.
図１を参照すると、これは、従来の技術によるソルダーボール方式で、プリント回路基板に電子素子用チップをボンディングする工程を説明するための図である。 Referring to FIG. 1, this is a diagram for explaining a process of bonding a chip for an electronic device to a printed circuit board by a solder ball method according to a conventional technique.
具体的には、電子素子用パッケージは、基本的には図１を参照すると、従来のフリップチップ接合方式による半導体パッケージ基板の場合を例に説明すると、絶縁基板１０上に回路パターン２０が形成され、順次にソルダーレジスト５０、そしてチップを実装するダイアタッチエポキシ６０を媒介にして、チップ７０が実装され、前記チップ７０は、回路パターン２０とワイヤ８０がボンディングされ、前記チップとワイヤを保護するためのモールディング９０が形成される構造を有することになる。特に、一般的にこのような半導体パッケージ基板は、後でボード(Board)にボンディングするための媒介体として基板の下部にソルダーボール３０を備え、前記のソルダーボール３０は、基板の回路パターン２０とソルダーパット４０を介して電気的に導通を可能にする。つまり、プリント回路基板１は、絶縁基板２上に回路パターン３が形成された構造の基板を形成することになり、回路パターン３とパッケージのソルダーボール３０が接触してボンディングがなされる。しかし、これらのソルダボンディング方法は、鉛が主成分の材料を使用するため、環境的に不利な材料を用いている。 Specifically, referring to FIG. 1, the electronic device package is basically described as an example of a conventional semiconductor package substrate using a flip chip bonding method. In this case, a circuit pattern 20 is formed on an insulating substrate 10. The chip 70 is mounted through the solder resist 50 and the die attach epoxy 60 for mounting the chip in order, and the chip 70 is bonded to the circuit pattern 20 and the wire 80 to protect the chip and the wire. The molding 90 is formed. In particular, such a semiconductor package substrate generally includes a solder ball 30 at the bottom of the substrate as a medium for later bonding to the board, and the solder ball 30 is connected to the circuit pattern 20 of the substrate. Electrical conduction is enabled through the solder pad 40. That is, the printed circuit board 1 forms a substrate having a structure in which the circuit pattern 3 is formed on the insulating substrate 2, and the circuit pattern 3 and the solder ball 30 of the package come into contact with each other for bonding. However, these solder bonding methods use materials that are environmentally disadvantageous because they use lead-based materials.
つまり、シリコン（Ｓｉ）のように化学的に安定した半導体以外に、カドミウム亜鉛テルライド（ＣｄＺｎＴｅ）、テルル化カドミウム（ＣｄＴｅ）、臭化チタン（ＴｉＢｒ）、ヨウ化水銀（ＨｇＩ２）のような半導体の場合、化学的に反応または汚染の原因となり、その性能を果たし得ないという短所がある。また、ボンディング時に使用される高温は、このような化合物半導体に大きな影響を与える欠点がある。従来の平面タイプセラミックまたはＰＣＢを用いた半導体実装時の光の反射抑制剤または閃光体のような物質を半導体と結合して使用する場合、工程上多くの困難がある。 That is, in addition to a chemically stable semiconductor such as silicon (Si), a semiconductor such as cadmium zinc telluride (CdZnTe), cadmium telluride (CdTe), titanium bromide (TiBr), and mercury iodide (HgI 2 ). In this case, there is a disadvantage in that the chemical reaction or contamination may not be performed. Moreover, the high temperature used at the time of bonding has the fault of having a big influence on such a compound semiconductor. When a material such as a light reflection inhibitor or a flash body is used in combination with a semiconductor when a conventional planar type ceramic or PCB is used for semiconductor mounting, there are many difficulties in the process.
本発明が解決しようとする技術的課題は、低い温度で溶け、粘着性の強い金属ボールを用いて半導体に影響を与えずに、化学反応や汚染のない半導体センサーを表面実装する実装基板およびその実装方法を提供する。 A technical problem to be solved by the present invention is a mounting substrate for surface mounting a semiconductor sensor free from chemical reaction or contamination without affecting the semiconductor by using a metal ball that melts at a low temperature and has high adhesion. Provide an implementation method.
本発明が解決しようとする他の技術的課題は、顕微鏡なしで肉眼にボンディングをする半導体センサーを表面実装する実装基板およびその実装方法を提供する。 Another technical problem to be solved by the present invention is to provide a mounting substrate for surface mounting a semiconductor sensor that is bonded to the naked eye without a microscope, and a mounting method thereof.
本発明が解決しようとするもう一つの技術的課題は、光反射抑制剤を塗布または閃光体の実装を容易にする、半導体センサーを表面実装する実装基板およびその実装方法を提供する。 Another technical problem to be solved by the present invention is to provide a mounting substrate on which a semiconductor sensor is surface-mounted and a mounting method thereof, which make it easy to apply a light reflection inhibitor or mount a flash body.
半導体センサーを表面実装する実装方法は、
金属パターンが形成された複数の基板の上面に溝が形成された実装基板を生成する第１の工程と、前記溝に金属ボールを安着する第２工程と、前記安着された金属ボールをリフロー(reflow)工程を通じて融解する第３工程と、前記融解した金属ボールの上側に半導体を実装する第４工程とを含む。
The mounting method for surface mounting a semiconductor sensor is
A first step of generating a mounting substrate having grooves formed on the upper surfaces of a plurality of substrates on which a metal pattern is formed; a second step of seating metal balls on the grooves; and the seated metal balls A third step of melting through a reflow step and a fourth step of mounting a semiconductor on the molten metal ball are included.
金属パターンが形成された複数の基板と孔が形成された少なくとも一つのダミー(dummy)基板を含み、前記複数の基板の上面に前記ダミー基板を圧着して溝を形成し、前記溝の底面に金属パットを具備し、前記複数の基板と、前記ダミー基板が圧着された形状の垂直断面が左右対称の∪字形状である。 A plurality of substrates having a metal pattern formed thereon and at least one dummy substrate having holes formed therein, and forming a groove by pressing the dummy substrate on an upper surface of the plurality of substrates; It has a metal pad, and the vertical cross section of the shape in which the plurality of substrates and the dummy substrate are pressure-bonded has a right-and-left symmetrical shape.
本発明に係る半導体センサーを表面実装する実装基板およびその実装方法は、低い温度で溶け、粘着性の強い金属ボールを用いて半導体に影響を与えず、化学反応や汚染の問題がない。 The mounting substrate on which the semiconductor sensor according to the present invention is surface-mounted and the mounting method thereof do not affect the semiconductor using a metal ball that melts at a low temperature and has high adhesion, and does not have a problem of chemical reaction or contamination.
また、高価な顕微鏡なしに肉眼でボンディングをする。 Bonding with the naked eye without an expensive microscope.
また、光反射抑制剤を塗布または閃光体の実装を容易にする。 In addition, it makes it easy to apply a light reflection inhibitor or mount a flashing body.
以下、本発明の実施例を添付の図を参照して詳細に説明することにする。まず、各図の構成要素に参照符号を付加するにおいて、同一の構成要素には、たとえ他の図上に表示されても、可能な限り同一符号を有するようにしていることに留意する必要がある。また、本発明を説明するにおいて、関連した公知の構成または機能に関する具体的な説明が当業者には自明で、または本発明の要旨を曖昧にすると判断される場合には、その詳細な説明は省略し得る。 Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components in each figure, it is necessary to keep in mind that the same components have the same reference numerals as much as possible even if they are displayed on other diagrams. is there. Further, in the description of the present invention, if a specific description related to a known configuration or function is obvious to a person skilled in the art, or it is determined that the gist of the present invention is ambiguous, the detailed description will be Can be omitted.
図２は、本発明の一実施形態による半導体センサーの表面実装を説明するための図である。 FIG. 2 is a view for explaining surface mounting of a semiconductor sensor according to an embodiment of the present invention.
図２を参照すると、図２（ａ）は、表面実装を垂直断面で示した断面図であり、図２（ｂ）は、表面実装の上面を示した上面図である。より詳細には、図２（ａ）および図２（ｂ）は、金属ボール２３０が実装基板２１０に安着される様子を示した例示図である。 Referring to FIG. 2, FIG. 2 (a) is a cross-sectional view showing a surface mounting in a vertical cross section, and FIG. 2 (b) is a top view showing a top surface of the surface mounting. More specifically, FIG. 2A and FIG. 2B are exemplary views showing how the metal ball 230 is seated on the mounting substrate 210.
図２（ａ）は、金属ボール２３０が、複数の基板２１１、２１２、２１３、２１４、２１５および２１６と孔が形成されたダミー(dummy)基板２１７、２１８を含んだ実装基板２１０への安着を示した断面図である。 FIG. 2A shows that a metal ball 230 is attached to a mounting substrate 210 including a plurality of substrates 211, 212, 213, 214, 215 and 216 and dummy substrates 217 and 218 in which holes are formed. It is sectional drawing which showed.
実装基板２１０は、ダミー基板２１７、２１８を複数の基板２１１、２１２、２１３、２１４、２１５および２１６の上面に圧着したものであり得る。実装基板２１０の垂直断面は左右対称な∪字形状であり得る。複数の基板２１１、２１２、２１３、２１４、２１５および２１６は、セラミック基板やプリント回路基板(Printed Circuit Board, PCB)であり得る。複数の基板２１１、２１２、２１３、２１４、２１５および２１６は、８０μｍないし１２０μｍの厚さを成し得る。また、ダミー基板２１７、２１８は、金属ボール２３０が安着されるので、前記金属ボール２３０は、ダミー基板の高さよりも直径が大きいことが好ましいことがあり得る。 The mounting substrate 210 may be a substrate in which dummy substrates 217 and 218 are pressure-bonded to the upper surfaces of the plurality of substrates 211, 212, 213, 214, 215 and 216. The vertical cross section of the mounting substrate 210 may have a symmetrical left and right shape. The plurality of substrates 211, 212, 213, 214, 215, and 216 may be ceramic substrates or printed circuit boards (PCBs). The plurality of substrates 211, 212, 213, 214, 215, and 216 may have a thickness of 80 μm to 120 μm. Further, since the metal balls 230 are seated on the dummy substrates 217 and 218, it may be preferable that the metal balls 230 have a diameter larger than the height of the dummy substrate.
実装基板２１０は、ダミー基板２１７、２１８の孔の大きさに応じて、溝の大きさが決定され得る。実装基板２１０は、ダミー基板２１７、２１８の積層量に応じて溝の深さが決定され得る。また、実装基板２１０の溝は、金属ボール２３０がリフロー(reflow)を通じて液体状態に融解された時、前記液体状態の金属ボールで満たし得る。 In the mounting substrate 210, the size of the groove can be determined according to the size of the holes of the dummy substrates 217 and 218. In the mounting substrate 210, the depth of the groove can be determined according to the stacking amount of the dummy substrates 217 and 218. Further, the groove of the mounting substrate 210 may be filled with the metal ball in the liquid state when the metal ball 230 is melted into the liquid state through reflow.
図２（ｂ）は、金属ボール２３０が、複数の基板２１１、２１２、２１３、２１４、２１５および２１６と孔が形成されたダミー基板２１７、２１８を含んだ実装基板２１０への安着を示した上面図である。 FIG. 2 (b) shows that the metal ball 230 is seated on the mounting substrate 210 including the plurality of substrates 211, 212, 213, 214, 215 and 216 and the dummy substrates 217 and 218 in which holes are formed. It is a top view.
実装基板２１０は、ダミー基板２１７、２１８の孔形状に応じて、溝の形状を決定することができる。ダミー基板２１７、２１８の孔形状は、円形、三角形、正方形、多角形のいずれかの形状であり得る。実装基板２１０は、実装される半導体の形、大きさ、材質に応じて、溝の形状を決定することができる。 The mounting substrate 210 can determine the shape of the groove according to the hole shape of the dummy substrates 217 and 218. The hole shape of the dummy substrates 217 and 218 may be any one of a circle, a triangle, a square, and a polygon. The mounting substrate 210 can determine the shape of the groove according to the shape, size, and material of the semiconductor to be mounted.
図３〜図１２は、本発明の一実施形態に係る半導体センサーの表面実装する方法を説明するための流れ図である。 3 to 12 are flowcharts for explaining a method of surface mounting a semiconductor sensor according to an embodiment of the present invention.
図３〜図１２を参照すると、表面実装は、低い温度で溶けて粘着性の強い金属ボール２３０を用いて、半導体に影響を与えずに化学反応や汚染の問題をなくし得る。表面実装は、顕微鏡なしで肉眼でボンディングすることができる。 Referring to FIGS. 3 to 12, surface mounting can eliminate the problems of chemical reaction and contamination without affecting the semiconductor by using a metal ball 230 that melts at a low temperature and has high adhesion. Surface mounting can be bonded with the naked eye without a microscope.
実装基板２１０は、複数の基板２１１、２１２、２１３、２１４、２１５および２１６と孔が形成された少なくとも一つのダミー基板２１７、２１８が含まれている。実装基板２１０は、複数の基板２１１、２１２、２１３、２１４、２１５および２１６の上面にダミー基板２１７、２１８を圧着して溝を形成し得る。前記溝は、ダミー基板２１７、２１８の積層量や孔の大きさに応じて調節することができる。このように、実装基板２１０は、ダミー基板２１７、２１８の積層量に応じて光反射抑制剤などの溶液を塗布した場合には、前記溶液を垂らさないようにできる。 The mounting substrate 210 includes a plurality of substrates 211, 212, 213, 214, 215, and 216 and at least one dummy substrate 217 and 218 in which holes are formed. The mounting substrate 210 can form grooves by pressing the dummy substrates 217 and 218 on the upper surfaces of the plurality of substrates 211, 212, 213, 214, 215 and 216. The groove can be adjusted according to the stacking amount of the dummy substrates 217 and 218 and the size of the holes. As described above, the mounting substrate 210 can prevent the solution from dripping when a solution such as a light reflection inhibitor is applied according to the amount of the dummy substrates 217 and 218 stacked.
実装基板２１０は、前記溝の底面に金属パット２２０を具備し得る。前記金属パット２２０は、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）、アルミニウム（Ａｌ）および前記金属の合金中の少なくとも一つの金属を含むことができる。 The mounting substrate 210 may include a metal pad 220 on the bottom surface of the groove. The metal pad 220 may include at least one metal in gold (Au), silver (Ag), copper (Cu), aluminum (Al), and an alloy of the metals.
実装基板２１０のホームは、金属ボール２３０が安着することができる。金属ボール２３０は、実装基板２１０の上側に撒いた、多量の金属ボールのいずれかの金属ボールであり得る。また、実装基板２１０は、一つの溝に一つの金属ボール２３０が安着することができる。このように、実装基板２１０は、金属ボール２３０を顕微鏡および精密シリンジなどの高価な装置を使用しなくても、ホームに安着させることができる。 The metal ball 230 can be seated on the home of the mounting substrate 210. The metal ball 230 may be any one of a large number of metal balls that are placed on the upper side of the mounting substrate 210. Further, the mounting substrate 210 can have one metal ball 230 seated in one groove. As described above, the mounting board 210 can make the metal ball 230 sit at home without using an expensive device such as a microscope and a precision syringe.
特に、金属ボール２３０は、低い温度で溶け、粘着性の強い金属ボールであり得る。特に、金属ボール２３０は、融点が９０℃〜１１０℃であり得、直径は１０μｍないし１００μｍであり得る。前記金属ボール２３０は、Ｉｎ／Ａｇ、Ｉｎ／Ｐｂ、Ｓｎ／Ｐｂ、Ｓｎ／Ａｇを含むことができ、金属ボール２３０は、インジウムボール(Indium ball)であることが好ましい。 In particular, the metal ball 230 may be a metal ball that melts at a low temperature and has high adhesion. In particular, the metal ball 230 may have a melting point of 90 ° C. to 110 ° C. and a diameter of 10 μm to 100 μm. The metal ball 230 may include In / Ag, In / Pb, Sn / Pb, and Sn / Ag, and the metal ball 230 is preferably an indium ball.
実装基板２１０は、金属ボール２３０を融解するためにリフロー工程を実行することができる。実装基板２１０は、リフロー工程を経て溝に液体の状態になった金属ボール２３０をいっぱいに満たすことができる。 The mounting substrate 210 can perform a reflow process to melt the metal balls 230. The mounting substrate 210 can fully fill the metal balls 230 that are in a liquid state in the grooves after the reflow process.
前記のリフロー工程は、リフローオーブン(reflow oven)を用いることができる。前記のリフロー工程は、金属ボール２３０の融点を考慮して工程を実行することができる。また、前記リフロー工程の時間は、１秒から１時間までに制限することができる。 In the reflow process, a reflow oven can be used. The reflow process may be performed in consideration of the melting point of the metal ball 230. The reflow process time can be limited to 1 second to 1 hour.
実装基板２１０は、融解した金属ボール２３０の上側に、半導体２４０が実装され得る。実装基板２１０は、半導体のパターンにしたがって実装することができる。実装基板２１０は、溝に満たされた液体状態の金属ボールの上側に、半導体２４０を実装し得る。実装基板２１０は、非常に優れた平面度を維持することができる。 The mounting substrate 210 may have the semiconductor 240 mounted on the upper side of the molten metal ball 230. The mounting substrate 210 can be mounted according to a semiconductor pattern. The mounting substrate 210 can mount the semiconductor 240 on the upper side of the liquid state metal ball filled in the groove. The mounting substrate 210 can maintain very good flatness.
半導体２４０は、ダミー基板２１７、２１８に生じた溝によって外部の衝撃から保護することができる。半導体２４０は、化合物半導体およびシリコン半導体のいずれかをベースにした半導体であり得る。半導体２４０は、ピクセル型またはストリップ型であり得る。 The semiconductor 240 can be protected from external impacts by grooves formed in the dummy substrates 217 and 218. The semiconductor 240 may be a semiconductor based on either a compound semiconductor or a silicon semiconductor. The semiconductor 240 may be a pixel type or a strip type.
半導体２４０の実装は、いかなる化学薬品も使用しないので、化学的な反応をし得る化合物半導体に影響を与えないようにできる。前記化合物半導体は、カドミウム亜鉛テルライド（ＣｄＺｎＴｅ）、テルル化カドミウム（ＣｄＴｅ）、臭化チタン（ＴｉＢｒ）、ヨウ化水銀（ＨｇＩ２）のいずれかであり得る。 The implementation of the semiconductor 240 does not use any chemicals, so that it does not affect compound semiconductors that can react chemically. The compound semiconductor may be any of cadmium zinc telluride (CdZnTe), cadmium telluride (CdTe), titanium bromide (TiBr), and mercury iodide (HgI 2 ).
実装基板２１０は、光反射抑制剤２５０と閃光体２６０のうち少なくとも一つの物質を実装または塗布することができる。実装基板２１０は、ダミー基板２１７、２１８に生じた溝を用いて、光反射抑制剤２５０を塗布し、閃光体２６０を実装することができる。特に、閃光体２６０は、ダミー基板を支持台として用いて実装することができ、前記ダミー基板は閃光体２６０の種類、サイズ、形態に応じて数を調節することができる。 The mounting substrate 210 can mount or apply at least one of the light reflection inhibitor 250 and the flash body 260. The mounting substrate 210 can be mounted with the flash body 260 by applying the light reflection inhibitor 250 using grooves formed in the dummy substrates 217 and 218. In particular, the flash body 260 can be mounted using a dummy substrate as a support, and the number of the dummy substrate can be adjusted according to the type, size, and form of the flash body 260.
図１３は、本発明の一実施形態による半導体センサーの表面実装する方法を説明するための流れ図である。 FIG. 13 is a flowchart for explaining a method of surface mounting a semiconductor sensor according to an embodiment of the present invention.
図１３を参照すると、実装基板２１０は、金属ボール２３０が溝に安着すると、リフロー工程を通じて半導体センサが実装され得る。また、実装基板２１０は、光反射抑制剤を塗布または閃光体の実装を追加することができる。 Referring to FIG. 13, the semiconductor sensor may be mounted on the mounting substrate 210 through a reflow process when the metal ball 230 is seated in the groove. In addition, the mounting substrate 210 can be coated with a light reflection inhibitor or mounted with a flashing body.
第１工程は、実装基板２１０を生成する（Ｓ１００）。第１工程は、複数の基板２１１、２１２、２１３、２１４、２１５および２１６と孔が形成された少なくとも一つのダミー基板２１７、２１８を含む実装基板２１０を生成することができる。第１工程は、複数の基板２１１、２１２、２１３、２１４、２１５および２１６の上面にダミー基板２１７、２１８を圧着して溝が形成された実装基板２１０を生成することができる。前記溝は、ダミー基板２１７、２１８の積層量または孔の大きさに応じて調節することができる。第１工程は、前記溝の底面に金属パット２２０を備えることができる。 In the first step, the mounting substrate 210 is generated (S100). In the first step, a mounting substrate 210 including a plurality of substrates 211, 212, 213, 214, 215 and 216 and at least one dummy substrate 217, 218 in which holes are formed can be generated. In the first step, the mounting substrate 210 in which grooves are formed by pressing the dummy substrates 217 and 218 on the upper surfaces of the plurality of substrates 211, 212, 213, 214, 215 and 216 can be generated. The groove can be adjusted according to the stacking amount of the dummy substrates 217 and 218 or the size of the hole. The first step may include a metal pad 220 on the bottom surface of the groove.
第２工程は、金属ボール２３０を溝に安着させる（Ｓ１１０）。第２工程は、実装基板２１０の溝に金属ボール２３０を安着させることができる。第２工程は、多量の金属ボールを撒いて実装基板２１０の溝に定着させることができる。また、第２工程は、一つの溝に一つの金属ボール２３０を安着させることができる。 In the second step, the metal ball 230 is seated in the groove (S110). In the second step, the metal ball 230 can be seated in the groove of the mounting substrate 210. In the second step, a large amount of metal balls can be poured and fixed in the grooves of the mounting substrate 210. In the second step, one metal ball 230 can be seated in one groove.
第３工程は、金属ボール２３０のリフロー工程を行う（Ｓ１２０）。第３工程は、金属ボール２３０を融解するためにリフロー工程を行うことができる。第３工程は、リフロー工程を経て実装基板２１０の溝に液体状態になった金属ボール２３０をいっぱいに満たすことができる。 In the third step, a reflow step of the metal ball 230 is performed (S120). In the third step, a reflow step can be performed to melt the metal ball 230. In the third step, the metal balls 230 that are in a liquid state can be filled in the grooves of the mounting substrate 210 through the reflow step.
第４工程は、半導体２４０を実装する（Ｓ１３０）。第４工程は、実装基板２１０は、溝に満たされた液体状態の金属ボールの上側に半導体を実装することができる。第４工程は、ダミー基板２１７、２１８に生じた溝によって半導体を外部の衝撃から保護することができ、非常に優れた平面度を維持することができる。 In the fourth step, the semiconductor 240 is mounted (S130). In the fourth step, the mounting substrate 210 can mount a semiconductor on the upper side of the liquid metal ball filled in the groove. In the fourth step, the semiconductor can be protected from external impacts by the grooves formed in the dummy substrates 217 and 218, and extremely excellent flatness can be maintained.
第５工程は、光反射抑制剤を塗布または閃光体を実装をする（Ｓ１４０）。第５工程は、光反射抑制剤２５０と閃光体２６０のうち少なくとも一つの物質を実装または塗布することができる。第５工程は、ダミー基板２１７、２１８に生じた溝を用いて、光反射抑制剤２５０を塗布して閃光体２６０を実装することができる。 In the fifth step, a light reflection inhibitor is applied or a flash body is mounted (S140). In the fifth step, at least one substance of the light reflection inhibitor 250 and the flash body 260 can be mounted or applied. In the fifth step, the flash 260 can be mounted by applying the light reflection inhibitor 250 using the grooves generated in the dummy substrates 217 and 218.
以下、本発明を実施例によりさらに具体的に説明する。ただし、以下の実施例は本発明の説明のためのものであり、本発明の範囲は下記の実施例によって限定されるものではない。 Hereinafter, the present invention will be described more specifically with reference to examples. However, the following examples are for explaining the present invention, and the scope of the present invention is not limited by the following examples.
＜実施例１＞
工程１：金属パターンが形成された複数の基板の上面に溝が形成された実装基板を作成した。ここで、前記基板には厚さ８０μｍ、２５０ｍｍ×２５０ｍｍのセラミックシート(sheet)を使用し、前記セラミックシートは、９０％のＡｌ２Ｏ３と１０％のガラス(glass)成分を含んでいる。また、前記シートは、テープキャスティング(tape casting)方法を用いて作成され、その上に金（Ａｕ）のパターンをスクリーン印刷(screen printing)方法を用いてパターンを形成した。
<Example 1>
Step 1: A mounting substrate in which grooves were formed on the upper surfaces of a plurality of substrates on which metal patterns were formed was prepared. Here, a ceramic sheet having a thickness of 80 μm and a thickness of 250 mm × 250 mm is used as the substrate, and the ceramic sheet includes 90% Al 2 O 3 and 10% glass component. In addition, the sheet was formed using a tape casting method, and a gold (Au) pattern was formed thereon using a screen printing method.
続いて、６４×６４ピクセルＣｄＺｎＴｅ化合物半導体をセラミック基板に安着させるために、Ａｕのパターンが形成された７枚のセラミックシートと、前記セラミック基板上に積層した。また、インジウムボールが溝の中に安着するためのダミー基板をさらに使用した。 Subsequently, in order to deposit a 64 × 64 pixel CdZnTe compound semiconductor on the ceramic substrate, seven ceramic sheets each having an Au pattern formed thereon were laminated on the ceramic substrate. In addition, a dummy substrate was also used for the indium balls to be seated in the grooves.
前記ダミー基板は、厚さ５０μｍ、２５０ｍｍ×２５０ｍｍのセラミック基板を使用し、パンチマシン(punching machine)を用いて、１２０μｍのサイズで孔を形成した。前記の孔は、後でインジウムボールが安着する部分である。 As the dummy substrate, a ceramic substrate having a thickness of 50 μm and 250 mm × 250 mm was used, and holes were formed in a size of 120 μm using a punching machine. The hole is a portion where an indium ball is later seated.
合計８枚のセラミック基板を１６００℃で焼結し、この時の合計の厚さは、焼結によって約２０％に減少することを考慮して製作した。 A total of 8 ceramic substrates were sintered at 1600 ° C., and the total thickness at this time was manufactured considering that the thickness was reduced to about 20% by sintering.
２５０ｍｍ×２５０ｍｍのサイズで焼結されたセラミック基板は、６４×６４ピクセルの基本モジュールに切断し、それによって、２５０ｍｍ×２５０ｍｍサイズのセラミック基板から約１００個の基本モジュールのセラミック基板が提供された。 The ceramic substrate sintered at a size of 250 mm × 250 mm was cut into 64 × 64 pixel basic modules, thereby providing about 100 basic module ceramic substrates from a 250 mm × 250 mm size ceramic substrate.
工程２：工程１で、ダミー基板に形成された孔に８０μｍサイズのインジウムボールを安着させた。セラミック基板をバンプボンダー(bump bonder)装置に位置させ、インジウムボールを安着させる。ＣｄＺｎＴｅ化合物半導体は、バンプボンダーの上部に位置させて、基板とパターンが揃うように調整した後、接合して、パターンマッチングした。 Step 2: In Step 1, 80 μm-sized indium balls were placed in the holes formed in the dummy substrate. The ceramic substrate is placed in a bump bonder device and the indium balls are seated. The CdZnTe compound semiconductor was positioned above the bump bonder, adjusted so that the pattern was aligned with the substrate, then joined and pattern matched.
前記バンプボンダーは、下に位置したセラミック基板と上部にあるＣｄＺｎＴｅ化合物半導体のパターンを同時に見ることができる装置であり、下に位置したセラミック基板に最大２５０℃まで加熱することができる装置である。 The bump bonder is an apparatus capable of simultaneously viewing a lower ceramic substrate and an upper CdZnTe compound semiconductor pattern, and is capable of heating the lower ceramic substrate to a maximum of 250 ° C.
工程３：セラミック基板とＣｄＺｎＴｅ化合物半導体を整列して、パターンマッチングさせた後、約９０℃で加熱した。 Step 3: The ceramic substrate and the CdZnTe compound semiconductor were aligned and pattern-matched, and then heated at about 90 ° C.
工程４：工程３の加熱を通じてインジウムボールが融解されることによって、セラミック基板とＣｄＺｎＴｅ化合物半導体がボンディングした。 Step 4: The ceramic substrate and the CdZnTe compound semiconductor were bonded by melting the indium balls through the heating in Step 3.
＜実施例２＞
前記実施例１の工程１において、前記ダミー基板にレーザ加工機を用いて、１２０μｍサイズの孔を形成することを除き、前記実施例１と同様に行って、セラミック基板とＣｄＺｎＴｅ化合物半導体を実装した。
<Example 2>
In Step 1 of Example 1, a ceramic substrate and a CdZnTe compound semiconductor were mounted in the same manner as in Example 1 except that a 120 μm size hole was formed on the dummy substrate using a laser processing machine. .
以上、本発明の好ましい実施例に対して説明したが、本発明は、上述した特定の好適な実施例に限定されず、特許請求の範囲で請求する本発明の要旨を逸脱することなく、当該発明の属する技術分野で通常の知識を有する者であれば誰でも多様な変形実施が可能であることはもちろん、そのような変更は、請求の範囲の記載の範囲内に含まれる。 The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the specific preferred embodiments described above, and does not depart from the gist of the present invention claimed in the claims. Anyone having ordinary knowledge in the technical field to which the invention pertains can make various modifications, and such modifications are included in the scope of the claims.
１：プリント回路基板
２、１０：絶縁基板
３、２０：回路パターン
３０：ソルダーボール
４０：ソルダーパット
５０：ソルダーレジスト
６０：ダイアタッチエポキシ
７０：チップ
８０：ワイヤー
９０：モールディング
２１０：実装基板
２１１、２１２、２１３、２１４、２１５、２１６：基板
２１７、２１８：ダミー基板
２２０：金属パット
２３０：金属ボール
２４０：半導体
２５０：光反射抑制剤
２６０：閃光体
1: Printed circuit board 2, 10: Insulating board 3, 20: Circuit pattern 30: Solder ball 40: Solder pad 50: Solder resist 60: Die attach epoxy 70: Chip 80: Wire 90: Molding 210: Mounting board 211, 212 213, 214, 215, 216: Substrate 217, 218: Dummy substrate 220: Metal pad 230: Metal ball 240: Semiconductor 250: Light reflection inhibitor 260: Flash
Claims (13)
前記溝に金属ボールを安着する第２工程と、
前記装着された金属ボールをリフロー(reflow)工程を通じて融合する第３工程と、
前記融解した金属ボールの上側に半導体を実装する第４工程とを含む半導体センサーを表面実装する実装方法。 A first step of generating a mounting substrate having grooves formed on the top surfaces of a plurality of substrates on which metal patterns are formed;
A second step of seating a metal ball in the groove;
A third step of fusing the mounted metal balls through a reflow step;
A mounting method for surface mounting a semiconductor sensor, comprising: a fourth step of mounting a semiconductor on the molten metal ball.
前記実装基板の垂直方向の断面が左右対称である∪字状の基板に生成されることを特徴とする、請求項１に記載の半導体センサーを表面実装する実装方法。 The first step includes
2. The mounting method for surface mounting a semiconductor sensor according to claim 1, wherein the mounting substrate is generated on a square-shaped substrate whose vertical cross section in the vertical direction is symmetrical.
孔が形成された少なくとも一つのダミー(dummy)基板を圧着したり、パンチングマシン(punching machine)またはレーザーマシンを用いて、前記溝を形成したりすることを特徴とする、請求項１に記載の半導体センサーを表面実装する実装方法。 The first step includes
2. The groove according to claim 1, wherein the groove is formed using a punching machine or a laser machine. A mounting method for surface mounting semiconductor sensors.
前記溝の底面に金属パットを備えることを特徴とする、請求項１に記載の半導体センサーを表面実装する実装方法。 The first step includes
The mounting method for surface mounting a semiconductor sensor according to claim 1, wherein a metal pad is provided on a bottom surface of the groove.
前記溝をダミー基板の積層量や孔の大きさに応じて調節することを特徴とする、請求項１に記載の半導体センサーを表面実装する実装方法。 The first step includes
The mounting method for surface mounting a semiconductor sensor according to claim 1, wherein the groove is adjusted according to a stacking amount of a dummy substrate and a size of a hole.
前記金属ボールを前記実装基板の上側に撒いて前記溝に安着させることを特徴とする、請求項１に記載の半導体センサーを表面実装する実装方法。 The second step includes
The mounting method for surface mounting a semiconductor sensor according to claim 1, wherein the metal ball is placed on the upper side of the mounting substrate to be seated in the groove.
前記半導体を化合物半導体およびシリコン半導体のいずれか一つをベースとすることを特徴とする、請求項１に記載の半導体センサーを表面実装する実装方法。 The fourth step is
2. The mounting method for surface mounting a semiconductor sensor according to claim 1, wherein the semiconductor is based on one of a compound semiconductor and a silicon semiconductor.
少なくとも一つのダミー(dummy)基板とを含み、
前記複数の基板の上面に前記ダミー基板を圧着して溝を形成し、
前記溝の底面に金属パットが具備され、
前記複数の基板と、前記ダミー基板の圧着された形状の垂直断面が左右対称である∪字形状であることを特徴とする、半導体センサーを表面実装する実装基板。 A plurality of substrates on which metal patterns are formed;
Including at least one dummy substrate,
The dummy substrate is pressure-bonded to the upper surface of the plurality of substrates to form a groove,
A metal pad is provided on the bottom surface of the groove,
A mounting substrate for surface-mounting a semiconductor sensor, wherein the plurality of substrates and the dummy substrate are in a cross-sectional shape in which a vertical cross-section of the crimped shape is symmetrical.
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| JP5976049B2 (en) | 2016-08-23 |
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