JP2015115514A5 - - Google Patents

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Publication number
JP2015115514A5
JP2015115514A5 JP2013257665A JP2013257665A JP2015115514A5 JP 2015115514 A5 JP2015115514 A5 JP 2015115514A5 JP 2013257665 A JP2013257665 A JP 2013257665A JP 2013257665 A JP2013257665 A JP 2013257665A JP 2015115514 A5 JP2015115514 A5 JP 2015115514A5
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JP
Japan
Prior art keywords
metal film
outer peripheral
addition
peripheral end
leakage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2013257665A
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Japanese (ja)
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JP6195514B2 (en
JP2015115514A (en
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Publication date
Application filed filed Critical
Priority to JP2013257665A priority Critical patent/JP6195514B2/en
Priority claimed from JP2013257665A external-priority patent/JP6195514B2/en
Publication of JP2015115514A publication Critical patent/JP2015115514A/en
Publication of JP2015115514A5 publication Critical patent/JP2015115514A5/ja
Application granted granted Critical
Publication of JP6195514B2 publication Critical patent/JP6195514B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Description

そのほかに、本実施形態の配線基板１００では、コア基板１０の外周端部の全周にわたって金属膜５０が形成されているため、外周端部の強度が高められている。また、金属膜５０は第１と第２の配線層４１，４２から電気的に独立しているため、金属膜５０を介した短絡や漏電、電気信号へのノイズの混入が発生してしまうことが抑制されている。 In addition, in the wiring substrate 100 of the present embodiment, since the metal film 50 is formed over the entire periphery of the outer peripheral end of the core substrate 10, the strength of the outer peripheral end is increased. In addition, since the metal film 50 is electrically independent from the first and second wiring layers 41 and 42 , a short circuit, leakage, and noise in the electrical signal through the metal film 50 may occur. Is suppressed.

JP2013257665A 2013-12-13 2013-12-13 Wiring board and manufacturing method thereof Expired - Fee Related JP6195514B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013257665A JP6195514B2 (en) 2013-12-13 2013-12-13 Wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013257665A JP6195514B2 (en) 2013-12-13 2013-12-13 Wiring board and manufacturing method thereof

Publications (3)

Publication Number Publication Date
JP2015115514A JP2015115514A (en) 2015-06-22
JP2015115514A5 true JP2015115514A5 (en) 2016-12-15
JP6195514B2 JP6195514B2 (en) 2017-09-13

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ID=53529038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013257665A Expired - Fee Related JP6195514B2 (en) 2013-12-13 2013-12-13 Wiring board and manufacturing method thereof

Country Status (1)

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JP (1) JP6195514B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021056427A1 (en) * 2019-09-27 2021-04-01 庆鼎精密电子（淮安）有限公司 Interposer, manufacturing method therefor, and circuit board assembly
JP7448788B2 (en) 2020-03-13 2024-03-13 日本製鉄株式会社 Manufacturing method for burring processed materials, cores for burring and burring processing equipment

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120658A (en) * 1992-10-06 1994-04-28 Fujitsu Ltd Production of printed board provided with power supply section
JP2005159330A (en) * 2003-11-05 2005-06-16 Hitachi Chem Co Ltd Method of manufacturing multilayer circuit board and multilayer circuit board manufactured by the same, and board with semiconductor chip mounted thereon and semiconductor package using the same
JP2005191243A (en) * 2003-12-25 2005-07-14 Ngk Spark Plug Co Ltd Build-up multilayer wiring board
JP4473935B1 (en) * 2009-07-06 2010-06-02 新光電気工業株式会社 Multilayer wiring board
JP2013062441A (en) * 2011-09-14 2013-04-04 Fujikura Ltd Printed board and manufacturing method of the same

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