JP2015115366A - Nitride semiconductor device and method for manufacturing the same, and diode and field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an element resistance by increasing mobility of electrons, while maintaining high carrier density in a two-dimensional electron gas in an electron transit layer.SOLUTION: A nitride semiconductor device comprises: a semiconductor laminated body having a structure where a base 11, an electron transit layer 12 consisting of GaN, and at least two layer of nitride semiconductor layers 13-1 to 13-n containing Al are laminated, and an electron supply layer 13 having an average Al composition ratio X which has a bandgap averagely being wider than that of the electron transit layer 12; a first electrode and a second electrode provided on at least part of layer forming the semiconductor laminated body. In the electron supply layer 13, first nitride layers having a maximum Al composition ratio X1 being higher than the average Al composition ratio X and second nitride layers having a minimum Al composition ratio X2 being lower than the average Al composition ratio X are alternately laminated at least once, and the maximum Al composition ratio X1 is higher than the average Al composition X within a range of 0.03-0.3.

Description

  The present invention relates to a nitride semiconductor device having an electron supply layer, a manufacturing method thereof, a diode, and a field effect transistor.

  Wide band gap semiconductors are very attractive as materials for semiconductor devices for high temperature environments, high power, or high frequency because they have high breakdown voltage, good electron transport properties, and good thermal conductivity. Typical wide band gap semiconductors include GaN, AlN, InN, BN, or a nitride semiconductor that is a mixed crystal of two or more of these. Further, for example, a field effect transistor (FET) having an AlGaN / GaN heterojunction structure generates two-dimensional electron gas (2DEG) at the heterojunction interface due to piezo polarization and spontaneous polarization. Yes. This 2DEG has high electron mobility and carrier density. Therefore, a heterojunction FET (HFET) using such an AlGaN / GaN heterojunction structure has a low on-resistance and a high switching speed, can operate at a high temperature, and is very suitable for power switching applications.

  Further, by adopting a configuration in which an AlN / GaN superlattice barrier layer is provided in a Schottky Barrier Diode (SBD) or a heterojunction field effect transistor (HFET), the semiconductor device is turned on. Methods for reducing resistance are known. Specifically, in Patent Document 1 and Non-Patent Document 1, an AlN / GaN pseudo-mixed crystal formed by a molecular beam epitaxy (MBE) method is used for a barrier layer (electron supply layer), whereby an AlGaN mixed crystal is used. A HEMT using a nitride semiconductor material is described which has an increased carrier concentration and carrier mobility compared to a barrier layer comprising: In Patent Document 2, a nitride semiconductor device having a hetero structure includes a spacer layer made of AlN between a GaN layer constituting a channel layer (electron transit layer) and an AlGaN layer constituting a barrier layer. The configuration is described.

Japanese Patent No. 4517077 Japanese Patent No. 4072858

APPLIED PHYSICS LETTERS 90, 242112 (2007)

  The present inventor has developed a superlattice structure AlN / GaN pseudo-mixed crystal as a barrier layer (electron supply layer) in order to reduce the on-resistance and reduce the element area, which is a problem of characteristics in conventional semiconductor devices. Adopted. Conventionally, 2DEG is used as a channel in a nitride semiconductor device, and if an AlN / GaN pseudo mixed crystal is used for the electron supply layer, the mobility of electrons in the 2DEG layer can be increased. However, further reduction in element resistance has been demanded.

  The present invention has been made in view of the above, and an object thereof is to reduce element resistance by increasing electron mobility while maintaining high carrier density in a two-dimensional electron gas in an electron transit layer. It is an object of the present invention to provide a nitride semiconductor device and a manufacturing method thereof, and a diode and a field effect transistor.

  In order to solve the above-described problems and achieve the above object, a nitride semiconductor device according to the present invention includes a base, a first semiconductor layer made of a nitride semiconductor provided on the base, and the first semiconductor layer. A semiconductor laminated body having a structure in which at least one nitride semiconductor layer containing aluminum is provided on the upper layer and having a second semiconductor layer having an average band gap wider than that of the first semiconductor layer and an average Al composition ratio X; The first electrode provided on at least a part of the layers constituting the semiconductor laminate, and the first electrode separated on the at least a part of the layers constituting the semiconductor laminate A first electrode including a nitride semiconductor having a maximum Al composition ratio higher than the average Al composition ratio X; and an average Al composition ratio X; Very low Al The second nitride semiconductor layers including the nitride semiconductor having the composition ratio are alternately stacked at least once, and the maximum Al composition ratio of the first nitride semiconductor layer is 0 with respect to the average Al composition ratio X. 0.03 or more and less than 0.3.

  The nitride semiconductor device according to the present invention is the first nitride semiconductor layer according to the above invention, wherein the Al composition ratio in the second semiconductor layer is along the stacking direction from the main surface of the base toward the surface of the second semiconductor layer. In the second nitride semiconductor layer, it is continuously increased and decreased so as to increase and decrease sequentially before and after the maximum Al composition ratio.

  The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the maximum Al composition ratio of the first nitride semiconductor layer is 0.2 or more and less than 0.6.

  In the nitride semiconductor device according to the present invention, in the above invention, the minimum Al composition ratio of the second nitride semiconductor layer is 0.03 or more and less than 0.2 with respect to the average Al composition ratio of the second semiconductor layer. It is characterized by being low within the range.

  The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the minimum Al composition ratio of the second nitride semiconductor layer is greater than 0 and less than 0.2.

  The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the average Al composition ratio of the second semiconductor layer is 0.1 or more and 0.4 or less.

  The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the thickness of the second semiconductor layer is 2 nm or more.

  The nitride semiconductor device according to the present invention is characterized in that, in the above invention, the thickness of the second semiconductor layer is 30 nm or less.

  In the nitride semiconductor device according to the present invention, in the above invention, the second semiconductor layer includes a first nitridation including a nitride semiconductor having at least one maximum Al composition ratio higher than an average Al composition ratio of the second semiconductor layer. The semiconductor layer and the second nitride semiconductor layer including the nitride semiconductor having at least one minimum Al composition ratio lower than the average Al composition ratio of the second semiconductor layer are alternately stacked 5 times or more and 10 times or less. It is characterized by being configured.

The nitride semiconductor device according to the present invention is the nitride semiconductor device according to the above invention, wherein the semiconductor stacked body is lower than a maximum Al composition ratio of the plurality of nitride semiconductor layers constituting the second semiconductor layer and has a minimum Al composition ratio. An etching sacrificial layer made of Al _Y Ga _1-Y N having a higher average Al composition ratio Y is formed on the second semiconductor layer. In this configuration, the nitride semiconductor device according to the present invention is characterized in that the thickness of the etching sacrificial layer is not less than 1 nm and not more than 12 nm.

  The nitride semiconductor device according to the present invention is the nitride semiconductor device according to the above invention, wherein the semiconductor stacked body is selectively provided on an upper layer of the second semiconductor layer and has an average band gap smaller than that of the second semiconductor layer. And a third semiconductor layer. In this configuration, the nitride semiconductor device according to the present invention is characterized in that the third semiconductor layer is made of gallium nitride having a thickness of 20 nm or more.

  In the above-described invention, the nitride semiconductor device according to the present invention is a third semiconductor device provided on at least a part of the layers constituting the semiconductor multilayer body and spaced apart from the first electrode and the second electrode. An electrode is further provided.

  A field effect transistor according to the present invention has the structure of the nitride semiconductor device according to the above invention, wherein the first electrode is a gate electrode, the second electrode is a drain electrode, and the third electrode is a source electrode. To do.

  The diode according to the present invention has the structure of the nitride semiconductor device according to the above-described invention, wherein the first electrode is an anode electrode and the second electrode is a cathode electrode.

  A method of manufacturing a nitride semiconductor device according to the present invention includes a base, a first semiconductor layer made of a nitride semiconductor provided on the base, and a nitride semiconductor layer having at least two different Al composition ratios stacked a plurality of times. And a semiconductor stacked body having a second semiconductor layer having a superlattice structure composed of a plurality of nitride semiconductor layers and having an average band gap wider than that of the first semiconductor layer, and among the layers constituting the semiconductor stacked body A first electrode provided on at least a part of the layer, and a second electrode provided on the at least part of the layers constituting the semiconductor stacked body and spaced apart from the first electrode, In the method for manufacturing a nitride semiconductor device provided, when the plurality of nitride semiconductor layers in the second semiconductor layer are formed by a growth process using metal organic chemical vapor deposition, the plurality of nitride semiconductor layers are formed on the plurality of nitride semiconductor layers. In between each growth step the nitride semiconductor layer that a predetermined time, and wherein the disrupting growth of the nitride semiconductor layer.

  In the method for manufacturing a nitride semiconductor device according to the present invention, in the above invention, the semiconductor stacked body is lower than the maximum Al composition ratio of the plurality of nitride semiconductor layers constituting the second semiconductor layer, and the minimum In the case of having an etching sacrificial layer made of AlGaN with an Al composition ratio higher than the Al composition ratio of the nitride, before growing the etching sacrificial layer, nitridation grown on the uppermost layer of the plurality of nitride semiconductor layers The physical semiconductor layer is etched away.

  According to the nitride semiconductor device and the manufacturing method thereof, the diode, and the field effect transistor according to the present invention, the device resistance is increased by increasing the electron mobility while maintaining a high carrier density in the two-dimensional electron gas in the electron transit layer. Can be reduced.

FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor multilayer substrate having an electron supply layer made of an AlGaN / AlGaN pseudo mixed crystal according to an embodiment. FIG. 2 is a schematic diagram for explaining each layer structure in the pseudo mixed crystal electron supply layer according to the embodiment and the prior art. FIG. 3 is a sequence chart for illustrating the method for manufacturing the semiconductor laminated substrate in the first embodiment. FIG. 4 is a graph showing measured values of the composition ratios of Al, Ga, and N along the depth direction of the semiconductor multilayer substrate in the first embodiment. FIG. 5 is a graph showing measured values of the Al composition ratio in group III along the depth direction of the semiconductor multilayer substrate in the first embodiment. FIG. 6 is a schematic cross-sectional view showing the structure of an SBD having an electron supply layer made of an AlGaN / AlGaN pseudo mixed crystal and a field plate structure according to the first embodiment of the present invention. FIG. 7 is a schematic cross-sectional view showing the structure of a HEMT having an electron supply layer made of an AlGaN / AlGaN pseudo mixed crystal and a field plate structure according to the second embodiment of the present invention. FIG. 8 is a schematic cross-sectional view showing the structure of an SBD having an electron supply layer made of an AlGaN / AlGaN pseudo mixed crystal according to Embodiment 3 of the present invention. FIG. 9 is a schematic cross-sectional view showing the structure of a HEMT having an electron supply layer made of an AlGaN / AlGaN pseudo mixed crystal according to Embodiment 4 of the present invention. FIG. 10 is a schematic cross-sectional view showing the structure of a MOSFET having an electron supply layer made of an AlGaN / AlGaN pseudo mixed crystal according to Embodiment 5 of the present invention. FIG. 11 is a schematic cross-sectional view showing the structure of a MISFET having an electron supply layer made of an AlGaN / AlGaN pseudo mixed crystal according to Embodiment 6 of the present invention. FIG. 12 is a schematic cross-sectional view showing the structure of an SBD for explaining the problems of the prior art. FIG. 13 is a graph showing the dependence of the contact specific resistance on the AlN layer design thickness in the electron supply layer made of AlGaN / AlN / GaN. FIG. 14 is a graph showing the Al composition ratio dependence of the contact specific resistance in the electron supply layer made of an AlN / GaN pseudo mixed crystal when AlN is 0.5 nm.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, this invention is not limited by the following embodiment. In the drawings, the same or corresponding elements are denoted by the same reference numerals as appropriate, and repeated descriptions are omitted as appropriate. Furthermore, it should be noted that the drawings are schematic, and dimensional relationships between elements may differ from actual ones. Even between the drawings, there are cases in which portions having different dimensional relationships and ratios are included. Further, “upper”, “upper” or “upper” and “lower”, “lower” or “lower” used in the description of the following embodiments are perpendicular to the main surface of the substrate of the semiconductor device, respectively. It should also be noted that the direction of moving away and the direction of approaching the main surface of the substrate are shown and do not necessarily coincide with the vertical direction in the mounting state of the semiconductor device.

  First, in describing embodiments of the present invention, in order to facilitate the understanding of the present invention, an intensive study conducted by the present inventor to solve the above-described problems will be described. First, a description will be given of a conventional nitride semiconductor device that has been the subject of intensive studies by the inventors. FIG. 12 is a schematic cross-sectional view showing a Schottky barrier diode (SBD) as a conventional nitride semiconductor device.

  That is, as shown in FIG. 12, the conventional SBD 100 selectively has an anode electrode 105 </ b> A and a cathode electrode 105 </ b> C on the buffer layer 102, the electron transit layer 103, and the electron supply layer 104 that are sequentially stacked on the substrate 101. And an insulating film 106.

  In the nitride semiconductor device such as the SBD 100 configured as described above, the element resistance is mainly determined by the access resistance and the contact resistance. Here, the contact resistance is a resistance at the contact portion Con between the cathode electrode 105 </ b> C that is an ohmic electrode and the 2 DEG layer A that is in ohmic contact with the cathode electrode 105 </ b> C via the electron supply layer 104. The access resistance is a resistance in the access part Ac between the anode electrode 105A that is a Schottky electrode and the contact part Con in the 2DEG layer A.

Here, the access resistance is inversely proportional to the product of electron carrier density (2DEG concentration Ns) and mobility (electron mobility) in the 2DEG layer A. Therefore, to reduce the access resistance, it is necessary to increase the 2DEG concentration Ns of the 2DEG layer A or increase the electron mobility. However, according to the knowledge of the present inventor, when the 2DEG concentration Ns is too high, there is a problem that the electric field strength becomes too strong in the portion of the anode electrode 105A that is a Schottky electrode. From the viewpoint of avoiding this problem, in the 2DEG concentration Ns, there is an upper limit where the optimum value is about 8 × 10 ¹² to 10 × 10 ¹² cm ⁻² . Thereby, the present inventor recalled that the electron mobility needs to be increased in order to reduce the element resistance. The same applies to nitride semiconductor devices such as HFETs, HEMTs, MOSFETs, and MISFETs that use 2DEG for the access unit, as well as the SBD 100.

Further, according to the knowledge of the present inventor, since the electron transit layer 103 is usually composed of undoped gallium nitride (u-GaN), there is a method for reducing the dislocation density in order to increase the electron mobility. . However, when GaN is grown on a silicon (Si) substrate usually used in a nitride semiconductor device, there is a lower limit of about 10 ⁸ cm ^{−2 on the} dislocation density due to the difference in lattice constant between the Si substrate and the GaN layer. Therefore, there is a limit in reducing the dislocation density.

Therefore, in order to increase the electron mobility, a method of reducing alloy scattering by suppressing the seepage of the electron wave function in the electron supply layer 104 is conceivable. Conventionally, in order to reduce this alloy scattering, an AlGaN / AlN / GaN laminated structure in which an AlN spacer layer is provided between an AlGaN layer constituting an electron supply layer and a GaN layer constituting an electron transit layer has been proposed. (See Patent Document 1). However, even if the electron mobility can be increased and the access resistance can be reduced, if a good ohmic contact cannot be obtained in the ohmic electrode such as the cathode electrode 105C, the contact resistance increases. Therefore, the inventor measures the contact resistance in the nitride semiconductor device described in Patent Document 1 by using a Ti / Al electrode as an ohmic electrode by a TLM (Transmission Line Model) method, and contacts the contact portion Con. The film thickness dependence of the AlN spacer layer in the specific resistance (Ω · cm ² ) was measured. The measurement results are shown in FIG. The film thickness of the AlN spacer layer was calculated using X-ray reflection measurement, and it was confirmed that there was almost no difference from the designed film thickness of AlN. In the graph shown in the drawings, αE ± β represents α × 10 ^{± β} .

From FIG. 13, it can be seen that in the semiconductor device employing the AlGaN / AlN / GaN laminated structure, the contact specific resistance of the contact portion increases as the thickness of the AlN spacer layer increases. Then, considering the range of 2.0 × 10 ⁻⁵ Ωcm ² or less, which is a contact specific resistance for obtaining good ohmic contact in the semiconductor device (in the direction of the arrow from the dotted line in FIG. 13), the film thickness of the AlN spacer layer Needs to be smaller than 0.5 nm. On the other hand, when the inventor measured the film thickness dependence of the electron mobility in the similar semiconductor device by the Hall effect (Hall effect) measurement, when the film thickness of the AlN spacer layer was 0.5 nm, It was confirmed that the electron mobility was maximized. That is, when an AlGaN / AlN / GaN laminated structure in which an AlN spacer layer is provided below the electron supply layer is adopted, it is extremely difficult to increase the electron mobility of 2DEG and achieve good ohmic contact. confirmed.

  Therefore, the present inventor has adopted a pseudo-mixed crystal structure in which an aluminum nitride (AlN) layer and a gallium nitride (GaN) layer are alternately and sequentially stacked to form an AlN / GaN superlattice layer in the electron supply layer. The method of increasing the electron mobility was examined. According to this configuration, the average Al composition ratio of the pseudo mixed crystal can be increased without lattice relaxation, and the film thickness of the electron supply layer 104 can be easily increased. Accordingly, by adjusting the number of AlN layers and GaN layers constituting the AlN / GaN superlattice layer, or the number of pairs in the case of combining the AlN layer and GaN layer, and the average Al composition ratio, 2DEG The 2DEG concentration Ns of the layer can be controlled. Furthermore, since the 2DEG concentration Ns can be maintained at a high concentration and the electron mobility can be increased, the access resistance in the semiconductor device can be reduced.

Therefore, for the reasons described above, the present inventor measured the contact resistance in a semiconductor device having the electron supply layer 104 in a pseudo mixed crystal structure, and the electron supply layer in the contact specific resistance (Ω · cm ² ) of the contact portion Con. The average Al composition ratio dependence of was measured. The electron supply layer 104 was formed by laminating 7 to 8 sets of an AlN layer having a thickness of 0.5 nm and a GaN layer having a thickness of 2 nm as one set. FIG. 14 shows the measurement results when the average Al composition ratio is changed by changing the film thickness of the GaN layer in the pseudo mixed crystal while fixing the film thickness of the AlN layer to 0.5 nm. The thicknesses of the AlN layer and the GaN layer were estimated from the X-ray reflection measurement (XRR) method.

FIG. 14 shows that when the electron supply layer has an AlN / GaN superlattice structure, the contact specific resistance at the contact portion Con is substantially constant even when the average Al composition ratio is increased. Even if a range of 2.0 × 10 ⁻⁵ Ωcm ² or less, which is a contact specific resistance applicable to a semiconductor device (in FIG. 14, from the dotted line to the arrow direction), is taken into account, the average Al of the AlN / GaN superlattice structure Assuming that the electron supply layer is composed of an AlGaN single layer, the composition ratio is an average Al composition ratio in which the amount of strain of the electron supply layer with respect to the electron transit layer is equal to or less than the critical thickness of the AlGaN single layer, specifically It can be seen that, for example, if the average Al composition ratio is 40% or less, good ohmic contact can be secured. Further, when the inventor measured the electron mobility of the 2DEG layer when the electron supply layer has a pseudo mixed crystal structure, in the semiconductor device in which the AlN spacer layer is provided under the electron supply layer, the film of the AlN spacer layer is formed. It was confirmed that high electron mobility almost equal to that obtained when the thickness was 0.5 nm was obtained.

  In addition, the present inventor has intensively studied to further reduce the contact resistance in order to further reduce the element resistance. First, the present inventor conducted various experiments and studies. As a result, when the AlN layer in the AlN / GaN superlattice layer constituting the pseudo-mixed crystal electron supply layer is thicker than 1 nm, the contact resistance may rapidly deteriorate. found. That is, the present inventor has found that the presence of the AlN layer in the pseudo mixed crystal has a great influence on the increase and decrease of the contact resistance. Therefore, the present inventor conducted various studies on the pseudo-mixed crystal structure that does not deteriorate the contact resistance. By using the pseudo-mixed crystal structure as an AlGaN / AlGaN superlattice layer, the present inventors do not deteriorate the contact resistance. Recalling that mobility can be improved.

That is, the present inventor replaces the AlN / GaN superlattice layer with the electron supply layer, and has a large Al composition ratio x1 (x1> X) and a small Al composition ratio x2 (X> x2) with respect to the average Al composition ratio X. And a configuration in which at least two AlGaN layers having different Al composition ratios are alternately stacked. In addition, the present inventor conducted further experiments and examinations, and in order to ensure good ohmic contact in the ohmic electrode portion, the Al composition ratio in the plurality of AlGaN layers constituting the AlGaN superlattice layer is AlGaN superlattice. A configuration has been conceived in which modulation is performed in a continuous manner along the film thickness direction (depth direction) of the lattice layer, for example, in a triangular wave shape or a sine wave shape. Further, the increase / decrease in the Al composition ratio is preferably made relatively gradual as compared with the conventional rectangular increase / decrease. In this case, the AlGaN superlattice layer constituting the electron supply layer has a maximum portion (hereinafter referred to as a maximum Al composition ratio x1) having an Al composition ratio x1 larger than the average Al composition ratio X, and smaller than the average Al composition ratio X. It has a so-called Al composition modulation superlattice structure in which minimal portions (hereinafter, minimal Al composition ratio x2) having an Al composition ratio x2 are alternately arranged. As a result, the wave function of the electrons constituting the 2DEG layer A is that the Al _x1 Ga _1-x1 N layer has lower energy at the conduction band edge than the AlN layer of the same film thickness. It becomes easy to ooze from the side toward the surface side, and the contact resistance can be reduced. As described above, in the nitride semiconductor device, the contact resistance can be reduced, and the access resistance is reduced by improving the electron mobility while maintaining the carrier density (2DEG concentration) of the 2DEG layer generated in the electron transit layer at a high level. be able to. The embodiment described below has been devised based on the above-mentioned diligent study.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing a configuration of a semiconductor laminated substrate for manufacturing a nitride semiconductor device according to Embodiment 1 of the present invention. In other words, the semiconductor laminated substrate 10 according to the first embodiment is configured such that the electron transit layer 12, the electron supply layer 13, the etching sacrificial layer 14, and the semiconductor layer 15 are sequentially laminated on the base 11.

  The base 11 is composed of, for example, a substrate and a buffer layer. The substrate is made of, for example, a silicon (Si) substrate, a gallium arsenide (GaAs) substrate, a gallium phosphide (GaP) substrate, a GaN substrate, an AlN substrate, a silicon carbide (SiC) substrate, a carbon (C) substrate, or a sapphire substrate. The buffer layer is made of, for example, a GaN layer or an AlN layer. Note that the buffer layer may be semi-insulated by adding impurities such as C, Fe, and Mg to the buffer layer. Moreover, you may provide the various layers required for the structure of a nitride semiconductor device as needed. And the base | substrate 11 is comprised by these board | substrates, the buffer layer, and the other layer as needed.

  The electron transit layer 12 as the first semiconductor layer is made of undoped gallium nitride (u-GaN) having a film thickness of 700 nm (0.7 μm), for example. In addition, as a material which comprises the electron transit layer 12, you may use materials other than GaN, and when using AlGaN, it is preferable that the Al composition ratio shall be 5% or less.

The electron supply layer 13 as the second semiconductor layer is composed of a superlattice layer in which a plurality of at least two types of group III nitride compound semiconductors having different Al composition ratios and different band gaps are stacked. In the first embodiment, the electron supply layer 13 has, for example, an Al _X Ga _1-X N pseudo mixed crystal structure with an average Al composition ratio X, and at least two different maximum Al composition ratios x1 or minimum Al compositions. The Al _x Ga _1-x N layers 13-1 to 13-n (n: natural number) having an Al composition ratio x having various values of the ratio x2 are composed of an AlGaN superlattice layer laminated. The electron supply layer 13 is composed of at least two, preferably four or more Al _x Ga _1-x N layers 13-1 to 13-n, depending on the design of the nitride semiconductor device. That is, the 2DEG concentration Ns is determined by the average Al composition ratio X of the electron supply layer 13 and the number of Al _x Ga _1-x N layers 13-1 to 13 -n or the number of the two layers as one set. To a desired concentration based on the design. The number of sets is 0.5 set unit. In the first embodiment, the average Al composition ratio X and the layers of the Al _x Ga _1-x N layers 13-1 to 13-n are set so that the 2DEG concentration Ns is, for example, less than 1 × 10 ¹³ cm. The number (n) or the number of sets (n / 2) is adjusted. Here, the number of pairs of Al _x Ga _1-x N layers 13-1 to 13-n in the _first embodiment is about 5 to 10 pairs of 4.5 or more, and the number of layers is 9 or more. About 10 to 20 layers are preferred. The Al composition ratio x of each of the Al _x Ga _1-x N layers 13-1 to 13-n constituting the electron supply layer 13 satisfies Al and Ga, and therefore satisfies at least 0 <x <1.

Also, each of the Al _x Ga _1-x N layers 13-1 to 13-n is preferably configured by adjusting the film thickness and the Al composition ratio so that 2DEG is not generated therein. Further, the band gap of the electron supply layer 13 is an average band gap. Specifically, the electron supply layer 13 is weighted (integrated) by the film thickness ratio of each of the Al _x Ga _1-x N layers 13-1 to 13-n constituting the stacked structure. ) Is the band gap value. The electron supply layer 13 is configured such that the average band gap is larger than the band gap of the electron transit layer 12. As a result, the 2DEG layer A is generated at the interface between the electron transit layer 12 and the electron supply layer 13.

Then, AlGaN superlattice layer constituting the specific electron supply layer 13, and Al _x1 Ga _1-x1 N layer maximum Al composition ratio x1, and the Al _x2 Ga _1-x2 N layer of minimum Al composition ratio x2 They are stacked so that they are arranged alternately. The Al _x1 Ga _1-x1 N layer refers to an AlGaN layer having a maximum Al composition ratio x1, and the Al _x2 Ga _1-x2 N layer refers to an AlGaN layer having a minimum Al composition ratio x2.

In addition, the Al composition ratio of the AlGaN superlattice layer is modulated up and down continuously in the depth direction (stacking direction), for example, in a triangular wave shape or a sine wave shape. FIG. 2 is a graph showing the relationship between the Al composition ratio x (vertical axis) and the film thickness d (horizontal axis) along the depth direction in each Al _x Ga _1-x N layer constituting the electron supply layer 13. It is. The left side of the graph is the etching sacrificial layer 14 or the semiconductor layer 15 side, and the right side is the electron transit layer 12 side. In FIG. 2, the solid line shows a graph of the Al composition ratio in the electron supply layer 13 of each pseudo-mixed crystal structure according to the first embodiment, and the numbers at the bottom indicate the corresponding symbols in FIG. In FIG. 2, the dotted line shows a graph of the Al composition ratio when the electron supply layer 13 is an AlN / GaN superlattice layer according to the prior art, and the numbers at the bottom indicate the corresponding symbols in FIG. In these Embodiment 1 and the conventional electron supply layer 13, the average Al composition ratio X is the same.

As shown in FIG. 2, the Al composition ratio of the electron supply layer 13 according to the first embodiment continuously increases and decreases along the depth direction. Specifically, in the Al _x1 Ga _1-x1 N layer 13-1 as the first nitride semiconductor layer, the average Al increases in a mountain shape along the stacking direction that is the direction opposite to the depth direction. It decreases through a maximum Al composition ratio x1 that is higher than the composition ratio X. Further, in the Al _x2 Ga _1-x2 N layer 13-2 as the second nitride semiconductor layer thereabove, a minimum Al composition that decreases continuously in a valley shape along the stacking direction and is lower than the average Al composition ratio X It increases through the minimum of the ratio x2. These are repeated, and the Al composition ratio x is laminated so as to continuously increase or decrease from the Al _x1 Ga _1-x1 N layer 13-1 to the Al _x1 Ga _1-x1 N layer 13-n.

Further, the Al composition ratio x in these Al _x Ga _1-x N layers 13-1 to 13-n is between the maximum Al composition ratio x1 and the minimum Al composition ratio x2 across the average Al composition ratio X. The number increases and decreases alternately. Here, along the depth direction of the electron supply layer 13, the absolute value of the average decrease rate at which the Al composition ratio x decreases from the maximum to the minimum is the average increase rate when the Al composition ratio x decreases from the minimum to the maximum. It is preferable to make it smaller than the absolute value of. In other words, along the stacking direction of the electron supply layer 13, the absolute value of the average increase rate when the Al composition ratio x changes from the minimum to the maximum is greater than the absolute value of the average decrease rate when the Al composition ratio x decreases from the maximum to the minimum. It is also preferable to make it smaller.

In FIG. 2, the maximum Al composition ratio x1 is set to the same Al composition ratio in each of the Al _x1 Ga _1-x1 N layers 13-1, 13-3,..., 13-n as the first nitride semiconductor layer. However, the maximum Al composition ratio x1 is an Al composition ratio which is different at least in each Al _x1 Ga _1-x1 N layer 13-1, 13-3,. good. Similarly, the minimum Al composition ratio x2 is set to the same Al composition ratio in each of the Al _x2 Ga _1-x2 N layers 13-2, 13-4, ..., 13- (n-1) as the second nitride semiconductor layer. However, even in these minimum Al composition ratios x2, at least a part of each Al _x2 Ga _1-x2 N layer 13-2, 13-4,..., 13- (n-1) may be different depending on the case. Al composition ratio may be sufficient. Further, in FIG. 2, the shape of increase / decrease in the Al composition ratio along the depth direction of the electron supply layer is a triangular wave shape in which the increase / decrease is gentle compared to the rectangular shape (dotted line in FIG. 2) where the increase / decrease is steep. However, a sine wave shape or a trapezoidal shape in which the increase / decrease is also gradual is possible.

Here, the Al _x1 Ga _1-x1 N layers 13-3,..., 13 -n as the first nitride semiconductor layers are in a direction (stacking direction) opposite to the depth direction of the electron supply layer 13. Along the region from the position of the intermediate value of the thickness difference from the minimum to the maximum of the Al composition ratio x to the position of the intermediate value of the thickness difference from the maximum to the next minimum including the maximum. Point to. Further, the Al _x2 Ga _1-x2 N layers 13-2, 13-4,..., 13- (n−1) as the second nitride semiconductor layers are opposite to the depth direction of the electron supply layer 13. Along the direction, the intermediate value of the thickness difference from the minimum value point to the next maximum point from the position of the intermediate value of the thickness difference from the maximum to the minimum of the Al composition ratio x. Refers to the area up to the position. However, the Al _x1 Ga _1-x1 N layer 13-1, which is one of the first nitride semiconductor layers located _{closest to} the electron transit layer 12, has a maximum value from the position of the boundary with the lower electron transit layer 12. An area up to the position of the next intermediate value is pointed out.

Further, when the maximum Al composition ratio x1 is large, the wave function of the electrons is difficult to ooze out at the maximum portion, and the 2DEG concentration Ns in the electron transit layer 12 can be increased, but the contact resistance increases. Therefore, in consideration of an increase in the 2DEG concentration Ns and a reduction in contact resistance, the maximum Al composition ratio x1 is preferably within a range of 0.03 or more and less than 0.3 with respect to the average Al composition ratio X of the electron supply layer 13. Is preferably in the range of 0.06 to less than 0.25, more preferably in the range of 0.1 to less than 0.2. That is, it is desirable that the following expression (1) is satisfied.
X + 0.03 ≦ x1 <X + 0.3 (1)

Further, when the maximum Al composition ratio x1 is different in at least a part of each Al _x1 Ga _{1 -x1} N layer 13-1, 13-3,. It is desirable that the expression (1) represented by the maximum Al composition ratio x1 holds for the maximum Al composition ratio x11, x13,. That, Al _x11 Ga _1-x11 N layer _{13-1, Al x13 Ga 1-x13} N layer 13-3, ..., in Al _x1n Ga _1-x1n N layer 13-n, the following equation (1-1) It is desirable to be established.
X + 0.03 ≦ x11, x13,..., X1n <X + 0.3 (1-1)

Further, if the minimum Al composition ratio x2 is small, it is necessary to increase the maximum Al composition ratio x1 from the viewpoint of securing the average Al composition ratio X in order to secure the desired 2DEG concentration Ns. Considering this point, the minimum Al composition ratio x2 is within the range of 0.03 or more and less than 0.2, preferably 0.06 or more and less than 0.18, with respect to the average Al composition ratio X of the electron supply layer 13. It is desirable to make it low within the range of 0.1, more preferably within the range of 0.1 or more and less than 0.15. That is, it is desirable that the following expression (2) is satisfied.
X−0.2 <x2 ≦ X−0.03 (2)

Further, when the minimum Al composition ratio x2 is different in each Al _x2 Ga _1-x2 N layer 13-2, 13-4,. It is desirable that the expression (2) represented by the minimum Al composition ratio x2 holds for the minimum Al composition ratio x22, x24,... X2 (n−1) in each layer. That, Al _x22 Ga _1-x22 N layer _{13-2, Al x24 Ga 1-x24} N layer _{13-4, ..., Al x2 (n} -1) Ga 1-x2 (n-1) N layer 13-(n In (-1), it is desirable that the following equation (2-1) is satisfied.
X−0.2 ≦ x22, x24,..., X2 (n−1) <X−0.03 (2-1)

  As described above, the etching sacrificial layer 14 is formed from the electron transit layer 12 side by laminating the AlGaN layer so that the Al composition ratio x continuously increases or decreases in a triangular wave shape or a sine wave shape along the stacking direction or the depth direction. In addition, since the 2DEG wave function can be easily exuded toward the surface of the electron supply layer 13 toward the semiconductor layer 15, the contact resistance can be reduced and a good ohmic contact can be obtained. Further, the Al composition ratios x1 (x11 to x1n) and x2 (x22 to x2 (n-1)) are 0 <x2 <X <x1 ≦ 1, and the 2DEG wave function in the electron supply layer 13 easily leaks out. In view of the above, the maximum Al composition ratio x1 (x11 to x1n) is preferably 20% or more and less than 60% (0.2 ≦ x1 <0.6), which is a relatively low range, and preferably 20% or more and 50%. % Or less (0.2 ≦ x1 ≦ 0.5), more preferably 20% or more and 40% or less (0.2 ≦ x1 ≦ 0.4). Further, from the viewpoint of securing the average Al composition ratio X for securing the desired 2DEG concentration Ns, the minimum Al composition ratio x2 (x22 to x2 (n-1)) is greater than 0% and less than 20% (0 < x2 <0.2), preferably more than 5% and less than 20% (0.05 <x2 <0.20), more preferably 10% or more and less than 20% (0.10 ≦ x1 <0. 20). That is, in consideration of setting the average Al composition ratio X so as to obtain a desired 2DEG concentration Ns, for example, if the minimum Al composition ratio x2 is set to 0, the electron mobility can be obtained when a pseudo mixed crystal structure is employed. In order to obtain about 15% of the average Al composition ratio X at which the Al increases, it is necessary to increase the maximum Al composition ratio x1. Increasing the maximum Al composition ratio x1 is not preferable because the electron wave function of the 2DEG layer A is difficult to ooze and the contact resistance deteriorates. Furthermore, it is difficult to ensure good crystal quality when these AlGaN layers, especially AlGaN layers having a high Al composition exceeding 50%, are grown by, for example, metal organic chemical vapor deposition (MOCVD). . Also from such a viewpoint, it is preferable that the maximum Al composition ratio x1 and the minimum Al composition ratio x2 are set in the above-described ranges.

In the first embodiment, the average Al composition ratio X of the electron supply layer 13 is such that 0 <X <1 is obtained, and a desired 2DEG concentration is obtained in the 2DEG layer A at the interface with the electron transit layer 12. In consideration, 10% or more and 40% or less (0.1 ≦ X ≦ 0.4) is preferable, preferably 15% or more and 35% or less (0.15 ≦ X ≦ 0.35), and more preferably 20%. It is 30% or less (0.2 ≦ X ≦ 0.3). Further, from the viewpoint of sheet resistance in the Al _x Ga _1-x N superlattice layer, and also from the viewpoint of lattice relaxation that can be laminated freely against strain, the average Al composition ratio X of the electron supply layer 13 is preferably in the above-mentioned range. .

Of the AlGaN layers constituting the electron supply layer 13, the film thicknesses of the Al _x1 Ga _1-x1 N layer having the maximum Al composition ratio x1 and the Al _x2 Ga _1-x2 N layer 13-i having the minimum Al composition ratio x2 As for (i = 1, 2, 3,..., N), two atomic layers or more which are the minimum film thickness to be layered, and further exuding the electron wave function of the 2DEG layer A by a desired average Al composition ratio. Specifically, for example, 0.5 nm to 4.0 nm, preferably 0.5 nm to 3.5 nm, more preferably 0.5 nm to 3.0 nm. In the first embodiment, for example, the thickness is about 1.5 nm. Further, the film thickness di of each Al _x Ga _1-x N layer 13-i is preferably set to a critical film thickness or less so as not to cause misfit dislocation. Specifically, the critical film thickness of the Al _x Ga _1-x N layer is about 5 nm when the Al composition ratio x is 0.6 with respect to the lattice constant of the GaN layer, and the Al composition ratio x is 0.1. In some cases, it is about 100 nm. The critical film thickness is not necessarily limited to these film thicknesses because the film thickness differs depending on the adjacent layers in the stacked structure. And based on the above-mentioned conditions, the film thickness of each Al _x Ga _1-x N layer 13-1 to 13-n, the number of layers (n) and the number of sets (n / 2) are 2DEG of 2DEG layer A. The optimum value is appropriately selected according to the set concentration of the concentration Ns and the design of the nitride semiconductor device.

The lower limit of the film thickness of the electron supply layer 13, and the Al _x2 Ga _1-x2 N layer of Al _x1 Ga _1-x1 N layer and the minimum Al composition ratio x2 of the maximum Al composition ratio x1 electron supply layer 13 In consideration of the structure composed of a set of Al _x1 Ga _1-x1 N / Al _x2 Ga _1-x2 N superlattice layers, the thickness is preferably 2 nm or more, and the 2DEG concentration Ns of the 2DEG layer A is increased. Is preferably 5 nm or more, more preferably 10 nm or more. The upper limit of the film thickness of the electron supply layer 13 is preferably a critical film thickness or less at which no misfit dislocation occurs, and considering the limit of ohmic contact, it is 100 nm or less, preferably 50 nm or less, and more preferably 30 nm or less. Is preferred.

In the etching sacrificial layer 14 shown in FIG. 1, the average Al composition ratio Y is larger than the average Al composition ratio X of the electron supply layer 13 (X <Y), and the Al _Y Ga _1-Y N layer (0 <Y <1). ). This is because when the semiconductor layer 15 provided on the Al _y Ga _1-y N layer is made of a material having an Al composition ratio of 0 or very small, such as a GaN layer, the etching rate with the GaN layer is about 100 times that of the AlGaN layer. This is because the AlGaN layer functions extremely effectively as an etching stop for the GaN layer. Further, as will be described in detail later, the local Al composition ratio y of AlGaN constituting the etching sacrificial layer 14 is set to a maximum Al composition ratio x1 or less and a minimum Al composition ratio x2 or more in the AlGaN layer constituting the electron supply layer 13. Configured to be. In addition, the local Al composition ratio y gradually decreases and increases so as to draw a valley-shaped profile along the stacking direction from the electron supply layer 13 side to the semiconductor layer 15 side of the etching sacrificial layer 14. It is configured.

The etching sacrificial layer 14 is configured such that the local Al composition ratio y gradually decreases from the vicinity of the surface of the etching sacrificial layer 14 toward the semiconductor layer 15. Thus, by etching the local Al composition ratio y continuously or stepwise from the etching sacrificial layer 14 made of the AlGaN layer toward the semiconductor layer 15 made of the GaN layer, at the time of etching the semiconductor layer 15, The etching rate changes continuously or stepwise from when the etching reaches the etching sacrificial layer 14. Thereby, in the etching of the semiconductor layer 15, the etching rate at the time of overetching the etching sacrificial layer 14 can be controlled. Therefore, the etching can be stopped with good controllability in the etching sacrifice layer 14 without the etching reaching the electron supply layer 13. Further, by providing the etching sacrificial layer 14, it is possible to prevent the Al _x1 Ga _1-x1 N layer having a relatively high Al composition ratio x1 in the electron supply layer 13 from being exposed to the outermost surface during etching. It is possible to prevent the on-voltage and contact resistance from increasing and current collapse from deteriorating.

  Here, the thickness of the etching sacrificial layer 14 is preferably greater than or equal to the thickness that can be precisely controlled by controlling the etching rate during overetching of the semiconductor layer 15 formed thereon. Is preferably 1 nm or more, for example. The thickness of the etching sacrificial layer 14 is preferably 12 nm or less in order to reduce the 2DEG concentration Ns of 2DEG generated therein to such an extent that the influence on the nitride semiconductor device can be ignored. Therefore, the thickness of the etching sacrificial layer 14 is 1 nm or more and 12 nm or less, and in this first embodiment, for example, about 4 nm.

Further, a semiconductor layer 15 as a third semiconductor layer is provided on the etching sacrificial layer 14 or the electron supply layer 13 in accordance with the structure of the nitride semiconductor device manufactured from the semiconductor laminated substrate 10. The semiconductor layer 15 is a group III nitride compound semiconductor narrower than the average band gap of the electron supply layer 13 in order to modulate the 2DEG concentration Ns of the 2DEG layer A generated in the electron transit layer 12 by at least two levels. It consists of an Al _z Ga _1-z N layer (0 ≦ z ≦ 1) having an Al composition ratio z. The thickness of the semiconductor layer 15 is 20 nm or more and 200 nm or less, preferably 20 nm or more and 100 nm or less, which makes it easy to control the 2DEG concentration by film thickness control using growth and etching, and more preferably the film thickness. It is 25 nm or more and 80 nm or less, which is less susceptible to variations in 2DEG concentration due to variations in the size. In the first embodiment, the semiconductor layer 15 is made of, for example, a GaN layer having a thickness of 30 nm.

  The above-described electron transit layer 12, electron supply layer 13, etching sacrificial layer 14, and semiconductor layer 15 constitute the semiconductor stacked body in the first embodiment. Note that, depending on the configuration of the nitride semiconductor device manufactured from the semiconductor multilayer substrate 10, the semiconductor multilayer body may be composed of the electron transit layer 12 and the electron supply layer 13. Further, when the uppermost layer of the electron supply layer 13 is used as an etching sacrificial layer and the etching sacrificial layer 14 is not provided, a semiconductor stacked body may be configured by the electron transit layer 12, the electron supply layer 13, and the semiconductor layer 15. good. As described above, the semiconductor laminated substrate 10 for manufacturing the nitride semiconductor device according to the first embodiment is configured.

(Manufacturing method of semiconductor laminated substrate)
Next, the manufacturing method of the semiconductor laminated substrate 10 in this Embodiment 1 is demonstrated. FIG. 3 is a sequence chart of the supply gas when each layer is grown on the base 11 of the semiconductor multilayer substrate 10 according to the first embodiment by the metal organic chemical vapor deposition (MOCVD) method. . In FIG. 3, “RUN” and “VENT” indicate the supply state and supply stop state (exhaust state) of the gas to the reaction furnace (MOCVD reaction furnace) of the MOCVD apparatus, respectively.

As shown in FIGS. 1 and 3, in the method for manufacturing a semiconductor laminated substrate 10 according to the first embodiment, first, for example, as a group III gas in an MOCVD reaction furnace (not shown) in which a base 11 is installed. Trimethylgallium (TMGa), ammonia (NH ₃ ) as a group V gas, and hydrogen (H ₂ ) and nitrogen (N ₂ ) as carrier gases are supplied. As a result, GaN is grown on the substrate 11 to form the electron transit layer 12 composed of the u-GaN layer. Here, as an example of the growth conditions of the electron transit layer 12 made of u-GaN, the atmospheric pressure is set to 200 Torr (26.7 kPa) at a relatively high pressure in consideration of the point of reducing the impurity concentration, and the group III element The molar ratio (V / III molar ratio) of the group V element (N) to (Ga) is about 10,000, and the flow rate of the carrier gas H ₂ gas is, for example, about 85 L / min.

Subsequently, the supply of TMGa is stopped while the supply of NH ₃ , H ₂ and N ₂ to the MOCVD reactor is continued. NH ₃ , H ₂ , and N ₂ are constantly supplied without interruption while the substrate 11 is installed in the MOCVD reactor. Then, during a predetermined time T _0, the growth conditions are changed by a predetermined operation in the MOCVD apparatus, and the inside of the MOCVD reactor is subsequently stabilized. Here, in the first embodiment, after changing the growth conditions for 120 seconds and stabilizing for 60 seconds, for example, an interruption time of about 6 seconds is further provided. That is, in the first embodiment, the predetermined time T ₀ is, for example, about 186 seconds (about 3 minutes).

Thereafter, with the supply of TMGa to the MOCVD reactor stopped, for example, trimethylaluminum (TMAl) as a group III gas is supplied to the MOCVD reactor. Thereby, the Al _x Ga _1-x N layer 13-1 is grown on the electron transit layer 12. Here, during the predetermined time T ₀ described above, H ₂ is supplied to the MOCVD reactor in addition to N ₂ and NH ₃ . Therefore, the surface of the u-GaN layer constituting the grown electron transit layer 12 is etched for a predetermined time T ₀ . At this time, on the etching surface of the u-GaN layer, while nitrogen (N) is desorbed, Ga remains. On the other hand, the covalent bond energy of AlN is larger than the covalent bond energy of GaN. As a result, when TMAl is supplied to the MOCVD reactor, Ga substitutes for Al, and AlN-dominant crystal growth is performed on the electron transit layer 12, and an Al _x composed of an AlGaN metamorphic layer having a relatively high Al composition ratio _x. A Ga _1-x N layer 13-1 is grown.

Subsequently, the supply of TMAl is stopped while the supply of NH ₃ , H ₂ , and N ₂ to the MOCVD reactor is continued. Then, the crystal growth is interrupted by interrupting the supply of the growth gas to the MOCVD reactor for, for example, 6 seconds as the interruption time t. During this interruption, H ₂ is supplied in addition to N ₂ and NH ₃ in the MOCVD reactor. Therefore, the surface of the grown Al _x Ga _1-x N layer 13-1 is etched for the interruption time t. At this time, on the etching surface of the Al _x Ga _1-x N layer 13-1, N is desorbed while Al and Ga remain.

Subsequently, TMGa is supplied in a state where the supply of TMAl to the MOCVD reactor is stopped. Here, under the same temperature condition, since the vapor pressure of Al is lower than the vapor pressure of Ga, Ga atoms are more easily desorbed than Al atoms. Therefore, Al remains mainly on the etching surface of the Al _x Ga _1-x N layer 13-1. This remaining Al is combined with GaN grown by TMGa and N. Moreover, Ga substitutes for Al for the same reason as described above. As a result, GaN-dominated crystal growth is performed on the Al _x Ga _1-x N layer 13-1, and an Al _x Ga _1-x N layer 13-2 made of an AlGaN metamorphic layer having a relatively low Al composition ratio x is formed. Grown up.

Thereafter, while continuing the supply of NH ₃ , H ₂ , and N ₂ to the MOCVD reactor, the supply of TMGa is stopped, for example, the supply of the growth gas is interrupted for an interruption time t of about 6 seconds. Suspend growth. During the interruption of the crystal growth, H ₂ is supplied in addition to N ₂ and NH ₃ in the MOCVD reactor. Therefore, the surface of the grown Al _x Ga _1-x N layer 13-2 is etched for the interruption time t. At this time, on the etched surface of the Al _x Ga _1-x N layer 13-2, Al and Ga remain while N is desorbed.

Then, after the interruption time t has elapsed, TMAl is supplied in a state where the supply of TMGa to the MOCVD reactor is stopped. As a result, AlN-dominant crystal growth is performed on the Al _x Ga _1-x N layer 13-2 having a relatively low Al composition ratio x, which is the same as the growth of the Al _x Ga _1-x N layer 13-1 described above. Then, an Al _x Ga _1-x N layer 13-3 made of an AlGaN metamorphic layer having a relatively high Al composition ratio x is grown. Thereafter, the supply of TMAl into the MOCVD reactor is stopped.

The supply and interruption of TMAl and the supply and interruption of TMGa are repeated alternately and sequentially until the desired Al _x Ga _1-x N layers 13-1 to 13-n are formed. Then, after the Al _x Ga _1-x N layer 13-n is grown, the crystal growth is interrupted for the interruption time t, and then TMGa is supplied in a state where the supply of TMAl to the MOCVD reactor is stopped. Accordingly, Al _x Ga _1-x N layer is relatively low Al composition ratio x on _{13-n Al x Ga 1-} x N layer (not shown) is grown. As described above, by repeating crystal growth alternately with the interruption time t interposed therebetween, the electron supply layer 13 made of an AlGaN superlattice layer having a pseudo mixed crystal structure is formed on the electron transit layer 12.

Here, as an example of the growth conditions of these Al _x Ga _1-x N layers 13-1 to 13-n, the flow rate of TMAl is 200 μmol / min, the flow rate of TMGa is 160 μmol / min, for example, NH ₃ . The flow rate is, for example, 35 L / min, the flow rate of H ₂ gas is, for example, 50 L / min, the flow rate of N ₂ gas, for example, 15 L / min, the V / III molar ratio at the time of TMAl supply is, for example, 8000, and the V / at the time of TMGa supply. The III molar ratio is, for example, 10,000. As an example of atmospheric conditions in the MOCVD reactor, the growth temperature is set to 960 ° C. or higher and 1060 ° C. or lower, for example, 1020 ° C., and the atmospheric pressure is lowered in order to suppress the gas phase reaction between TMAl and NH _3. It is set to 30 Torr (4.0 kPa) or more and 200 Torr (26.7 kPa) or less, for example, 50 Torr (6.67 kPa). Under these conditions, the growth rate when TMAl is supplied for growth is about 7 nm / min, and the growth rate when TMGa is supplied for growth is about 3 nm / min. Then, the supply time of TMAl or TMGa is calculated from the growth rate and the desired film thickness in each of the Al _x Ga _1-x N layers 13-1 to 13-n and applied. When changing the Al composition ratio, the flow rate of TMAl or TMGa is changed with the NH ₃ flow rate fixed. As a result, the respective Al composition ratios in the Al _x Ga _1-x N layers 13-1 to 13-n are controlled to a desired ratio.

Next, the supply of TMGa is interrupted while the supply of NH ₃ , H ₂ and N ₂ to the MOCVD reactor is continued. Then, during a predetermined time T ₁ , the supply of TMGa is interrupted, the change to the growth condition of the etching sacrificial layer 14 in the MOCVD apparatus, and the stabilization of the MOCVD apparatus are sequentially performed. Here, in the first embodiment, the interruption is performed, for example, for 6 seconds, the growth condition is changed, for example, for 120 seconds, and the stabilization is performed, for example, for 60 seconds. That is, in the first embodiment, the predetermined time T ₁ is, for example, about 186 seconds. Even during the predetermined time T ₁ , NH ₃ , H ₂ , and N ₂ are supplied to the MOCVD reactor. Therefore, the uppermost Al _x Ga _1-x N layer formed on the Al _x Ga _1-x N layer 13-n is removed by etching during the predetermined time T ₁ .

Then, TMGa and TMAl are supplied into the MOCVD reactor after the elapse of the predetermined time T ₁ . Thereby, an etching sacrificial layer 14 is formed on the electron supply layer 13. Here, as an example of the growth conditions of the etching sacrificial layer 14, the growth temperature is 960 to 1060 ° C., for example, 1020 ° C., the pressure is 30 to 200 Torr, for example 60 Torr, and the V / III molar ratio is about 8000 in TMAl. , About 10,000 for TMGa. As an example of the flow rate of each gas, the flow rate of TMGa is, for example, 160 μmol / min, the flow rate of TMAl is, for example, 200 μmol / min, the flow rate of NH _{3 is} , for example, 35 L / min, and the flow rate of H ₂ as a carrier gas. Is 50 L / min, for example, and the flow rate of N ₂ is 15 L / min, for example. Then, after the etching sacrificial layer 14 is formed to a desired film thickness, the supply of TMGa and TMAl into the MOCVD reactor is stopped.

Next, the supply of TMGa and TMAl is interrupted while the supply of NH ₃ , H ₂ and N ₂ to the MOCVD reactor is continued. Then, during the predetermined time T ₂ , the change to the growth condition of the semiconductor layer 15 in the MOCVD apparatus and the stabilization in the MOCVD reactor are sequentially performed. Here, in the first embodiment, the growth condition is changed, for example, for 120 seconds, and the stabilization, for example, for 60 seconds. That is, in the first embodiment, the predetermined time T ₂ is, for example, about 180 seconds. At this time, the surface of the AlGaN layer in the etching sacrificial layer 14 is etched, Ga is detached, and a state in which Al remains on the surface can be created.

Then, after the elapse of the predetermined time T ₂ , the semiconductor layer 15 is formed on the etching sacrificial layer 14 by supplying TMGa into the MOCVD reactor. Thereby, the local Al composition ratio y in the etching sacrificial layer 14 can be gradually reduced from the vicinity of the surface of the etching sacrificial layer 14 toward the semiconductor layer 15. Here, an example of the growth conditions of the semiconductor layer 15 is substantially the same as the growth conditions of the electron transit layer 12 described above except that the V / III molar ratio is slightly higher than about 20000. Omitted.

  Thus, the semiconductor laminated substrate 10 shown in FIG. 1 is formed. And the result of having analyzed the laminated structure using the three-dimensional atom probe (3DAP) method with respect to the semiconductor laminated substrate 10 manufactured as mentioned above is shown in FIG. 4 and FIG. 4, in the semiconductor multilayer substrate 10 shown in FIG. 1, the total composition ratio of Al, Ga, and N is 100%, the N content is 50%, and the composition ratio of Al, Ga, and N is It is the graph analyzed along the depth direction. 5 shows an Al composition ratio x (%) along the depth direction of the semiconductor multilayer substrate 10 shown in FIG. 1 when the group III element (Al, Ga) and the group V element (N) have the same ratio. In FIG. 5, the analysis results of the group III Al composition ratio (%)), the numerical values at the top of the graph correspond to the symbols shown in FIG.

4 and 5, it can be seen that the AlGaN layers in the electron supply layer 13 are alternately stacked with AlGaN layers having a maximum Al composition ratio x1 and AlGaN layers having a minimum Al composition ratio x2. The average Al composition ratio X is about 24% (X = 0.24), whereas the maximum Al composition ratio x1 is about 27% to 35% (0.27 ≦ x1 ≦ 0.35). It can be seen that the minimum Al composition ratio x2 is about 15% to 18% (0.15 ≦ x2 ≦ 0.18). In addition, when the present inventor performed an SBD manufacturing process using the semiconductor laminated substrate 10 and measured the ohmic contact characteristics in the ohmic electrode portion by the TLM method, the contact resistance value was 5 × 10 ⁻⁶ Ω · It was confirmed to be about cm ^2, and it was confirmed that a good ohmic contact with extremely low contact resistance could be obtained. Further, when the inventor manufactured various semiconductor multilayer substrates 10 based on the above-described manufacturing method of the semiconductor multilayer substrate 10 and analyzed by the 3DAP method, the maximum maximum Al composition ratio x1 was 20% or more and 60%. Less than (0.2 ≦ x1 <0.6) and the minimum minimum Al composition ratio x2 is greater than 0% and less than 20% (0 <x2 <0.2). It was confirmed that a semiconductor laminated substrate having a layer can be manufactured.

From FIG. 5, the local Al composition ratio y of the Al _y Ga _1-y N layer constituting the etching sacrificial layer 14 is the maximum Al composition ratio x 1 or less in the AlGaN layer constituting the electron supply layer 13, and the minimum Al It can be seen that the composition ratio is x2 or more. In addition, the local Al composition ratio y gradually decreases and increases so as to draw a valley-like profile along the stacking direction from the electron supply layer 13 side to the semiconductor layer 15 side of the etching sacrificial layer 14. It can be seen that there is a gradual decrease from the maximum position in the vicinity of the surface of the sacrificial layer 14 toward the semiconductor layer 15 side. The portion where the Al composition ratio y in the vicinity of the surface of the etching sacrificial layer 14 has a local maximum peak is provided with an interruption period of a predetermined time T ₂ after the growth of the etching sacrificial layer 14 in the manufacturing method described above. It is thought that it was caused by. As described above, since the Al composition ratio y changes continuously or stepwise from the etching sacrificial layer 14 toward the semiconductor layer 15, the etching reaches the upper surface of the etching sacrificial layer 14 during the etching of the semiconductor layer 15. From this point, the etching rate changes continuously or stepwise according to the Al composition ratio y. Accordingly, the etching rate can be controlled by etching the surface of the etching sacrificial layer 14, and the etching can be stopped in the etching sacrificial layer 14 with good controllability.

  Next, a nitride semiconductor device having an electron supply layer according to the first embodiment of the present invention configured as described above will be described.

  First, the SBD as the nitride semiconductor device according to the first embodiment will be described. FIG. 6 is a schematic cross-sectional view of an SBD as the nitride semiconductor device according to the first embodiment.

As shown in FIG. 6, in addition to the structure of the semiconductor laminated substrate 10 described above, the SBD 1 according to the first embodiment selectively has an anode electrode 16A as a Schottky electrode and an anode on the etching sacrificial layer 14. A cathode electrode 16C as an ohmic electrode spaced apart from the electrode 16A is provided. Further, on the etching sacrificial layer 14, a field plate layer 15 a made of a part of the semiconductor layer 15 is provided on the anode electrode 16 A side so as to be separated from the cathode electrode 16 C. An insulating film 17 is provided so as to cover at least a part of the etching sacrificial layer 14 and the field plate layer 15a, and the anode electrode 16A and the cathode electrode 16C. Here, the insulating film 17 is made of, for example, SiO ₂ , but other materials, specifically, silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ : alumina), or the like may be used. The materials may be appropriately combined or sequentially stacked.

  In the SBD 1, by providing the field plate layer 15a, the 2DEG concentration Ns of the 2DEG layer a is modulated to be lower than the 2DEG concentration Ns in the 2DEG layer A other than the 2DEG layer a. Thereby, the electric field strength in the portion where the field plate layer 15a is provided can be suppressed. On the other hand, in the state where the semiconductor layer 15 constituting the field plate layer 15a is provided as in the semiconductor laminated substrate 10 shown in FIG. 1, the 2DEG concentration Ns is low, so that the access resistance in the access portion of the electron transit layer 12 is low. Is higher than when the semiconductor layer 15 is not provided. Therefore, in order to reduce the access resistance while controlling the 2DEG concentration Ns of the 2DEG layer A, in the manufacture of the SBD 1, as shown in FIG. 6, the semiconductor layer 15 other than the formation region of the desired field plate layer 15a is etched. Removed. At this time, as described above, since the local Al composition ratio y of the etching sacrificial layer 14 is gradually decreased toward the semiconductor layer 15, the surface of the etching sacrificial layer 14 is formed when the field plate layer 15a is formed. The portion is over-etched to control the etching rate, and the semiconductor layer 15 can be etched with good controllability. Further, the 2DEG concentration Ns generated in the electron transit layer 12 is modulated so as to decrease as the film thickness of the field plate layer 15a formed of a part of the semiconductor layer 15 increases. Therefore, in the first embodiment, the film thickness of the field plate layer 15a, that is, the film thickness of the semiconductor layer 15 is preferably 20 nm or more and 200 nm or less, and preferably 2 DEG concentration Ns by controlling the film thickness using growth and etching. 20 nm or more and 100 nm or less, more preferably 25 nm or more and 80 nm or less, which is less susceptible to variations in the 2DEG concentration Ns due to film thickness variations.

  The anode electrode 16A as the first electrode has, for example, a Ni / Au laminated structure in which the lower electrode layer is a Ni layer and the upper electrode layer is an Au layer. As a result, the anode electrode 16A comes into Schottky contact with the 2DEG layer A generated in the electron transit layer 12 via the etching sacrificial layer 14 and the electron supply layer 13. The anode electrode 16A may be formed by removing the formation region of the anode electrode 16A in the electron supply layer 13 by recess etching and making Schottky contact from the side surface with 2DEG existing under the field plate layer 15a.

  The anode electrode 16A runs on the field plate layer 15a to form at least one step, and extends so as to protrude toward the cathode electrode 16C. In the first embodiment, the anode electrode 16A is provided in contact with part of the side surface and the upper surface of the field plate layer 15a. It should be noted that another semiconductor film or dielectric film may be interposed between the anode electrode 16A and the field plate layer 15a so as not to contact each other. Further, in the first embodiment, the field plate portion is provided in a shape having multi-steps, for example, two steps in the anode electrode 16A.

  The cathode electrode 16C as the second electrode has, for example, a Ti / Al laminated structure in which the lower electrode layer is a Ti layer and the upper electrode layer is an Al layer. As a result, the cathode electrode 16 </ b> C comes into ohmic contact with the 2DEG layer A generated in the electron transit layer 12 via the etching sacrificial layer 14 and the electron supply layer 13.

The insulating film 17 is made of, for example, silicon oxide (SiO ₂ ). The insulating film 17 mainly protects the surfaces of the field plate layer 15a, the anode electrode 16A, the cathode electrode 16C, and the etching sacrificial layer 14. The SBD 1 according to the first embodiment is configured as described above.

(Embodiment 2)
Next, a HEMT field effect transistor as a nitride semiconductor device according to the second embodiment of the present invention will be described. FIG. 7 is a schematic cross-sectional view showing HEMT 2 as the nitride semiconductor device according to the second embodiment.

  As shown in FIG. 7, the HEMT 2 according to the second embodiment includes a field plate layer 15 b and a source spaced apart from each other selectively on the etching sacrificial layer 14 in addition to the structure of the semiconductor multilayer substrate 10 in the first embodiment. An electrode 21S, a gate electrode 21G, a drain electrode 21D, and an insulating film 22 are provided.

  Here, the 2DEG concentration Ns generated in the electron transit layer 12 is modulated so as to decrease as the film thickness of the field plate layer 15b formed of a part of the semiconductor layer 15 increases. For this reason, in the second embodiment, the film thickness of the field plate layer 15b is preferably 20 nm or more and 200 nm or less, preferably 20 nm or more and 100 nm or less, more preferably, for the same reason as in the first embodiment. It is 25 nm or more and 80 nm or less. Further, the field plate layer 15b is formed by etching the semiconductor layer 15 in the semiconductor multilayer substrate 10 using the etching sacrificial layer 14 as an etching stop layer to be over-etched, as in the first embodiment.

In the second embodiment, the electron transit layer 12, the electron supply layer 13, the etching sacrificial layer 14, and the field plate layer 15b constitute a semiconductor stacked body. Then, the 2DEG concentration Ns inside the semiconductor stacked body is modulated by the field plate layer 15b. That is, the 2DEG layer a having a low 2DEG concentration is generated in the lower region of the field plate layer 15b. Here, from the viewpoint of increasing the breakdown voltage of the HEMT ² , the 2DEG concentration Ns of the 2DEG layer a is preferably 7 × 10 ¹² cm ⁻² or less. From the viewpoint of reducing the on-resistance of the HEMT 2, the 2DEG concentration of the 2DEG layer A having a relatively high 2DEG concentration is preferably higher than 7 × 10 ¹² cm ⁻² . As described above, the 2DEG concentration Ns is set to be lower than 10.0 × 10 ¹² cm ⁻² by adjusting the average Al composition ratio X and the number of stacked layers in the electron supply layer 13.

  In addition, the drain electrode 21D as the second electrode and the source electrode 21S as the third electrode are provided on the etching sacrificial layer 14, and are composed of, for example, a laminated structure of Ti / Al. As a result, the drain electrode 21D and the source electrode 21S are in ohmic contact with the 2DEG layer A via the etching sacrificial layer 14 and the electron supply layer 13.

  Further, the gate electrode 21G as the first electrode is disposed between the drain electrode 21D and the source electrode 21S, and is provided on the field plate layer 15b and the insulating film 22. The gate electrode 21G is formed of, for example, a Ni / Au laminated structure. As a result, the gate electrode 21G is in Schottky contact with the 2DEG layer A in the electron transit layer 12 via the etching sacrificial layer 14 and the electron supply layer 13. In addition, the gate electrode 21G is provided to extend in such a manner that the field plate portion protrudes in a stepped manner in multiple steps, for example, toward both sides of the source electrode 21S and the drain electrode 21D. In the second embodiment, the gate electrode 21G is formed so as to be in contact with the etching sacrificial layer 14, but the field plate layer 15b is interposed between the etching sacrificial layer 14 and the gate electrode 21G. It is also possible to configure.

The insulating film 22 is made of, for example, SiO ₂ . The insulating film 22 mainly protects the field plate layer 15a, the gate electrode 21G, the drain electrode 21D, the source electrode 21S, and the surface of the etching sacrificial layer 14. As described above, the HEMT 2 according to the second embodiment is configured.

(Embodiment 3)
Next, SBD as a nitride semiconductor device according to the third embodiment of the present invention will be described. FIG. 8 is a schematic sectional view showing SBD 3 as the nitride semiconductor device according to the third embodiment.

  As shown in FIG. 8, the SBD 3 according to the third embodiment has a configuration in which the etching sacrificial layer 14 and the semiconductor layer 15 are not provided in the structure of the semiconductor laminated substrate 10 according to the first embodiment. That is, the anode electrode 31A as a Schottky electrode and the cathode electrode 31C as an ohmic electrode are selectively provided on the electron supply layer 13 according to the first embodiment so as to be separated from each other. The configurations of the anode electrode 31A and the cathode electrode 31C are the same as those in the first embodiment. The insulating film 32 has the same configuration as the insulating film in the first and second embodiments. As described above, in the case where the semiconductor layer 15 is not provided, the etching sacrificial layer 14 may not be provided because there is no step of etching the semiconductor layer 15 in the manufacture of the SBD 3. As described above, the SBD 3 according to the third embodiment is configured.

(Embodiment 4)
Next, a HEMT as a nitride semiconductor device according to the fourth embodiment of the present invention will be described. FIG. 9 is a schematic cross-sectional view showing a HEMT 4 as a nitride semiconductor device according to the fourth embodiment.

  As shown in FIG. 9, the HEMT 4 according to the fourth embodiment has a configuration in which the etching sacrificial layer 14 and the semiconductor layer 15 are not provided in the structure of the semiconductor laminated substrate 10 according to the first embodiment. That is, the source electrode 41S, the gate electrode 41G, and the drain electrode 41D are selectively provided apart from each other on the electron supply layer 13 according to the embodiment. The source electrode 41S and the drain electrode 41D function as ohmic electrodes formed on the electron supply layer 13, and the gate electrode 41G functions as a Schottky electrode formed on the electron supply layer 13. The configurations of the source electrode 41S, the gate electrode 41G, and the drain electrode 41D are the same as those in the second embodiment. The insulating film 42 has the same configuration as in the first to third embodiments. As described above, the HEMT 4 according to the fourth embodiment is configured.

(Embodiment 5)
Next, a MOSFET (Metal Oxide Semiconductor FET) as a nitride semiconductor device according to the fifth embodiment of the present invention will be described. FIG. 10 is a schematic sectional view showing MOSFET 5 as the nitride semiconductor device according to the fifth embodiment.

  As shown in FIG. 10, MOSFET 5 according to the fifth embodiment has a configuration in which etching sacrificial layer 14 and semiconductor layer 15 are not provided in the structure of semiconductor laminated substrate 10 in the first embodiment. That is, the source electrode 51 </ b> S and the drain electrode 51 </ b> D that are selectively separated from each other are provided on the electron supply layer 13 according to the embodiment. In addition, a gate electrode 51G is formed through a gate oxide film 52 in a recess portion selectively removed by etching of the electron supply layer 13 and the electron transit layer 12 between the source electrode 51S and the drain electrode 51D. . The configurations of the source electrode 51S, the gate electrode 51G, and the drain electrode 51D are the same as those in the second and fourth embodiments. The insulating film 53 has the same configuration as the insulating film in the first to fourth embodiments. As described above, the MOSFET 5 according to the fifth embodiment is configured. In the MOSFET 5, a field plate layer may be provided in a lower layer portion of the gate electrode 51G. In this case, since it is necessary to form the field plate layer by etching the semiconductor layer 15, the MOSFET 5 is manufactured using the semiconductor multilayer substrate 10 including the etching sacrificial layer 14 and the semiconductor layer 15 according to the embodiment.

(Embodiment 6)
Next, a MISFET (Metal Insulator Semiconductor FET) according to the sixth embodiment of the present invention will be described. FIG. 11 is a schematic sectional view showing a MISFET according to the sixth embodiment.

  As shown in FIG. 11, the MISFET 6 according to the sixth embodiment has a configuration in which the etching sacrificial layer 14 and the semiconductor layer 15 are not provided in the structure of the semiconductor laminated substrate 10 according to the first embodiment. That is, the source electrode 61S and the drain electrode 61D are selectively provided on the electron supply layer 13 according to the embodiment. A gate electrode 61G is formed on the electron supply layer 13 between the source electrode 61S and the drain electrode 61D with a gate insulating film 62 interposed therebetween. The configurations of the source electrode 61S, the gate electrode 61G, and the drain electrode 61D are the same as those in the second, fourth, and fifth embodiments. The insulating film 63 has the same configuration as the insulating film in the first to fifth embodiments. As described above, the MISFET 6 according to the sixth embodiment is configured. In the MISFET 6, a field plate layer may be provided in a lower layer portion of the gate electrode 61G. In this case, since it is necessary to form the field plate layer by etching the semiconductor layer 15, the MOSFET 5 is manufactured using the semiconductor multilayer substrate 10 including the etching sacrificial layer 14 and the semiconductor layer 15 according to the embodiment.

  According to the embodiment of the present invention described above, the electron supply layer in the nitride semiconductor device includes an AlGaN layer having a maximum Al composition ratio x1 larger than the average Al composition ratio and a minimum Al composition ratio smaller than the average Al composition ratio. By laminating at least two different types of AlGaN layers with x2 and the AlGaN layer, 2DEG is formed on the interface side of the electron transit layer 12 provided below the electron supply layer 13 with the electron supply layer 13. The nitride semiconductor device can reduce the contact resistance by increasing the electron mobility and reducing the access resistance by increasing the electron wave function in the 2DEG layer to the ohmic electrode side. The element resistance can be reduced. Therefore, while maintaining a high carrier density (2 DEG concentration Ns) in the two-dimensional electron gas in the electron transit layer 12, the electron mobility is increased to reduce the element resistance, and the nitride semiconductor device for power switching having the same rated current Therefore, the element area of the nitride semiconductor device can be reduced by about 20%, so that the nitride semiconductor device can be miniaturized and miniaturized, and a semiconductor substrate having the same diameter is used. In manufacturing, the number of chips that can be taken as a product per semiconductor substrate can be increased, so that the manufacturing cost can be reduced.

  Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications based on the technical idea of the present invention are possible. For example, the numerical values given in the above embodiment are merely examples, and different numerical values may be used as necessary. Further, the present invention is not limited to the above-described embodiment. What was comprised combining each component mentioned above suitably is also contained in this invention. Further effects and modifications can be easily derived by those skilled in the art.

For example, in the above-described embodiment, the electron supply layer is an AlGaN superlattice layer, but in addition to the AlGaN superlattice layer, a plurality of In _u Al _v Ga _{1 -uv} N layers (0 ≦ u <1, 0 It is also possible to employ an InAlGaN superlattice layer in which <v ≦ 1, 0 <u + v <1) is laminated to form a superlattice layer.

For example, in the above-described embodiment, the configuration in which the etching sacrificial layer 14 is provided on the electron supply layer 13 has been described. However, the uppermost layer of the electron supply layer 13 has an Al composition ratio x with an average Al composition ratio X. It can be used as an etching sacrificial layer consisting of a larger Al _x Ga _1-x N layer. This uppermost Al _x Ga _1-x N layer functions as an etching sacrificial layer for preventing the electron supply layer 13 from being over-etched during etching of a field plate layer or the like formed thereon. In order to function in this way, it is preferable that the film thickness of the uppermost Al _x Ga _1-x N layer of the electron supply layer 13 be 1 nm or more. In order to make the Al _x Ga _1-x N layer a part of the electron supply layer 13 of the AlGaN superlattice layer, the film thickness is preferably 10 nm or less. Furthermore, the Al composition ratio x is preferably 0 <x ≦ 0.35 so that oxidation does not become a problem when it is exposed as the etching sacrificial layer on the outermost layer during etching.

  In addition to those described in the above embodiment, various pseudo-mixed crystal structures belonging to the scope of the present invention can be adopted for the electron supply layer according to the structure design based on desired characteristics in the semiconductor device. Is possible.

The electron supply layer 13 includes two different types of Al _x Ga _1-x N layers that are different from each other, and an Al _x1 Ga _1-x1 N layer having a maximum Al composition ratio x1 with a film thickness d1 and a minimum Al composition ratio with a film thickness d2. It is also possible to form a pair of _x2 Al _x2 Ga _1-x2 N layers and to laminate them a plurality of times.

  The anode electrode of the diode and the lower electrode layer of the gate electrode of the transistor are electrodes that are in Schottky contact with the electron supply layer. Therefore, besides nickel (Ni) and titanium (Ti) described above, for example, platinum (Pt), palladium (Pd), tungsten (W), gold (Au), silver (Ag), copper (Cu), tantalum ( Ta), a metal film containing at least one of aluminum (Al), or a metal film made of an alloy containing at least one of Ti, Ni, Pt, Pd, W, Au, Ag, Cu, Ta, and Al Of these, various metal materials satisfying the above conditions, such as a metal film containing at least one or a metal film made of a nitride alloy containing at least one of Ti, W, and Ta may be used. good.

  The upper electrode layer of the anode electrode of the diode and the gate electrode of the transistor is made of a metal having a work function smaller than that of the lower electrode layer, and various materials may be used as long as the metal material satisfies this condition.

  In addition, the cathode electrode of the diode and the source electrode and drain electrode of the transistor are electrodes that are in ohmic contact with the electron supply layer or in contact with a sufficiently small contact resistance. However, the present invention is not limited thereto. For example, a metal film containing at least one of Ti, Al, silicon (Si), lead (Pb), chromium (Cr), In, Ta, Ti, Al, Si, Metal film made of an alloy containing at least one of Pb, Cr, In, Ta, or metal film made of a silicide alloy containing at least one of Ti, Al, Si, Ta, or Ti, W, Ta Any metal material satisfying the above conditions, such as a metal film including at least one of metal films made of a nitride alloy including at least one of them, may be used.

  In the above-described embodiments, SBD, HEMT, MOSFET, and MISFET are given as examples of the semiconductor device according to the present invention. However, the present invention is not limited to this. That is, the present invention can be applied to various semiconductor devices such as MESFET (Metal Semiconductor FET). When the present invention is applied to these FETs, an insulating film such as an oxide film can be provided between the gate electrode and the field plate layer.

  In the above-described embodiment, the electrodes are formed on the surface of the electron supply layer and the etching sacrificial layer. However, the present invention is not limited thereto, and the electron transit layer, the electron supply layer, the etching sacrificial layer, In addition, an electrode can be provided on at least one of the semiconductor laminates including the semiconductor layer and the field plate layer and other layers as necessary. That is, an electrode may be provided on another layer constituting the semiconductor stacked body. Specifically, an anode electrode, a cathode electrode, a gate electrode, a drain electrode, or a source electrode is formed on the surface of the electron supply layer via a nitride-based semiconductor layer such as an insulating layer or a field plate layer, or a laminated film thereof. It is also possible to provide. Further, a part of the electrode formation region of the electron supply layer is removed by etching until reaching the electron transit layer to form a recess portion, and the surface of the recess portion, or the surface of the recess portion via a predetermined film, the anode electrode It is also possible to provide a cathode electrode, a gate electrode, a drain electrode, or a source electrode.

1,3 SBD
2,4 HEMT
5 MOSFET
6 MISFET
10 semiconductor multilayer substrate 11 substrate 12 electron transit layer 13 electron supply layer _{13-1~13-n Al x Ga 1-} x N layer 14 etching sacrificial layer 15 semiconductor layer 15a, 15b field plate layer 16A, 31A anode electrode 16C, 31C Cathode electrode 17, 22, 32, 42, 53, 63 Insulating film 21D, 41D, 51D, 61D Drain electrode 21G, 41G, 51G, 61G Gate electrode 21S, 41S, 51S, 61S Source electrode 52 Gate oxide film 62 Gate insulating film Ac Access part Con Contact part

Claims (18)

A substrate;
The first semiconductor layer has a structure in which a first semiconductor layer made of a nitride semiconductor provided on the substrate and at least one nitride semiconductor layer containing aluminum provided on an upper layer of the first semiconductor layer are stacked. A semiconductor multilayer body having a second semiconductor layer having an average Al composition ratio X having a wider band gap than the average,
A first electrode provided on at least a part of the layers constituting the semiconductor laminate;
A second electrode provided apart from the first electrode on at least a part of the layers constituting the semiconductor laminate, and
A first nitride semiconductor layer including a nitride semiconductor having a maximum Al composition ratio higher than the average Al composition ratio X; and a nitride having a minimum Al composition ratio lower than the average Al composition ratio X. Second nitride semiconductor layers containing semiconductors are alternately stacked at least once, and
The nitride semiconductor device, wherein the maximum Al composition ratio of the first nitride semiconductor layer is higher than the average Al composition ratio X within a range of 0.03 or more and less than 0.3. The Al composition ratio in the second semiconductor layer sequentially increases before and after the maximum Al composition ratio in the first nitride semiconductor layer along the stacking direction from the main surface of the base toward the surface of the second semiconductor layer. 2. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device continuously decreases and increases and decreases in order in the second nitride semiconductor layer before and after the minimum Al composition ratio.   3. The nitride semiconductor device according to claim 1, wherein a maximum Al composition ratio of the first nitride semiconductor layer is 0.2 or more and less than 0.6. 4.   The minimum Al composition ratio of the second nitride semiconductor layer is lower than the average Al composition ratio of the second semiconductor layer within a range of 0.03 or more and less than 0.2. 4. The nitride semiconductor device according to claim 1.   5. The nitride semiconductor device according to claim 1, wherein a minimum Al composition ratio of the second nitride semiconductor layer is greater than 0 and less than 0.2.   6. The nitride semiconductor device according to claim 1, wherein an average Al composition ratio X of the second semiconductor layer is 0.1 or more and 0.4 or less.   The nitride semiconductor device according to claim 1, wherein a film thickness of the second semiconductor layer is 2 nm or more.   The nitride semiconductor device according to claim 1, wherein the second semiconductor layer has a thickness of 30 nm or less.   A first nitride semiconductor layer including a nitride semiconductor having at least one maximum Al composition ratio higher than an average Al composition ratio of the second semiconductor layer; and an average Al of the second semiconductor layer. The second nitride semiconductor layer including a nitride semiconductor having a minimum Al composition ratio that is lower than the composition ratio is alternately stacked at least 5 times and not more than 10 times. The nitride semiconductor device according to any one of 1 to 8. Al _Y Ga ₁ having an average Al composition ratio Y lower than the maximum Al composition ratio and higher than the minimum Al composition ratio of the plurality of nitride semiconductor layers constituting the second semiconductor layer in the semiconductor stacked body. the nitride semiconductor device according to any one of claims 1-9, characterized in that the etching sacrificial layer formed of _-Y N are configured to have the second semiconductor layer.   The nitride semiconductor device according to claim 10, wherein a thickness of the etching sacrificial layer is not less than 1 nm and not more than 12 nm.   The semiconductor stacked body further includes a third semiconductor layer made of a nitride-based semiconductor that is selectively provided above the second semiconductor layer and has an average band gap narrower than that of the second semiconductor layer. The nitride semiconductor device according to any one of claims 1 to 11.   13. The nitride semiconductor device according to claim 12, wherein the third semiconductor layer is made of gallium nitride having a thickness of 20 nm to 200 nm.   The third electrode provided further apart from the first electrode and the second electrode on at least a part of the layers constituting the semiconductor stacked body. The nitride semiconductor device according to any one of ˜13. A structure of the nitride semiconductor device according to claim 14,
The field effect transistor, wherein the first electrode is a gate electrode, the second electrode is a drain electrode, and the third electrode is a source electrode. It has the structure of the nitride semiconductor device according to any one of claims 1 to 13,
The diode, wherein the first electrode is an anode electrode and the second electrode is a cathode electrode. A substrate, a first semiconductor layer made of a nitride semiconductor provided on the substrate, and a nitride semiconductor layer made of at least two different Al composition ratios are stacked a plurality of times to form a superstructure made of a plurality of nitride semiconductor layers. A semiconductor stacked body having a lattice structure and a second semiconductor layer having an average band gap wider than that of the first semiconductor layer, and provided on at least a part of the layers constituting the semiconductor stacked body And a second electrode provided on and separated from the first electrode on at least a part of the layers constituting the semiconductor stacked body, and a method for manufacturing a nitride semiconductor device In
Growth of each nitride semiconductor layer in the plurality of nitride semiconductor layers when forming the plurality of nitride semiconductor layers in the second semiconductor layer by a growth process by metal organic chemical vapor deposition A method of manufacturing a nitride semiconductor device, wherein the growth of the nitride semiconductor layer is interrupted for a predetermined time between the steps.   Etching in which the semiconductor stacked body is made of AlGaN having an Al composition ratio lower than a maximum Al composition ratio and higher than a minimum Al composition ratio in the plurality of nitride semiconductor layers constituting the second semiconductor layer When the sacrificial layer is provided, the nitride semiconductor layer grown on the uppermost layer of the plurality of nitride semiconductor layers is etched away before the etching sacrificial layer is grown. Item 18. A method for manufacturing a nitride semiconductor device according to Item 17.

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