JP2015111999A - Inverter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter circuit that prevents the occurrence of an excess voltage or an excess current in a DC link.SOLUTION: An inverter circuit 100 includes: a rectifier section 1 rectifying an AC voltage supplied from a three-phase AC power supply PS into a DC voltage; and a smoothing section 2 smoothing the DC voltage outputted from the rectifier section 1. The inverter circuit 100 also includes an inverter section 3 converting the smoothed DC voltage into a three-phase AC voltage and supplying the three-phase AC voltage to a motor M. The inverter circuit 100 further includes a prevention section 6 preventing the occurrence of an excess voltage or an excess current in a DC section (DC link) 4 between the rectifier section 1 and the inverter section 3.

Description

  The present invention relates to an inverter circuit.

  An inverter circuit used to control a motor or the like converts a commercial AC voltage into a DC voltage by a diode bridge, smoothes a pulsating current remaining in the converted DC voltage with a smoothing capacitor, and smoothes the DC voltage. Is input to the inverter unit to generate an AC voltage.

  Conventionally, in order to prevent the pulsating flow remaining in the AC voltage applied to the motor or the like from adversely affecting the control of the motor or the like, there is almost no pulsating amplitude remaining in the DC voltage input to the inverter unit. It was smoothed until. For this reason, a smoothing capacitor having a large capacitance and a large volume has been used.

  However, a switching control method has been developed that prevents the motor control from being adversely affected even if the amplitude of the pulsating current remaining in the DC voltage is large, and the capacitance of the smoothing capacitor does not have to be increased as much as in the past. It has become. Therefore, replacement of an electrolytic capacitor having a large capacitance and volume with a ceramic capacitor or a film capacitor having a small capacitance and volume has been performed.

Patent Document 1 discloses a diode bridge that rectifies an input three-phase AC voltage into a DC voltage, an inverter unit that converts the DC voltage converted by the diode bridge into an AC voltage, and outputs one of the diode bridges. An LC filter having an inductor L _dc connected between the input terminal and one input terminal of the conversion unit, a capacitor C _dc connected between the input terminals of the inverter unit, and a voltage across the inductor L _dc are detected. A voltage detection unit, and a control unit that controls the inverter unit, wherein the control unit determines the transfer characteristic of the input / output voltage of the inverter unit based on the voltage across the inductor L _dc detected by the voltage detection unit. An inverter device for controlling the inverter unit is described.

  Patent Document 2 discloses a rectifier circuit comprising a diode element for rectifying the voltage of an AC system of commercial frequency and outputting it to a DC bus, and an inverter comprising a semiconductor switching element for converting the DC bus voltage to AC and supplying it to a load. A voltage clamp circuit comprising a series body of a switch and a resistor connected between the DC buses, and the voltage between the DC buses is set to the predetermined overvoltage so that a voltage exceeding a predetermined overvoltage is not generated between the DC buses. A power conversion device including a switch control circuit that closes the switch that is normally open when there is a risk or when there is a risk is described.

  In Patent Document 3, switching of switching elements Trp, Ttp, Trn, and Ttn provided in at least two-phase upper and lower arms of a converter circuit connected to a three-phase AC power source and a capacitor, and opening / closing of an open / close relay are controlled. After the energization of the converter circuit is started, the control unit closes the open / close relay until the inrush current can be suppressed, the one-phase upper and lower arms are turned on, and the remaining upper and lower arms are turned off. A power conversion circuit that controls switching of each of the switching elements Trp, Trn, Ttp, Ttn so as to be in a state is described.

JP 2008-29151 A JP 2010-239736 A JP 2012-235632 A

By the way, in a so-called capacitor-less (capacitor-less) inverter circuit using a smoothing capacitor having a small electrostatic capacity, a problem that does not occur when the smoothing capacitor has a large electrostatic capacity has occurred. That is, overvoltage or overcurrent may occur in a portion (DC link) to which a DC voltage is applied in the inverter circuit. There has been a risk that the inverter circuit may fail due to overvoltage or overcurrent.
An object of the present invention is to provide an inverter circuit that suppresses occurrence of overvoltage or overcurrent in a DC link.

  For this purpose, an inverter circuit to which the present invention is applied includes a rectifier that rectifies an input AC voltage into a DC voltage, and a smoothing unit that smoothes a DC voltage output from the rectifier. Prepare. The inverter circuit includes an inverter unit connected to a load and converting the DC voltage smoothed by the smoothing unit into an AC voltage and outputting the AC voltage to the load. The inverter circuit includes a suppressing unit that is provided between the rectifying unit and the smoothing unit and suppresses overvoltage or overcurrent of a DC link to which a DC voltage is applied in the smoothing unit.

  In such an inverter circuit, the rectification unit may include one output terminal and the other output terminal connected to a common potential line for setting a common potential. The smoothing unit may include one input terminal and the other input terminal connected to the common potential line. The suppression unit includes a DC reactor provided between the one output terminal of the rectification unit and the one input terminal of the smoothing unit, and a resistor and a capacitor provided in parallel with the DC reactor. And a series circuit.

Thereby, since the suppression part is comprised by passive components, such as a DC reactor, resistance, and a capacitor | condenser, a suppression part can be comprised cheaply.
Furthermore, the inverter circuit can be miniaturized by using a small smoothing portion with a small capacitance.
In addition, the harmonic current generated by the load can be suppressed by a DC reactor and a series circuit of a resistor and a capacitor provided in the suppression unit.

  In such an inverter circuit, the smoothing unit may include one input terminal and the other input terminal connected to the common potential line. In addition, the suppression unit includes an overvoltage in a series circuit of a surge absorber and a control switch element provided between the one input terminal of the smoothing unit and the common potential line, and a voltage of the DC link. And an overvoltage detection means for detecting the overvoltage and setting the control switch element to ON.

  Thereby, when the inverter circuit is in a normal state, power consumption by the suppressing unit can be reduced.

The surge absorber may be a varistor.
Thereby, absorption of instantaneous electric power can be performed easily.

And the varistor which is a surge absorber in the said suppression part can have a discharge start voltage smaller than the voltage of the said DC link which the said overvoltage detection means detects as an overvoltage.
Thereby, when an overvoltage is detected, the overvoltage can be stably suppressed.

  In such an inverter circuit, the suppression unit includes a series circuit of two capacitors connected in parallel to the smoothing unit, the other phase other than one phase of the input AC voltage, and the rectification. And a first switch provided between the first portion and the second portion. The suppression unit includes a connection point of the two capacitors in the series circuit, and a series circuit of a current limiting resistor and a second switch connected to a neutral point of the input AC voltage. Can be characterized.

Thereby, components lower than the line voltage of the AC voltage input to the first switch and the second switch can be used.
In addition, the harmonic current generated by the load can be suppressed by the DC circuit of the two capacitors provided in the suppression unit.

  Furthermore, the suppression unit includes a series circuit of two capacitors connected in parallel to the smoothing unit, and a phase other than one of the phases of the input AC voltage and the rectifying unit. And a first switch provided therebetween. Further, the suppression unit includes a current limiting resistor and a second switch connected to a connection point of the two capacitors in the series circuit and one phase of an AC voltage provided with the first switch. And a series circuit.

  Thereby, it is applicable also when the alternating voltage input is a three-phase three-wire system.

  ADVANTAGE OF THE INVENTION According to this invention, the inverter circuit which suppressed generation | occurrence | production of the overvoltage or overcurrent in a DC link can be provided.

It is a figure which shows an example of the inverter circuit to which embodiment of this invention is applied. It is a figure which shows an example of the inverter circuit to which 1st Embodiment is applied. It is a figure which shows the inverter circuit to which 1st Embodiment is not applied. FIG. 4 is a diagram comparing an inverter circuit to which the first embodiment shown in FIG. 2 is applied and an inverter circuit to which the first embodiment shown in FIG. 3 is not applied. It is a figure which shows the actual measurement result by the actual machine of the inverter circuit to which 1st Embodiment is applied. It is the figure which showed the frequency response characteristic of the power supply current about three models (simulation model) of an inverter circuit. It is a figure which shows the current waveform of the power supply in a 1st simulation model. (A) is a figure which shows a 1st simulation model, (b) is a figure which shows the relationship between a power supply current and time. It is a figure which shows the current waveform of the power supply in a 2nd simulation model. (A) is a figure which shows a 2nd simulation model, (b) is a figure which shows the relationship between a power supply current and time. It is a figure which shows the current waveform of the power supply in the 3rd simulation model corresponding to the inverter circuit to which 1st Embodiment is applied. (A) is a figure which shows a 3rd simulation model, (b) is a figure which shows the relationship with the time of power supply current. It is a figure which shows an example of the inverter circuit to which 2nd Embodiment is applied. It is a figure which shows the overvoltage detection circuit in the suppression part of the inverter circuit to which 2nd Embodiment is applied as an example. It is a figure which shows an example of the voltage of the DC link in the inverter circuit to which 2nd Embodiment is applied. It is a figure which shows an example of the voltage of the DC link in the inverter circuit to which 2nd Embodiment is not applied. It is a figure which shows an example of the inverter circuit to which 3rd Embodiment is applied. It is a figure which shows the power supply current with respect to the inverter circuit to which 3rd Embodiment is applied. (A) is an inverter circuit to which the third embodiment is applied, and (b) is a power supply current for an inverter circuit to which the third embodiment is not applied. It is a figure which shows the modification of the inverter circuit to which 3rd Embodiment is applied.

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.
First, items common to the following embodiments will be described.
The inverter circuit described in this embodiment is used to supply power to a load such as a motor used in a compressor such as an air conditioner or a refrigerator. That is, the inverter circuit converts (rectifies) the AC voltage supplied from the AC power source into a DC voltage, smoothes the DC voltage, and then converts it to an AC voltage suitable for controlling the load.

FIG. 1 is a diagram showing an example of an inverter circuit 100 to which an embodiment of the present invention is applied.
Here, the AC power supply is assumed to be a three-phase AC power supply PS, and the load such as a motor is assumed to be a motor M controlled by a three-phase AC voltage.
The inverter circuit 100 includes a rectifying unit 1 that rectifies an AC voltage supplied from a three-phase AC power supply PS into a DC voltage, and a smoothing unit 2 that smoothes the DC voltage output from the rectifying unit 1. The inverter circuit 100 includes an inverter unit 3 that converts the smoothed DC voltage into a three-phase AC voltage and supplies the converted voltage to the motor M. The inverter circuit 100 includes a suppressing unit 6 provided between the rectifying unit 1 and the smoothing unit 2. The suppression unit 6 suppresses the occurrence of overvoltage or overcurrent in the DC link 4 to which the DC voltage of the smoothing unit 2 is applied.

In the inverter circuit 100, the rectification unit 1, the suppression unit 6, the smoothing unit 2, and the inverter unit 3 are connected in this order. That is, the rectification unit 1 and the suppression unit 6 are connected by the terminals P1 and P2. The suppression unit 6 and the smoothing unit 2 are connected by terminals P3 and P4. The smoothing unit 2 and the inverter unit 3 are connected by terminals P5 and P6. As will be described later, the terminals P2, P4, and P6 are connected to a common potential line 5 that supplies a common potential.
Here, the terminal P1 is one output terminal of the rectifying unit 1, and the terminal P2 is the other output terminal of the rectifying unit 1. The terminal P3 is one input terminal of the smoothing unit 2, and the terminal P4 is the other input terminal of the smoothing unit 2.

  The rectifying unit 1 is a diode bridge composed of, for example, six rectifying diodes Dc. Six rectifier diodes Dc are connected in a bridge shape so as to rectify the AC voltage of each phase supplied from the three-phase AC power supply PS into a DC voltage.

  The smoothing unit 2 includes a smoothing capacitor (smoothing capacitor) Cs. Here, an electrolytic capacitor having a large capacitance and volume is not used, and a ceramic capacitor or a film capacitor having a small capacitance and volume is used. The inverter circuit 100 is a so-called capacitor (capacitor) -less.

The inverter unit 3 includes, for example, six switching circuits. Each switching circuit includes a switching element St and a feedback diode Df that allows a reverse current to flow. The inverter unit 3 supplies a three-phase AC voltage to the motor M by controlling on / off of the switching element St in each switching circuit.
The inverter unit 3 is controlled so that the influence of the pulsating flow does not appear on the motor M even if the amplitude of the pulsating flow is greater than or equal to a predetermined value in the DC voltage output from the smoothing unit 2. The Therefore, even when the amplitude of the pulsating current in the DC voltage output from the smoothing unit 2 is large, the same control of the motor M as when the electrolytic capacitor is used for the smoothing unit 2 can be realized.
For example, an insulated gate bipolar transistor (IGBT) can be used as the switching element St.

The motor M is, for example, a DC brushless motor. The motor M may be another three-phase AC motor.
The suppressing unit 6 will be described later. In order to distinguish each, the suppression part 6 demonstrated by the following several embodiment is described as suppression part 6A, 6B.

  The DC link 4 is a portion to which a DC voltage is applied, such as between one terminal of the smoothing capacitor Cs in the smoothing unit 2 and between the terminals P2 and P3 to which the terminal is connected. The other terminal of the smoothing capacitor Cs is connected to the common potential line 5 connected to the terminals P2, P4, and P6. The voltage of the DC link 4 (DC link voltage) is the difference between the potential of the common potential line 5 and the potential of the DC link 4.

[First Embodiment]
FIG. 2 is a diagram illustrating an example of the inverter circuit 100 to which the first embodiment is applied.
The inverter circuit 100 according to the first embodiment includes a suppressing unit 6A as the suppressing unit 6 illustrated in FIG. The suppressing unit 6A suppresses the inverter circuit 100 from being broken due to an induced electromotive current generated when the motor M is urgently stopped, for example. That is, an induced electromotive current generated when the motor M is stopped urgently flows in each switching circuit constituting the inverter unit 3. As a result, the voltage of the DC link 4 increases. At this time, if the voltage of the DC link 4 becomes an overvoltage higher than or equal to the breakdown voltage of the switching element St, the switching element St may be destroyed. Therefore, the suppressing unit 6A suppresses the DC link 4 from becoming overvoltage when the motor M is in an emergency stop.
The suppressing unit 6A suppresses harmonic current components in the power supply current.

  The suppression unit 6A includes a DC reactor Lp, a resistor Rp, and a capacitor Cp. The DC reactor Lp is connected between the terminals P1 and P3. The resistor Rp and the capacitor Cp are a series circuit connected in series, and are connected in parallel with the DC reactor Lp.

For example, the capacitance of the smoothing capacitor Cs in the smoothing unit 2 is preferably 1 to 100 μF, and is set to 40 μF here. The inductance of the DC reactor Lp is preferably 1 to 10 mH, and is set to 2 mH here. The resistance value of the resistor Rp is preferably 5 to 100Ω, and is set to 15Ω here. The capacitance of the capacitor Cp is preferably 1 to 100 μF, and is set to 10 μF here.
The resistance value of the resistor Rp and the capacitance of the capacitor Cp may be set so that the voltage increase of the DC link 4 is lower than the breakdown voltage of the switching element St.

<Suppression of overvoltage of DC link 4>
Here, it will be described that the overvoltage of the DC link 4 is suppressed by the suppressing unit 6A in the inverter circuit 100.
FIG. 3 is a diagram illustrating an inverter circuit 100 to which the first embodiment is not applied.
In the inverter circuit 100 to which the first embodiment is not applied, the inverter circuit 100 shown in FIG. 2 includes a DC reactor Ldc instead of the suppressing unit 6A.
The inductance of the DC reactor Ldc is set to 2 mH.
Since the other configuration is the same as that of the inverter circuit 100 shown in FIG. 2, the same reference numerals are given and the description thereof is omitted.

  FIG. 4 is a diagram comparing the inverter circuit 100 to which the first embodiment shown in FIG. 2 is applied and the inverter circuit 100 to which the first embodiment shown in FIG. 3 is not applied. Here, the voltage of the DC link 4 (DC link voltage) is shown for the worst case in which the voltage of the DC link 4 is most likely to increase when the motor M stops in an emergency. Specifically, the motor M was stopped immediately in the vicinity of 5 ms, and the voltage of the DC link 4 was simulated. In FIG. 4, the inverter circuit 100 to which the first embodiment shown in FIG. 3 is not applied is referred to as “an inverter circuit having only a DC reactor Ldc”.

  As shown in FIG. 4, in the inverter circuit 100 to which the first embodiment is applied, the increase in the DC link voltage is 873V. On the other hand, in the inverter circuit 100 (the inverter circuit 100 having only the DC reactor Ldc) to which the first embodiment is not applied, the increase in the DC link voltage is 972V. That is, the suppression unit 6A of the inverter circuit 100 suppresses a voltage increase of the DC link 4 by about 100V.

FIG. 5 is a diagram illustrating an actual measurement result of an actual inverter circuit 100 to which the first embodiment is applied. The upper part of FIG. 5 is an entire measurement period at the time of emergency stop of the motor M, and the lower part of FIG. 5 is an enlarged view of a part where the voltage of the DC link 4 is rising in the central part of the upper part. FIG. 5 shows the measured voltage of the DC link 4 (DC link voltage) and the current flowing through the DC reactor Lp (DC reactor current).
Whether or not the simulation result shown in FIG. 4 can simulate the increase in the voltage (DC link voltage) of the DC link 4 of the actual inverter circuit 100 was confirmed by an actual machine.

Although the worst case is not completely realized in FIG. 5, the rising tendency of the voltage of the DC link 4 (DC link voltage) after the emergency stop of the motor M can be almost reproduced. That is, the DC link voltage that was 510 V has increased to 791 V after the emergency stop of the motor M.
This 791V is lower than 873V obtained from the simulation results.

  As described above, by providing the inverter circuit 100 with the suppressing unit 6A, the occurrence of overvoltage in the DC link 4 is suppressed.

<Suppression of harmonic current>
Next, it will be described that the suppressing unit 6A in the inverter circuit 100 can suppress the harmonic current generated due to the load fluctuation of the motor M or the like.
FIG. 6 is a diagram illustrating the frequency response characteristics of the power supply current for three models (simulation models) of the inverter circuit 100. In each simulation model, an EMI (Electro-Magnetic Interference) filter 7 not shown in FIG. 2 is added, and the motor M is replaced with a load current source CC.
The EMI filter 7 is provided between the rectification unit 1 and the suppression unit 6 (smoothing unit 2 when the suppression unit 6 is not provided), and includes a DC reactor Lf and a capacitor Cf.
Here, as an example, the reactance of the DC reactor Lf is 20 μH, and the capacitance of the capacitor Cf is 1 μF.
In FIG. 6, only one phase of the three phases of the inverter circuit 100 is taken out and described.

Each simulation model will be described.
The first simulation model is obtained by omitting the suppressing unit 6A from the inverter circuit 100 to which the first embodiment is applied.
In the second simulation model, a DC reactor Ldc is provided instead of the suppressing unit 6A of the inverter circuit 100 to which the first embodiment is applied. That is, the second simulation model corresponds to the inverter circuit 100 to which the first embodiment shown in FIG. 3 is not applied.
The third simulation model corresponds to the inverter circuit 100 to which the first embodiment shown in FIG. 2 is applied.

As shown in FIG. 6, the first simulation model does not include the suppression unit 6A. Therefore, an LC resonance circuit is configured by the DC reactor Lf and the capacitor Cf in the EMI filter 7 and the smoothing capacitor Cs. As described above, the reactance of the DC reactor Lf is 20 μH, the capacitance of the capacitor Cf is 1 μF, and the capacitance of the smoothing capacitor Cs is 40 μF. Therefore, the resonance frequency is 5.56 kHz.
The resonance frequency is on the high frequency band side compared to other simulation models, and harmonic current components in particular in the high frequency band cannot be suppressed. Therefore, for example, there is a possibility that the harmonic countermeasure standards of each country cannot be satisfied.

In the second simulation model, a DC reactor Ldc is provided instead of the suppressing unit 6A of the inverter circuit 100 to which the first embodiment is applied. Therefore, an LC resonance circuit is constituted by the DC reactor Ldc and the smoothing capacitor Cs. As described above, the reactance of the DC reactor Ldc is 2 mH, and the capacitance of the smoothing capacitor Cs is 40 μF. Therefore, a resonance frequency is generated in the 100 to 1000 Hz band.
For this reason, the high frequency band component of the harmonic current can be sufficiently suppressed. However, since the resonance peak is large at the resonance frequency of the LC resonance circuit, the low frequency band component of the harmonic current is amplified, and there is a possibility that it is not a sufficient countermeasure against the harmonic current.

On the other hand, the third simulation model corresponds to the inverter circuit 100 to which the first embodiment is applied, and includes a suppressing unit 6A. Thereby, the resonance peak at the resonance frequency of the LC resonance circuit by the DC reactor Lp and the smoothing capacitor Cs is reduced, and the low frequency band component of the harmonic current is sufficiently reduced.
That is, the load current source CC is a source of harmonic current. The high frequency band component of this harmonic current is bypassed by the smoothing capacitor Cs. The low frequency band component of this harmonic current is suppressed by the DC reactor Lp. Furthermore, the current flowing through the LC resonance circuit of the smoothing capacitor Cs and the DC reactor Lp is reduced by the series circuit of the resistor Rp and the capacitor Cp.

Next, the current waveform of the power supply in each simulation model will be described.
FIG. 7 is a diagram showing a current waveform of the power supply in the first simulation model. FIG. 7A is a diagram showing the first simulation model, and FIG. 7B is a diagram showing the relationship between the power supply current and time.
The harmonics in the high frequency band shown in FIG. 6 are superimposed on the current waveform of the power source shown in FIG.

FIG. 8 is a diagram illustrating a current waveform of a power supply in the second simulation model. FIG. 8A is a diagram showing the second simulation model, and FIG. 8B is a diagram showing the relationship between the power supply current and time.
The harmonics in the high frequency band shown in FIG. 7 are suppressed in the current waveform of the power source shown in FIG. 8B, but the harmonics in the low frequency band shown in FIG. 6 are superimposed. Moreover, the harmonics in the low frequency band are larger than those in the third simulation model shown below.

FIG. 9 is a diagram showing a current waveform of the power supply in the third simulation model corresponding to the inverter circuit 100 to which the first embodiment is applied. FIG. 9A is a diagram showing a third simulation model, and FIG. 9B is a diagram showing the relationship with the time of the power supply current.
In the current waveform of the power source shown in FIG. 9B, the amplitude of the harmonics in the low frequency band is reduced as compared with FIG.

  As described above, in the third simulation model corresponding to the inverter circuit 100 to which the first embodiment is applied, the harmonic current in the power supply current is most suppressed.

Next, the results of calculating THC (Total Harmonic Current) and PWHC (Partial Weighted Harmonic Current), which are indicators of the power supply harmonic current, for each simulation model will be described.
THC and PWHC are calculated by Equation (1) and Equation (2), respectively.

  Here, Ih: current spectrum amplitude at order h, Iref: current spectrum amplitude at power supply frequency (h = 1), and power supply frequency: 50 Hz.

  Table 1 shows the calculated THC and PWHC. Table 1 shows THC and PWHC for the above three simulation models.

In the first simulation model, THC is the smallest 30.2%, while PWHC is the largest 56.2%. In the second simulation model, THC is the largest 39.0%, while PWHC is the smallest 50.0%. On the other hand, in the third simulation model, THC is close to the smallest value (30.2%) as 31.8%, and PWHC is close to the smallest value (50.0%) as 50.5%.
That is, the inverter circuit 100 to which the first embodiment corresponding to the third simulation model is applied suppresses the harmonic current in the power supply current with a good balance.

  The inverter circuit 100 in the first embodiment is downsized as a whole by using a smoothing capacitor Cs having a small capacitance and a small volume in the smoothing unit 2. However, the suppressing unit 6A suppresses the DC link 4 from being overvoltage due to an induced electromotive current generated when the motor M is stopped urgently. Therefore, it is suppressed that the voltage of the DC link 4 rises over the breakdown voltage of the switching element St of the inverter unit 3 and the inverter circuit 100 breaks down.

  Furthermore, the suppression unit 6A of the inverter circuit 100 to which the first embodiment is applied reduces the resonance peak of the LC resonance circuit formed by the smoothing capacitor Cs and the DC reactor Lp. Thereby, the harmonic current in the power supply current is reduced.

  In addition, the suppressing unit 6A includes a DC reactor Lp and a series circuit of a resistor Rp and a capacitor Cp connected in parallel to the DC reactor Lp. That is, the suppressing unit 6A is configured only with a passive circuit (passive component). Therefore, the overvoltage of the DC link 4 that occurs when the motor M is in an emergency stop or the like is suppressed without using a complicated control circuit (control logic). Therefore, the inverter circuit 100 can be manufactured at low cost.

Next, a modification of the inverter circuit 100 to which the first embodiment is applied will be described.
In the above, the suppression unit 6A mainly suppresses the inverter unit 3 from being destroyed. However, the resistance value of the resistor Rp and the capacitance of the capacitor Cp may be set based on the breakdown voltage of other elements.

  Further, the failure of the inverter circuit 100 does not only indicate that the inverter unit 3 is destroyed. For example, it is a concept including that some trouble occurs due to an induced electromotive current generated when the motor M is stopped urgently, and the inverter circuit 100 cannot sufficiently perform its function.

  In the above, parameters such as the resistance value of the resistor Rp and the electrostatic capacity of the capacitor Cp of the suppressing unit 6A are set from the viewpoint of preventing the above-described failure. However, for example, it may be set in consideration of suppression of the resonance peak of the LC resonance circuit formed by the smoothing capacitor Cs and the DC reactor Lp. Then, the above parameters may be set while performing predetermined weighting on both the voltage of the DC link 4 and the resonance peak of the LC resonance circuit.

[Second Embodiment]
The suppression unit 6A in the inverter circuit 100 to which the first embodiment is applied is configured by a DC reactor Lp and a series circuit of a resistor Rp and a capacitor Cp connected in parallel to the DC reactor Lp. The overvoltage of the DC link 4 that occurs during the emergency stop of the motor M is suppressed by the suppression unit 6A.
The inverter circuit 100 of the second embodiment includes a suppression unit 6B having a different configuration from the suppression unit 6A in the inverter circuit 100 to which the first embodiment is applied. And the suppression part 6B suppresses the overvoltage of the DC link 4 that occurs during the emergency stop of the motor M.

FIG. 10 is a diagram illustrating an example of the inverter circuit 100 to which the second embodiment is applied.
The inverter circuit 100 to which the second embodiment is applied includes a suppression unit 6B as the suppression unit 6 of FIG. The same parts as those of the inverter circuit 100 to which the first embodiment shown in FIG. 1 is applied are denoted by the same reference numerals, description thereof is omitted, and the suppressing part 6B which is a different part will be described.

The suppression unit 6B includes a surge absorber SA, a control switch element Sc, and an overvoltage detection circuit 61 as an example of an overvoltage detection unit. The surge absorber SA and the control switch element Sc are connected in series. The surge absorber SA side is connected to the terminal P3 (terminal P1), and the control switch element Sc side is connected to the terminal P4 (terminal P2).
The overvoltage detection circuit 61 is provided between the terminal P3 (terminal P1) and the terminal P4 (terminal P2), and detects the voltage of the DC link 4.

For the surge absorber SA, for example, a varistor using zinc oxide or a micro gap may be used. The varistor has a characteristic that when a voltage equal to or higher than a predetermined voltage (discharge start voltage) is applied, the varistor shifts from the off state to the on state and current starts to flow instantaneously. The varistor has a large power withstand capability (energy withstand capability), and can absorb the instantaneous power accompanying the discharge even if a large current flows instantaneously due to the discharge when the discharge start voltage is exceeded.
The control switch element Sc is, for example, an IGBT or the like, and shifts from an off state to an on state when a predetermined voltage is applied to the control gate Gc.
The overvoltage detection circuit 61 detects whether or not the voltage of the DC link 4 exceeds a predetermined detection voltage. When the voltage of the DC link 4 exceeds the detection voltage, a voltage that causes the control switch element Sc to shift from the off state to the on state is supplied to the control gate Gc.
The discharge start voltage of the surge absorber SA is set lower than the detection voltage of the overvoltage detection circuit 61.

The operation of the suppression unit 6B will be described.
When the inverter circuit 100 is operating normally, the voltage of the DC link 4 is equal to or lower than the detection voltage of the overvoltage detection circuit 61. In this case, the overvoltage detection circuit 61 supplies the control gate Gc with a voltage that maintains the control switch element Sc in the off state. Since the control switch element Sc is in the OFF state, no current flows through the surge absorber SA connected in series to the control switch element Sc.
During an emergency stop of the motor M, the voltage of the DC link 4 rises and exceeds the detection voltage. Then, the overvoltage detection circuit 61 supplies the control gate Gc with a voltage that causes the control switch element Sc to shift from the off state to the on state. Thereby, the control switch element Sc is turned on, and the voltage of the DC link 4 is applied to the series circuit of the control switch element Sc and the surge absorber SA. At this time, the voltage of the DC link 4 is divided by the control switch element Sc and the surge absorber SA. The resistance value of the control switch element Sc in the on state is smaller than the resistance value of the surge absorber SA. Therefore, most of the voltage of the DC link 4 is applied to the surge absorber SA.
At this time, since the voltage applied to the surge absorber SA exceeds the discharge start voltage of the surge absorber SA, the surge absorber SA shifts from the off state to the on state. Then, current flows from the DC link 4 toward the common potential line 5 via the surge absorber SA and the control switch element Sc, and the voltage of the DC link 4 decreases.

When the voltage of the DC link 4 becomes equal to or lower than the detection voltage, the overvoltage detection circuit 61 supplies a voltage at which the control switch element Sc shifts from the on state to the off state to the control gate Gc. Thereby, the control switch element Sc shifts from the on state to the off state, and the surge absorber SA also shifts from the on state to the off state. Then, the current flowing from the DC link 4 toward the common potential line 5 is interrupted through the surge absorber SA and the control switch element Sc. Then, the voltage of the DC link 4 is not affected by the suppression unit 6B.
That is, when the DC link 4 exceeds the detection voltage, the suppression unit 6B is operated, and when the voltage of the DC link 4 becomes equal to or lower than the detection voltage, the operation of the suppression unit 6B is stopped.

  It is conceivable that the control switch element Sc is provided between the DC link 4 and the common potential line 5 without using the surge absorber SA. However, when the DC link 4 becomes overvoltage and the control switch element Sc is switched from the off state to the on state, a large instantaneous power instantaneously flows from the DC link 4 to the common potential line 5. If the instantaneous power is absorbed by the control switch element Sc, the control switch element Sc may be out of the stable operation region and destroyed.

It is also conceivable to provide the surge absorber SA between the DC link 4 and the common potential line 5 without using the control switch element Sc. However, the surge absorber SA such as a varistor has a larger leakage current than the control switch element Sc. For this reason, the surge absorber SA consumes power even in the off state.
Further, it is necessary to select a surge absorber SA having a discharge start voltage corresponding to an overvoltage to be suppressed in the DC link 4. For example, when the line voltage of the three-phase AC power supply PS is 220V, the voltage of the DC link 4 in a normal state is about 540V. In this case, if the surge absorber SA is operated when the voltage of the DC link 4 reaches 600V, the surge absorber SA having a discharge start voltage of 600V is used.

Therefore, in the inverter circuit 100 to which the second embodiment is applied, a series circuit of the surge absorber SA and the control switch element Sc is used. In a normal state, that is, when the voltage of the DC link 4 is equal to or lower than the detection voltage, no current flows through the series circuit of the surge absorber SA and the control switch element Sc. Therefore, power consumption is suppressed in a normal state.
When the voltage of the DC link 4 exceeds the detection voltage, the control switch element Sc is shifted from the off state to the on state, and the surge absorber SA is turned on. Therefore, the discharge start voltage of the surge absorber SA can be set separately from the detection voltage for detecting the overvoltage of the DC link 4. For example, when the detection voltage of the overvoltage detection circuit 61 is set to 600 V, a surge absorber SA having a discharge start voltage of 450 V lower than the detection voltage of 600 V can be used. By setting the discharge start voltage (450V) lower than the voltage (600V) for operating the suppressing unit 6B, the surge absorber SA can be operated reliably.
Furthermore, since the surge absorber SA has a large ability to absorb instantaneous power (power withstand capability), it is difficult to be destroyed by the instantaneous power.

FIG. 11 is a diagram illustrating an example of the overvoltage detection circuit 61 in the suppressing unit 6B of the inverter circuit 100 to which the second embodiment is applied.
In the following, the same parts as those of the inverter circuit 100 to which the second embodiment shown in FIG. 10 is applied are denoted by the same reference numerals and description thereof is omitted, and the overvoltage detection circuit 61 of the suppressing unit 6B which is a different part. Will be explained.

The overvoltage detection circuit 61 includes resistors R1, R2, R3, R4, a differential amplifier Op, a pnp bipolar transistor Tr, and a reference power supply Vref.
The resistor R1 and the resistor R2 are connected in series, and are connected between the DC link 4 and the common potential line 5.
The pnp bipolar transistor Tr, the resistor R3, and the resistor R4 are connected in series in this order, and are connected between the drive power supply Vdd and the common potential line 5.

The differential amplifier Op includes a + input terminal, a − input terminal, and an output terminal, and outputs a voltage corresponding to the difference between the voltage at the + input terminal and the voltage at the − input terminal from the output terminal. Here, the + input terminal of the differential amplifier Op is connected to a connection point between the resistor R1 and the resistor R2, and the − input terminal is connected to one terminal of the reference power supply Vref. The output terminal of the differential amplifier Op is connected to the base terminal of the pnp bipolar transistor Tr.
The other terminal of the reference power supply Vref is connected to the common potential line 5.
The voltage of the drive power supply Vdd is, for example, DC 15V. The drive power supply Vdd is also used as a power supply for driving the differential amplifier Op.
The voltage of the reference power supply Vref is, for example, DC 2.5V.

The operation of the overvoltage detection circuit 61 will be described.
The voltage of the DC link 4 is divided by the resistor R1 and the resistor R2. The divided voltage is input to the + input terminal of the differential amplifier Op. Then, the differential amplifier Op compares the divided voltage of the DC link 4 that is the voltage of the + input terminal with the voltage of the reference power supply Vref that is the voltage of the − input terminal. That is, the detection voltage of the overvoltage detection circuit 61 is set as a voltage divided by the resistor R1 and the resistor R2.

  First, a case where the voltage of the DC link 4 is equal to or lower than the detection voltage, that is, a case where the inverter circuit 100 is in a normal state will be described. In this case, the voltage divided by the resistors R1 and R2 (the voltage at the + input terminal of the differential amplifier Op) is equal to or lower than the voltage of the reference power supply Vref (the voltage at the −input terminal of the differential amplifier Op). Then, the differential amplifier Op outputs a voltage for maintaining the pnp bipolar transistor Tr in the off state from the output terminal. When the pnp bipolar transistor Tr is in the OFF state, the control gate Gc of the control switch element Sc becomes the potential of the common potential line 5 (common potential). Therefore, the control switch element Sc is in the off state, and the surge absorber SA is in the off state.

  On the other hand, a case where the voltage of the DC link 4 exceeds the detection voltage, that is, a case where the inverter circuit 100 is in an abnormal state will be described. In this case, the voltage divided by the resistors R1 and R2 (the voltage at the + input terminal of the differential amplifier Op) exceeds the voltage of the reference power supply Vref (the voltage at the −input terminal of the differential amplifier Op). Then, the differential amplifier Op outputs a voltage for shifting the pnp bipolar transistor Tr from the off state to the on state from the output terminal. As a result, the pnp bipolar transistor Tr shifts from the off state to the on state. Then, the control gate Gc of the control switch element Sc becomes a voltage obtained by dividing the voltage of the drive power supply Vdd by the resistor R3 and the resistor R4. The divided voltage is set to be a voltage that shifts the control switch element Sc from the off state to the on state. Therefore, the control switch element Sc shifts from the off state to the on state, and the surge absorber SA shifts from the off state to the on state. Then, a current flows from the DC link 4 toward the common potential line 5. As a result, the voltage of the DC link 4 decreases.

  When the voltage of the DC link 4 becomes equal to or lower than the detection voltage, the voltage divided by the resistor R1 and the resistor R2 of the DC link 4 (the voltage at the + input terminal of the differential amplifier Op) is the voltage of the reference power supply Vref. Reduced to: Then, the output terminal of the differential amplifier Op shifts to a voltage that shifts the pnp bipolar transistor Tr from the on state to the off state. As a result, the pnp bipolar transistor Tr shifts from the on state to the off state. Then, the control gate Gc shifts to a voltage that shifts the control switch element Sc from the on state to the off state. Therefore, the control switch element Sc shifts from the on state to the off state, and the surge absorber SA shifts from the on state to the off state.

  In this overvoltage detection circuit 61, high-voltage components are required for the resistors R1 and R2 that divide the voltage of the DC link 4. However, low-voltage general-purpose components can be used for the differential amplifier Op, the pnp bipolar transistor Tr, and the resistors R3 and R4. For the control switch element Sc, general-purpose components having a low withstand voltage can be used. Therefore, the inverter circuit 100 can be manufactured at low cost.

  The overvoltage detection circuit 61 using the differential amplifier Op has been described above. The overvoltage detection circuit 61 may have another configuration, and a circuit called a shunt regulator may be used.

FIG. 12 is a diagram illustrating an example of a voltage of the DC link 4 in the inverter circuit 100 to which the second embodiment is applied. The upper part of FIG. 12 shows the relationship between the voltage of the DC link 4 (DC link voltage) and time, and the lower part of FIG. 12 shows the relationship between the voltage of the control gate Gc (gate voltage) and time.
In FIG. 12, the emergency stop of the motor M has occurred at 12 ms. Thereafter, the DC link voltage once suddenly decreases but then increases due to the induced electromotive current. When the DC link voltage exceeds 800 V (at 24 ms), the overvoltage detection circuit 61 is activated. The overvoltage detection circuit 61 applies a voltage that shifts the control switch element Sc from the off state to the on state to the control gate Gc. Thereby, the control switch element Sc shifts from the off state to the on state, and the surge absorber SA also shifts from the off state to the on state. Then, a current flows from the DC link 4 to the common potential line 5 through the surge absorber SA and the control switch element Sc, and the DC link voltage decreases.
When the DC link voltage decreases (at the time of 25 ms), the overvoltage detection circuit 61 applies a voltage that shifts the control switch element Sc from the on state to the off state to the control gate Gc. Thereby, the control switch element Sc shifts from the on state to the off state, and the surge absorber SA also shifts from the on state to the off state.
In this case, the maximum value of the DC link voltage was 840V.

FIG. 13 is a diagram illustrating an example of the voltage of the DC link 4 in the inverter circuit 100 to which the second embodiment is not applied. The inverter circuit 100 to which the second embodiment is not applied does not include the suppressing unit 6B in the inverter circuit 100 illustrated in FIG. 10 (FIG. 11).
Similar to FIG. 12, the emergency stop of the motor M occurs at 12 ms. Thereafter, the DC link voltage once suddenly decreases but then increases due to the induced electromotive current. The maximum value reached 916V.

As described above, the suppressing unit 6B of the inverter circuit 100 to which the second embodiment is applied suppresses the occurrence of overvoltage of the DC link 4. Therefore, the failure of the inverter circuit 100 due to destruction of the switching element St or the like of the inverter unit 3 in the inverter circuit 100 exceeding the breakdown voltage is suppressed.
Note that the second embodiment may be used in combination with the first embodiment.

[Third Embodiment]
The suppression unit 6 </ b> A of the inverter circuit 100 in the first embodiment and the suppression unit 6 </ b> B of the inverter circuit 100 in the second embodiment suppressed the occurrence of overvoltage of the DC link 4.
The suppression unit 6 of the inverter circuit 100 in the third embodiment suppresses an overcurrent generated by an inrush current flowing into the smoothing capacitor Cs when the inverter circuit 100 is powered on.
Moreover, the suppression part 6 of the inverter circuit 100 in 3rd Embodiment suppresses the harmonic current in power supply current.

FIG. 14 is a diagram illustrating an example of the inverter circuit 100 to which the third embodiment is applied.
The inverter circuit 100 in the third embodiment includes a suppression unit 6C as the suppression unit 6 in FIG. The same parts as those of the inverter circuit 100 to which the first embodiment shown in FIG. 1 is applied are denoted by the same reference numerals, description thereof is omitted, and a suppressing part 6C which is a different part will be described.
The three-phase AC power source PS is a three-phase four-wire system, and the three phases are denoted as R phase, S phase, T phase, and the neutral point (neutral line) as N phase. Further, the six rectifying diodes Dc of the rectifying unit 1 are expressed as rectifying diodes Dc1 to Dc6.

The suppression unit 6C of the inverter circuit 100 according to the third embodiment includes capacitors C1 and C2, switches Sw1, Sw2, and Sw3, and a current limiting resistor R5.
Capacitors C1 and C2 are connected in series to form a series circuit, with one terminal connected to DC link 4 and the other terminal connected to common potential line 5. The connection point between the capacitors C1 and C2 is connected to one terminal of the current limiting resistor R5. The other terminal of the current limiting resistor R5 is connected to one terminal of the switch Sw1, and the other terminal of the switch Sw1 is connected to the N phase of the three-phase AC power source PS.
A switch Sw2 is provided between the S phase of the three-phase alternating current and the rectifying unit 1, and a switch Sw3 is provided between the T phase and the rectifying unit 1.
As an example, the line voltage of the three-phase AC power source PS is 400 V, the smoothing capacitor Cs has a capacitance of 40 μF, and the capacitors C1 and C2 each have a capacitance of 0.22 μF. The resistance value of the current limiting resistor R5 is 800Ω.
Here, the switch Sw1 is an example of the second switch, and the switches Sw2 and Sw3 are examples of the first switch.

<Suppression of overcurrent caused by inrush current>
The suppression of the overcurrent generated by the inrush current in the inverter circuit 100 to which the third embodiment is applied will be described.
When power is supplied to the inverter circuit 100, the switch Sw1 is closed (on) and the switches Sw2 and Sw3 are opened (off). Then, the three-phase AC power supply PS is turned on.
Then, the capacitors C1 and C2 are charged via the R phase of the three-phase AC power source PS. That is, when the R phase is a positive phase, the capacitor C1 is charged via the rectifier diode Dc1. On the other hand, when the R phase is a negative phase, the capacitor C2 is charged via the rectifier diode Dc2. That is, when the R phase is a positive phase, since the rectifier diode Dc2 is connected in the reverse direction, only the capacitor C1 can be seen from the R phase of the three-phase AC power supply PS. Conversely, when the R phase is a negative phase, since the rectifier diode Dc1 is connected in the reverse direction, only the capacitor C2 can be seen from the R phase of the three-phase AC power supply PS.
When the capacitor C1 is charged, the smoothing capacitor Cs is charged by the charge accumulated in the capacitor C2. Conversely, when the capacitor C2 is being charged, the smoothing capacitor Cs is charged by the electric charge accumulated in the capacitor C1.

After the smoothing capacitor Cs is charged to a predetermined voltage, the switch Sw1 is opened (off) and the switches Sw2 and Sw3 are closed (on).
Note that the switch Sw1 may be opened (off) and the switches Sw2 and Sw3 may be closed (on) after a predetermined time has elapsed since the three-phase AC power supply PS is turned on.
Thereby, the inverter circuit 100 shifts to a normal operation state.

In the inverter circuit 100 to which the third embodiment is applied, the capacitors C1 and C2 are alternately charged by the R phase of the three-phase AC power supply PS. Then, the smoothing capacitor Cs is gradually charged by the charges accumulated in the charged capacitors C1 and C2. By repeating this, the smoothing capacitor Cs is charged.
That is, the circuit constituted by the switch Sw1 and the current limiting resistor R5 is a charging circuit.

  On the other hand, when the inverter circuit 100 does not include the suppression unit 6C, when the three-phase AC power supply PS is turned on, a current for charging the smoothing capacitor Cs flows. This current is called inrush current, and is larger as the capacitance of the smoothing capacitor Cs is larger. If the inrush current is large, the rectifier diode Dc of the rectifier 1 may be destroyed. Therefore, it is required to suppress a current that may destroy the rectifying diode Dc of the rectifying unit 1 as an overcurrent.

  On the other hand, in the inverter circuit 100 in the third embodiment, the capacitances of the capacitors C1 and C2 are set smaller than the capacitance of the smoothing capacitor Cs. A current limiting resistor R5 is provided. As a result, the inrush current that flows into the inverter circuit 100 from the R phase of the three-phase AC power source PS is kept small. Therefore, the rectifier diode Dc of the rectifying unit 1 is prevented from being destroyed by an overcurrent, and thereby the inverter circuit 100 is prevented from being damaged.

  Instead of the capacitors C1 and C2, a smoothing capacitor Cs can be considered as a series circuit of two capacitors. However, the capacitance of each of the two capacitors is twice that of the smoothing capacitor Cs, resulting in an increase in size. In addition, a large inrush current flows through each of the two capacitors from the R phase of the three-phase AC power supply PS.

Furthermore, when the line voltage is 400V, the three-phase AC power supply PS is 230V between the N phase, the R phase, the S phase, and the T phase. Therefore, an inexpensive and small relay widely used in the 200V system can be applied to the switches Sw1, Sw2 and Sw3, not an expensive and large relay corresponding to 400V. Therefore, the inverter circuit 100 can be made inexpensive and small.
Further, since the capacitors C1 and C2 having small capacitances are used as compared with the case where the smoothing capacitor Cs is a series circuit of two capacitors, the inverter circuit 100 can be made small.

<Suppression of harmonic current>
It has been described that the inverter circuit 100 to which the first embodiment is applied can suppress the harmonic current in the power supply current.
It will be described that the harmonic current in the power supply current is suppressed even in the inverter circuit 100 to which the third embodiment is applied. The series circuit of the capacitors C1 and C2 in the suppression unit 6C of the inverter circuit 100 is provided in parallel with the smoothing capacitor Cs. Therefore, the capacitors C1 and C2 also function as smoothing capacitors like the smoothing capacitor Cs.

FIG. 15 is a diagram showing a power supply current for the inverter circuit 100 to which the third embodiment is applied. FIG. 15A is a power supply current for the inverter circuit 100 to which the third embodiment is applied, and FIG. 15B is a power supply current for the inverter circuit 100 to which the third embodiment is not applied.
The inverter circuit 100 to which the third embodiment of FIG. 15A is applied is the inverter circuit 100 shown in FIG. Here, the capacitance of the smoothing capacitor Cs is 10 μF, and the capacitances of the capacitors C1 and C2 are each 20 μF. That is, the total capacitance of the smoothing capacitor Cs and the capacitors C1 and C2 is 20 μF. The current limiting resistor R5 is 25Ω.
On the other hand, the inverter circuit 100 to which the third embodiment of FIG. 15B is not applied is obtained by removing the suppressing unit 6C from the inverter circuit 100 shown in FIG. The capacitance of the smoothing capacitor Cs is 20 μF.
That is, the capacitance in the DC link 4 is the same at 20 μF in any case.
The inverter circuit 100 to which the third embodiment is applied and the inverter circuit 100 to which the third embodiment is not applied include a DC reactor between the rectifying unit 1 and the suppressing unit 6. The reactance of this DC reactor is 75 μH.

  Comparing the power supply current in FIG. 15A and the power supply current in FIG. 15B, the fluctuation in the amplitude of the power supply current is smaller in FIG. 15A than in FIG. 15B.

  Table 2 shows a value (Ih / Iref) obtained by dividing the harmonic current spectrum amplitude Ih by the current spectrum amplitude Iref at the power supply frequency (h = 1). Here, an inverter circuit 100 to which the third embodiment is applied and an inverter circuit 100 to which the third embodiment is not applied are shown. Table 2 also shows THC and PWHC.

The inverter circuit 100 to which the third embodiment is applied has improved I5 / Iref, I11 / Iref, and I13 / Iref compared to the inverter circuit 100 to which the third embodiment is not applied. Therefore, THC and PWHC are improved.
That is, although the electrostatic capacity in the DC link 4 is the same, THC and the like are improved when the series circuit of the capacitors C1 and C2 is arranged in parallel with the smoothing capacitor Cs.

<Modification of Inverter Circuit 100 to which Third Embodiment is Applied>
Next, a modification of the inverter circuit 100 to which the third embodiment is applied will be described.
The inverter circuit 100 shown in FIG. 14 is connected to a three-phase four-wire three-phase AC power source PS. The inverter circuit 100 of the modification is connected to a three-phase three-wire three-phase AC power source PS.
FIG. 16 is a diagram illustrating a modification of the inverter circuit 100 to which the third embodiment is applied.
In the inverter circuit 100 of the modification, the switch Sw1 is connected to the S phase of the three-phase AC power source PS. And the N phase is not used.
As an example, the line voltage of the three-phase AC power supply PS is 200 V, the capacitance of the smoothing capacitor Cs is 40 μF, and the capacitances of the capacitors C1 and C2 are each 0.22 μF. The current limiting resistor R5 is 800Ω.

  When power is supplied to the inverter circuit 100, the switch Sw1 is closed (on) and the switches Sw2 and Sw3 are opened (off). Then, the three-phase AC power supply PS is turned on. Then, the capacitor C1 is charged when the line voltage between the R phase and the S phase is a positive phase, and the capacitor C2 is charged when the line voltage between the R phase and the S phase is a negative phase. The subsequent operation is the same as that of the three-phase four-wire inverter circuit 100 shown in FIG. Description is omitted.

  The switch Sw1 needs to be connected to either the S phase provided with the switch Sw2 or the T phase provided with the switch Sw3. As can be seen from FIG. 16, even when the switch Sw1 is connected to the R phase, no voltage is applied to the capacitors C1 and C2.

  Also in the modification of the inverter circuit 100 to which the third embodiment shown in FIG. 16 is applied, the suppressing unit 6 suppresses overcurrent when the inverter circuit 100 is powered on. Thereby, it is suppressed that the inverter circuit 100 fails. Moreover, the suppression part 6 suppresses the harmonic current in power supply current.

  The inverter circuit 100 to which the third embodiment is applied has been described above. The DC reactor Ldc shown in FIG. 3 may be used between the rectifying unit 1 and the suppressing unit 6 of the inverter circuit 100 to which the third embodiment shown in FIG. 14 is applied. Further, it may be used in combination with the first embodiment or the second embodiment. The same applies to a modification of the inverter circuit 100 to which the third embodiment shown in FIG. 16 is applied.

In the first to third embodiments, the load of the inverter circuit 100 is the motor M, but another load may be used. In addition, the effect is large in the case of an inductive load (a load having a large reactance element).
Furthermore, in the first to third embodiments, the three-phase case has been described. However, the inverter circuit 100 that connects a single-phase AC power supply and a load such as a single-phase motor has a suppression unit. 6A, 6B, and 6C may be applied.

  In the first to third embodiments, the inverter circuit 100 uses the elements having the reactance, capacitance, and resistance values described above, and thus can be made compact.

  In addition, various modifications and combinations of embodiments may be performed without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Rectification part, 2 ... Smoothing part, 3 ... Inverter part, 4 ... DC link, 5 ... Common potential line, 6, 6A, 6B, 6C ... Suppression part, 7 ... EMI filter, 61 ... Overvoltage detection circuit, 100 ... inverter circuit, C1, C2, Cf, Cp, Cp ... capacitor, CC ... load current source, Cs ... smoothing capacitor, Dc, Dc1-Dc6 ... rectifier diode, Df ... feedback diode, Ldc, Lf, Lp ... DC reactor, M ... Motor, Op ... Differential amplifier, PS ... Three-phase AC power supply, R1, R2, R3, R4, Rp ... Resistor, R5 ... Current limiting resistor, SA ... Surge absorber, Sc ... Control switch element, St ... Switching element , Sw1, Sw2, Sw3, Sw4 ... switch, Tr ... pnp bipolar transistor, Vdd ... drive power supply, Vref ... reference power supply

Claims (7)

A rectifier that rectifies the input AC voltage into a DC voltage;
A smoothing unit that smoothes a DC voltage output from the rectifying unit;
An inverter unit connected to a load and converting the DC voltage smoothed by the smoothing unit into an AC voltage and outputting the AC voltage;
An inverter circuit provided between the said rectification | straightening part and the said smoothing part, and the suppression part which suppresses the overvoltage or overcurrent of the DC link to which the DC voltage in the said smoothing part was applied. The rectifying unit includes one output terminal and the other output terminal connected to a common potential line that sets a common potential.
The smoothing unit includes one input terminal and the other input terminal connected to the common potential line,
The suppressor is
A DC reactor provided between the one output terminal of the rectifying unit and the one input terminal of the smoothing unit; and a series circuit of a resistor and a capacitor provided in parallel with the DC reactor. The inverter circuit according to claim 1. The smoothing unit includes one input terminal and the other input terminal connected to the common potential line,
The suppressor is
A series circuit of a surge absorber and a control switch element provided between the one input terminal of the smoothing unit and the common potential line;
2. The inverter circuit according to claim 1, further comprising an overvoltage detection unit configured to detect the overvoltage and set the control switch element to be on when the voltage of the DC link becomes an overvoltage.   The inverter circuit according to claim 3, wherein the surge absorber in the suppression unit is a varistor.   5. The inverter circuit according to claim 4, wherein the varistor, which is a surge absorber in the suppression unit, has a discharge start voltage smaller than a voltage of the DC link detected by the overvoltage detection unit as an overvoltage. The suppression unit includes a series circuit of two capacitors connected in parallel to the smoothing unit;
A first switch provided between a phase other than one phase of the input AC voltage and the rectifying unit;
The connection circuit of the two capacitors in the series circuit, and a series circuit of a current limiting resistor and a second switch connected to a neutral point of the input AC voltage. The inverter circuit according to 1. The suppression unit includes a series circuit of two capacitors connected in parallel to the smoothing unit;
A first switch provided between the rectification unit and a phase other than one phase of the input AC voltage phase;
A series circuit of a current limiting resistor and a second switch connected to a connection point of the two capacitors in the series circuit and one phase of an AC voltage provided with the first switch. The inverter circuit according to claim 1.

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