JP2015111741A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device and a ferroelectric element that are easily used in a liquid process and capable of controlling orientation.SOLUTION: A manufacturing method according to the present invention relates to a semiconductor device, comprises: source and drain electrodes; an organic semiconductor film disposed between the source electrode and the drain electrode and having a channel portion; a gate electrode; and a gate insulating film disposed between the channel portion and the gate electrode. The manufacturing method comprises the steps of: heating the channel portion to a first temperature; and forming the gate insulating film by a coating process of arranging a droplet material including an insulating polymer of a second temperature lower than the first temperature on the organic semiconductor film of the first temperature and extending the droplet material in a certain direction.

Description

  The present invention relates to a method for manufacturing a semiconductor device, a method for manufacturing a ferroelectric element, and more particularly to a film forming technique based on a solution process using a liquid material containing a polymer material.

In recent years, a solution process (liquid phase process) has attracted attention as a method for manufacturing a semiconductor element such as a thin film transistor (TFT). For example, a constituent film material of a semiconductor element is contained in a liquid material and applied by a spin coat method or an ink jet method, and then heat treatment is performed to form a film.
For example, Patent Document 1 below discloses a semiconductor element manufacturing technique using a solution process.

JP 2005-215616 A JP 2007-258282 A

The present inventor is engaged in research and development related to semiconductor elements such as TFTs, and is examining device configurations and manufacturing processes that can improve the characteristics thereof.
For example, when the gate insulating film is formed by a solution process containing an insulating polymer, as will be described in detail later, since the main chain of the polymer is randomly located, even after heat treatment, The orientation of the film was lowered.
In particular, when it is used for a gate insulating film or the like, a leakage current is generated due to an orientation component in the channel direction, which causes a deterioration in semiconductor element characteristics. Further, since the ferroelectric characteristics are greatly influenced by the orientation of the film, it is important to control the orientation in order to improve the characteristics.

The present inventors have proposed using the friction transfer method described in Patent Document 2 as a technique for aligning the direction of the main chain of the polymer.
However, the above-described friction transfer method forms a film while pressing a solid (pellet), and the problem is that the underlying film is damaged by the frictional force and the flatness is low.
Therefore, a specific aspect of the present invention aims to provide a semiconductor device and a ferroelectric element manufacturing method capable of controlling the orientation that can be easily adopted in a liquid process.

  The method of manufacturing a semiconductor device according to the present invention includes a source electrode and a drain electrode, an organic semiconductor film having a channel portion disposed between the source electrode and the drain electrode, a gate electrode, the channel portion, and the channel portion. A method of manufacturing a semiconductor device having a gate insulating film disposed between a gate electrode, a step of heating the channel portion to a first temperature, and a step of forming the organic semiconductor film at the first temperature. And a step of forming the gate insulating film by a coating step of disposing a droplet material containing an insulating polymer having a second temperature lower than the first temperature and extending in a certain direction.

According to this method, the orientation of the gate insulating film can be improved by a simple method in the solution process. This can also improve the device characteristics.
For example, the first temperature is higher than the firing temperature of the insulating polymer, and the second temperature is lower than the firing temperature of the insulating polymer. According to this method, the droplet material does not fire until the droplet material is disposed, and the droplet material starts to be fired at the heated place on the substrate side. Therefore, the gate insulating film can be made uniform and the orientation of the gate insulating film can be improved.
For example, the certain direction is a second direction that is a direction intersecting the first direction from the source electrode to the drain electrode. According to this method, the orientation of the gate insulating film can be controlled in the direction intersecting the channel length direction (the direction of movement of carriers (electrons / holes)), and the leakage current between the source and drain can be reduced.
For example, the solvent of the gate insulating film material is changed to a solvent having a high volatilization rate during the coating. According to this method, the drying speed of the liquid material can be increased.
For example, the thickness of the insulating film is adjusted by adjusting the solid content ratio of the gate insulating film material during the coating. According to this method, the film thickness can be easily adjusted.
For example, the coating may be repeated twice or more. Thus, the film can be thickened by repeatedly forming the film.
For example, the insulating polymer is a ferroelectric polymer. Thus, a ferroelectric polymer may be used. By improving the orientation, the ferroelectric properties are improved.
For example, the ferroelectric polymer is mainly composed of at least one of a copolymer P (VDF / TrFE) of vinylidene fluoride and ethylene trifluoride and a polymer PVDF of vinylidene fluoride. . Such a material has good ferroelectric characteristics and is suitable for use in the semiconductor device.

  A method of manufacturing a ferroelectric element according to the present invention is a method of manufacturing a ferroelectric element having a first electrode and a second electrode disposed via the first electrode and a ferroelectric film, A step of setting the first electrode to a first temperature; and a second polymer that includes a ferroelectric polymer on the first electrode that is set to the first temperature and that is lower than the first temperature. A second step of forming the ferroelectric film by a coating step of disposing a temperature liquid material and extending in a certain direction.

The thickness of the gate insulating film or the ferroelectric film is adjusted by adjusting the solid content concentration of the liquid material during the coating. According to this method, the film thickness can be easily adjusted.
The coating may be repeated twice or more. Thus, the film can be thickened by repeatedly forming the film.

  The ferroelectric polymer is mainly composed of at least one of a copolymer P (VDF / TrFE) of vinylidene fluoride and ethylene trifluoride and a polymer PVDF of vinylidene fluoride. Such a material has good ferroelectric characteristics and is suitable for use in the ferroelectric element.

It is process sectional drawing which shows the formation method of 1T type ferroelectric memory of this Embodiment. It is a perspective view which shows the outline of the apparatus used for the orientation method of this Embodiment. It is sectional drawing which shows the outline of the apparatus used for the orientation method of this Embodiment. It is the top view and sectional drawing for demonstrating the effect of this Embodiment typically. It is sectional drawing which shows the structural example of TFT. It is sectional drawing which shows the structural example of TFT. It is sectional drawing which shows the structural example of TFT.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same or related code | symbol is attached | subjected to what has the same function, and the repeated description is abbreviate | omitted.
<Embodiment>
FIG. 1 is a process sectional view showing a method of forming a 1T type ferroelectric memory according to the present embodiment. The 1T type means that a memory cell is composed of one TFT. In this case, the gate insulating film of the TFT is composed of a ferroelectric film.

  First, as shown in FIG. 1A, for example, a glass substrate is prepared as the substrate 2, and the surface is washed with, for example, an organic solvent and dried. In addition to glass substrates, plastic groups composed of polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyacrylate, polycarbonate (PC), polyethersulfone (PES), aromatic polyester (liquid crystal polymer), etc. A material (resin substrate), a quartz substrate, a silicon substrate, a gallium arsenide substrate, or the like may be used.

Next, as illustrated in FIG. 1B, the source electrode 3 and the drain electrode 4 are formed over the base material 2. The distance (channel length L) between the source electrode 3 and the drain electrode 4 is, for example, 35 μm, and the channel width is, for example, about 0.3 mm. These electrodes are formed by, for example, disposing a metal shadow mask having an opening in a desired region on the base 2 and depositing a conductive material. As the electrode, a laminated film of an Au (gold) film and a Cu (copper) film can be used. In addition to Au and Cu, for example, Pd, Pt, W, Ta, Mo, Al, Cr, Ti, Cu, Ni, Li, Ca, Mg, a single layer film, a laminated film thereof, or an alloy containing these The metal material may be used. The constituent materials of the source electrode 3 and the drain electrode 4 include the above metal materials, transparent conductive oxides such as ITO, FTO, ATO and SnO ₂ , carbon materials such as carbon black, carbon nanotubes and fullerenes, polyacetylene. Conductive polymer materials such as polythiophene, polypyrrole, polythiophene such as PEDOT (poly-ethylenedioxythiophene), polyaniline, poly (p-phenylene), poly (p-phenylenevinylene), polyfluorene, polycarbazole, polysilane or derivatives thereof It may be used. One or more of these can be used in combination. Alternatively, the source electrode 3 and the drain electrode 4 may be formed by depositing the material on the entire surface of the substrate 2 and then patterning the material by an etching method. Alternatively, the source electrode 3 and the drain electrode 4 may be formed by applying a liquid material containing the above-described particulate material to a desired region, and drying and baking (heat treatment).

  Next, the surface of the substrate 2 including the source electrode 3 and the drain electrode 4 is washed with, for example, an organic solvent and dried, and then, as shown in FIG. 1C, between the source electrode 3 and the drain electrode 4 (channel The semiconductor film 5 is formed on the region. The semiconductor film 5 is an organic semiconductor film. As a method for forming the semiconductor film 5, for example, an F8T2 solution as an organic semiconductor material is applied on the substrate 2 by a spin coating method, and then dried and baked. F8T2 is a derivative of a fluorene-bithiophene copolymer.

  As organic semiconductor materials, in addition to F8T2, for example, naphthalene, anthracene, tetracene, pentacene, hexacene, phthalocyanine, perylene, hydrazone, triphenylmethane, diphenylmethane, stilbene, arylvinyl, pyrazoline, triphenylamine, triarylamine, oligo Low molecular organic semiconductor materials such as thiophene, phthalocyanine or derivatives thereof, poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene, polyalkylthiophene, polyhexylthiophene, poly (p-phenylenevinylene), poly Tinylene vinylene, polyarylamine, pyrene formaldehyde resin, ethylcarbazole formaldehyde resin, fluorene-arylamine copolymer or The organic semiconductor material of a polymer such as a derivative thereof (conjugated polymer material). These may be used singly or in combination of two or more of them.

  Next, as shown in FIG. 1D, a gate insulating film (ferroelectric film) 6 is formed on the semiconductor film 5 using a die coater. Here, for example, a copolymer P (VDF / TrFE) of vinylidene fluoride and ethylene trifluoride is used as the ferroelectric polymer, and, for example, a ketone solvent is used as the organic solvent. The P (VDF / TrFE) solution 6a is applied onto the substrate 2 using a die coater, and dried and baked (heat treated) on a stage that has already been heated, and a gate insulating film (ferroelectric film) 6 is formed. The coating direction is the channel width direction, that is, the direction orthogonal to the direction from the source electrode 3 to the drain electrode 4. Processing conditions include, for example, a ferroelectric polymer concentration of 1 wt% and a coating amount of 10 μm [WET The temperature of the liquid material containing the ferroelectric polymer is about 25 ° C. which is the second temperature (room temperature), the gap between the die head and the substrate 2 is 30 μm, and the stage temperature is 120 ° C. which is the first temperature. A gate insulating film (ferroelectric film) 6 having a thickness of about 100 nm is formed at a temperature of about 100 to 140 ° C. and a stage moving speed of 5 m / min. For example, when the directions of the transistors are not all the same, the coating is performed in a direction in which the number of transistors that can be applied in the channel width direction, which is a constant direction, increases. The coating process using this die coater will be described later. As this ferroelectric polymer, for example, PVDF or a combination of these can be used in addition to P (VDF / TrFE). PVDF is a polymer of vinylidene fluoride. Such a material has good ferroelectric properties and is suitable for use as a ferroelectric film.

  Next, as shown in FIG. 1E, a gate electrode 7 is formed on the gate insulating film (ferroelectric film) 6. As a method for forming the gate electrode 7, for example, a solution in which conductive particles such as Ag (silver) are dispersed on the channel region is discharged, dried, and fired, for example, a gate having an average width of about 40 μm. The electrode 7 is formed. Through the above steps, the 1T type ferroelectric memory 1 is substantially completed.

  Hereinafter, a method for forming a gate insulating film using a die coater will be described in detail with reference to FIGS. 2 and 3 are a perspective view and a cross-sectional view showing an outline of an apparatus used for forming a gate insulating film using a die coater. As shown in FIG. 2, the base material 2 is mounted on a stage 20 with a built-in heater. At this time, the stage which is already a heating means is heated to 120 degrees. The stage temperature is set higher than the firing temperature of the P (VDF / TrFE) solution 6a.

  Next, the P (VDF / TrFE) solution 6a is discharged from the die head, and the stage on which the base material 2 is mounted in a state where the discharged liquid material connects the base material and the die head discharge portion, the channel width direction, that is, Film formation (drying and firing) is performed while moving in a direction (y direction in the figure) perpendicular to the direction from the source electrode 3 to the drain electrode 4. The temperature of the P (VDF / TrFE) solution 6a discharged from the die head is lower than the temperature of the surface of the substrate 2 on which the P (VDF / TrFE) solution 6a is applied, for example, about 25 ° C. (room temperature). / TrFE) Set lower than the firing temperature of the solution 6a. The shape of the die head 10 can be changed as appropriate.

  As described above, according to the present embodiment, in the solution process using the insulating polymer, the thin film is dried and baked while being applied while the discharged liquid material is connected to the base and the die head discharge portion. Since the liquid material starts to solidify when heated on the substrate side, the main chain of the insulating polymer is aligned in the coating direction due to the force of extending the liquid in one direction, and the orientation is good A film can be formed.

  In particular, by applying in a direction that intersects (preferably orthogonally) the channel direction, an orientation plane (crystal plane) can be formed in the direction intersecting the channel, and a leakage current between the source and drain electrodes ( Off current) can be reduced.

  Further, as long as the discharge unit or the stage moves in a state where the stage can be heated, the liquid is discharged, and the liquid is connected between the discharge unit and the base material, it is not limited to the die coater.

  FIG. 4 is a plan view (left view) and a cross-sectional view (right view) for schematically explaining the effect of the present embodiment. As shown in FIG. 4A, the alignment (orientation) of the main chain 9 of the insulating polymer can be improved. For example, P (VDF / TrFE) is a polar molecule having a permanent dipole moment, and the dipole moment is a vector from the fluorine side to the hydrogen side across a molecular chain composed of a single bond of carbon. Therefore, by the above coating, crystallization is performed while maintaining the crystal plane in the direction perpendicular to the substrate surface (that is, the thickness direction of the substrate) while aligning the vector direction of the dipole moment of P (VDF / TrFE). Is possible. As a result, it is possible to form a film in which the b-axis is preferentially oriented at (010) perpendicular to the substrate surface.

On the other hand, as shown in FIG. 4 (B), when baking is performed in a separate process after coating, the direction of the main chain 9 of the insulating polymer is not fixed and becomes random. The orientation of the film tends to deteriorate, and mixed orientation tends to occur. Furthermore, in a film forming method in which baking is performed after application by a spin coating method, the surface energy is the smallest and the orientation is likely to be stable (110) or (100).
As described above, the crystal plane orientation of the ferroelectric film whose characteristics are greatly influenced by the crystallinity can be controlled, the polarization amount and the hysteresis characteristics can be improved, and the memory characteristics can be improved.

  In addition, according to the orientation method in which coating is performed by a die coater on the heated substrate of the present embodiment, by increasing the coating amount, a thick film can be secured, and conversely, the coating amount By reducing the thickness, the film thickness can be controlled by the coating amount, such as reducing the film thickness. Further, finer film thickness control can be performed by adjusting the solid content concentration of the insulating polymer. Next, when the film thickness is large and it takes time until firing, and the alignment (orientation) of the main chain of the insulating polymer is lowered, the thin film coating (10 nm to 30 nm) treatment is repeated twice or more. It may be thicker. As described above, the coating amount, the solid content concentration of the insulating polymer, and the orientation thereof may be adjusted depending on the type of the insulating polymer, and the film may be formed under conditions that provide good film characteristics. In addition, you may adjust the speed | rate and temperature of the base material 2 not only the said coating.

  In addition, according to the orientation method in which coating is performed by the die coater of the present embodiment, it is not necessary to use pellets as in the above-described friction transfer method, and coating parameters (coating amount, coating amount are determined based on frictional force). The process speed, gap, temperature, and gate insulating film solid content concentration are more easily adjusted, and a film having better flatness than the film formed by the friction transfer method can be formed. In addition, damage to an underlying film (for example, an electrode) due to frictional force (stress) can be reduced, and it can be used for devices having various structures. In addition, occurrence of pinholes and spikes can be suppressed, thinning is easy, and low voltage driving is also possible.

  The operation of the 1T type ferroelectric memory will be described below. The semiconductor film 5 is p-type. When writing to the ferroelectric memory 1, first, between the source electrode 3 (and the drain electrode 4) and the gate electrode 7 with the source electrode 3 and the drain electrode 4 kept at the same potential. A voltage Vwrite higher than the coercive voltage of the gate ferroelectric is applied. When the voltage Vwrite is a negative voltage with respect to the source electrode 3 (and the drain electrode 4), holes are induced (aggregated) in the vicinity of the interface between the semiconductor film 5 and the gate insulating film (ferroelectric film) 6. ) State. That is, the transistor is turned on. Even when the application of the voltage Vwrite is stopped and the writing is completed, the polarization state of the gate insulating film (ferroelectric film) 6 is maintained, so that the on state of the transistor is maintained.

  On the other hand, when the voltage Vwrite is a positive voltage with respect to the source electrode 3 (and the drain electrode 4), no hole is induced in the vicinity of the interface between the semiconductor film 5 and the gate insulating film (ferroelectric film) 6. Become. That is, the transistor is turned off. Even when the application of the voltage Vwrite is stopped and the writing is finished, the polarization state of the gate insulating film (ferroelectric film) is maintained, so that the off state of the transistor is maintained.

When reading (reproducing) the information written by writing as described above, a read voltage Vread (Vds) is applied between the source electrode 3 and the drain electrode 4 so that the source electrode 3 and the drain electrode 4 A current Iread (Ids) flowing between the two is detected.
If a negative voltage is applied to the gate electrode at the time of writing, carriers (h: holes in this embodiment) are induced in the channel region 51 at this time, and therefore, between the source electrode 3 and the drain electrode 4. A very large current Iread flows.

On the other hand, if a positive voltage is applied to the gate electrode during writing, carriers (h: holes in this embodiment) are not induced in the channel region 51 at this time, so that the source electrode 3 and the drain electrode 4 Almost no current Iread flows during this period.
By detecting this Iread difference, this element functions as a non-volatile memory. However, in such reading, no voltage is applied between the source electrode 3 (and the drain electrode 4) and the gate electrode 7, The polarization state of the gate insulating film (ferroelectric film) 6 does not change. Therefore, the ferroelectric memory 1 can perform nondestructive reading (NDRO), and basically can be read any number of times.

  As described above, according to the present embodiment, the film characteristics of the gate insulating film (ferroelectric film) 6 can be improved, so that the writing and reading characteristics can be improved.

  In this embodiment, the 1T type ferroelectric memory is described as an example of the semiconductor device, but the present invention can also be applied to a normal TFT using a paraelectric material. In this case, this embodiment is the same as the present embodiment except that a paraelectric polymer (insulating polymer) is used instead of the ferroelectric polymer. As the polymer, for example, polyvinylphenol can be used. Even in such a TFT, the off-current can be reduced by adjusting the orientation by using an orientation method in which baking is performed while coating with a die coater. In this embodiment, the TFT in which the semiconductor film 5 is disposed over the source electrode 3 and the drain electrode 4 (FIG. 1E) has been described as an example. However, the present invention can also be applied to TFTs having other configurations. is there. 5 to 7 are cross-sectional views showing structural examples of TFTs. As shown in FIG. 5, the source electrode 3 and the drain electrode 4 may be disposed on the semiconductor film 5. Further, as shown in FIG. 6, a bottom gate-top contact structure may be adopted, and as shown in FIG. 7, a bottom gate-bottom contact structure may be adopted. In any TFT, the gate insulating film (ferroelectric film) 6 is formed by an orientation method in which the gate insulating film (ferroelectric film) 6 is baked while being coated with a die coater. In addition, the same code | symbol is attached | subjected to the location which has the same function as FIG.

The present invention is also applicable to a ferroelectric memory having a ferroelectric capacitor (ferroelectric element) such as a 1T1C type or a 2T2C type. That is, when forming a ferroelectric film sandwiched between two electrodes, alignment is performed by using an alignment method in which baking is performed while coating with a die coater in the same manner as the gate insulating film (ferroelectric film) 6. The ferroelectric characteristics can be improved by adjusting.
In this embodiment, the gate insulating film is described as an example. However, for example, the gate insulating film may be used when forming the organic semiconductor film. Further, it can be widely applied not only to TFTs and ferroelectric capacitors but also to devices having a film forming process using a solution containing a polymer.

Examples according to the present inventors will be described in detail below.
(Example)
(Sample A)
In the above process, the ferroelectric polymer concentration is 1 wt%, the coating amount is 10 μm [WET], the gap between the die head and the substrate 2 is 30 μm, the stage temperature is about 120 ° C. Then, a gate insulating film (ferroelectric film) 6 having a thickness of about 100 nm was formed.
(Sample B)
In the above process, the P (VDF / TrFE) solution was changed to polyvinylphenol to form a paraelectric gate insulating film 6. The processing conditions are the same as in sample A above.
(Comparative sample C)
Using a P (VDF / TrFE) solution, the coating film was directly dried and baked after coating without performing baking while coating.
(Sample D for comparison)
Using a polyvinylphenol solution, the coating film was directly dried and baked after coating without performing baking while coating.

Regarding the TFT (semiconductor device) using the samples A to D, a potential of −5 V was applied to the drain electrode 4 with respect to the source electrode 3, and a potential of +20 V was applied to the gate electrode with respect to the source electrode 3. The off-state current was measured. Each sample was measured and the average value of off current was measured.
As a result, the effect of reducing the off current (leakage current) was confirmed in the case where the coating was performed on the heated substrate.
In addition, in the TFT shown in FIGS. 5 to 7, the effect of reducing the off-current (leakage current) has been confirmed by the experiments of the present inventors.

The ferroelectric memory can be incorporated into various electronic devices. Although there is no particular limitation on the electronic device, for example, it can be incorporated in any device that requires a storage device, such as a general computer device equipped with the above memory, a mobile phone, a PHS, a PDA, an electronic notebook, and an IC card.
The TFT can be incorporated in various electro-optical devices (electronic devices) as, for example, a pixel transistor of a liquid crystal device or a driving transistor constituting a driving circuit.
In this way, by incorporating various devices formed using an orientation method in which baking is performed while coating with the die coater of the present embodiment into an electronic device, its characteristics are improved and productivity is also improved. Can do.

  It should be noted that the examples and application examples described through the above-described embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements. The present invention is described in the description of the above-described embodiments. It is not limited.

  DESCRIPTION OF SYMBOLS 1 ... Ferroelectric memory, 2 ... Base material, 3 ... Source electrode, 4 ... Drain electrode, 5 ... Semiconductor film 51 ... Channel region, 6 ... Gate insulating film, 6 '... Gate insulating film (conventional), 6a ... P (VDF / TrFE) solution, 7 ... gate electrode, 9 ... main chain of insulating polymer, 11 ... die head, 20 ... stage, L ... channel length.

A semiconductor device according to the present invention includes a source electrode, a drain electrode, an organic semiconductor film having a channel portion, a gate electrode, the channel portion, and the gate electrode, disposed between the source electrode and the drain electrode. The gate insulating film is a ferroelectric film formed of a plurality of layers.
In the above semiconductor device, the gate insulating film includes a main chain of an insulating polymer, and the main chain of the insulating polymer is in a direction intersecting a moving direction of carriers between the source electrode and the drain electrode. It is preferably oriented.
In the above semiconductor device, the insulating polymer is preferably a ferroelectric polymer.
In the above semiconductor device, the ferroelectric polymer is mainly composed of at least one of a copolymer P (VDF / TrFE) of vinylidene fluoride and ethylene trifluoride and a polymer PVDF of vinylidene fluoride. It is preferable that
The method of manufacturing a semiconductor device according to the present invention includes a source electrode and a drain electrode, an organic semiconductor film having a channel portion disposed between the source electrode and the drain electrode, a gate electrode, the channel portion, and the channel portion. A method of manufacturing a semiconductor device having a gate insulating film disposed between a gate electrode, a step of heating the channel portion to a first temperature, and a step of forming the organic semiconductor film at the first temperature. And a step of forming the gate insulating film by a coating step of disposing a droplet material containing an insulating polymer having a second temperature lower than the first temperature and extending in a certain direction.

Claims (11)

A source electrode and a drain electrode;
An organic semiconductor film disposed between the source electrode and the drain electrode and having a channel portion;
A gate electrode;
A method for manufacturing a semiconductor device, comprising: a gate insulating film disposed between the channel portion and the gate electrode;
Heating the channel portion to a first temperature;
The gate insulating film is formed by a coating process in which a droplet material containing an insulating polymer having a second temperature lower than the first temperature is disposed on the organic semiconductor film having the first temperature and extends in a certain direction. Forming, and
A method for manufacturing a semiconductor device, comprising: The first temperature is higher than the firing temperature of the insulating polymer,
The method for manufacturing a semiconductor device according to claim 1, wherein the second temperature is lower than a firing temperature of the insulating polymer.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the certain direction is a second direction that is a direction intersecting with the first direction from the source electrode to the drain electrode.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the gate insulating film is adjusted by adjusting a solid content concentration of the liquid material during the coating. 5. .   5. The method of manufacturing a semiconductor device according to claim 1, wherein the coating is repeated twice or more.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating polymer is a ferroelectric polymer.   The ferroelectric polymer is mainly composed of at least one of a copolymer P (VDF / TrFE) of vinylidene fluoride and ethylene trifluoride and a polymer PVDF of vinylidene fluoride. 6. A method for manufacturing a semiconductor device according to 6. A method of manufacturing a ferroelectric element having a first electrode and a second electrode disposed via the first electrode and a ferroelectric film,
A step of setting the first electrode to a first temperature; and a second polymer that includes a ferroelectric polymer on the first electrode that is set to the first temperature and that is lower than the first temperature. And a second step of forming the ferroelectric film by a coating step of disposing a liquid material at a temperature and extending in a certain direction.   10. The method for manufacturing a ferroelectric element according to claim 8, wherein the film thickness of the ferroelectric film is adjusted by adjusting a solid content concentration of the liquid material during the coating.   10. The method for manufacturing a ferroelectric element according to claim 8, wherein the coating is repeated twice or more.   The ferroelectric polymer is mainly composed of at least one of a copolymer P (VDF / TrFE) of vinylidene fluoride and ethylene trifluoride and a polymer PVDF of vinylidene fluoride. The method for manufacturing a ferroelectric element according to claim 8.

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