JP2015111719A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device comprising an ESD protection diode which has high ESD resistance and a small ineffective area.SOLUTION: According to an embodiment, a semiconductor device comprises: a semiconductor substrate; a semiconductor layer which is provided on the semiconductor substrate via an insulating film and extends to a first direction along an outer edge of the semiconductor substrate; a first electrode; and a second electrode. The semiconductor layer is provided in parallel to a second direction which is perpendicular to the first direction, and includes: a plurality of first-conductivity-type first semiconductor regions extending to the first direction; and a second-conductivity-type second semiconductor region which is disposed between adjacent ones of the first semiconductor regions and extends to the first direction. The width of the second semiconductor region in the second direction is larger than the thickness of the semiconductor layer in the direction perpendicular to the semiconductor substrate. The first electrode is provided on one of the plurality of first semiconductor regions, which is positioned at one end. The second electrode is provided on one of the plurality of first semiconductor regions, which is positioned at the other end.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with an ESD protection diode.

With the recent trend toward high-speed and large-capacity information, technical demands for miniaturization and high-frequency operation of electronic elements are increasing. As a result, the demand for improving ESD (electrostatic breakdown) resistance of electronic elements is also increasing rapidly. Even in a small high-speed switching element used for a portable device or the like, or a MOS transistor widely used for a voltage converter circuit or the like, there is a concern that the ESD tolerance is lowered due to the miniaturization of the element or the thinning of the gate oxide film.
In such an element, an ESD protection diode is often simultaneously formed on a silicon substrate. In particular, a protection element using polycrystalline silicon has a high degree of freedom in the element manufacturing process and is widely used.

  Conventionally, since the ESD protection diode is provided in a ring-shaped closed annular structure, the area of the central portion becomes an ineffective area. Therefore, if the junction area of the protection diode is increased in order to obtain a large ESD tolerance, the reactive area increases and the area of the entire element increases.

  Therefore, there is a proposal to provide a high-breakdown-voltage protection diode by connecting in series a ring-shaped protection diode formed on the outer periphery of the chip and a ring-shaped protection diode formed on the outer periphery of the electrode pad (for example, Patent Document 1).

JP 2000-294778 A

  The present invention provides a semiconductor device including an ESD protection diode having a large ESD tolerance and a small ineffective area.

  According to the embodiment, a semiconductor device includes a semiconductor substrate, a semiconductor layer provided on the semiconductor substrate via an insulating film, extending in a first direction along an outer edge of the semiconductor substrate, a first electrode, And a second electrode. The semiconductor layer includes a plurality of first conductivity type first semiconductor regions extending in the first direction and a second conductivity type second semiconductor region extending in the first direction. The plurality of first semiconductor regions are arranged in a second direction along the semiconductor substrate in a second direction orthogonal to the first direction, and the second semiconductor region is the plurality of first semiconductors. Disposed between adjacent first semiconductor regions in the region. The second semiconductor region has a width in the second direction wider than a thickness of the semiconductor layer in a direction perpendicular to the semiconductor substrate. The first electrode is provided on a first semiconductor region located at one end of the plurality of first semiconductor regions. The second electrode is provided on a first semiconductor region located at the other end of the plurality of first semiconductor regions.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device provided with the ESD protection diode with a large ESD tolerance and a small invalid area is provided.

1 is a schematic plan view illustrating the configuration of a semiconductor device according to an embodiment of the invention. FIG. 2 is a cross-sectional view of the semiconductor device illustrated in FIG. FIG. 2 is a graph of calculated values of current density of the semiconductor device illustrated in FIG. 1. It is a typical top view of the semiconductor device of a comparative example. FIG. 10 is a schematic plan view illustrating another configuration of the semiconductor device according to the embodiment of the invention. FIG. 10 is a schematic plan view illustrating another configuration of the semiconductor device according to the embodiment of the invention. FIG. 7 is a cross-sectional view taken along line AA of the semiconductor device illustrated in FIG. 6.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
The drawings are schematic or conceptual, and the shape of each part, the relationship between vertical and horizontal dimensions, the size ratio between the parts, and the like are not necessarily the same as the actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

FIG. 1 is a schematic plan view illustrating the configuration of a semiconductor device according to an embodiment of the invention.
FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.
As shown in FIGS. 1 and 2, the semiconductor device 60 of this example includes a semiconductor substrate 5, an insulating film 17, a semiconductor region 50, and first and second electrodes 20 and 21.

  A semiconductor region 50 is provided on the semiconductor substrate 5 via an insulating film 17. In the present embodiment, the case where the semiconductor region 50 has a strip shape is illustrated. In the semiconductor region 50, N-type semiconductor regions 18a, 18b, 18c and P-type semiconductor regions 19a, 19b are alternately formed in stripes up to the end face Q (side wall). That is, the PN junction between the N-type semiconductor regions 18 a, 18 b and 18 c and the P-type semiconductor regions 19 a and 19 b is exposed at the end face Q (side wall) of the semiconductor region 50. The electrodes 20 and 21 are provided apart from the end face Q.

  The P-type semiconductor region 19a and the N-type semiconductor region 18a constitute a protection diode 28a. Similarly, the P-type semiconductor region 19b and the N-type semiconductor region 18b constitute a protection diode 28b. The P-type semiconductor region 19a and the N-type semiconductor region 18b constitute a protection diode 29a, and the P-type semiconductor region 19b and the N-type semiconductor region 18c constitute a protection diode 29b.

In the semiconductor region 50, a plurality of protective diodes 28a, 29a, 28b, and 29b connected in anti-series with an NPNPN structure are formed.
Further, the first electrode 20 and the second electrode 21 are connected to the N-type semiconductor regions 18 a and 18 c of the semiconductor region 50, respectively. The overvoltage applied to the first electrode 20 and the second electrode 21 causes the protection diodes 28a, 29a, 28b, 29b having an NPNPN structure to break down and a current flows.
Note that, as will be described later with reference to FIG. 6, such a semiconductor region 50 can be integrated with another element such as a transistor. In these cases, the shape of the semiconductor region 50 is not limited to a straight belt shape as shown in FIG. 1, but may be a belt shape bent into various shapes such as an L shape and a crank shape. be able to.

Here, as shown in FIG. 1, the main surface of the semiconductor region 50 is taken as the XY plane, and the Z axis is taken in the first direction perpendicular to the XY plane. The direction of the current flowing between the first and second electrodes 20 and 21 is taken as the Y axis, and the X axis is taken perpendicular to the Y axis and the Z axis.
The interval between the first and second electrodes 20 and 21 in the Y-axis direction is Ld.

At this time, the end face Q (side wall) of the semiconductor region 50 where the PN junctions of the protection diodes 28a, 29a, 28b, and 29b are exposed is at least in the X-axis direction from the end portion P of the first and second electrodes 20 and 21. The distance Ld is formed to the outside. That is, when the distance between the end surface Q and the end portion P is Ws, the semiconductor region 50 is formed to satisfy Ws ≧ Ld.
In FIG. 1, the end face Q and the end portion P are shown only on the right side of the electrodes 20, 21 and the semiconductor region 50, but the same applies to the left side.

The semiconductor device 60 of the present embodiment can be manufactured, for example, by the following manufacturing process.
First, an oxide film (insulating film) 17 is formed on the N-type silicon substrate 5 with a film thickness of 0.5 μm, for example. A polycrystalline silicon region (semiconductor region) 50 is formed thereon with a film thickness of 0.6 μm, for example. Further, an oxide film (insulating film) 17 is formed with a film thickness of 0.1 μm, for example.

Next, boron (B) ion implantation is performed in the polycrystalline silicon region (semiconductor region) 50 at, for example, an acceleration voltage of 40 keV and a dose of 5 × 10 ¹³ cm ⁻² . The polycrystalline silicon region (semiconductor region) 50 becomes a P-type semiconductor region.
An unnecessary region of the polycrystalline silicon region (semiconductor region) 50 is removed by using, for example, a RIE (reactive ion etching) method using a photolithography technique.

An oxide film (insulating film) 17 is formed on the entire surface.
Thereafter, arsenic (As) ions are implanted into a selective region in the polycrystalline silicon region (semiconductor region) 50 by using a photolithography technique. The ion implantation is performed, for example, at an acceleration voltage of 70 keV and a dose amount of 5 × 10 ¹⁴ cm ⁻² to form N-type semiconductor regions 18a, 18b, and 18c. The regions of the polycrystalline silicon region (semiconductor region) 50 where arsenic (As) ion implantation has not been performed become P-type semiconductor regions 19a and 19b.

The heat treatment is performed, for example, in a nitrogen gas (N ₂ ) atmosphere at a temperature of 900 ° C. for a time of 20 minutes, and each region is activated.
Further, first and second electrodes 20 and 21 are formed in the N-type semiconductor regions 18a and 18c.
Further, if necessary, an electrode wiring metal with another electrode and an electrode pad are formed.

Through the above manufacturing process, the semiconductor device 60 of this embodiment shown in FIGS. 1 to 2 is manufactured.
Since the impurity diffusion due to the above ion implantation and heat treatment is about 1 to 2 μm, the minimum length of the N-type semiconductor regions 18a, 18b and 18c and the P-type semiconductor regions 19a and 19b is about 2 μm. Therefore, the minimum length of an NPN / PNP structure having three P-type or N-type semiconductor regions is 6 μm.

  In the semiconductor device 60 of the present embodiment, the lengths of the N-type semiconductor regions 18a, 18b, 18c and the P-type semiconductor regions 19a, 19b are each 4 μm, for example. Further, the distance between the first electrode 20 and the nearest P-type semiconductor region 19a and the distance between the second electrode 21 and the nearest P-type semiconductor region 19b are also each set to 4 μm, for example.

  In this case, the distance Ld between the first and second electrodes 20 and 21 in the Y-axis direction is 20 μm. In the present embodiment, the distance Ws between the end face Q (side wall) of the semiconductor region 50 where the PN junctions of the protection diodes 28a, 29a, 28b, and 29b are exposed and the end portions P of the first and second electrodes 20 and 21 are exposed. For example, it is formed in 20 micrometers.

  In this embodiment, the case where the N-type semiconductor regions 18a, 18b and 18c and the P-type semiconductor regions 19a and 19b constitute the protection diodes 28a, 29a, 28b and 29b having an NPNPN structure is illustrated. However, the present invention is not limited to this, and an arbitrary number of protection diodes can be formed by alternately forming an arbitrary number of N-type semiconductor regions and P-type semiconductor regions. A protective diode having a PNPNP structure can also be configured.

When an overvoltage is applied to the first electrode 20 and the second electrode 21 of such a semiconductor device 60, the protection diodes 28a, 29a, 28b, and 29b formed in the semiconductor region 50 break down, and the current is reduced. Flowing.
When a high voltage is applied to the first electrode 20 and a low voltage is applied to the second electrode 21, the protection diodes 28 a and 28 b break down due to the overvoltage, and the first electrode 20 toward the second electrode 21. Current flows. Conversely, when a low voltage is applied to the first electrode 20 and a high voltage is applied to the second electrode 21, the protection diodes 29 a and 29 b break down due to the overvoltage, and the second electrode 21 to the first electrode Current flows toward

FIG. 3 is a graph of the calculated current density of the semiconductor device shown in FIG.
The direction of the X axis in FIG. 3 corresponds to the direction of the X axis shown in FIG. Further, the position of the X axis in FIG. 3 is a position passing through the center in the vertical direction of the N-type semiconductor region 18b in FIG. Further, the center of the first and second electrodes 20 and 21 in the X-axis direction is taken as the origin O, and the Y-axis is set as shown in FIG. The current density in the Y direction on the X axis when current 2I was passed between the first and second electrodes 20 and 21 was taken as J.
In FIG. 3, the position X on the X-axis at this time is taken on the horizontal axis, and the calculated value of the current density J in the Y-axis direction is shown on the vertical axis.

  In the calculation of the current density J, the thickness of the semiconductor region 50 is 1 μm, and the lengths of the first and second electrodes 20 and 21 in the Y-axis direction are 6 μm. Further, the width Wd in the X-axis direction of the first and second electrodes 20 and 21 is set to 50 μm, respectively, and a current 2I = 2A is passed.

That is, the end portions P of the first and second electrodes 20 and 21 are positioned at X = ± Wd / 2 = ± 25 μm. The semiconductor device 60 is symmetrical in FIG. Therefore, in FIG. 3, the current density J in the Y-axis direction on the X-axis when the current I = 1A is passed through the portion where 0 ≦ X ≦ 25 μm is calculated.
From the symmetry, the current I flows parallel to the Y axis at X = 0. Further, on Y = 0, that is, on the X axis, the current I flows in parallel to the Y axis.

  Assuming an HBM (human body model) as ESD, if a current of 1 A flows, it corresponds to 1500 V when converted to a voltage at the HBM. In the entire semiconductor device 60, a current of 2A flows and corresponds to 3000V.

As shown in FIG. 3, the current density J at a position about 10 μm away from the end portion P of the first and second electrodes 20 and 21 is almost zero. Also, a large recombination current does not concentrate on the end face Q (side wall) of the semiconductor region 50 where the PN junctions of the protection diodes 28a, 29a, 28b, 29b are exposed.
Therefore, as will be described later, according to the semiconductor device 60 of the present embodiment, it is possible to obtain a protection diode structure having a large ESD tolerance and a small ineffective area.

Here, a semiconductor device of a comparative example will be described.
FIG. 4 is a schematic plan view of a semiconductor device of a comparative example.
As shown in FIG. 4, the semiconductor device 160 of the comparative example includes a semiconductor substrate 5, an insulating film 17, a polycrystalline silicon region 150, and first and second electrodes 120 and 121.

A cross-sectional view taken along the line AA of the semiconductor device 160 of the comparative example is the same as the cross-sectional view taken along the line AA of the semiconductor device 60 of the present embodiment illustrated in FIG.
However, in the semiconductor device 160 of the comparative example, the N-type semiconductor region 118 c is also formed in a rectangular shape inside the second electrode 121. Further, the planar shape of the polycrystalline silicon region 150 is rectangular. Further, the N-type semiconductor regions 118a, 118b, and 118c and the P-type semiconductor regions 119a and 119b have an annular structure in which the planar shapes are alternately formed in concentric rectangular shapes and the PN junctions are closed. Therefore, in the semiconductor device 160 of the comparative example, the polycrystalline silicon region 150 does not have an end face (side wall) from which the PN junction is exposed. The other points are the same as those of the semiconductor device 60 of the present embodiment shown in FIGS.

  That is, the P-type semiconductor region 119a and the N-type semiconductor region 118a constitute a protection diode 128a. Similarly, the P-type semiconductor region 119b and the N-type semiconductor region 118b constitute a protection diode 128b. The P-type semiconductor region 119a and the N-type semiconductor region 118b constitute a protection diode 129a, and the P-type semiconductor region 119b and the N-type semiconductor region 118c constitute a protection diode 129b.

In the polycrystalline silicon region 150, a plurality of protective diodes 128a, 129a, 128b, and 129b connected in anti-series with an NPNPN structure are formed.
The first electrode 120 and the second electrode 121 are connected to the outermost N-type semiconductor region 118a and the innermost N-type semiconductor region 118c of the polycrystalline silicon region 150, respectively. The overvoltage applied to the first electrode 120 and the second electrode 121 causes the NPNPN protective diodes 128a, 129a, 128b, and 129b to break down, and a current flows. Since the current flows between the first electrode 120 and the second electrode 121, the portion of the N-type semiconductor region 118c inside the second electrode 121 has an invalid area as described later.

  In the semiconductor device 160 of the comparative example, the first electrode 120 and the second electrode 121 are electrically connected to, for example, the source and gate of a MOS transistor formed on the same semiconductor substrate 5, respectively. ESD protection diode.

  When an ESD voltage is applied between the gate and source of the MOS transistor, the protection diodes 128a, 129a, 128b, and 129b of the semiconductor device 160 break down, and a current flows. That is, the ESD voltage is discharged between the gate and the source through this diode structure, and the MOS transistor is protected.

  By the way, this diode structure is formed in an annular structure having a rectangular planar shape and a closed PN junction. This is because the PN junction is not exposed at the end face of the polycrystalline silicon region 150. This is because, when the PN junction is exposed at the end face of the polycrystalline silicon region 150, the end face is worried about having a high recombination speed because of the disorder of the crystal structure or the crushing region generated in the manufacturing process.

  When the recombination rate is fast, the energy corresponding to the band gap released during recombination in this region destroys the crystal lattice and further increases the region with a fast recombination rate, which tends to cause deterioration of the diode characteristics. There is. For this reason, an annular structure is adopted as a device for preventing the PN junction from being exposed to the end face of the polycrystalline silicon region 150.

When protecting a MOS transistor or the like, it is natural that the ESD resistance of the protection diode itself must be high, and a structure in which the ESD protection diode does not easily deteriorate is necessary.
However, when the annular structure is used in order to avoid the deterioration of the protection diode as described above, there is a problem that the area efficiency of the protection diode portion is deteriorated.

  That is, in general, the ESD protection function is higher as the diode junction area is larger, and a large ESD resistance can be ensured. Therefore, in order to obtain a large ESD tolerance, it is necessary to obtain a diode junction area as large as possible. However, as shown in FIG. 4, in order to increase the diode junction area, it is necessary to increase the peripheral length of the rectangular structure. In this case, the area of the central portion, that is, the portion of the N-type semiconductor region 118c inside the second electrode 121 shown in FIG. In addition, the total area of the device is increased and the manufacturing cost is increased, which is not preferable in the industry.

It is also effective to increase the thickness of the polycrystalline silicon region 150, but in this case, it is known that a stress difference between the polycrystalline silicon, the oxide film, and the substrate silicon causes a problem such as cracking. The limit is about 1 μm. As described above, when a protection diode having a high ESD protection function is obtained, there is a problem in that the invalid area is increased and the entire element area is increased.
In the semiconductor device 160 of the comparative example, the case where the planar shape of the protective diode is a concentric rectangular shape has been described, but the same applies to the case of a ring shape.

On the other hand, in the semiconductor device 60 of the present embodiment, the protection diodes 28a, 29a, 28b, and 29b are formed in a band shape in the semiconductor region 50 and have a small ineffective area.
That is, as shown in FIG. 3, when an ESD voltage is applied, it is considered that a current path is formed between the first and second electrodes 20 and 21. In this case, the current path spreads outward, but the extent is generally within the interelectrode distance Ld. Therefore, even when ESD is applied, the current does not reach the PN junction exposed portion of the end face Q (side wall) of the semiconductor region 50, and the diode structure does not deteriorate extremely.

  As described above, according to the semiconductor device 60 of the present embodiment, a large recombination current does not concentrate on the PN junction exposed portion of the end face Q (side wall) of the semiconductor region 50, the ESD resistance is large, and the ineffective area is small. A protective diode structure can be obtained.

FIG. 5 is a schematic plan view illustrating another configuration of the semiconductor device according to the embodiment of the invention.
As shown in FIG. 5, the semiconductor device 60 a of this example includes a semiconductor substrate 5, an insulating film 17, a semiconductor region 50, and first and second electrodes 20 a and 21 a.

In the semiconductor device 60a, both end portions 25 in the X-axis direction of the first and second electrodes 20a and 21a are formed in a semi-cylindrical shape. That is, as shown in FIG. 5, the planar shape (cross-sectional shape) of the first and second electrodes 20a and 21a is such that both end portions 25 in the X-axis direction are formed in an arc shape with a radius of 3 mm, for example. However, the semiconductor device 60 is different. Other than this, the semiconductor device 60 is the same as the semiconductor device 60.
In addition, in the present Example, although the structure which formed the both ends 25 in circular arc shape is illustrated, it should just have a curvature relaxation part not only in circular arc shape. That is, the planar shape (cross-sectional shape) of both end portions 25 as shown in FIG. 5 is not limited to a polygon but may be a curved line.

  When the end shapes are close to a right angle like the first and second electrodes 20 and 21, current concentration occurs due to electric field concentration, and abnormal heat is generated in this portion, resulting in diode degradation. Therefore, by providing a curvature relaxation portion at the end portion 25, such abnormal current concentration can be avoided and deterioration of the diode structure can be suppressed.

  Therefore, according to the semiconductor device 60a, a large recombination current does not concentrate on the PN junction exposed portion of the end face Q (side wall) of the semiconductor region 50. In addition, a current can not be concentrated on the end portions 25 of the first and second electrodes 20a and 21a, so that a protection diode structure having a large ESD resistance and a small ineffective area can be obtained.

FIG. 6 is a schematic plan view illustrating another configuration of the semiconductor device according to the embodiment of the invention.
As shown in FIG. 6, the semiconductor device 61 of this example includes the semiconductor substrate 5, the insulating film 17, the semiconductor regions 50 a to 50 e, the first and second electrodes 20 a and 21 a, the MOS transistor region 40, and the electrode pad 45. Is provided.

In the semiconductor device 61 of this embodiment, the semiconductor regions 50 a to 50 d are provided in the peripheral portion of the semiconductor substrate 5. The semiconductor region 50e is provided around the electrode pad 45.
Only the first and second electrodes 20a and 21a connected to the semiconductor region 50a are shown, and the first and second electrodes connected to the other semiconductor regions 50b to 50e are omitted. .

Here, the semiconductor substrate 5, the insulating film 17, the semiconductor region 50a, and the first and second electrodes 20a and 21a are the same as those of the semiconductor device 60a. The semiconductor regions 50b and 50c are the same except that the planar shape of the semiconductor region 50a is U-shaped and L-shaped, respectively. The semiconductor region 50d is the same as the semiconductor region 50a except that the semiconductor region 50d is provided in the periphery of the semiconductor substrate 5 inside the semiconductor region 50a.
Further, the distance Wp between the semiconductor regions 50a and 50b is not particularly limited and may be zero. However, even when one end of each of the semiconductor regions 50a and 50b is connected with the distance Wp being zero, the PN junction is exposed at the end face at least at the other end of the semiconductor regions 50a and 50b.

The MOS transistor region 40 is a region where a MOS transistor element that protects against ESD is formed by a protection diode formed in the semiconductor regions 50a to 50e, and is formed simultaneously with the semiconductor regions 50a to 50e.
The electrode pad 45 is electrically connected to the gate 8 of the MOS transistor region 40 (not shown). In the present embodiment, the case of one electrode pad 45 is illustrated, but an arbitrary number may be provided.

7 is a cross-sectional view taken along line AA of the semiconductor device shown in FIG.
As shown in FIG. 7, the MOS transistor region 40 of the semiconductor device 61 is provided with the back surface drain electrode 4 on the lower side of the semiconductor substrate 5. In addition, P-type base regions 6 a, 6 b, 6 c are formed on the surface of the N-type semiconductor substrate 5. N-type source regions 7a and 7b are formed on the surface of the P-type base region 6a, N-type source regions 7c and 7d are formed on the surface of the P-type base region 6b, and N-type source regions 7c and 7d are formed on the surface of the P-type base region 6c. Source regions 7e and 7f are respectively formed.

A polycrystalline silicon gate electrode 8a is formed on the N-type source region 7c through the oxide film 17 on the N-type source region 7b. Similarly, a polycrystalline silicon gate electrode 8b is formed on the N-type source region 7e through the oxide film 17 on the N-type source region 7d.
Further, a source electrode 10 connected to the N-type source regions 7a to 7e is formed.

  Second electrode 21a of semiconductor regions 50a-50e functioning as an ESD protection diode and polycrystalline silicon gate electrodes 8a, 8b are electrically connected (not shown). The first electrode 20a and the source electrode 10 are electrically connected (not shown). Thereby, the MOS transistor region 40 is protected from ESD applied between the gate and the source.

  In this embodiment, the semiconductor substrate 5 is N-type and the MOS transistor region 40 has an N-channel vertical MOS transistor structure. However, the present invention is not limited to this, and a P-type semiconductor substrate may be used. Further, it may have a P channel MOS transistor region, and may further have a bipolar transistor region.

The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, with regard to the specific configuration of each element constituting the semiconductor device, the present invention is similarly implemented by appropriately selecting from a well-known range by those skilled in the art, as long as the same effect can be obtained. Included in the range.
Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

In addition, all semiconductor devices that can be implemented by those skilled in the art based on the semiconductor device described above as an embodiment of the present invention are included in the scope of the present invention as long as they include the gist of the present invention.
In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

4 Back surface drain electrode 5 N-type semiconductor substrate (semiconductor substrate)
6a, 6b, 6c P-type base region 7a, 7b, 7c, 7d, 7e N-type source region 8, 8a, 8b Polycrystalline silicon gate electrode 10 Source electrode 17 Insulating film 18a, 18b, 18c N-type semiconductor region 19a, 19b P-type semiconductor region 20, 20a First electrode 21, 21a Second electrode 25 End portion 28a, 28b, 29a, 29b Protection diode 40 MOS transistor region 45 Electrode pad 50, 50a-50e Semiconductor region 60, 60a, 61 Semiconductor Device 118a, 118b, 118c N-type semiconductor region 119a, 119b P-type semiconductor region 120 First electrode 121 Second electrode 128a, 128b, 129a, 129b Protection diode 150 Polycrystalline silicon region 160 Semiconductor device P First and second Electrode end Q semiconductor layer end face Side wall)
Ld Distance between the first and second electrodes Ws Distance between the end portions PQ Wd Width of the first and second electrodes Wp Distance between the semiconductor regions

Claims (15)

A semiconductor substrate;
A semiconductor layer provided on the semiconductor substrate via an insulating film and extending in a first direction along an outer edge of the semiconductor substrate;
A plurality of first semiconductor regions of a first conductivity type extending in the first direction;
A second semiconductor region of a second conductivity type extending in the first direction,
The plurality of first semiconductor regions are arranged in a second direction along the semiconductor substrate and in a second direction orthogonal to the first direction,
The second semiconductor region is disposed between adjacent first semiconductor regions of the plurality of first semiconductor regions,
The second semiconductor region includes a semiconductor layer having a width in the second direction wider than a thickness of the semiconductor layer in a direction perpendicular to the semiconductor substrate;
A first electrode provided on a first semiconductor region located at one end of the plurality of first semiconductor regions;
A second electrode provided on the first semiconductor region located at the other end of the plurality of first semiconductor regions;
A semiconductor device comprising:   2. The semiconductor according to claim 1, wherein the first semiconductor region provided with the first electrode has a width in the second direction equal to or wider than a width of the second semiconductor region in the second direction. apparatus.   The first semiconductor region in which the second electrode is provided has a width in the second direction that is equal to or wider than a width of the second semiconductor region in the second direction. The semiconductor device described. The distance between the first electrode and the end in the first direction of the first semiconductor region in which the first electrode is provided is the first electrode and the second semiconductor region adjacent to the first electrode; Wider than the interval,
The distance between the second electrode and the first direction end of the first semiconductor region in which the second electrode is provided is the second electrode and the second semiconductor region adjacent to the second electrode; The semiconductor device according to claim 1, wherein the semiconductor device is wider than the distance between the two.   The semiconductor device according to claim 1, wherein the semiconductor layer includes at least two first semiconductor regions. A boundary between the first semiconductor region and the second semiconductor region extends to an end of the semiconductor layer in the first direction;
The semiconductor device according to claim 1, wherein the semiconductor device is exposed at an end face of the semiconductor layer.   An interval between the end of the semiconductor layer in the first direction and one of the first electrode and the second electrode is larger than an interval between the first electrode and the second electrode; Or it is the same, The semiconductor device as described in any one of Claims 1-6.   The semiconductor device according to claim 1, wherein the semiconductor layer is provided in the insulating film. The semiconductor substrate has a rectangular shape,
The semiconductor device according to claim 1, wherein the semiconductor layer is provided along two opposing sides of the semiconductor substrate. The semiconductor substrate has a rectangular shape,
The semiconductor device according to claim 1, wherein the semiconductor layer is provided along one side of the semiconductor substrate and a side perpendicular thereto. The semiconductor substrate includes a transistor,
The semiconductor device according to claim 1, wherein the semiconductor layer is provided around the transistor. The semiconductor substrate has an electrode pad provided thereon via an insulating film,
The semiconductor device according to claim 1, wherein the semiconductor layer is provided around the electrode pad.   The semiconductor device according to claim 1, wherein an end portion of the first electrode and an end portion of the second electrode each have a curvature relaxation portion.   The semiconductor device according to claim 1, wherein a length of the first semiconductor region in the second direction is 2 μm or more.   The length of the said 2nd direction of a said 2nd semiconductor region is 2 micrometers or more, The semiconductor device as described in any one of Claims 1-14.

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