JP2015103779A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which reduces a difference in thermal expansion amounts of each insulator layer in thermal history, thereby inhibiting warpage occurring in a substrate.SOLUTION: A wiring board A includes: multiple insulator layers 1a, 1b laminated in a vertical direction; and a ground conductor 2b and a power supply conductor 2c, where a number of circular opening parts are formed, deposited on surfaces of the insulator layers 1a, 1b. The opening parts are formed by a number of large diameter opening parts 8a arranged and small diameter opening parts 8b which are respectively disposed in areas between the large diameter opening parts 8a.

Description

  The present invention relates to a high-density wiring board on which a semiconductor integrated circuit element or the like is mounted.

In recent years, as electronic devices typified by portable game machines and communication devices have been reduced in size and functionality, the wiring boards used for these devices are equipped with small and highly functional semiconductor elements. High density wiring is required. Conventionally, a well-known build-up board is suitably used for such a high-density wiring board.
The build-up board is formed by alternately laminating conductor layers and build-up insulating layers on both upper and lower surfaces of a core insulating layer, for example, and a part of the conductor layer formed on the uppermost layer on the upper surface side. And the electrodes of the semiconductor element are connected via solder by a reflow process.

Such a conventional wiring board is shown in FIG. In the conventional wiring board B, a conductor layer 12 is disposed between the upper and lower surfaces of the insulating substrate 11 in which a plurality of build-up insulating layers 11b are laminated on both main surfaces of the core insulating layer 11a and between the insulating layers. Furthermore, solder resist layers 13 are deposited on the upper and lower surfaces of the insulating substrate 11. Each insulating layer is electrically connected via a through conductor 14a in the through hole 14 formed in the core insulating layer 11a and a via conductor 15a in the via hole 15 formed in the build-up insulating layer 11b. Connected to.
Next, FIG. 4 shows an enlarged plan view of a main part of the conductor layer 12. The conductor layer 12 includes a signal wiring conductor layer 12a through which an electric signal is transmitted, a grounding conductor layer 12b for supplying a potential, or a conductor layer 12c for power supply. It is selectively formed on the surfaces of the layers 11a and 11b. The grounding conductor layer 12b and the power source conductor layer 12c are generally arranged at predetermined intervals along the signal wiring conductor layer 12a. The grounding conductor layer 12b and the power supply conductor layer 12c formed in each insulating layer are electrically connected by a via conductor 15a.
Further, in order to adjust the occupation area ratio of the conductor layer 12 on the surfaces of the insulating layers 11a and 11b, a circular opening 18 having the same diameter is provided in the ground conductor layer 12b and the power source conductor layer 12c. Arranged in an array.

By the way, in such a wiring board B, the difference between the occupied area ratio of the conductor layer 12 formed on the upper surface side around the core insulating layer 11a and the occupied area ratio of the conductor layer 12 formed on the lower surface side. It is necessary to reduce the difference between the thermal expansion coefficient of the multilayer body including the conductor layer 12 on the upper surface side and the thermal expansion coefficient of the multilayer body including the conductor layer 12 on the lower surface side. Thus, for example, during the above-described reflow process, the difference between the amount of thermal expansion / contraction that occurs in the laminate on the upper surface side and the amount of thermal expansion / contraction that occurs on the laminate on the lower surface side can be reduced, so that warping of the substrate is minimized Can do.
However, as the density of the wiring board increases as described above, the ratio of the signal wiring conductor layer 12a on the surface is high, and the ratio of the grounding conductor layer 12b and the power source conductor layer 12c is low. Layers 11a and 11b are formed. In such insulating layers 11a and 11b, as described above, there are many intervals where the conductor layer 12 is not deposited around the signal wiring conductor layer 12a, so that the occupied area ratio of the conductor layer 12 becomes very small. However, in order to correspond to the occupied area ratio of the conductor layer 12 in the insulating layers 11a and 11b, the diameter of the opening 18 is reduced in order to reduce the occupied area ratio of the conductor layer 12 on the surface of the other insulating layers 11a and 11b. When the size is increased, in the arrangement in which the circular openings 18 having the same diameter as described above are formed in a square lattice shape, the interval between the openings 18 adjacent to each other vertically and horizontally along the square lattice becomes narrow. End up. In the grounding conductor layer 12b and the power supply conductor layer 12c in which the openings 18 are formed, the gap between the adjacent openings 18 becomes narrow so that the ground potential and the power supply potential can be supplied. It becomes difficult for an electric current to flow favorably between these openings 18. Therefore, since it is necessary to leave a predetermined interval between the adjacent openings 18, the diameter of the openings 18 cannot be increased beyond a certain level. For this reason, in the conventional arrangement of the openings 18, it is difficult to reduce the occupied area ratio so as to correspond to the insulating layers 11a and 11b having an extremely small occupied area ratio.

JP-A-61-220398

  The present invention suppresses the warpage that occurs on the substrate by reducing the difference in the ratio of the area occupied by the conductor layers in the insulating layers stacked one above the other and reducing the difference in the amount of thermal expansion and contraction of each insulating layer during the thermal history. It is an object of the present invention to provide a wiring board that can be used.

  The wiring board according to the present invention includes a plurality of insulating layers stacked one above the other and a grounding or power supply conductor layer that is attached to the surface of the insulating layer and has a large number of circular openings formed therein. The substrate is characterized in that the opening includes a large-diameter opening arranged in a large number and a small-diameter opening disposed between the large-diameter openings.

  According to the wiring board of the present invention, the opening formed in the conductor layer for grounding or power supply includes a large-diameter opening, and a small-diameter opening disposed between these large-diameter openings. Therefore, for example, a predetermined interval is provided between these large-diameter openings at the center between the four large-diameter openings arranged so as to be adjacent to each other vertically and horizontally with a predetermined interval. By arranging the small-diameter opening with the space remaining, the area ratio occupied by the conductor layer for grounding or power supply can be reduced by the small-diameter opening. Alternatively, by arranging the small-diameter opening in a space where the large-diameter opening cannot be arranged, the area ratio of the grounding or power supply conductor layer can be reduced by the small-diameter opening. As a result, even when it is necessary to cope with an insulating layer having a very small occupation area ratio as described above, it is possible to cope with a reduction in the occupation area ratio of the conductor layer for grounding or power supply. As a result, the difference in the occupied area ratio of the conductor layers in the insulating layers stacked above and below is reduced, and the difference in the amount of thermal expansion and contraction of each insulating layer during the thermal history is reduced, thereby suppressing the warpage generated in the substrate. It is possible to provide a wiring board capable of satisfying the requirements.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a main part enlarged plan view showing an example of the embodiment of the wiring board of the present invention. FIG. 3 is a schematic cross-sectional view showing an example of an embodiment of a conventional wiring board. FIG. 4 is an enlarged plan view of a main part showing an example of an embodiment of a conventional wiring board.

  Next, an example of an embodiment of the wiring board of the present invention will be described in detail with reference to FIG.

  FIG. 1 shows a schematic cross-sectional view of the wiring board A of this example. The wiring board A has a conductor layer 2 between the upper and lower surfaces of the insulating substrate 1 in which a plurality of build-up insulating layers 1b are laminated on both main surfaces of the core insulating layer 1a and between the insulating layers 1a and 1b. Further, solder resist layers 3 are deposited on the upper and lower surfaces of the insulating substrate 1.

  The core insulating layer 1a is made of an electrically insulating material in which a glass cloth is impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, and a plurality of through holes 4 having a diameter of about 100 to 300 μm are formed. Yes. A through conductor 4a is formed on the side wall of the through hole 4 by plating or the like, and the conductor layers 2 on the upper and lower surfaces of the core insulating layer 1a are electrically connected through the through conductor 4a. The thickness of the core insulating layer 1a is about 40 to 400 μm.

  The build-up insulating layer 1b is made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin, and has a plurality of via holes 5 penetrating from the upper surface to the lower surface. A portion of the conductor constituting the conductor layer 2 is filled in the via hole 5 as a via conductor 5a, thereby establishing conduction between the upper and lower conductor layers 2 of the build-up insulating layer 1b.

The conductor layer 2 is mainly formed of a highly conductive metal such as copper, and the one disposed on the core insulating layer 1a is formed by, for example, a well-known subtractive method. The material disposed on the insulating layer 1b is formed by, for example, a known semi-additive method. The conductor layer 2 includes a signal wiring conductor layer 2a for transmitting electrical signals to and from the semiconductor element S and the circuit board, a grounding conductor layer 2b for supplying a potential, or a power source conductor layer 2c. There is. Further, a semiconductor element connection pad 6 connected to the electrode T of the semiconductor element S is formed at the center of the upper surface of the wiring board A, and a circuit connected to the electrode of the circuit board on the lower surface of the wiring board A. Substrate connection pads 7 are formed.
The semiconductor element connection pad 6 is electrically connected to the circuit board connection pad 7 via the signal wiring conductor layer 2a, the via conductor 5a, or the through conductor 4a.

  The solder resist layer 3 is made of an electrically insulating material containing a thermosetting resin such as an epoxy resin or a polyimide resin, and is reflowed when connecting the wiring board A and the semiconductor element S or connecting the semiconductor package to the circuit board. It coat | covers in order to protect the insulated substrate 1 and the conductor layer 2 from the heat | fever at the time of a process. An exposed portion 3a is formed in the solder resist layer 3 provided on the upper surface side of the insulating substrate 1 to expose a part of the conductor layer 2 on the upper surface of the insulating substrate 1 as a semiconductor element pad 6 connected to the electrode T of the semiconductor element S. In the solder resist layer 3 provided on the lower surface side, there is an exposed portion 3b that exposes a part of the conductor layer 2 on the lower surface of the insulating substrate 1 as a circuit board connection pad 7 connected to the electrode of the external circuit board. Is formed.

In FIG. 2, the principal part enlarged plan view of the conductor layer 2 is shown. In the wiring board A of this example, as shown in FIG. 2, conductor layers 2b and 2c for grounding or power supply are formed along the signal wiring conductor layer 2a. The conductor layers 2b and 2c for grounding or power supply are alternately formed with an array of large-diameter openings 8a and an array of small-diameter openings 8b that are vertically and horizontally with a predetermined adjacent interval between them. Yes. In this example, the arrangement pitch of the large-diameter openings 8a and the small-diameter openings 8b are alternately shifted by half a pitch.
In this example, the arrangement pitch of the large-diameter openings 8a and the arrangement pitch of the small-diameter openings 8b are, for example, 1/2 of the arrangement pitch of the circuit board connection pads 7.
Further, when there is a space where the large-diameter opening cannot be arranged in the ground or power supply conductor layers 2b and 2c, the small-diameter opening 8b is formed in the space, for example, 1/4 of the arrangement pitch of the circuit board connection pads 7. May be arranged at high density. At this time, it is preferable that the intervals between the openings are arranged with a separation of 35 μm or more. If the distance between the openings is less than 35 μm, the adhesion strength between the grounding or power supply conductor layers 2b, 2c and the insulating layers 1a, 1b may be weakened and peeled off.
As described above, according to the wiring board A of the present invention, a predetermined interval is provided between the large-diameter openings 8a disposed with a predetermined adjacent interval therebetween. Since the small-diameter opening 8b is formed, the opening can be formed at a high area ratio in the ground or power conductor layers 2b and 2c. For this reason, even when it is necessary to reduce the occupied area ratio of the conductor layer in the insulating layer, the occupied area ratio of the conductor layer can be easily reduced. As a result, the difference in the occupied area ratio of the conductor layers in the insulating layers stacked up and down is reduced, and the thermal expansion / contraction amount difference of each insulating layer during the thermal history is reduced, thereby suppressing the warpage generated in the substrate. A possible high-density wiring board can be provided.

DESCRIPTION OF SYMBOLS 1a, 1b Insulating layer 2b Grounding conductor layer 2c Power supply conductor layer 8a Large diameter opening 8b Small diameter opening A Wiring board

Claims (1)

  A wiring board comprising a plurality of insulating layers stacked one above the other, and a grounding or power supply conductor layer deposited on the surface of the insulating layer and having a large number of circular openings, A wiring board comprising: a plurality of large-diameter openings arranged in a large number; and a small-diameter opening disposed between the large-diameter openings.

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