JP2015103540A - Power semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor module which improves the reliability of soldering between a metal heat radiation plate and a conductor pattern of an insulation substrate and between the conductor pattern of the insulation substrate and a lower end of an external lead-out terminal.SOLUTION: A power semiconductor module 100 is manufactured by: providing on an insulation substrate 2 a conductor pattern 2b1 electrically connected with a lower surface electrode of a power semiconductor chip 3a, a conductor pattern 2b2 electrically connected with an upper surface electrode of the same, and a lower surface side conductor pattern 2c; and fixing a metal heat radiation plate 1 to a basing jig so that a lower surface of the heat radiation plate 1 is deformed in a convex shape while following a concave upper surface of the jig at execution of soldering between the heat radiation plate 1 and the conductor pattern 2c and between the conductor patterns 2b1 and 2b2 and lower ends 6a4 and 6b4 of external lead-out terminals 6a and 6b. In the power semiconductor module 100, a Pb-free solder 10a containing Sb is used for the soldering between the heat radiation plate 1 and the conductor pattern 2c, and a Pb-free solder 10f1 and 10f2 not containing Sb is used for the soldering between the conductor patterns 2b1 and 2b2 and the lower ends 6b4 and 6a4 of the external lead-out terminals 6b and 6a.

Description

  The present invention provides an insulation having an upper surface side conductor pattern electrically connected to the lower surface electrode of the power semiconductor chip, an upper surface side conductor pattern electrically connected to the upper surface electrode of the power semiconductor chip, and a lower surface side conductor pattern. When the soldering between the metal heat sink and the lower surface side conductor pattern and the soldering connection between the upper surface side conductor pattern and the lower end portion of the external lead terminal is performed, the concave upper surface of the basing jig is provided. It is related with the power semiconductor module manufactured by fixing a metal heat sink with respect to a basing jig so that the lower surface of a metal heat sink may deform | transform into convex shape.

  In particular, the present invention improves the reliability of solder bonding between the metal heat sink and the lower surface side conductor pattern of the insulating substrate, and between the upper surface side conductor pattern of the insulating substrate and the lower end portion of the external lead-out terminal. The present invention relates to a power semiconductor module capable of improving the reliability of solder bonding.

  The present invention further includes an upper surface side conductor pattern electrically connected to the lower surface electrode of the power semiconductor chip, an upper surface side conductor pattern electrically connected to the upper surface electrode of the power semiconductor chip, and a lower surface side conductor pattern. A solder between the metal heat dissipation plate and the lower surface side conductor pattern, comprising a connecting member for electrically connecting the upper surface electrode of the power semiconductor chip and the upper surface side conductor pattern of the insulating substrate. When performing bonding and solder bonding between the upper surface side conductor pattern electrically connected to the upper surface electrode of the power semiconductor chip and one lower end portion of the connecting member, metal heat dissipation follows the concave upper surface of the basing jig. The metal heat sink is fixed to the basing jig so that the lower surface of the plate is deformed in a convex shape, the gel case resin is filled in the enclosing case arranged on the metal heat sink, It relates to a power semiconductor module covering the connecting member and the power semiconductor chip by fat.

  In particular, the present invention provides an upper surface side conductor pattern electrically connected to the upper surface electrode of the power semiconductor chip while improving the reliability of solder bonding between the metal heat sink and the lower surface side conductor pattern of the insulating substrate. The present invention relates to a power semiconductor module capable of improving the reliability of solder bonding between one lower end portion of a connection member.

  Conventionally, an insulating substrate having an upper surface side conductor pattern (metal circuit layer) and a lower surface side conductor pattern (metal circuit layer) is provided, and a metal heat sink (base) and a lower surface side conductor pattern (metal circuit layer) The metal heat sink (base) is based so that the lower surface of the metal heat sink (base) deforms into a convex shape following the concave upper surface of the basing jig (soldering jig) when soldering between the two. A power semiconductor module (semiconductor device) manufactured by being fixed to a jig (soldering jig) is known. Examples of this type of power semiconductor module include those described in FIG. 1 to FIG. 6 of Patent Document 1 (Japanese Patent Laid-Open No. 2010-199251), for example.

  In the power semiconductor module described in Patent Document 1, the power semiconductor chip is mounted on the upper surface side conductor pattern (metal circuit layer) of the insulating substrate. An outer case (plastic case) formed of a resin material is disposed on a metal heat sink (base). Furthermore, a gel-like resin (liquid gel) is filled in an outer case (plastic case), and the power semiconductor chip is covered with the gel-like resin (liquid gel).

  Incidentally, Patent Document 1 does not describe an external lead-out terminal that is electrically connected to the upper surface electrode of the power semiconductor chip. Moreover, it does not describe the external lead-out terminal that is electrically connected to the lower electrode of the power semiconductor chip.

  That is, Patent Document 1 describes solder used for solder bonding between a metal heat sink (base) and a lower surface side conductor pattern (metal circuit layer) of an insulating substrate, but the upper surface side of the insulating substrate. It does not describe solder used for solder bonding between the conductor pattern (metal circuit layer) and the lower end portion of the external lead-out terminal.

  Therefore, in the power semiconductor module described in Patent Document 1, the insulating substrate is improved while improving the reliability of the solder joint between the metal heat sink (base) and the lower surface side conductor pattern (metal circuit layer) of the insulating substrate. Soldering can be performed using a basing jig (soldering jig) so as to improve the reliability of solder bonding between the upper surface side conductor pattern (metal circuit layer) and the lower end of the external lead-out terminal. Can not.

  In Patent Document 1, a metal plate is used as a connection member for electrically connecting the upper surface electrode of the power semiconductor chip and the upper surface side conductor pattern (metal circuit layer) of the insulating substrate, and the metal plate is soldered. However, it does not describe the details of the solder used for joining the metal plates.

  Therefore, in the power semiconductor module described in Patent Document 1, the power semiconductor is improved while improving the reliability of the solder joint between the metal heat sink (base) and the lower surface side conductor pattern (metal circuit layer) of the insulating substrate. A basing jig (in order to improve the reliability of solder bonding between the upper surface side conductor pattern (metal circuit layer) electrically connected to the upper surface electrode of the chip and one lower end portion of the connection member (metal plate) ( Solder joining using a soldering jig) cannot be performed.

JP 2010-199251 A

  In view of the above problems, the present invention improves the reliability of solder bonding between the metal heat sink and the lower surface side conductor pattern of the insulating substrate, while reducing the upper surface side conductor pattern of the insulating substrate and the lower end portion of the external lead terminal. It is an object of the present invention to provide a power semiconductor module that can improve the reliability of solder joints between the two.

  Furthermore, the present invention provides an upper surface side conductor pattern electrically connected to the upper surface electrode of the power semiconductor chip while improving the reliability of solder bonding between the metal heat sink and the lower surface side conductor pattern of the insulating substrate. An object of the present invention is to provide a power semiconductor module capable of improving the reliability of solder bonding between one lower end portion of a connection member.

According to the first aspect of the present invention, a power semiconductor chip (3a) having an upper surface electrode through which a large current flows and a lower surface electrode through which a large current flows is provided.
A first insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the power semiconductor chip (3a) and is electrically connected to the lower surface electrode of the power semiconductor chip (3a). An upper surface side conductor pattern (2b1), a second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a); An insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat radiating plate (1) for radiating the heat generated by the power semiconductor chip (3a) is provided,
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
A first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2) is insert-molded into the outer case (6);
A second outer lead-out terminal (6b) having a lower end (6b4) electrically connected to the first upper surface side conductor pattern (2b1) is insert-molded in the outer case (6);
Solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the second external lead terminal ( 6b) between the lower end (6b4) of the solder and between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). By fixing the metal heat radiating plate (1) to the basing jig so that the lower surface of the metal heat radiating plate (1) is deformed into a convex shape following the concave upper surface of the basing jig during the soldering of In the manufactured power semiconductor module (100),
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
More than the Pb-free solder (10a) containing Sb in the solder joint between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end (6b4) of the second external lead-out terminal (6b). Using a Pb-free solder (10f2) having a low tensile strength and containing no Sb,
More than the Pb-free solder (10a) containing Sb in the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). There is provided a power semiconductor module (100) characterized by using Pb-free solder (10f1) having a low tensile strength and containing no Sb.

According to invention of Claim 2, the power semiconductor chip (3a) which has the upper surface electrode through which a large current flows, and the lower surface electrode through which a large current flows is provided,
A first insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the power semiconductor chip (3a) and is electrically connected to the lower surface electrode of the power semiconductor chip (3a). An upper surface side conductor pattern (2b1), a second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a); An insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat radiating plate (1) for radiating the heat generated by the power semiconductor chip (3a) is provided,
A first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2);
A second external lead terminal (6b) having a lower end (6b4) electrically connected to the first upper surface side conductor pattern (2b1) is provided,
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
Solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the second external lead terminal ( 6b) between the lower end (6b4) of the solder and between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). At the time of performing the solder joining, the metal heat radiating plate (1) is fixed to the basing jig so that the lower surface of the metal heat radiating plate (1) deforms into a convex shape following the concave upper surface of the basing jig,
The outer casing (6) disposed on the metal heat sink (1) is filled with a gel resin, and the gel semiconductor allows the power semiconductor chip (3a) and the center of the first external lead-out terminal (6a). In the power semiconductor module (100) covering the part (6a2) and the lower end part (6a4) and the central part (6b2) and the lower end part (6b4) of the second external lead-out terminal (6b),
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
More than the Pb-free solder (10a) containing Sb in the solder joint between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end (6b4) of the second external lead-out terminal (6b). Using a Pb-free solder (10f2) having a low tensile strength and containing no Sb,
More than the Pb-free solder (10a) containing Sb in the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). There is provided a power semiconductor module (100) characterized by using Pb-free solder (10f1) having a low tensile strength and containing no Sb.

According to invention of Claim 3, the power semiconductor chip (3a) which has the upper surface electrode through which a large current flows, and the lower surface electrode through which a large current flows is provided,
A first insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the power semiconductor chip (3a) and is electrically connected to the lower surface electrode of the power semiconductor chip (3a). An upper surface side conductor pattern (2b1), a second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a); An insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat radiating plate (1) for radiating the heat generated by the power semiconductor chip (3a) is provided,
A connection member (5a) for electrically connecting the upper surface electrode of the power semiconductor chip (3a) and the second upper surface side conductor pattern (2b2) of the insulating substrate (2);
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
Solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), and one lower end (5a1) of the connecting member (5a) and the insulating substrate (2) When performing solder joining with the second upper surface side conductor pattern (2b2), a metal heat radiating plate (1) is formed so that the lower surface of the metal heat radiating plate (1) deforms into a convex shape following the concave upper surface of the basing jig. 1) is fixed to the basing jig,
A power semiconductor module in which an enclosing case (6) disposed on a metal heat sink (1) is filled with a gel resin and the power semiconductor chip (3a) and the connection member (5a) are covered with the gel resin. (100)
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
The solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end portion (5a1) of the connection member (5a) is pulled more than the Pb-free solder (10a) containing Sb. There is provided a power semiconductor module (100) characterized by using a Pb-free solder (10d1) having low strength and containing no Sb.

According to invention of Claim 4, the 1st power semiconductor chip (3a) which has the upper surface electrode into which a large current flows, and the lower surface electrode into which a large current flows is provided,
Providing a second power semiconductor chip (3c) having a top electrode through which a large current flows and a bottom electrode through which a large current flows;
An insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the first power semiconductor chip (3a) and the second power semiconductor chip (3c), and the first power semiconductor chip (3a) ) And the first upper surface side conductor pattern (2b1) electrically connected to the lower surface electrode of the second power semiconductor chip (3c), and the first upper surface side conductor pattern (2a). The second upper surface side conductor pattern (2b2) electrically connected to the upper surface electrode of the power semiconductor chip (3a), the upper surface side of the insulating layer (2a), and the second power semiconductor chip (3c) Providing an insulating substrate (2) having a third upper surface side conductor pattern (2b6) electrically connected to the upper surface electrode and a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat dissipating plate (1) for dissipating heat generated by the first power semiconductor chip (3a) and the second power semiconductor chip (3c);
A first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2);
A second external lead terminal (6b) having a lower end (6b4) electrically connected to the third upper surface side conductor pattern (2b6);
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
Solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the second external lead terminal ( 6b) between the lower end (6b4) of the solder and between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). At the time of performing the solder joining, the metal heat radiating plate (1) is fixed to the basing jig so that the lower surface of the metal heat radiating plate (1) deforms into a convex shape following the concave upper surface of the basing jig,
The outer casing (6) disposed on the metal heat sink (1) is filled with a gel resin, and the first power semiconductor chip (3a) and the second power semiconductor chip (3c) are filled with the gel resin. And a power semiconductor covering the central part (6a2) and the lower end part (6a4) of the first external lead-out terminal (6a) and the central part (6b2) and the lower end part (6b4) of the second external lead-out terminal (6b) In module (100),
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
More than the Pb-free solder (10a) containing Sb in the solder joint between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). Using a Pb-free solder (10f2) having a low tensile strength and containing no Sb,
More than the Pb-free solder (10a) containing Sb in the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). There is provided a power semiconductor module (100) characterized by using Pb-free solder (10f1) having a low tensile strength and containing no Sb.

  The power semiconductor module (100) according to claim 1 is provided with a power semiconductor chip (3a) having an upper surface electrode through which a large current flows and a lower surface electrode through which a large current flows. In addition, an insulating layer (2a) and a power semiconductor chip (3a) are formed on the upper surface side of the insulating layer (2a) for mounting, and are electrically connected to the lower surface electrode of the power semiconductor chip (3a). First upper surface side conductor pattern (2b1) and second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a) And an insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a). Furthermore, the metal heat sink (1) for radiating the heat generated by the power semiconductor chip (3a) is provided.

  The power semiconductor module (100) according to claim 1 has a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), and is made of an electrically insulating resin material. An outer case (6) formed by molding is provided. Further, a first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2) is insert-molded in the outer case (6). A second external lead-out terminal (6b) having a lower end portion (6b4) electrically connected to the first upper surface side conductor pattern (2b1) is insert-molded in the outer case (6).

  Furthermore, in the power semiconductor module (100) according to claim 1, the solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the insulating substrate (2) Solder joint between the first upper surface side conductor pattern (2b1) and the lower end portion (6b4) of the second external lead-out terminal (6b), and the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the second 1 When the solder joint with the lower end (6a4) of the external lead-out terminal (6a) is executed, the metal heat sink (1) is deformed into a convex shape following the concave upper surface of the basing jig. A heat-radiating plate (1) is fixed to the basing jig.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for power semiconductor modules, the present inventors have made solder bonding between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2). The temperature cycle test was conducted. Specifically, in the study by the present inventors, the solder joint between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2) contains Sb having a low tensile strength. A temperature cycle test was conducted using Pb-free solder. As a result, after the temperature cycle test, it was confirmed that the Pb-free solder containing no Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) peeled off. .

  The present inventors consider that the tensile strength of the solder between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) is insufficient, A temperature cycle test was conducted using Pb-free solder containing Sb with high tensile strength for solder bonding between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2). It was. As a result, it was confirmed that the Pb-free solder containing Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) did not peel after the temperature cycle test.

  Furthermore, in order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion of the second external lead-out terminal (6b). A temperature cycle test of solder joint with (6b4) was performed. Specifically, in the research by the present inventors, solder bonding between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) is performed. A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the Pb-free solder containing Sb between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). Although no peeling was observed, it was confirmed that the first upper surface side conductor pattern (2b1) of the insulating substrate (2) was damaged.

  The amount of thermal expansion and contraction in the vertical direction during the temperature cycle test of the second external lead terminal (6b) insert-molded in the outer case (6), and the outer case (6 ) Is different from the amount of thermal expansion and contraction in the vertical direction during the temperature cycle test, so the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion of the second external lead terminal (6b) ( 6b4) When using Pb-free solder with high tensile strength and containing Sb for solder joint with 6b4), the amount of thermal expansion and contraction in the vertical direction of the second external lead-out terminal (6b) during the temperature cycle test And the amount of thermal expansion and contraction in the vertical direction of the outer casing (6) cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb. As a result, the insulating substrate (2 ) First upper surface side conductor pattern (2b1) By such thermal stress, the first upper surface conductor pattern of the insulating substrate (2) (2b1) is corrupted, the present inventors have thought.

  Therefore, in the research by the present inventors, the tensile strength is applied to the solder joint between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). A temperature cycle test was conducted using Pb-free solder having a low Sb content and containing no Sb. As a result, after the temperature cycle test, Pb-free solder containing no Sb between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) is obtained. It was confirmed that the first upper surface side conductor pattern (2b1) of the insulating substrate (2) was not damaged without peeling.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion of the first external lead terminal (6a). A temperature cycle test of solder joint with (6a4) was performed. Specifically, in the research by the present inventors, solder bonding between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a) is performed. A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the Pb-free solder containing Sb between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). Although no separation was observed, it was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was damaged.

  The amount of thermal expansion and contraction in the vertical direction during the temperature cycle test of the first external lead terminal (6a) insert-molded in the outer case (6), and the outer case (6 ) Is different from the amount of thermal expansion / contraction in the vertical direction at the time of the temperature cycle test, the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion of the first external lead terminal (6a) ( When a Pb-free solder containing Sb and having high tensile strength is used for solder joint with 6a4), the amount of thermal expansion and contraction in the vertical direction of the first external lead-out terminal (6a) during the temperature cycle test And the amount of thermal expansion and contraction in the vertical direction of the outer casing (6) cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb. As a result, the insulating substrate (2 ) Second upper surface side conductor pattern (2b2) By such thermal stress, the second upper surface conductor pattern of the insulating substrate (2) (2b2) is corrupted, the present inventors have thought.

  Therefore, in the research by the present inventors, the tensile strength is applied to the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). A temperature cycle test was conducted using Pb-free solder having a low Sb content and containing no Sb. As a result, after the temperature cycle test, the Pb-free solder containing no Sb between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a) is obtained. It was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was not damaged without peeling.

  In view of the research results of the present inventors, in the power semiconductor module (100) according to claim 1, the solder between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2). Pb-free solder (10a) containing Sb is used for bonding.

  Therefore, according to the power semiconductor module (100) of the first aspect, the solder (1) between the metal heat sink (1) after the temperature cycle test and the lower surface side conductor pattern (2c) of the insulating substrate (2) The peeling of 10a) can be avoided, and the reliability of solder bonding between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2) can be improved.

  Furthermore, in the power semiconductor module (100) according to claim 1, between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). Pb-free solder (10f2) containing no Sb and having a lower tensile strength than Pb-free solder (10a) containing Sb is used for solder bonding.

  Therefore, according to the power semiconductor module (100) of claim 1, the lower end portions of the first upper surface side conductor pattern (2b1) and the second external lead terminal (6b) of the insulating substrate (2) after the temperature cycle test. The peeling of the solder (10f2) with respect to (6b4) and the damage of the first upper surface side conductor pattern (2b1) of the insulating substrate (2) can be avoided at the same time, and the first upper surface side conductor of the insulating substrate (2). The reliability of the solder joint between the pattern (2b1) and the lower end (6b4) of the second external lead-out terminal (6b) can be improved.

  In the power semiconductor module (100) according to claim 1, between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). Pb-free solder (10f1) not containing Sb, which has a lower tensile strength than Pb-free solder (10a) containing Sb, is used for solder bonding.

  Therefore, according to the power semiconductor module (100) of the first aspect, the second upper surface side conductor pattern (2b2) of the insulating substrate (2) after the temperature cycle test and the lower end portion of the first external lead terminal (6a) The peeling of the solder (10f1) with respect to (6a4) and the damage of the second upper surface side conductor pattern (2b2) of the insulating substrate (2) can be avoided at the same time, and the second upper surface side conductor of the insulating substrate (2). The reliability of the solder joint between the pattern (2b2) and the lower end portion (6a4) of the first external lead-out terminal (6a) can be improved.

  In other words, according to the power semiconductor module (100) of the first aspect, the reliability of solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2). Soldering between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) and the second of the insulating substrate (2). The reliability of the solder joint between the upper surface side conductor pattern (2b2) and the lower end portion (6a4) of the first external lead-out terminal (6a) can be improved.

  The power semiconductor module (100) according to claim 2 is provided with a power semiconductor chip (3a) having a top electrode through which a large current flows and a bottom electrode through which a large current flows. In addition, an insulating layer (2a) and a power semiconductor chip (3a) are formed on the upper surface side of the insulating layer (2a) for mounting, and are electrically connected to the lower surface electrode of the power semiconductor chip (3a). First upper surface side conductor pattern (2b1) and second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a) And an insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a). Furthermore, the metal heat sink (1) for radiating the heat generated by the power semiconductor chip (3a) is provided.

  In the power semiconductor module (100) according to claim 2, the first external lead-out terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2) is provided. ing. Furthermore, a second external lead terminal (6b) having a lower end (6b4) electrically connected to the first upper surface side conductor pattern (2b1) is provided. In addition, an outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g) and formed by molding an electrically insulating resin material is provided. ing.

  Furthermore, in the power semiconductor module (100) according to claim 2, solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the insulating substrate (2) Solder joint between the first upper surface side conductor pattern (2b1) and the lower end portion (6b4) of the second external lead-out terminal (6b), and the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the second 1 When the solder joint with the lower end (6a4) of the external lead-out terminal (6a) is executed, the metal heat sink (1) is deformed into a convex shape following the concave upper surface of the basing jig. A heat-radiating plate (1) is fixed to the basing jig.

  Moreover, in the power semiconductor module (100) according to claim 2, gel-like resin is filled in the outer case (6) disposed on the metal heat sink (1), and the power semiconductor is formed by the gel-like resin. The chip (3a), the central portion (6a2) and the lower end portion (6a4) of the first external lead-out terminal (6a), and the central portion (6b2) and the lower end portion (6b4) of the second external lead-out terminal (6b) Covered.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for power semiconductor modules, the present inventors have made solder bonding between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2). The temperature cycle test was conducted. Specifically, in the study by the present inventors, the solder joint between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2) contains Sb having a low tensile strength. A temperature cycle test was conducted using Pb-free solder. As a result, after the temperature cycle test, it was confirmed that the Pb-free solder containing no Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) peeled off. .

  The present inventors consider that the tensile strength of the solder between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) is insufficient, A temperature cycle test was conducted using Pb-free solder containing Sb with high tensile strength for solder bonding between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2). It was. As a result, it was confirmed that the Pb-free solder containing Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) did not peel after the temperature cycle test.

  Furthermore, in order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion of the second external lead-out terminal (6b). A temperature cycle test of solder joint with (6b4) was performed. Specifically, in the research by the present inventors, solder bonding between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) is performed. A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the Pb-free solder containing Sb between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). Although no peeling was observed, it was confirmed that the first upper surface side conductor pattern (2b1) of the insulating substrate (2) was damaged.

  The amount of thermal expansion and contraction in the vertical direction during the temperature cycle test of the second external lead terminal (6b) covered with the gel resin in the outer case (6), and the temperature cycle test of the gel resin Since the amount of thermal expansion and contraction in the vertical direction of the first and second plates is different, the distance between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end (6b4) of the second external lead-out terminal (6b) is different. When Pb-free solder containing high Sb and containing Sb is used for solder joint, the amount of thermal expansion and contraction in the vertical direction of the second external lead-out terminal (6b) and the amount of gel-like resin during the temperature cycle test The difference between the amount of thermal expansion and contraction in the vertical direction cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb, and as a result, the first upper surface side conductor pattern ( 2b1) due to the thermal stress applied to the insulating substrate ( ) And the first upper surface conductor pattern (2b1) is broken, the present inventors have thought.

  Therefore, in the research by the present inventors, the tensile strength is applied to the solder joint between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). A temperature cycle test was conducted using Pb-free solder having a low Sb content and containing no Sb. As a result, after the temperature cycle test, Pb-free solder containing no Sb between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) is obtained. It was confirmed that the first upper surface side conductor pattern (2b1) of the insulating substrate (2) was not damaged without peeling.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion of the first external lead terminal (6a). A temperature cycle test of solder joint with (6a4) was performed. Specifically, in the research by the present inventors, solder bonding between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a) is performed. A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the Pb-free solder containing Sb between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). Although no separation was observed, it was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was damaged.

  The amount of thermal expansion and contraction in the vertical direction during the temperature cycle test of the first external lead terminal (6a) covered with the gel resin in the outer case (6), and the temperature cycle test of the gel resin Since the amount of thermal expansion and contraction in the vertical direction of the second is different, the distance between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). When a Pb-free solder containing Sb and having a high tensile strength is used for solder joining, the amount of thermal expansion and contraction in the vertical direction of the first external lead-out terminal (6a) and the amount of gel-like resin during the temperature cycle test The difference between the amount of thermal expansion and contraction in the vertical direction cannot be sufficiently absorbed by the deformation of the Pb-free solder containing Sb. As a result, the second upper surface side conductor pattern ( 2b2) due to the thermal stress applied to the insulating substrate ( ) And the second upper surface conductor pattern (2b2) is broken, the present inventors have thought.

  Therefore, in the research by the present inventors, the tensile strength is applied to the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). A temperature cycle test was conducted using Pb-free solder having a low Sb content and containing no Sb. As a result, after the temperature cycle test, the Pb-free solder containing no Sb between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a) is obtained. It was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was not damaged without peeling.

  In view of the research results of the present inventors, in the power semiconductor module (100) according to claim 2, the solder between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2). Pb-free solder (10a) containing Sb is used for bonding.

  Therefore, according to the power semiconductor module (100) of claim 2, the solder (1) between the metal heat sink (1) after the temperature cycle test and the lower surface side conductor pattern (2c) of the insulating substrate (2) The peeling of 10a) can be avoided, and the reliability of solder bonding between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2) can be improved.

  Furthermore, in the power semiconductor module (100) according to claim 2, between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end (6b4) of the second external lead-out terminal (6b). Pb-free solder (10f2) containing no Sb and having a lower tensile strength than Pb-free solder (10a) containing Sb is used for solder bonding.

  Therefore, according to the power semiconductor module (100) according to claim 2, the lower end portions of the first upper surface side conductor pattern (2b1) and the second external lead-out terminal (6b) of the insulating substrate (2) after the temperature cycle test. The peeling of the solder (10f2) with respect to (6b4) and the damage of the first upper surface side conductor pattern (2b1) of the insulating substrate (2) can be avoided at the same time, and the first upper surface side conductor of the insulating substrate (2). The reliability of the solder joint between the pattern (2b1) and the lower end (6b4) of the second external lead-out terminal (6b) can be improved.

  In the power semiconductor module (100) according to claim 2, between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). Pb-free solder (10f1) not containing Sb, which has a lower tensile strength than Pb-free solder (10a) containing Sb, is used for solder bonding.

  Therefore, according to the power semiconductor module (100) of the second aspect, the second upper surface side conductor pattern (2b2) of the insulating substrate (2) after the temperature cycle test and the lower end portion of the first external lead terminal (6a) The peeling of the solder (10f1) with respect to (6a4) and the damage of the second upper surface side conductor pattern (2b2) of the insulating substrate (2) can be avoided at the same time, and the second upper surface side conductor of the insulating substrate (2). The reliability of the solder joint between the pattern (2b2) and the lower end portion (6a4) of the first external lead-out terminal (6a) can be improved.

  In other words, according to the power semiconductor module (100) according to claim 2, the reliability of the solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2). Soldering between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) and the second of the insulating substrate (2). The reliability of the solder joint between the upper surface side conductor pattern (2b2) and the lower end portion (6a4) of the first external lead-out terminal (6a) can be improved.

  In the power semiconductor module (100) according to claim 3, a power semiconductor chip (3a) having an upper surface electrode through which a large current flows and a lower surface electrode through which a large current flows is provided. In addition, an insulating layer (2a) and a power semiconductor chip (3a) are formed on the upper surface side of the insulating layer (2a) for mounting, and are electrically connected to the lower surface electrode of the power semiconductor chip (3a). First upper surface side conductor pattern (2b1) and second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a) And an insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a). Furthermore, the metal heat sink (1) for radiating the heat generated by the power semiconductor chip (3a) is provided.

  Further, in the power semiconductor module (100) according to claim 3, for electrically connecting the upper surface electrode of the power semiconductor chip (3a) and the second upper surface side conductor pattern (2b2) of the insulating substrate (2). A connecting member (5a) is provided. Further, an outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g) and formed by molding an electrically insulating resin material is provided. ing.

  Furthermore, in the power semiconductor module (100) according to claim 3, the solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), and the connecting member (5a) ) And the second upper surface side conductor pattern (2b2) of the insulating substrate (2) when performing solder bonding, the metal heat sink (1) follows the concave upper surface of the basing jig. The metal heat radiating plate (1) is fixed to the basing jig so that the lower surface of the metal plate is deformed into a convex shape.

  Moreover, in the power semiconductor module (100) according to claim 3, gel resin is filled in the enclosing case (6) disposed on the metal heat sink (1), and the power semiconductor chip is formed by the gel resin. (3a) and the connecting member (5a) are covered.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for power semiconductor modules, the present inventors have made solder bonding between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2). The temperature cycle test was conducted. Specifically, in the study by the present inventors, the solder joint between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2) contains Sb having a low tensile strength. A temperature cycle test was conducted using Pb-free solder. As a result, after the temperature cycle test, it was confirmed that the Pb-free solder containing no Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) peeled off. .

  The present inventors consider that the tensile strength of the solder between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) is insufficient, A temperature cycle test was conducted using Pb-free solder containing Sb with high tensile strength for solder bonding between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2). It was. As a result, it was confirmed that the Pb-free solder containing Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) did not peel after the temperature cycle test.

  Furthermore, in order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end portion of the connection member (5a) ( A temperature cycle test of the solder joint with 5a1) was performed. Specifically, in the research by the present inventors, the solder bonding between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end (5a1) of the connection member (5a), A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the Pb-free solder containing Sb between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end (5a1) of the connecting member (5a) is peeled off. However, it was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was damaged.

  The amount of thermal expansion and contraction in the vertical direction during the temperature cycle test of the connecting member (5a) covered with the gel resin in the outer case (6) and the vertical direction during the temperature cycle test of the gel resin Since the thermal expansion amount and the thermal contraction amount of the semiconductor substrate are different from each other, solder bonding between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end portion (5a1) of the connection member (5a) When Pb-free solder containing Sb with high tensile strength is used, the thermal expansion amount and thermal contraction amount in the vertical direction of the connection member (5a) and the thermal expansion amount in the vertical direction of the gel-like resin in the temperature cycle test The difference from the amount of thermal shrinkage cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb, and as a result, due to the thermal stress applied to the second upper surface side conductor pattern (2b2) of the insulating substrate (2). The second upper surface side guide of the insulating substrate (2) And pattern (2b2) is damaged, the inventors have thought.

  Therefore, in the studies by the present inventors, the tensile strength is applied to the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end portion (5a1) of the connecting member (5a). A temperature cycle test was conducted using a Pb-free solder containing no Sb. As a result, after the temperature cycle test, the Pb-free solder containing no Sb is peeled between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end (5a1) of the connecting member (5a). It was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was not damaged.

  In view of the research results of the present inventors, in the power semiconductor module (100) according to claim 3, the solder between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2). Pb-free solder (10a) containing Sb is used for bonding.

  Therefore, according to the power semiconductor module (100) of the third aspect, the solder between the metal heat sink (1) after the temperature cycle test and the lower surface side conductor pattern (2c) of the insulating substrate (2). Peeling (10a) can be avoided, and the reliability of solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) can be improved.

  Furthermore, in the power semiconductor module (100) according to claim 3, solder between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end portion (5a1) of the connecting member (5a). Pb-free solder (10d1) containing no Sb and having a tensile strength lower than that of Pb-free solder (10a) containing Sb is used for joining.

  Therefore, according to the power semiconductor module (100) of claim 3, the second upper surface side conductor pattern (2b2) of the insulating substrate (2) after the temperature cycle test and one lower end portion of the connection member (5a) ( 5a1) and the second upper surface side conductor pattern (2b2) of the insulating substrate (2) can be simultaneously avoided and the second upper surface side conductor pattern of the insulating substrate (2) can be avoided. The reliability of the solder joint between (2b2) and one lower end (5a1) of the connection member (5a) can be improved.

  In other words, according to the power semiconductor module (100) according to claim 3, the reliability of the solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2). The reliability of solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end portion (5a1) of the connection member (5a) can be improved.

  The power semiconductor module (100) according to claim 4 is provided with a first power semiconductor chip (3a) having an upper surface electrode through which a large current flows and a lower surface electrode through which a large current flows. Further, a second power semiconductor chip (3c) having an upper surface electrode through which a large current flows and a lower surface electrode through which a large current flows is provided. The first power semiconductor chip is formed on the upper surface side of the insulating layer (2a) for mounting the insulating layer (2a) and the first power semiconductor chip (3a) and the second power semiconductor chip (3c). A first upper surface side conductor pattern (2b1) electrically connected to the lower surface electrode of (3a) and the lower surface electrode of the second power semiconductor chip (3c); and an upper surface side of the insulating layer (2a); and The second upper surface side conductor pattern (2b2) electrically connected to the upper surface electrode of the first power semiconductor chip (3a), the second power semiconductor chip (3c) formed on the upper surface side of the insulating layer (2a). ) Having a third upper surface side conductor pattern (2b6) electrically connected to the upper surface electrode and a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a). Is provided. Furthermore, the metal heat sink (1) for radiating the heat generated by the first power semiconductor chip (3a) and the second power semiconductor chip (3c) is provided.

  In the power semiconductor module (100) according to claim 4, the first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2) is provided. ing. Furthermore, a second external lead terminal (6b) having a lower end (6b4) electrically connected to the third upper surface side conductor pattern (2b6) is provided. In addition, an outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g) and formed by molding an electrically insulating resin material is provided. ing.

  Furthermore, in the power semiconductor module (100) according to claim 4, the solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the insulating substrate (2) Solder joint between the third upper surface side conductor pattern (2b6) and the lower end portion (6b4) of the second external lead-out terminal (6b), and the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the second 1 When the solder joint with the lower end (6a4) of the external lead-out terminal (6a) is executed, the metal heat sink (1) is deformed into a convex shape following the concave upper surface of the basing jig. A heat-radiating plate (1) is fixed to the basing jig.

  Moreover, in the power semiconductor module (100) according to claim 4, the outer casing (6) disposed on the metal heat sink (1) is filled with the gel resin, and the first resin is formed by the gel resin. Power semiconductor chip (3a), second power semiconductor chip (3c), center portion (6a2) and lower end portion (6a4) of first external lead-out terminal (6a), and center of second external lead-out terminal (6b) The part (6b2) and the lower end part (6b4) are covered.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for power semiconductor modules, the present inventors have made solder bonding between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2). The temperature cycle test was conducted. Specifically, in the study by the present inventors, the solder joint between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2) contains Sb having a low tensile strength. A temperature cycle test was conducted using Pb-free solder. As a result, after the temperature cycle test, it was confirmed that the Pb-free solder containing no Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) peeled off. .

  The present inventors consider that the tensile strength of the solder between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) is insufficient, A temperature cycle test was conducted using Pb-free solder containing Sb with high tensile strength for solder bonding between the metal heat sink (1) and the lower surface conductor pattern (2c) of the insulating substrate (2). It was. As a result, it was confirmed that the Pb-free solder containing Sb between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2) did not peel after the temperature cycle test.

  Furthermore, in order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided a lower end portion of the third upper surface side conductor pattern (2b6) and the second external lead-out terminal (6b) of the insulating substrate (2). A temperature cycle test of solder joint with (6b4) was performed. Specifically, in the research by the present inventors, solder bonding between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) is performed. A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the Pb-free solder containing Sb between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). Although no separation was observed, it was confirmed that the third upper surface side conductor pattern (2b6) of the insulating substrate (2) was damaged.

  The amount of thermal expansion and contraction in the vertical direction during the temperature cycle test of the second external lead terminal (6b) covered with the gel resin in the outer case (6), and the temperature cycle test of the gel resin Since the amount of thermal expansion and contraction in the vertical direction of the second substrate is different, the distance between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end (6b4) of the second external lead-out terminal (6b) is different. When Pb-free solder containing high Sb and containing Sb is used for solder joint, the amount of thermal expansion and contraction in the vertical direction of the second external lead-out terminal (6b) and the amount of gel-like resin during the temperature cycle test The difference between the amount of thermal expansion and contraction in the vertical direction cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb, and as a result, the third upper surface side conductor pattern ( 2b6) due to the thermal stress applied to the insulating substrate ( ) And the third upper surface conductor pattern (2b6) is broken, the present inventors have thought.

  Therefore, in the research by the present inventors, the tensile strength is applied to the solder joint between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). A temperature cycle test was conducted using Pb-free solder having a low Sb content and containing no Sb. As a result, after the temperature cycle test, the Pb-free solder containing no Sb between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b) is obtained. It was confirmed that the third upper surface side conductor pattern (2b6) of the insulating substrate (2) was not damaged without peeling.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion of the first external lead terminal (6a). A temperature cycle test of solder joint with (6a4) was performed. Specifically, in the research by the present inventors, solder bonding between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a) is performed. A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the Pb-free solder containing Sb between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). Although no separation was observed, it was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was damaged.

  The amount of thermal expansion and contraction in the vertical direction during the temperature cycle test of the first external lead terminal (6a) covered with the gel resin in the outer case (6), and the temperature cycle test of the gel resin Since the amount of thermal expansion and contraction in the vertical direction of the second is different, the distance between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). When a Pb-free solder containing Sb and having a high tensile strength is used for solder joining, the amount of thermal expansion and contraction in the vertical direction of the first external lead-out terminal (6a) and the amount of gel-like resin during the temperature cycle test The difference between the amount of thermal expansion and contraction in the vertical direction cannot be sufficiently absorbed by the deformation of the Pb-free solder containing Sb. As a result, the second upper surface side conductor pattern ( 2b2) due to the thermal stress applied to the insulating substrate ( ) And the second upper surface conductor pattern (2b2) is broken, the present inventors have thought.

  Therefore, in the research by the present inventors, the tensile strength is applied to the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). A temperature cycle test was conducted using Pb-free solder having a low Sb content and containing no Sb. As a result, after the temperature cycle test, the Pb-free solder containing no Sb between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a) is obtained. It was confirmed that the second upper surface side conductor pattern (2b2) of the insulating substrate (2) was not damaged without peeling.

  In view of the research results of the present inventors, in the power semiconductor module (100) according to claim 4, the solder between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2). Pb-free solder (10a) containing Sb is used for bonding.

  Therefore, according to the power semiconductor module (100) of the fourth aspect, the solder (1) between the metal heat sink (1) after the temperature cycle test and the lower surface side conductor pattern (2c) of the insulating substrate (2) The peeling of 10a) can be avoided, and the reliability of solder bonding between the metal heat sink (1) and the lower conductor pattern (2c) of the insulating substrate (2) can be improved.

  Furthermore, in the power semiconductor module (100) according to claim 4, between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). Pb-free solder (10f2) containing no Sb and having a lower tensile strength than Pb-free solder (10a) containing Sb is used for solder bonding.

  Therefore, according to the power semiconductor module (100) of claim 4, the lower end portion of the third upper surface side conductor pattern (2b6) and the second external lead terminal (6b) of the insulating substrate (2) after the temperature cycle test. The peeling of the solder (10f2) with respect to (6b4) and the damage of the third upper surface side conductor pattern (2b6) of the insulating substrate (2) can be avoided at the same time, and the third upper surface side conductor of the insulating substrate (2). The reliability of the solder joint between the pattern (2b6) and the lower end portion (6b4) of the second external lead-out terminal (6b) can be improved.

  In the power semiconductor module (100) according to claim 4, between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end portion (6a4) of the first external lead-out terminal (6a). Pb-free solder (10f1) not containing Sb, which has a lower tensile strength than Pb-free solder (10a) containing Sb, is used for solder bonding.

  Therefore, according to the power semiconductor module (100) of claim 4, the lower end portion of the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the first external lead terminal (6a) after the temperature cycle test. The peeling of the solder (10f1) with respect to (6a4) and the damage of the second upper surface side conductor pattern (2b2) of the insulating substrate (2) can be avoided at the same time, and the second upper surface side conductor of the insulating substrate (2). The reliability of the solder joint between the pattern (2b2) and the lower end portion (6a4) of the first external lead-out terminal (6a) can be improved.

  In other words, according to the power semiconductor module (100) of the fourth aspect, the reliability of solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2). Soldering between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead terminal (6b) and the second of the insulating substrate (2). The reliability of the solder joint between the upper surface side conductor pattern (2b2) and the lower end portion (6a4) of the first external lead-out terminal (6a) can be improved.

It is the figure which showed the metal heat sink 1 which comprises some power semiconductor modules 100 of 1st Embodiment. It is the figure which showed the insulating substrate 2 which comprises some power semiconductor modules 100 of 1st Embodiment. It is the figure which showed a mode that the insulated substrate 2 grade | etc., Was mounted on the metal heat sinks. It is the figure which showed a mode that the connection members 5a and 5b were mounted on the assembly shown to FIG. 3 (A). FIG. 5 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. FIG. 5 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. It is the figure which showed a mode that the surrounding case 6 shown in FIG.5 and FIG.6 was covered on the assembly shown to FIG. 4 (A). FIG. 8 is a component diagram of the lid body 7 that is put on the assembly shown in FIG. It is the figure which showed the power semiconductor module 100 of 1st Embodiment. It is the figure which showed the metal heat sink 1 which comprises some power semiconductor modules 100 of 2nd Embodiment. It is the figure which showed the insulated substrate 2 which comprises some power semiconductor modules 100 of 2nd Embodiment. It is the figure which showed a mode that the insulated substrate 2 grade | etc., Was mounted on the metal heat sinks. It is the figure which showed a mode that the connection members 5a and 5a 'were mounted on the assembly shown to FIG. 12 (A). It is the figure which showed a mode that the external derivation | leading-out terminal 6a, 6b was mounted on the assembly shown to FIG. 13 (A). It is the figure which showed a mode that the external derivation | leading-out terminal 6a, 6b was mounted on the assembly shown to FIG. 13 (A). FIG. 15 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. 14. FIG. 15 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. 14. FIG. 18 is a component diagram of a lid body 7 that covers the outer casing 6 illustrated in FIGS. 16 and 17 that covers the assembly illustrated in FIG. 14. It is the figure which showed the power semiconductor module 100 of 2nd Embodiment. It is the figure which showed the metal heat sink 1 which comprises some power semiconductor modules 100 of 3rd Embodiment. It is the figure which showed the insulated substrate 2 which comprises some power semiconductor modules 100 of 3rd Embodiment. It is the figure which showed a mode that the insulated substrate 2 grade | etc., Was mounted on the metal heat sinks. It is the figure which showed a mode that the connection members 5a and 5a 'were mounted on the assembly shown to FIG. 22 (A). It is the figure which showed a mode that the external derivation | leading-out terminal 6a, 6b was mounted on the assembly shown to FIG. 23 (A). It is the figure which showed a mode that the external derivation | leading-out terminal 6a, 6b was mounted on the assembly shown to FIG. 23 (A). FIG. 25 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. 24. FIG. 25 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. 24. FIG. 28 is a component diagram of the lid body 7 that covers the outer casing 6 shown in FIGS. 26 and 27 that covers the assembly shown in FIG. 24. It is the figure which showed the power semiconductor module 100 of 3rd Embodiment. It is the figure which showed the metal heat sink 1 which comprises some power semiconductor modules 100 of 4th Embodiment. It is the figure which showed the insulated substrate 2 which comprises a part of power semiconductor module 100 of 4th Embodiment. It is the figure which showed a mode that power semiconductor chip 3a, 3b, 3c was mounted on the insulated substrate 2. FIG. FIG. 33 is a part diagram of an outer casing 6 that covers the assembly shown in FIG. FIG. 33 is a part diagram of an outer casing 6 that covers the assembly shown in FIG. FIG. 35 is a view showing a state in which the assembly shown in FIG. 32 (D) is mounted on the metal heat sink 1 shown in FIG. 30 and the outer case 6 shown in FIGS. 33 and 34 is covered. is there. FIG. 36 is a component diagram of the lid body 7 that covers the assembly shown in FIG. It is the figure which showed the power semiconductor module 100 of 4th Embodiment. It is the figure which showed the metal heat sink 1 which comprises some power semiconductor modules 100 of 5th Embodiment. It is the figure which showed the insulating substrate 2 which comprises some power semiconductor modules 100 of 5th Embodiment. It is the figure which showed a mode that power semiconductor chip 3a, 3b, 3c, 3d was mounted on the insulated substrate 2. FIG. It is a component figure of the cover body 7 which comprises a part of power semiconductor module 100 of 5th Embodiment. FIG. 6 is a view showing an assembly obtained by attaching external lead terminals 6a, 6b, 6c and signal terminals 6j, 6k, 6m, 6n to the lid body 7; 43 is a view of the external lead-out terminals 6a, 6b, and 6c as seen through the lid body 7 of the assembly shown in FIG. FIG. 43 is a view of signal terminals 6j, 6k, 6m, and 6n as seen through the lid body 7 in the assembly shown in FIG. It is the figure which showed a mode that the assembly shown in FIG.40 (C) is mounted on the metal heat sink 1 shown in FIG.38, and the assembly shown in FIG.42 is mounted on it. FIG. 46 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. It is the figure which showed the power semiconductor module 100 of 5th Embodiment. It is the figure which showed the metal heat sink 1 which comprises some power semiconductor modules 100 of 6th Embodiment. It is the figure which showed the insulating substrate 2 which comprises a part of power semiconductor module 100 of 6th Embodiment. The power semiconductor chips 3a, 3a ′, 3b, 3b ′, 3c, 3c ′, 3d, 3d ′, 3e, 3f and the gate resistance chips R1, R1 ′, R2, R2 ′ are mounted on the insulating substrate 2. FIG. It is a top view of the assembly obtained by performing wire bonding with respect to the assembly shown to FIG. 50 (A). It is a component figure of the cover body 7 which comprises a part of power semiconductor module 100 of 6th Embodiment. FIG. 6 is a view showing an assembly obtained by attaching external lead terminals 6a, 6b, 6c and signal terminals 6j, 6k, 6m, 6n to the lid body 7; It is the figure of the external derivation | leading-out terminal 6a, 6b, 6c seen through the cover body 7 of the assembly shown in FIG. FIG. 54 is a view of signal terminals 6j, 6k, 6m, and 6n as seen through the lid body 7 in the assembly shown in FIG. It is the figure which showed a mode that the assembly shown in FIG. 51 was mounted on the metal heat sink 1 shown in FIG. 48, and the assembly shown in FIG. 53 is mounted on it. FIG. 57 is a component diagram of an outer casing 6 that covers the assembly shown in FIG. 56 (A). It is the figure which showed the power semiconductor module 100 of 6th Embodiment.

  A power semiconductor module according to a first embodiment of the present invention will be described below. FIG. 1 is a view showing a metal heat radiating plate 1 constituting a part of the power semiconductor module 100 of the first embodiment. Specifically, FIG. 1A is a plan view of the metal heat radiating plate 1, and FIG. 1B is a vertical sectional view taken along the line AA in FIG. FIG. 2 is a view showing an insulating substrate 2 constituting a part of the power semiconductor module 100 of the first embodiment. Specifically, FIG. 2A is a plan view of the insulating substrate 2, FIG. 2B is a vertical sectional view taken along line BB in FIG. 2A, and FIG. It is a bottom view. FIG. 3 is a view showing a state in which the insulating substrate 2 and the like are mounted on the metal heat sink 1. Specifically, in FIG. 3A, an insulating substrate 2 is mounted on a metal heat sink 1, power semiconductor chips (diode chips) 3a and 3b are mounted on the insulating substrate 2, and power semiconductor chips (diode chips). It is the top view which showed the state by which anode electrode plates 4a and 4b, such as an anode PCM (pig iron) plate and an anode molybdenum plate, were mounted on 3a and 3b. 3B is an exploded sectional view taken along the line CC in FIG. 3A, and FIG. 3C is an exploded sectional view taken along the line DD in FIG. 3A.

  FIG. 4 is a view showing a state in which the connection members 5a and 5b are mounted on the assembly shown in FIG. Specifically, FIG. 4A is a plan view showing a state in which the connection members 5a and 5b are mounted on the assembly shown in FIG. 4B is an exploded sectional view taken along line EE in FIG. 4A, and FIG. 4C is an exploded sectional view taken along line FF in FIG. 4A. 5 and 6 are part views of the enclosing case 6 that covers the assembly shown in FIG. Specifically, FIG. 5A is a plan view of the outer case 6, FIG. 5B is a front view of the outer case 6, and FIG. 5C is a bottom view of the outer case 6. 6A is a vertical sectional view taken along line GG in FIG. 5A, and FIG. 6B is a vertical sectional view taken along line HH in FIG.

  FIG. 7 is a view showing a state in which the enclosing case 6 shown in FIGS. 5 and 6 is put on the assembly shown in FIG. 4 (A). Specifically, FIG. 7 (A) is a plan view showing a state where the outer casing 6 shown in FIGS. 5 and 6 is put on the assembly shown in FIG. 4 (A). 7B is an exploded sectional view taken along the line KK in FIG. 7A, and FIG. 7C is an exploded sectional view taken along the line LL in FIG. 7A. FIG. 8 is a component diagram of the lid 7 that covers the assembly shown in FIG. Specifically, FIG. 8A is a plan view of the lid body 7, FIG. 8B is a front view of the lid body 7, and FIG. 8C is a bottom view of the lid body 7. FIG. 9 is a diagram showing the power semiconductor module 100 of the first embodiment. Specifically, FIG. 9A is a plan view of the power semiconductor module 100 of the first embodiment obtained by covering the assembly shown in FIG. 7A with the lid 7 shown in FIG. FIG. FIG. 9B is a schematic vertical sectional view of the power semiconductor module 100 of the first embodiment obtained by bending the upper end portions of the external lead terminals 6a, 6b, 6c shown in FIG. 9A. is there. FIG. 9C is an equivalent circuit diagram of the power semiconductor module 100 of the first embodiment.

  In the power semiconductor module 100 of the first embodiment, as shown in FIGS. 3B and 3C, the heat generated by the power semiconductor chips (diode chips) 3a and 3b (see FIG. 3) is radiated. And a lower surface formed on the lower surface side of the insulating layer 2a (see FIGS. 2 and 3) of the insulating substrate 2 (see FIGS. 2 and 3). Solder 10a (see FIGS. 3B and 3C) between the side conductor pattern 2c (see FIGS. 2B, 2C, 3B, and 3C) Is arranged. Further, as shown in FIG. 3B, the upper surface side conductor pattern 2b1 (see FIGS. 2A, 3A, and 3B) of the insulating substrate 2 (see FIGS. 2 and 3) and Solder 10b1 (see FIG. 3B) is disposed between the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3a (see FIGS. 3A and 3B). Further, as shown in FIG. 3C, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 3A, and 3) of the insulating substrate 2 (see FIGS. 2 and 3). (See (C)) and a solder 10b2 (see FIG. 3 (C)) between the power semiconductor chip (diode chip) 3b (see FIG. 3 (A) and FIG. 3 (C)) and the lower electrode (cathode electrode). Has been placed.

  In the power semiconductor module 100 of the first embodiment, as shown in FIG. 3B, the upper surface electrode (see FIG. 3A and FIG. 3B) of the power semiconductor chip (diode chip) 3a (see FIG. 3A). Solder 10c1 (see FIG. 3B) is disposed between the anode electrode) and the lower surface of the anode electrode plate 4a (see FIGS. 3A and 3B). Further, as shown in FIG. 3C, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3b (see FIGS. 3A and 3C) and the anode electrode plate 4b (FIG. 3C). Solder 10c2 (see FIG. 3C) is disposed between the lower surface of A) and FIG. 3C.

  Furthermore, in the power semiconductor module 100 of the first embodiment, as shown in FIG. 4, connection members 5 a and 5 b formed by, for example, metal material pressing or the like are provided. More specifically, as shown in FIG. 4B, the upper surface of the anode electrode plate 4a (see FIGS. 4A and 4B) and the front lower end 5a2 (see FIG. 4) of the connecting member 5a (see FIG. 4). Solder 10e1 (see FIG. 4B) is arranged between the lower surface of 4 (A) and FIG. 4B). 4C, the upper surface of the anode electrode plate 4b (see FIGS. 4A and 4C) and the rear lower end 5b1 of the connecting member 5b (see FIG. 4) (see FIG. 4). Solder 10d2 (see FIG. 4C) is disposed between the lower surface of (A) and FIG. 4C).

  In the power semiconductor module 100 of the first embodiment, as shown in FIG. 4C, the upper surface side conductor pattern 2b2 (see FIGS. 4A and 4C) of the insulating substrate 2 (see FIG. 4). The solder 10d1 (see FIG. 4C) is disposed between the lower surface of the rear lower end 5a1 (see FIG. 4A and FIG. 4C) of the connection member 5a (see FIG. 4). ing. Further, as shown in FIG. 4B, the upper surface side conductor pattern 2b3 (see FIGS. 4A and 4B) of the insulating substrate 2 (see FIG. 4) and the connection member 5b (see FIG. 4). Solder 10e2 (see FIG. 4B) is disposed between the lower surface of the front lower end 5b2 (see FIGS. 4A and 4B).

  Furthermore, in the power semiconductor module 100 of the first embodiment, as shown in FIGS. 5 and 6, the right side wall 6d (see FIG. 5C), the left side wall 6e (see FIG. 5C), and the front side wall 6f (see FIG. 5 and FIG. 6) and a rear side wall 6g (see FIG. 5 (A), FIG. 5 (C) and FIG. 6 (A)), and is formed by molding an electrically insulating resin material. A surrounding case 6 (see FIGS. 5 and 6) is provided.

  Further, in the power semiconductor module 100 of the first embodiment, as shown in FIG. 6A, the upper end portion 6a1 protruding upward from the rear side wall 6g of the outer case 6 and the rear side wall of the outer case 6 An external lead-out terminal 6a having a central portion 6a2 embedded in 6g and a lower end portion 6a4 protruding downward from the rear side wall 6g of the outer casing 6 is formed by, for example, pressing a metal material.

  Furthermore, in the power semiconductor module 100 of the first embodiment, as shown in FIG. 6A, the upper end portion 6b1 protruding upward from the front side wall 6f of the outer case 6 and the front side wall of the outer case 6 An external lead-out terminal 6b having a central portion 6b2 embedded in 6f and a lower end portion 6b4 protruding downward from the front side wall 6f of the outer casing 6 is formed by, for example, pressing a metal material.

  Further, in the power semiconductor module 100 of the first embodiment, as shown in FIG. 6B, the upper end portion 6c1 protruding upward from the front side wall 6f of the outer case 6 and the front side wall of the outer case 6 An external lead-out terminal 6c having a central portion 6c2 embedded in 6f and a lower end portion 6c4 protruding downward from the front side wall 6f of the outer casing 6 is formed by, for example, press working of a metal material.

  That is, in the power semiconductor module 100 of the first embodiment, as shown in FIGS. 5 (A), 5 (C) and 6 (A), the external lead-out terminal 6a is connected to the rear side wall 6g of the enclosing case 6. Insert molded. In addition, as shown in FIGS. 5A, 5 C, and 6 A, the external lead-out terminal 6 b is insert-molded on the front side wall 6 f of the outer case 6. Further, as shown in FIGS. 5A, 5 C, and 6 B, the external lead-out terminal 6 c is insert-molded on the front side wall 6 f of the outer case 6.

  In the power semiconductor module 100 of the first embodiment, as shown in FIG. 7B, the upper surface side conductor pattern 2b2 (see FIG. 7) of the insulating substrate 2 (see FIGS. 7A and 7B). (See (A) and FIG. 7 (B)) and the lower end portion 6a4 (see FIG. 7 (A) and FIG. 7 (B)) of the external lead-out terminal 6a (see FIG. 7 (A) and FIG. 7 (B)). Solder 10f1 (see FIG. 7B) is disposed between the lower surface, upper surface side conductor pattern 2b2 (see FIGS. 7A and 7B) and external lead-out terminal 6a (see FIG. 7A and FIG. 7). 7B) is electrically connected. Further, as shown in FIG. 7C, the upper surface side conductor pattern 2b1 (see FIGS. 7A and 7C) of the insulating substrate 2 (see FIGS. 7A and 7C) and The solder 10f2 (see FIG. 7C) is disposed between the lower surface of the lower end portion 6b4 (see FIGS. 7A and 7C) of the external lead-out terminal 6b (see FIG. 7A). The upper surface side conductor pattern 2b1 (see FIGS. 7A and 7C) and the external lead-out terminal 6b (see FIG. 7A) are electrically connected. Further, as shown in FIG. 7C, the upper surface side conductor pattern 2b3 (see FIGS. 7A and 7C) of the insulating substrate 2 (see FIGS. 7A and 7C) and The solder 10f3 (see FIG. 7C) is disposed between the lower surface of the lower end portion 6c4 (see FIGS. 7A and 7C) of the external lead-out terminal 6c (see FIG. 7A). The upper surface side conductor pattern 2b3 (see FIGS. 7A and 7C) and the external lead-out terminal 6c (see FIG. 7A) are electrically connected.

  Furthermore, in the power semiconductor module 100 of the first embodiment, a gel resin (not shown) is filled inside the outer casing 6 of the assembly shown in FIG. ) At least the insulating substrate 2 (see FIG. 7), power semiconductor chips (diode chips) 3a and 3b (see FIG. 7), electrode plates 4a and 4b (see FIG. 7), and connecting members 5a and 5b (see FIG. 7). 4 and 9B) and the lower end portions 6a4, 6b4, 6c4 (see FIG. 5C) of the external lead-out terminals 6a, 6b, 6c (see FIGS. 5, 6 and 7A). 6, FIG. 7 (B) and FIG. 7 (C)) are covered. Further, the lid shown in FIG. 8 is put on the assembly shown in FIG. Specifically, when the lid 7 (see FIGS. 8, 9A and 9B) is mounted, as shown in FIG. 9A, the external lead-out terminal 6a (FIG. 7A, FIG. 7 (B) and FIG. 9 (A)) upper end portion 6a1 (see FIG. 6 (A)) is the lead-out hole 7a (see FIG. 8, FIG. 9 (A) and FIG. 9 (B)). 8A and 8C), and the upper end portion 6b1 (see FIG. 6A) of the external lead-out terminal 6b (see FIGS. 7A and 9A) is the lid. 7 (see FIG. 8, FIG. 9A and FIG. 9B) is passed through the lead-out hole 7b (see FIG. 8A and FIG. 8C), and the external lead-out terminal 6c (see FIG. 7A) And the upper end 6c1 (see FIG. 6B) of the lid 7 (see FIGS. 8, 9A, and 9B) is the lead-out hole 7c (see FIG. 8A). ) And FIG. 8 (C)). Next, a nut (not shown) is inserted into the recess 7f (see FIGS. 8A and 9A) on the upper surface of the lid 7 (see FIGS. 8, 9A, and 9B). Is done. Next, upper end portions 6a1, 6b1, 6c1 (see FIGS. 6A and 6B) of external lead-out terminals 6a, 6b, 6c (see FIGS. 7A and 9A) are bent, The power semiconductor module 100 of the first embodiment shown in FIG. 9B is completed.

  That is, in the power semiconductor module 100 of the first embodiment, as shown in FIGS. 9B and 9C, the upper electrode (anode electrode) through which a large current flows and the lower electrode (cathode) through which a large current flows. Power semiconductor chips (diode chips) 3a and 3b having electrodes) are provided. Further, as shown in FIG. 3A, a power semiconductor chip (diode chip) 3a is mounted on the upper surface side conductor pattern 2b1 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Further, as shown in FIG. 3B, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3a are electrically connected. As shown in FIG. 3A, a power semiconductor chip (diode chip) 3b is mounted on the upper surface side conductor pattern 2b2 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Further, as shown in FIG. 3C, the upper surface side conductor pattern 2b2 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3b are electrically connected.

  Moreover, in the power semiconductor module 100 of 1st Embodiment, as shown in FIG. 4, via the connection member 5a (refer FIG. 4) and the electrode plate 4a (refer FIG. 4 (A) and FIG. 4 (B)). The upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3a (see FIGS. 4A and 4B) and the upper surface side conductor pattern 2b2 of the insulating substrate 2 (see FIG. 4) (see FIG. 4A). ) And FIG. 4C) are electrically connected. Furthermore, the power semiconductor chip (diode chip) 3b (FIGS. 4A and 4) is connected via the connecting member 5b (see FIG. 4) and the electrode plate 4b (see FIGS. 4A and 4C). C)) and an upper surface side conductor pattern 2b3 (see FIGS. 4A and 4B) of the insulating substrate 2 (see FIG. 4) are electrically connected.

  Specifically, in the power semiconductor module 100 of the first embodiment, the lower surface side conductor pattern 2c (FIG. 2) of the metal heat sink 1 (see FIGS. 1 and 3) and the insulating substrate 2 (see FIGS. 2 and 3). (B), FIG. 2 (C), FIG. 3 (B), and FIG. 3 (C)) joining with the solder 10a (see FIG. 3 (B) and FIG. 3 (C)), insulating substrate 2 ( The upper surface side conductor pattern 2b1 (see FIG. 2A, FIG. 7A and FIG. 7C) and the external lead terminal 6b (FIG. 5, FIG. 6A) and FIG. (A) and a lower end portion 6b4 (see FIG. 7C) are joined by solder 10f2 (see FIG. 7C), and the upper surface side conductor pattern of the insulating substrate 2 (see FIGS. 2 and 7). 2b2 (see FIGS. 2A, 2B, 7A, and 7B) and the external lead-out terminal 6a (FIGS. 5 and 6) A), bonding by solder 10f1 (see FIG. 7B) to the lower end portion 6a4 (see FIG. 7B) of FIG. 7A and FIG. 7B), insulating substrate 2 (see FIG. 7B). 2 and FIG. 7) and the external lead terminal 6c (FIGS. 5, 6B, and 7) (see FIGS. 2A, 7A, and 7C). A) and the lower end 6c4 (see FIG. 7C) of the soldering member 10f3 (see FIG. 7C), the rear lower end 5a1 (see FIG. 4) of the connecting member 5a (see FIG. 4). (See (A) and FIG. 4 (C)) and the upper surface side conductor pattern 2b2 (see FIG. 2 (A), FIG. 2 (B), FIG. 4 (A) and FIG. 4) of the insulating substrate 2 (see FIG. 2 and FIG. 4). (See FIG. 4C), joining by solder 10d1 (see FIG. 4C), front lower end 5b2 of the connecting member 5b (see FIG. 4) (see FIG. 4A) 4B) and the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4). Joining by solder 10e2 (see FIG. 4B), front lower end 5a2 (see FIGS. 4A and 4B) of connection member 5a (see FIG. 4) and electrode plate 4a (FIG. 3A) 3 (B), FIG. 4 (A) and FIG. 4 (B)) joining by solder 10e1 (see FIG. 4 (B)), lower end of the rear side of the connecting member 5b (see FIG. 4) 5b1 (see FIGS. 4A and 4C) and the electrode plate 4b (see FIGS. 3A, 3C, 4A and 4C) 10d2 (see FIG. 4C), electrode plate 4a (see FIGS. 3A and 3B) and power semiconductor chip (diode chip) 3a (FIG. 3A) And bonding with the upper surface electrode (anode electrode) of FIG. 3B by solder 10c1 (see FIG. 3B), electrode plate 4b (see FIG. 3A and FIG. 3C) and A power semiconductor chip (diode chip) 3b (see FIG. 3C) and a power semiconductor chip (diode chip) 3b (see FIG. 3C) joined to the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3b. Diode chip) 3a (see FIG. 3A and FIG. 3B), the lower surface electrode (cathode electrode) and the upper surface side conductor pattern 2b1 of the insulating substrate 2 (see FIG. 3) (FIG. 3A and FIG. 3). B)) and the lower surface electrode (cathode) of power semiconductor chip (diode chip) 3b (see FIGS. 3A and 3C), and solder 10b1 (see FIG. 3B) Electrode) and insulating substrate 2 (see FIG. 3) Bonding by solder 10b2 (see FIG. 3 (C)) between the top-side conductor pattern 2b2 (see FIG. 3 (A) and FIG. 3 (C)) are performed by the batch process. Further, at the time of performing the solder bonding, the metal follows the concave upper surface of a basing jig (not shown) like the power semiconductor module described in FIG. The metal heat sink 1 (see FIG. 7) is fixed to a basing jig (not shown) such that the lower surface of the heat sink 1 (see FIG. 7) is deformed into a convex shape. Specifically, in the power semiconductor module 100 of the first embodiment, a screw (not shown) for fixing the metal heat radiating plate 1 (see FIG. 7) to a base jig (not shown), The outer case 6 (see FIG. 7) is also fastened together. That is, the assembly in the state shown in FIG. 7A is fixed to a basing jig (not shown) with screws (not shown).

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have made the lower surface conductor pattern 2c (see FIG. 3) of the metal heat sink 1 (see FIG. 3) and the insulating substrate 2 (see FIG. 3). 3 (B) and FIG. 3 (C)) were subjected to a temperature cycle test of the solder joint. Specifically, in the research by the present inventors, the lower surface side conductor pattern 2c (FIGS. 3B and 3C) of the metal heat sink 1 (see FIG. 3) and the insulating substrate 2 (see FIG. 3). A temperature cycle test was performed using Pb (lead) -free solder having a low tensile strength and containing no Sb (antimony). As a result, after the temperature cycle test, between the metal heat sink 1 (see FIG. 3) and the lower surface side conductor pattern 2c (see FIGS. 3B and 3C) of the insulating substrate 2 (see FIG. 3). It was confirmed that the Pb-free solder containing no Sb was peeled off.

  The present inventors have soldered between the metal heat sink 1 (see FIG. 3) and the lower surface side conductor pattern 2c (see FIGS. 3B and 3C) of the insulating substrate 2 (see FIG. 3). In the research by the present inventors, the lower surface side conductor pattern 2c (see FIG. 3B) of the metal heat sink 1 (see FIG. 3) and the insulating substrate 2 (see FIG. 3) is considered. And Pb-free solder (Sn-3.9Ag-0.6Cu-3.0Sb having an alloy composition, for example) having high tensile strength and containing Sb, A temperature cycle test was conducted. As a result, after the temperature cycle test, between the metal heat sink 1 (see FIG. 3) and the lower surface side conductor pattern 2c (see FIGS. 3B and 3C) of the insulating substrate 2 (see FIG. 3). It was confirmed that the Pb-free solder containing Sb was not peeled off.

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b1 (FIG. 2A, FIG. 7) of the insulating substrate 2 (see FIG. 2 and FIG. 7). A) and FIG. 7C)) and a solder joint between the lower end portion 6b4 (see FIG. 7C) of the external lead-out terminal 6b (see FIG. 5, FIG. 6A and FIG. 7A) The temperature cycle test was conducted. Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7). And Sb is contained in the solder joint between the lower end portion 6b4 (see FIG. 7 (C)) of the external lead terminal 6b (see FIG. 5, FIG. 6 (A) and FIG. 7 (A)) A temperature cycle test was conducted using Pb-free solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and the external lead-out terminal 6b. Pb-free solder containing Sb between the lower end 6b4 (see FIG. 7C) of FIG. 5, FIG. 6 (A) and FIG. 7 (A)) is not observed, but the insulating substrate 2 (see FIG. 2 and FIG. 7), it was confirmed that the upper surface side conductor pattern 2b1 (see FIG. 2A, FIG. 7A and FIG. 7C) was damaged.

  Vertical direction (FIG. 6) during the temperature cycle test of the external lead-out terminal 6b (see FIG. 5, FIG. 6 (A) and FIG. 7 (A)) insert-molded in the outer case 6 (see FIG. 5 and FIG. 6). The amount of thermal expansion and contraction in the vertical direction of (A) and the vertical direction during the temperature cycle test of the surrounding case 6 (see FIGS. 5 and 6) made of a resin material (FIG. 6A) Since the thermal expansion amount and thermal contraction amount in the vertical direction are different, the upper surface side conductor pattern 2b1 (FIGS. 2A, 7A, and 7) of the insulating substrate 2 (see FIGS. 2 and 7) is used. C)) and a lower end portion 6b4 (see FIG. 7C) of the external lead-out terminal 6b (see FIGS. 5, 6A, and 7A) have high tensile strength. When Pb-free solder containing Sb is used, the external lead-out terminal 6b (FIGS. 5 and 5) is used during a temperature cycle test. (A) and FIG. 7 (A)) in the vertical direction (vertical direction in FIG. 6 (A)) and the thermal expansion / contraction amount in the vertical direction (see FIG. 5 and FIG. 6) The difference between the thermal expansion amount and the thermal contraction amount in the vertical direction of FIG. 6A cannot be sufficiently absorbed by the deformation of the Pb-free solder containing Sb, and as a result, the insulating substrate 2 (FIG. 2). And the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the upper surface side of the insulating substrate 2 (see FIGS. 2 and 7). The present inventors considered that the side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) was damaged.

  Therefore, in the study by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and external derivation Pb-free that has low tensile strength and does not contain Sb for solder joint with the lower end 6b4 (see FIG. 7C) of the terminal 6b (see FIG. 5, FIG. 6A and FIG. 7A) A temperature cycle test was performed using solder (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.). As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and the external lead-out terminal 6b. Pb-free solder not containing Sb between the lower end 6b4 (see FIG. 7C) of FIG. 5, FIG. 6 (A) and FIG. 7 (A)) does not peel off, and the insulating substrate 2 (FIG. 2 and FIG. 7), it was confirmed that the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) was not damaged.

  In order to meet the recent high reliability requirements for power semiconductor modules, the present inventors have provided the upper surface side conductor pattern 2b2 (FIGS. 2A and 2) of the insulating substrate 2 (see FIGS. 2 and 7). B), FIG. 7 (A) and FIG. 7 (B)) and the lower end 6a4 (see FIG. 5) of the external lead-out terminal 6a (see FIG. 5, FIG. 6 (A), FIG. 7 (A) and FIG. 7 (B)). 7 (B)) was subjected to a temperature cycle test of the solder joint. Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 7A) and FIG. 7B) and the lower end 6a4 (see FIG. 7B) of the external lead-out terminal 6a (see FIGS. 5, 6A, 7A, and 7B). A temperature cycle test was performed using Pb-free solder containing Sb and having a high tensile strength for solder joining. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 2A, 2B, 7A, and 7B) of the insulating substrate 2 (see FIGS. 2 and 7). ) And the external lead terminal 6a (see FIGS. 5, 6A, 7A, and 7B) Pb containing Sb between the lower end 6a4 (see FIG. 7B) Although peeling of free solder is not recognized, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 7A, and 7B) of the insulating substrate 2 (see FIGS. 2 and 7). ))) Was confirmed to be damaged.

  During a temperature cycle test of the external lead-out terminal 6a (see FIGS. 5, 6A, 7A, and 7B) insert-molded in the outer case 6 (see FIGS. 5 and 6) In the vertical direction (the vertical direction in FIG. 6A) and the vertical direction during the temperature cycle test of the outer case 6 (see FIGS. 5 and 6) made of a resin material. Since the thermal expansion amount and thermal contraction amount in the vertical direction (FIG. 6A) are different, the upper surface side conductor pattern 2b2 (FIG. 2A, FIG. 2) of the insulating substrate 2 (see FIGS. 2 and 7). B), FIG. 7 (A) and FIG. 7 (B)) and the lower end 6a4 (see FIG. 5) of the external lead-out terminal 6a (see FIG. 5, FIG. 6 (A), FIG. 7 (A) and FIG. 7 (B)). 7 (B)), when using Pb-free solder containing Sb and having high tensile strength, the temperature cycle During the test, the amount of thermal expansion and contraction in the vertical direction (vertical direction in FIG. 6A) of the external lead-out terminal 6a (see FIGS. 5, 6A, 7A, and 7B) The difference between the amount and the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 6A) of the surrounding case 6 (see FIGS. 5 and 6) is the deformation of the Pb-free solder containing Sb. As a result, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 7A and 7A and 7B) of the insulating substrate 2 (see FIGS. 2 and 7) and FIG. 7B)), the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 7A, and 7) of the insulating substrate 2 (see FIGS. 2 and 7). The present inventors considered that (see (B)) was damaged.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 7A and 7B) of the insulating substrate 2 (see FIGS. 2 and 7). )) And a lower end portion 6a4 (see FIG. 7B) of the external lead-out terminal 6a (see FIGS. 5, 6A, 7A, and 7B). Using a Pb-free solder having a low tensile strength and containing no Sb (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) went. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 2A, 2B, 7A, and 7B) of the insulating substrate 2 (see FIGS. 2 and 7). ) And the external lead terminal 6a (see FIG. 5, FIG. 6 (A), FIG. 7 (A) and FIG. 7 (B)), Pb not containing Sb between the lower end portion 6a4 (see FIG. 7 (B)) The free solder does not peel off, and the upper surface side conductor pattern 2b2 of the insulating substrate 2 (see FIGS. 2 and 7) (see FIGS. 2A, 2B, 7A, and 7B) Was confirmed not to break.

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b3 (FIG. 2A, FIG. 7) of the insulating substrate 2 (see FIG. 2 and FIG. 7). A) and FIG. 7 (C)) and a solder joint between the lower end portion 6c4 (see FIG. 7 (C)) of the external lead terminal 6c (see FIG. 5, FIG. 6 (B) and FIG. 7 (A)). The temperature cycle test was conducted. Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7). And Sb is contained in the solder joint between the lower end portion 6c4 (see FIG. 7C) of the external lead terminal 6c (see FIG. 5, FIG. 6B and FIG. 7A) A temperature cycle test was conducted using Pb-free solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and the external lead-out terminal 6c. Pb-free solder containing Sb between the lower end 6c4 (see FIG. 7C) of FIG. 5, FIG. 6B and FIG. 7A is not observed, but the insulating substrate 2 (see FIG. 2 and FIG. 7), it was confirmed that the upper surface side conductor pattern 2b3 (see FIG. 2A, FIG. 7A and FIG. 7C) was damaged.

  Up and down direction (FIG. 6) at the time of a temperature cycle test of the external lead-out terminal 6c (see FIG. 5, FIG. 6 (B) and FIG. 7 (A)) insert-molded in the outer case 6 (see FIG. 5 and FIG. 6). (B) vertical direction) thermal expansion / shrinkage amount and vertical direction during temperature cycle test of the surrounding case 6 (see FIGS. 5 and 6) made of resin material (FIG. 6B) Since the thermal expansion amount and thermal contraction amount in the vertical direction are different, the upper surface side conductor pattern 2b3 (FIGS. 2A, 7A, and 7) of the insulating substrate 2 (see FIGS. 2 and 7) is used. C)) and a lower end portion 6c4 (see FIG. 7C) of the external lead-out terminal 6c (see FIGS. 5, 6B, and 7A) have high tensile strength. When Pb-free solder containing Sb is used, the external lead-out terminal 6c (FIGS. (B) and FIG. 7A)) in the vertical direction (vertical direction in FIG. 6B) and the vertical direction of the outer case 6 (see FIG. 5 and FIG. 6) The difference between the thermal expansion amount and the thermal contraction amount in the vertical direction of FIG. 6B cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb, and as a result, the insulating substrate 2 (FIG. 2). And the upper surface of the insulating substrate 2 (see FIGS. 2 and 7) due to the thermal stress applied to the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C). The present inventors considered that the side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) was damaged.

  Therefore, in the studies by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and the external derivation. Pb-free that has low tensile strength and does not contain Sb for solder joint with the lower end 6c4 (see FIG. 7C) of the terminal 6c (see FIGS. 5, 6B, and 7A) A temperature cycle test was performed using solder (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.). As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and the external lead-out terminal 6c. Pb-free solder not containing Sb between the lower end 6c4 (see FIG. 7C) of FIG. 5, FIG. 6B and FIG. 7A does not peel off, and the insulating substrate 2 (FIG. 2 and FIG. 7), it was confirmed that the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) was not damaged.

  In order to meet the recent high reliability requirements for power semiconductor modules, the present inventors have provided the upper surface side conductor pattern 2b2 (FIGS. 2A and 2) of the insulating substrate 2 (see FIGS. 2 and 4). B), solder between FIG. 4 (A) and FIG. 4 (C)) and rear lower end portion 5a1 (see FIG. 4 (A) and FIG. 4 (C)) of the connecting member 5a (see FIG. 4). A bonding temperature cycle test was conducted. Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 4A, and 4) of the insulating substrate 2 (see FIGS. 2 and 4) and FIG. 4 (C)) and the lower end portion 5a1 of the connecting member 5a (see FIG. 4) (see FIGS. 4 (A) and 4 (C)), Sb having high tensile strength is used. A temperature cycle test was performed using the contained Pb-free solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 2A, 2B, 4A, and 4C) of the insulating substrate 2 (see FIGS. 2 and 4). ) And the rear lower end portion 5a1 of the connecting member 5a (see FIG. 4) (see FIGS. 4A and 4C), the Pb-free solder containing Sb is not peeled off but is insulated. It is confirmed that the upper surface side conductor pattern 2b2 (see FIGS. 2A, 2B, 4A, and 4C) of the substrate 2 (see FIGS. 2 and 4) is damaged. It was done.

  Thermal expansion amount / heat in the vertical direction during the temperature cycle test of the connecting member 5a (see FIGS. 4 and 9B) covered with the gel-like resin in the outer case 6 (see FIG. 9B) Since the amount of shrinkage differs from the amount of thermal expansion / shrinkage in the vertical direction during the temperature cycle test of the gel resin, the upper surface side conductor pattern 2b2 (see FIG. 2A) of the insulating substrate 2 (see FIGS. 2 and 4). ), FIG. 2 (B), FIG. 4 (A) and FIG. 4 (C)) and the rear lower end 5a1 (FIG. 4 (A) and FIG. 4) of the connecting member 5a (see FIG. 4 and FIG. 9 (B)). 4 (C)), when Pb-free solder containing Sb and having high tensile strength is used, the connecting member 5a (see FIGS. 4 and 9B) is used during a temperature cycle test. The difference between the amount of thermal expansion and contraction in the vertical direction and the amount of thermal expansion and contraction in the vertical direction of the gel resin The Pb-free solder containing Sb cannot be sufficiently absorbed by deformation, and as a result, the upper surface side conductor pattern 2b2 (FIGS. 2A and 2B) of the insulating substrate 2 (see FIGS. 2 and 4). ) And FIG. 4 (A) and FIG. 4 (C)), the upper surface side conductor pattern 2b2 (FIG. 2 (A) and FIG. 2 (B)) of the insulating substrate 2 (see FIG. 2 and FIG. 4). The present inventors considered that FIG. 4 (A) and FIG. 4 (C)) were damaged.

  Therefore, in the study by the present inventors, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 4A, and 4C) of the insulating substrate 2 (see FIGS. 2 and 4). )) And the rear lower end 5a1 of the connecting member 5a (see FIGS. 4 and 9B) (see FIGS. 4A and 4C), the tensile strength is low. A temperature cycle test was performed using Pb-free solder containing no Sb (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.). As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 2A, 2B, 4A, and 4C) of the insulating substrate 2 (see FIGS. 2 and 4). ) And the connecting member 5a (see FIGS. 4 and 9B) and the rear lower end 5a1 (see FIGS. 4A and 4C) of Pb-free solder containing no Sb is peeled off. In addition, the upper surface side conductor pattern 2b2 (see FIGS. 2A, 2B, 4A, and 4C) of the insulating substrate 2 (see FIGS. 2 and 4) may not be damaged. confirmed.

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b3 (FIG. 2A, FIG. 4) of the insulating substrate 2 (see FIG. 2 and FIG. 4). A) and a temperature cycle test of a solder joint between the front lower end portion 5b2 (see FIGS. 4A and 4B) of the connection member 5b (see FIG. 4) is performed. It was. Specifically, in the research conducted by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4). Pb-free solder having high tensile strength and containing Sb is used for solder joining between the front end 5b2 (see FIGS. 4A and 4B) of the connecting member 5b (see FIG. 4) A temperature cycle test was conducted. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4) and the connection member 5b (see FIG. 2). Pb-free solder containing Sb between the front lower end portion 5b2 (see FIG. 4A and FIG. 4B) of FIG. 4) is not observed, but the insulating substrate 2 (see FIG. 2 and FIG. 2) 4) (see FIG. 4), it was confirmed that the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) was damaged.

  Thermal expansion amount / heat in the vertical direction during the temperature cycle test of the connecting member 5b (see FIGS. 4 and 9B) covered with the gel-like resin in the outer case 6 (see FIG. 9B) Since the amount of shrinkage differs from the amount of thermal expansion / shrinkage in the vertical direction during the temperature cycle test of the gel-like resin, the upper surface side conductor pattern 2b3 (see FIG. 2A) of the insulating substrate 2 (see FIGS. 2 and 4). ), FIG. 4 (A) and FIG. 4 (B)) and the front lower end 5b2 of the connecting member 5b (see FIG. 4 and FIG. 9 (B)) (see FIG. 4 (A) and FIG. 4 (B)). When Pb-free solder containing Sb and having high tensile strength is used for the solder joint between the two, the thermal expansion amount in the vertical direction of the connecting member 5b (see FIGS. 4 and 9B) during the temperature cycle test The difference between the amount of thermal shrinkage and the amount of thermal expansion / shrinkage in the vertical direction of the gel resin contains Sb. As a result, the upper surface side conductor pattern 2b3 (FIGS. 2A, 4A and 4) of the insulating substrate 2 (see FIGS. 2 and 4) cannot be absorbed sufficiently by the deformation of the Pb-free solder. 4B)), the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4) is caused. The inventors thought it was damaged.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4) and the connection member. 5b (see FIG. 4 and FIG. 9B) Pb-free with low tensile strength and no Sb for solder joint with the front lower end 5b2 (see FIG. 4A and FIG. 4B) A temperature cycle test was performed using solder (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.). As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4) and the connection member 5b (see FIG. 2). Pb-free solder that does not contain Sb between the front lower end 5b2 (see FIGS. 4A and 4B) of FIG. 4 and FIG. 9B) does not peel off, and the insulating substrate 2 (FIG. 2 and FIG. 4), it was confirmed that the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) was not damaged.

  In view of the research results of the present inventors, in the power semiconductor module 100 of the first embodiment, the lower surface side of the metal heat sink 1 (see FIGS. 1 and 3) and the insulating substrate 2 (see FIGS. 2 and 3). Pb-free solder 10a containing Sb (see FIG. 3 (B)) for solder joint with the conductor pattern 2c (see FIG. 2 (B), FIG. 2 (C), FIG. 3 (B) and FIG. 3 (C)). ) And FIG. 3 (C)).

  Therefore, according to the power semiconductor module 100 of the first embodiment, the lower surface side conductors of the metal heat sink 1 (see FIGS. 1 and 3) and the insulating substrate 2 (see FIGS. 2 and 3) after the temperature cycle test. Peeling of solder 10a (see FIGS. 3B and 3C) between pattern 2c (see FIGS. 2B, 2C, 3B, and 3C) The lower surface side conductor pattern 2c (FIGS. 2B and 2C) of the metal heat sink 1 (see FIGS. 1 and 3) and the insulating substrate 2 (see FIGS. 2 and 3). 3B and FIG. 3C), it is possible to improve the reliability of the solder joint.

  Furthermore, in the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7). ) And a lower end portion 6b4 (see FIGS. 7A and 7C) of the external lead-out terminal 6b (see FIG. 7A), Pb-free solder 10a containing Sb (see FIG. 7A). 3 (B) and Pb-free solder 10f2 (see FIG. 7C) that does not contain Sb and has a tensile strength lower than that of FIG. 3C is used.

  Therefore, according to the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b1 (FIGS. 2A and 7A) of the insulating substrate 2 (see FIGS. 2 and 7) after the temperature cycle test. And the solder 10f2 between the lower end portion 6b4 (see FIGS. 7A and 7C) of the external lead terminal 6b (see FIG. 7A) (see FIG. 7C). )) And the damage of the upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) at the same time. The upper surface side conductor pattern 2b1 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and the external lead-out terminal 6b (see FIG. 7A) )) At the lower end 6b4 (see FIGS. 7A and 7C) Can be improved-reliability.

  In the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 7A) and 7A of the insulating substrate 2 (see FIGS. 2 and 7) and Solder joint between the lower end portion 6a4 (see FIGS. 7A and 7B) of the external lead-out terminal 6a (see FIGS. 7A and 7B)) In addition, Pb-free solder 10f1 (see FIG. 7B) that does not contain Sb and has a lower tensile strength than Pb-free solder 10a containing Sb (see FIGS. 3B and 3C) is used. ing.

  Therefore, according to the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b2 (FIGS. 2A and 2B) of the insulating substrate 2 (see FIGS. 2 and 7) after the temperature cycle test. 7A and 7B) and the lower end 6a4 of the external lead-out terminal 6a (see FIGS. 7A and 7B) (see FIGS. 7A and 7B). ) And the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, and 7) of the insulating substrate 2 (see FIGS. 2 and 7). (A) and FIG. 7 (B)) can be avoided at the same time, and the upper surface side conductor pattern 2b2 (FIG. 2 (A), FIG. 2 (B)) of the insulating substrate 2 (see FIG. 2 and FIG. 7). 7A and 7B) and external lead-out terminal 6a (see FIGS. 7A and 7B). It is possible to improve the reliability of the solder joint between the lower end 6a4 (see FIG. 7 (A) and FIG. 7 (B)).

  Furthermore, in the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7). ) And a lower end portion 6c4 (see FIGS. 7A and 7C) of the external lead-out terminal 6c (see FIG. 7A), Pb-free solder 10a containing Sb (see FIG. 7A). Pb-free solder 10f3 (see FIG. 7C) that does not contain Sb and has a tensile strength lower than that of 3B and 3C) is used.

  Therefore, according to the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b3 (FIGS. 2A and 7A) of the insulating substrate 2 (see FIGS. 2 and 7) after the temperature cycle test. And the solder 10f3 (see FIG. 7C) between the lower end portion 6c4 (see FIGS. 7A and 7C) of the external lead-out terminal 6c (see FIG. 7A). )) And the damage of the upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) at the same time. The upper surface side conductor pattern 2b3 (see FIGS. 2A, 7A, and 7C) of the insulating substrate 2 (see FIGS. 2 and 7) and the external lead-out terminal 6c (see FIG. 7A) ))) At the lower end 6c4 (see FIG. 7A and FIG. 7C) Can be improved-reliability.

  In the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 4A) and 4A of the insulating substrate 2 (see FIGS. Pb-free containing Sb for solder joint between the lower end 5a1 (see FIGS. 4A and 4C) of the connection member 5a (see FIG. 4C) and the rear lower end 5a1 of the connecting member 5a (see FIG. 4) Pb-free solder 10d1 (see FIG. 4C) that does not contain Sb and has a lower tensile strength than the solder 10a (see FIGS. 3B and 3C) is used.

  Therefore, according to the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b2 (FIGS. 2A and 2B) of the insulating substrate 2 (see FIGS. 2 and 4) after the temperature cycle test. 4A and 4C) and a solder 10d1 (see FIGS. 4A and 4C) between the rear lower end 5a1 of the connecting member 5a (see FIG. 4) (see FIGS. 4A and 4C). 4C) and the upper surface side conductor pattern 2b2 of the insulating substrate 2 (see FIGS. 2 and 4) (FIGS. 2A, 2B, 4A, and 4C). )) Can be avoided at the same time, and the upper surface side conductor pattern 2b2 (FIGS. 2A, 2B, 4A and 4) of the insulating substrate 2 (see FIGS. 2 and 4) and FIG. 4 (C)) and rear lower end 5a1 of the connecting member 5a (see FIG. 4) (FIG. 4 (A) and FIG. 4 (C)). It is possible to improve the reliability of the solder joint between the irradiation).

  Furthermore, in the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4). ) And the front lower end 5b2 of the connecting member 5b (see FIG. 4) (see FIGS. 4A and 4B), Pb-free solder 10a containing Sb (see FIG. 3B) ) And Pb-free solder 10e2 (see FIG. 4B) that does not contain Sb and has a lower tensile strength than that of FIG. 3C.

  Therefore, according to the power semiconductor module 100 of the first embodiment, the upper surface side conductor pattern 2b3 (FIGS. 2A and 4A) of the insulating substrate 2 (see FIGS. 2 and 4) after the temperature cycle test. And the solder 10e2 (see FIG. 4 (B)) between the connecting member 5b (see FIG. 4) and the front lower end 5b2 (see FIGS. 4 (A) and 4 (B)). Peeling of the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4) can be avoided at the same time, Front-side lower end portion of the upper surface side conductor pattern 2b3 (see FIGS. 2A, 4A, and 4B) of the insulating substrate 2 (see FIGS. 2 and 4) and the connection member 5b (see FIG. 4) Improves the reliability of solder joints with 5b2 (see FIGS. 4A and 4B) It can be.

  In the power semiconductor module 100 of the first embodiment, the solders 10b1 and 10c1 (see FIG. 3B) are more than the Pb-free solder 10a containing Sb (see FIGS. 3B and 3C). A Pb-free solder having a low tensile strength and containing no Sb is used, but in the modification of the power semiconductor module 100 of the first embodiment, instead of the solders 10b1 and 10c1 (see FIG. 3B). Similarly to the solder 10a (see FIGS. 3B and 3C), it is also possible to use Pb-free solder containing Sb having high tensile strength.

  In the power semiconductor module 100 of the first embodiment, Pb-free solder 10a containing Sb (see FIGS. 3B and 3C) is used as the solders 10b2 and 10c2 (see FIG. 3C). Pb-free solder having a lower tensile strength than Sb is used, but in the modified example of the power semiconductor module 100 of the first embodiment, instead of the solders 10b2 and 10c2 (see FIG. 3C) ), It is also possible to use a Pb-free solder containing Sb and having a high tensile strength like the solder 10a (see FIGS. 3B and 3C).

  Furthermore, in the power semiconductor module 100 of the first embodiment, the solder 10e1 (see FIG. 4B) is more than the Pb-free solder 10a containing Sb (see FIGS. 3B and 3C). A Pb-free solder having a low tensile strength and containing no Sb is used. However, in the modified example of the power semiconductor module 100 of the first embodiment, instead of the solder 10e1 (see FIG. 4B), a solder is used. Similarly to 10a (see FIGS. 3B and 3C), it is also possible to use Pb-free solder containing Sb having high tensile strength.

  In the power semiconductor module 100 of the first embodiment, the solder 10d2 (see FIG. 4C) is more than the Pb-free solder 10a containing Sb (see FIGS. 3B and 3C). Pb-free solder having a low tensile strength and containing no Sb is used. However, in the modified example of the power semiconductor module 100 of the first embodiment, instead of the solder 10d2 (see FIG. 4C), a solder is used. Similarly to 10a (see FIGS. 3B and 3C), it is also possible to use Pb-free solder containing Sb having high tensile strength.

  Hereinafter, a second embodiment of the power semiconductor module of the present invention will be described. FIG. 10 is a view showing a metal heat radiating plate 1 constituting a part of the power semiconductor module 100 of the second embodiment. Specifically, FIG. 10 (A) is a plan view of the metal heat sink 1 and FIG. 10 (B) is a vertical sectional view taken along the line A1-A1 of FIG. 10 (A). FIG. 11 is a view showing an insulating substrate 2 constituting a part of the power semiconductor module 100 of the second embodiment. Specifically, FIG. 11A is a plan view of the insulating substrate 2, FIG. 11B is a vertical sectional view taken along line B1-B1 of FIG. 11A, and FIG. It is a bottom view. FIG. 12 is a diagram showing a state where the insulating substrate 2 and the like are mounted on the metal heat sink 1. Specifically, in FIG. 12A, the insulating substrate 2 is mounted on the metal heat sink 1, the power semiconductor chip (diode chip) 3a is mounted on the insulating substrate 2, and the power semiconductor chip (diode chip) 3a is mounted. 2 is a plan view showing a state where an anode electrode plate 4a such as an anode PCM (pig iron) plate, an anode molybdenum plate, or the like is mounted. FIG. 12B is an exploded sectional view taken along line C1-C1 in FIG.

  FIG. 13 is a view showing a state in which the connection members 5a and 5a 'are mounted on the assembly shown in FIG. Specifically, FIG. 13A is a plan view showing a state in which the connection members 5a and 5a 'are mounted on the assembly shown in FIG. 13B is an exploded sectional view taken along line E1-E1 in FIG. 13A, and FIG. 13C is an exploded sectional view taken along line F1-F1 in FIG. FIG. 14 and FIG. 15 are diagrams showing how the external lead-out terminals 6a and 6b are mounted on the assembly shown in FIG. Specifically, FIG. 14 is a plan view showing a state where the external lead-out terminals 6a and 6b are mounted on the assembly shown in FIG. FIG. 15A is an exploded sectional view taken along line G1-G1 in FIG. 14, and FIG. 15B is an exploded sectional view taken along line H1-H1 in FIG. 16 and 17 are component diagrams of the enclosing case 6 that covers the assembly shown in FIG. Specifically, FIG. 16A is a plan view of the outer case 6, and FIG. 16B is a front view of the outer case 6. 17A is a vertical cross-sectional view taken along line K1-K1 in FIG. 16A, and FIG.

  18 is a component diagram of the lid body 7 that covers the outer casing 6 shown in FIGS. 16 and 17 that covers the assembly shown in FIG. Specifically, FIG. 18A is a plan view of the lid 7, FIG. 18B is a front view of the lid 7, and FIG. 18C is a bottom view of the lid 7. FIG. 19 is a diagram showing a power semiconductor module 100 according to the second embodiment. Specifically, in FIG. 19A, the outer casing 6 shown in FIGS. 16 and 17 is put on the assembly shown in FIG. 14, and then the lid 7 shown in FIG. 18 is put. It is a top view of the power semiconductor module 100 of 2nd Embodiment obtained by these. FIG. 19B is a schematic vertical sectional view of the power semiconductor module 100 of the second embodiment. FIG. 19C is an equivalent circuit diagram of the power semiconductor module 100 of the second embodiment.

  In the power semiconductor module 100 of the second embodiment, as shown in FIG. 12B, a metal heat radiating plate 1 (for dissipating heat generated by the power semiconductor chip (diode chip) 3a (see FIG. 12)) ( 10 and FIG. 12) and a lower surface side conductor pattern 2c (FIG. 11 (FIG. 11) formed on the lower surface side of the insulating layer 2a (see FIGS. 11 and 12) of the insulating substrate 2 (see FIGS. 11 and 12). B) and solder 10a (see FIG. 12B) are arranged between FIG. 11C and FIG. 12B. Further, as shown in FIG. 12B, the upper surface side conductor pattern 2b1 (see FIGS. 11A, 12A, and 12B) of the insulating substrate 2 (see FIGS. 11 and 12) and Solder 10b1 (see FIG. 12B) is disposed between the lower surface electrode (cathode electrode) of power semiconductor chip (diode chip) 3a (see FIGS. 12A and 12B).

  In the power semiconductor module 100 of the second embodiment, as shown in FIG. 12B, the upper surface electrode (see FIG. 12A and FIG. 12B) of the power semiconductor chip (diode chip) 3a (see FIG. 12A). Solder 10c1 (see FIG. 12B) is disposed between the anode electrode) and the lower surface of the anode electrode plate 4a (see FIGS. 12A and 12B).

  Furthermore, in the power semiconductor module 100 of the second embodiment, as shown in FIG. 13, connection members 5a and 5a 'formed by, for example, metal material pressing or the like are provided. Specifically, as shown in FIG. 13B, the upper surface of the anode electrode plate 4a (see FIGS. 13A and 13B) and the connecting member 5a (FIGS. 13A and 13B). The solder 10e1 (see FIG. 13B) is disposed between the lower surface of the right lower end portion 5a2 (see FIG. 13A and FIG. 13B). Further, as shown in FIG. 13C, the upper surface of the anode electrode plate 4a (see FIGS. 13A and 13C) and the connecting member 5a ′ (see FIGS. 13A and 13C). The solder 10e1 ′ (see FIG. 13C) is disposed between the lower end of the right lower end 5a2 ′ (see FIG. 13A and FIG. 13C).

  In the power semiconductor module 100 of the second embodiment, as shown in FIG. 13B, the upper surface side conductor pattern 2b2 (FIGS. 13A and 13B) of the insulating substrate 2 (see FIG. 13). 10d1 (see FIG. 13) between the lower end portion 5a1 (see FIGS. 13A and 13B) on the left side of the connecting member 5a (see FIGS. 13A and 13B) (See (B)). Further, as shown in FIG. 13C, the upper surface side conductor pattern 2b2 (see FIGS. 13A and 13C) of the insulating substrate 2 (see FIG. 13) and the connecting member 5a ′ (see FIG. 13A). ) And FIG. 13 (C)), the solder 10d1 ′ (see FIG. 13 (B)) is disposed between the lower surface of the left lower end 5a1 ′ (see FIG. 13 (A) and FIG. 13 (C)). Yes.

  Furthermore, in the power semiconductor module 100 of the second embodiment, as shown in FIGS. 14 and 15, an upper end 6a1 extending in the up-down direction (up-down direction in FIG. 15), and branched from the upper end 6a1 and bent. The external lead-out terminals 6a having the center portions 6a2 and 6a2 ′ and the lower end portions 6a4 and 6a4 ′ extending in the horizontal direction (left and right direction in FIG. 15) are formed by, for example, pressing a metal material. . Further, in the power semiconductor module 100 of the second embodiment, as shown in FIGS. 14 and 15, an upper end portion 6b1 extending in the vertical direction (the vertical direction in FIG. 15), and a branch from the upper end portion 6b1 and bending. The outer lead-out terminals 6b having the center portions 6b2 and 6b2 ′ and the lower end portions 6b4 and 6b4 ′ extending in the horizontal direction (left and right direction in FIG. 15) are formed by, for example, pressing a metal material. .

  In the power semiconductor module 100 of the second embodiment, as shown in FIGS. 14 and 15A, the upper surface side conductor pattern 2b2 (see FIG. 14) of the insulating substrate 2 (see FIGS. 14 and 15A). 15A) and the lower surface of the lower end portion 6a4 (see FIG. 15A) of the external lead terminal 6a (see FIG. 15A), the solder 10f1 (see FIG. 15A). )) Is arranged. Further, as shown in FIGS. 14 and 15B, the upper surface side conductor pattern 2b2 (see FIGS. 14 and 15B) of the insulating substrate 2 (see FIGS. 14 and 15B) and external derivation Solder 10f1 ′ (see FIG. 15B) is disposed between the lower surface of the lower end portion 6a4 ′ (see FIG. 15B) of the terminal 6a (see FIG. 14 and FIG. 15B). As a result, the upper surface side conductor pattern 2b2 (see FIGS. 14 and 15) and the external lead-out terminal 6a (see FIGS. 14 and 15) are electrically connected.

  Furthermore, in the power semiconductor module 100 of the second embodiment, as shown in FIGS. 14 and 15A, the upper surface side conductor pattern 2b1 (see FIG. 14) of the insulating substrate 2 (see FIGS. 14 and 15A). 15f) and the lower surface of the lower end portion 6b4 (see FIG. 15A) of the external lead-out terminal 6b (see FIG. 14A), the solder 10f2 (see FIG. 15A). )) Is arranged. Further, as shown in FIGS. 14 and 15B, the upper surface side conductor pattern 2b1 (see FIGS. 14 and 15B) of the insulating substrate 2 (see FIGS. 14 and 15B) and external derivation Solder 10f2 ′ (see FIG. 15B) is disposed between the lower surface of the lower end 6b4 ′ (see FIG. 15B) of the terminal 6b (see FIG. 14 and FIG. 15B). As a result, the upper surface side conductor pattern 2b1 (see FIGS. 14 and 15) and the external lead-out terminal 6b (see FIGS. 14 and 15) are electrically connected.

  In the power semiconductor module 100 of the second embodiment, as shown in FIGS. 16 and 17, the right side wall 6d (see FIGS. 17A and 17B) and the left side wall 6e (FIG. 17A). ) And FIG. 17B), a front side wall 6f (see FIG. 16B and FIG. 17B), and a rear side wall 6g (see FIG. 17A and FIG. 17B), An outer case 6 (see FIGS. 16 and 17) formed by molding an electrically insulating resin material is provided. Specifically, the outer case 6 (see FIGS. 16, 17, 19A, and 19B) is put on the assembly shown in FIG.

  That is, the power of the first embodiment in which the external lead-out terminals 6a and 6b (see FIGS. 5 and 6A) are inserted and formed integrally with the outer case 6 (see FIGS. 5 and 6). Unlike the semiconductor module 100 (see FIG. 9), in the power semiconductor module 100 of the second embodiment, as shown in FIGS. 14 to 17, external lead-out terminals 6a and 6b (see FIGS. 14 and 15) It is not inserted into the outer case 6 (see FIGS. 16 and 17), and is configured as a separate member from the outer case 6 (see FIGS. 16 and 17).

  Furthermore, in the power semiconductor module 100 of the second embodiment, a gel-like resin (not shown) is filled inside the outer casing 6 that covers the assembly shown in FIG. Specifically, gel resin (not shown) is filled up to the height HT indicated by the broken line in FIG. In other words, the insulating substrate 2 (see FIG. 19B), the power semiconductor chip (diode chip) 3a (see FIG. 19B), and the electrode plate 4a (see FIG. 19B) are made of gel resin (not shown). B)), connecting members 5a, 5a ′ (see FIGS. 13 and 19B), and lower end portions 6a4 of external lead-out terminals 6a, 6b (see FIGS. 14, 15 and 19B). 6a4 ′, 6b4, 6b4 ′ (see FIGS. 15A and 15B) and the central portions 6a2, 6a2 ′, 6b2, 6b2 ′ (see FIGS. 15A and 15B) are covered. It has been broken. Further, an epoxy resin (not shown) is placed on the inner side of the surrounding case 6 covered on the assembly shown in FIG. 14 and above the height HT indicated by a broken line in FIG. 19B. Filled. Further, as shown in FIGS. 19A and 19B, the cover body 7 shown in FIG. 18 is put on the outer case 6 (see FIGS. 19A and 19B). ing. Specifically, when the lid 7 (see FIGS. 18, 19A and 19B) is mounted, as shown in FIG. 19A, the external lead-out terminal 6a (FIGS. 14, 15, and FIG. 19 (A) and FIG. 19 (B)) is provided at the upper end 6a1 (see FIG. 15) of the lead-out hole 7a (see FIG. 18 (FIG. 18 (B)). A), see FIG. 18C and FIG. 19A). Further, the upper end portion 6b1 (see FIG. 15) of the external lead-out terminal 6b (see FIGS. 14, 15, 19A and 19B) is the lid 7 (see FIGS. 18, 19A and 19). 19 (B)) through the lead-out hole 7b (see FIG. 18 (A), FIG. 18 (C) and FIG. 19 (A)). Next, a nut (not shown) is inserted into the recess 7f (see FIGS. 18A and 19A) on the upper surface of the lid 7 (see FIGS. 18, 19A, and 19B). Is done. Next, the upper end portions 6a1 and 6b1 (see FIG. 15) of the external lead-out terminals 6a and 6b (see FIGS. 14, 15, 19A and 19B) are bent, and the power of the second embodiment The semiconductor module 100 is completed.

  That is, in the power semiconductor module 100 of the second embodiment, as shown in FIGS. 19B and 19C, the upper electrode (anode electrode) through which a large current flows and the lower electrode (cathode) through which a large current flows. A power semiconductor chip (diode chip) 3a having an electrode) is provided. As shown in FIG. 12A, a power semiconductor chip (diode chip) 3a is mounted on the upper surface side conductor pattern 2b1 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Furthermore, as shown in FIG. 12B, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3a are electrically connected.

  Further, in the power semiconductor module 100 of the second embodiment, as shown in FIG. 13, the connection member 5a (see FIGS. 13A and 13B) and the electrode plate 4a (FIG. 13A and FIG. 13 (B)) through the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3a (see FIG. 13 (A)) and the upper surface side conductor pattern 2b2 (see FIG. 13) of the insulating substrate 2 (see FIG. 13). 13 (A) and FIG. 13 (B)) are electrically connected. Further, the power semiconductor chip (diode chip) 3a is connected via the connecting member 5a ′ (see FIGS. 13A and 13C) and the electrode plate 4a (see FIGS. 13A and 13C). The upper surface electrode (anode electrode) (see FIG. 13A) and the upper surface side conductor pattern 2b2 (see FIGS. 13A and 13C) of the insulating substrate 2 (see FIG. 13) are electrically connected. Has been.

  Specifically, in the power semiconductor module 100 of the second embodiment, the lower surface side conductor pattern 2c (FIG. 11) of the metal heat sink 1 (see FIGS. 10 and 12) and the insulating substrate 2 (see FIGS. 11 and 12). (B), bonding with solder 10a (see FIG. 12B) between FIG. 11 (C) and FIG. 12 (B)), upper surface of insulating substrate 2 (see FIG. 11, FIG. 14 and FIG. 15) Solder 10f2 between the side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) and the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the external lead terminal 6b (see FIGS. 14 and 15) 10f2 ′ (see FIG. 15), the upper surface side conductor pattern 2b2 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead-out terminal 6a (see FIG. 11). See FIG. 14 and FIG. The lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the solder joints by solders 10f1 and 10f1 ′ (see FIG. 15), the left lower end portions 5a1 and 5a1 ′ (see FIG. 13) of the connecting members 5a and 5a ′ (see FIG. 13). 13) and the solder 10d1, 10d1 ′ (see FIGS. 13B and 13) between the upper surface side conductor pattern 2b2 (see FIGS. 11A and 13) of the insulating substrate 2 (see FIGS. 11 and 13). (See (C)), the right lower ends 5a2 and 5a2 '(see FIG. 13) of the connecting members 5a and 5a' (see FIG. 13) and the electrode plate 4a (see FIGS. 12A and 12B) and FIG. 13) and solder electrode 10a1, 10e1 ′ (see FIG. 13), electrode plate 4a (see FIGS. 12A and 12B) and power semiconductor chip (diode chip) 3a (see FIG. 12). A) and FIG. Between the upper surface electrode (see FIG. 12B) and the power semiconductor chip (diode chip) 3a (see FIG. 12 (A) and FIG. 12 (B)). Solder 10b1 (see FIG. 12 (B)) between the lower surface electrode (cathode electrode) and the upper surface side conductor pattern 2b1 (see FIGS. 12 (A) and 12 (B)) of the insulating substrate 2 (see FIG. 12). The joining by is performed by batch processing. Further, at the time of performing the solder bonding, the metal follows the concave upper surface of the basing jig (not shown) like the power semiconductor module described in FIG. 3 of Patent Document 1 (Japanese Patent Laid-Open No. 2010-199251). The metal heat radiating plate 1 (see FIGS. 10, 14 and 15) is a basing jig (not shown) so that the lower surface of the heat radiating plate 1 (see FIGS. 10, 14 and 15) is deformed into a convex shape. Fixed against.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have made the lower surface side conductor pattern 2c (see FIG. 12) of the metal heat sink 1 (see FIG. 12) and the insulating substrate 2 (see FIG. 12). 12 (B)) was subjected to a temperature cycle test of solder bonding. Specifically, in the research by the present inventors, between the metal heat sink 1 (see FIG. 12) and the lower surface side conductor pattern 2c (see FIG. 12B) of the insulating substrate 2 (see FIG. 12). A temperature cycle test was performed using Pb (lead) -free solder having a low tensile strength and containing no Sb (antimony) for solder bonding. As a result, Pb not containing Sb between the metal heat sink 1 (see FIG. 12) and the lower surface side conductor pattern 2c (see FIG. 12B) of the insulating substrate 2 (see FIG. 12) after the temperature cycle test. It was confirmed that the free solder was peeled off.

  The present inventors have insufficient solder tensile strength between the metal heat sink 1 (see FIG. 12) and the lower surface side conductor pattern 2c (see FIG. 12B) of the insulating substrate 2 (see FIG. 12). In the research conducted by the present inventors, between the metal heat sink 1 (see FIG. 12) and the lower surface side conductor pattern 2c (see FIG. 12B) of the insulating substrate 2 (see FIG. 12). A temperature cycle test was carried out using Pb-free solder (alloy composition such as Sn-3.9Ag-0.6Cu-3.0Sb) containing Sb and having high tensile strength for solder bonding. As a result, after the temperature cycle test, Pb containing Sb between the metal heat sink 1 (see FIG. 12) and the lower surface side conductor pattern 2c (see FIG. 12B) of the insulating substrate 2 (see FIG. 12). It was confirmed that the free solder did not peel off.

  Furthermore, in order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b1 (FIG. 11A) of the insulating substrate 2 (see FIGS. 11, 14, and 15), A temperature cycle test of the solder joint between the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the external lead-out terminal 6b (see FIG. 14 and FIG. 15) was performed. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and external derivation. A temperature cycle test was performed using Pb-free solder containing Sb with high tensile strength for solder joint with the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the terminal 6b (see FIGS. 14 and 15). It was. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead-out terminal 6b (see FIG. 14). And Pb-free solder containing Sb between the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15). It was confirmed that the upper surface side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) was damaged.

  External lead-out terminal 6b (see FIG. 19B) covered with a gel-like resin (not shown) in the outer case 6 (see FIGS. 16, 17, 19A and 19B) ) In the vertical direction during the temperature cycle test (the vertical direction in FIG. 19B) and the vertical direction during the temperature cycle test of the gel resin (not shown) (see FIG. 19B). ) Of the upper surface side conductor pattern 2b1 (FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15). When a Pb-free solder containing high tensile strength and containing Sb is used for solder joining between the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the external lead-out terminal 6b (see FIG. 14 and FIG. 15). In the temperature cycle test, the external lead-out terminal 6b (see FIG. 19B) The amount of thermal expansion / heat shrinkage in the vertical direction (vertical direction in FIG. 19B) and the amount of thermal expansion / heat in the vertical direction (vertical direction in FIG. 19B) of the gel resin (not shown). The difference from the shrinkage amount cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb, and as a result, the upper surface side conductor pattern 2b1 (see FIG. 11, FIG. 14 and FIG. 15) of the insulating substrate 2 The upper surface side conductor pattern 2b1 (FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) due to the thermal stress applied to FIGS. 11A, 14 and 15). The present inventors considered that it was damaged.

  Therefore, in the study by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead terminal 6b (see FIG. Pb-free solder having a low tensile strength and not containing Sb (alloy composition is Sn-0.3Ag-, for example) for solder joints between the lower ends 6b4 and 6b4 '(see FIG. 15) of FIG. 14 and FIG. 0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead-out terminal 6b (see FIG. 14). And Pb-free solder that does not contain Sb between the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the insulating substrate 2 (see FIGS. 11, 14, and 15). It was confirmed that the conductor pattern 2b1 (see FIGS. 11A, 14 and 15) was not damaged.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b2 (FIG. 11 (A)) of the insulating substrate 2 (see FIG. 11, FIG. 14 and FIG. 15). A temperature cycle test of the solder joint between the lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the external lead-out terminal 6a (see FIGS. 14 and 15) was performed. Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and external derivation. A temperature cycle test was performed using Pb-free solder containing Sb having high tensile strength for solder joint with the lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the terminal 6a (see FIGS. 14 and 15). It was. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead-out terminal 6a (see FIG. 14). And Pb-free solder containing Sb between the lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15). It was confirmed that the upper surface side conductor pattern 2b2 (see FIGS. 11A, 14 and 15) was damaged.

  External lead-out terminal 6a (see FIG. 19B) covered with a gel-like resin (not shown) in the outer case 6 (see FIGS. 16, 17, 19A and 19B) ) In the vertical direction during the temperature cycle test (the vertical direction in FIG. 19B) and the vertical direction during the temperature cycle test of the gel resin (not shown) (see FIG. 19B). ) Of the upper surface side conductor pattern 2b2 (FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15). When a Pb-free solder containing high Sb and containing Sb is used for solder joining between the lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the external lead-out terminal 6a (see FIGS. 14 and 15). In the temperature cycle test, the external lead-out terminal 6a (see FIG. 19B) The amount of thermal expansion / heat shrinkage in the vertical direction (vertical direction in FIG. 19B) and the amount of thermal expansion / heat in the vertical direction (vertical direction in FIG. 19B) of the gel resin (not shown). The difference from the shrinkage amount cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb, and as a result, the upper surface side conductor pattern 2b2 (see FIG. 11, FIG. 14, and FIG. 15) The upper surface side conductor pattern 2b2 (FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) due to the thermal stress applied to FIGS. The present inventors considered that it was damaged.

  Therefore, in the studies by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead-out terminal 6a (see FIG. Pb-free solder having a low tensile strength and not containing Sb (alloy composition is Sn-0.3Ag-, for example) for solder joints with lower end portions 6a4, 6a4 '(see FIG. 15) of FIG. 14 and FIG. 0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead-out terminal 6a (see FIG. 14). And Pb-free solder containing no Sb between the lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the insulating substrate 2 (see FIGS. 11, 14, and 15). It was confirmed that the conductor pattern 2b2 (see FIGS. 11A, 14 and 15) was not damaged.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b2 (FIGS. 11A and 11) of the insulating substrate 2 (see FIGS. 11 and 13). B) and FIG. 13) and a temperature cycle test of the solder joint between the left lower ends 5a1 and 5a1 ′ (see FIG. 13) of the connecting members 5a and 5a (see FIG. 13) were performed. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13) and the connection member. A temperature cycle test was performed using Pb-free solder containing Sb with high tensile strength for solder joint between the lower left ends 5a1 and 5a1 ′ (see FIG. 13) of 5a and 5a ′ (see FIG. 13). It was. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13) and the connection members 5a and 5a ′ (see FIG. 11). Although peeling of Pb-free solder containing Sb between the left lower end portions 5a1, 5a1 ′ (see FIG. 13) of FIG. 13) is not recognized, the upper surface side of the insulating substrate 2 (see FIGS. 11 and 13) It was confirmed that the conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) was damaged.

  Up and down direction (FIG. 19) during the temperature cycle test of the connecting members 5a and 5a ′ (see FIG. 13 and FIG. 19 (B)) covered with the gel-like resin in the outer case 6 (see FIG. 19 (B)). The amount of thermal expansion / shrinkage in the vertical direction (B) is different from the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 19B) during the temperature cycle test of the gel resin. The upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13) and the connection members 5a and 5a ′ (see FIGS. 13 and 19B) When a Pb-free solder containing Sb and having a high tensile strength is used for solder joining to the left lower end portions 5a1 and 5a1 ′ (see FIG. 13)), the connecting members 5a and 5a '(See Fig. 13 and Fig. 19B) in the vertical direction ( The difference between the thermal expansion amount / heat shrinkage amount in the vertical direction of 19 (B) and the thermal expansion amount / heat shrinkage amount in the vertical direction of the gel-like resin (vertical direction in FIG. 19B) contains Sb. As a result, the upper surface side conductor pattern 2b2 of the insulating substrate 2 (see FIGS. 11 and 13) (FIGS. 11A, 11B) and FIG. 13), the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13) is damaged. Thought.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13) and the connection members 5a and 5a. Pb-free solder having a low tensile strength and containing no Sb (for example, having an alloy composition) for solder joining with the left lower end portions 5a1, 5a1 '(see FIG. 13) of' (see FIG. 13 and FIG. 19B) (Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to conduct a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13) and the connection members 5a and 5a ′ (see FIG. 11). Pb-free solder that does not contain Sb between the lower left ends 5a1 and 5a1 ′ (see FIG. 13) of FIG. 13 and FIG. 19B) does not peel off, and the insulating substrate 2 (see FIG. 11 and FIG. 13) It was confirmed that the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) was not damaged.

  In view of the research results of the present inventors, in the power semiconductor module 100 of the second embodiment, the lower surface side of the metal heat sink 1 (see FIGS. 10 and 12) and the insulating substrate 2 (see FIGS. 11 and 12). Pb-free solder 10a containing Sb (see FIG. 12B) is used for solder joint with the conductor pattern 2c (see FIGS. 11B, 11C, and 12B). ing.

  Therefore, according to the power semiconductor module 100 of the second embodiment, the lower surface side conductors of the metal heat sink 1 (see FIGS. 10 and 12) and the insulating substrate 2 (see FIGS. 11 and 12) after the temperature cycle test. The peeling of the solder 10a (see FIG. 12 (B)) between the pattern 2c (see FIGS. 11 (B), 11 (C) and 12 (B)) can be avoided, and the metal heat sink 1 (See FIGS. 10 and 12) and the lower surface side conductor pattern 2c (see FIGS. 11B, 11C, and 12B) of the insulating substrate 2 (see FIGS. 11 and 12). The reliability of solder joint can be improved.

  Furthermore, in the power semiconductor module 100 of the second embodiment, the upper surface side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the outside In the solder joint between the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the lead terminal 6b (see FIGS. 14 and 15), it is more tensioned than the Pb-free solder 10a containing Sb (see FIG. 12 (B)). Pb-free solders 10f2 and 10f2 ′ (see FIG. 15) that are low in strength and do not contain Sb are used.

  Therefore, according to the power semiconductor module 100 of the second embodiment, the upper surface side conductor pattern 2b1 (FIGS. 11A and 14) of the insulating substrate 2 (see FIGS. 11, 14 and 15) after the temperature cycle test. And the peeling of the solder 10f2, 10f2 ′ (see FIG. 15) between the lower end portions 6b4 and 6b4 ′ (see FIG. 15) of the external lead-out terminal 6b (see FIGS. 14 and 15) and the insulating substrate 2 Damage to the upper surface side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) can be avoided at the same time. 15) and upper end side conductor pattern 2b1 (see FIGS. 11A, 14 and 15) and lower end portions 6b4 and 6b4 ′ of external lead-out terminal 6b (see FIGS. 14 and 15) (see FIG. 15). ) Can improve the reliability of the solder joint between.

  In the power semiconductor module 100 of the second embodiment, the upper surface side conductor pattern 2b2 (FIGS. 11A, 11B, 14 and 14) of the insulating substrate 2 (see FIGS. 11, 14 and 15) is used. Pb-free solder 10a containing Sb (see FIG. 12B) for solder joint between the lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the external lead-out terminal 6a (see FIG. 14 and FIG. 15). Pb-free solders 10f1 and 10f1 ′ (see FIG. 15) that do not contain Sb and have a tensile strength lower than that of (see FIG. 15) are used.

  Therefore, according to the power semiconductor module 100 of the second embodiment, the upper surface side conductor pattern 2b2 (FIGS. 11A and 11) of the insulating substrate 2 (see FIGS. 11, 14 and 15) after the temperature cycle test. (B), see FIG. 14 and FIG. 15) and solder 10f1, 10f1 ′ (see FIG. 15) between the lower end portions 6a4 and 6a4 ′ (see FIG. 15) of the external lead-out terminal 6a (see FIG. 14 and FIG. 15). And simultaneous damage to the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) The upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, 14 and 15) of the insulating substrate 2 (see FIGS. 11, 14 and 15) and the external lead terminal 6a (see FIG. 14 and FIG. Lower end 6a4,6a4 reference) '(it is possible to improve the reliability of the solder joint between the see Figure 15).

  In the power semiconductor module 100 of the second embodiment, connection is made with the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13). In the solder joint between the lower left ends 5a1 and 5a1 '(see FIG. 13) of the members 5a and 5a' (see FIG. 13), it is more tensioned than the Pb-free solder 10a containing Sb (see FIG. 12 (B)). Pb-free solders 10d1 and 10d1 ′ having low strength and containing no Sb (see FIGS. 13B and 13C) are used.

  Therefore, according to the power semiconductor module 100 of the second embodiment, the upper surface side conductor pattern 2b2 (FIGS. 11A and 11B) of the insulating substrate 2 (see FIGS. 11 and 13) after the temperature cycle test. And FIG. 13) and solders 10d1, 10d1 ′ (FIG. 13B and FIG. 13C) between the left lower end portions 5a1, 5a1 ′ (see FIG. 13) of the connecting members 5a, 5a ′ (see FIG. )) And the damage of the upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13) of the insulating substrate 2 (see FIGS. 11 and 13) can be avoided at the same time, The upper surface side conductor pattern 2b2 (see FIGS. 11A, 11B, and 13C) of the insulating substrate 2 (see FIGS. 11 and 13) and the connection members 5a and 5a ′ (see FIG. 13). Left lower edge 5a1,5 1 'can improve the reliability of the solder joint between the (see FIG. 13).

  In the power semiconductor module 100 of the second embodiment, as the solders 10b1 and 10c1 (see FIG. 12B), the tensile strength is lower than the Pb-free solder 10a containing Sb (see FIG. 12B). Pb-free solder that does not contain Pb is used, but in the modification of the power semiconductor module 100 of the second embodiment, instead of the solder 10b1 and 10c1 (see FIG. 12B), the solder 10a (FIG. 12) is used. Similarly to (B), it is also possible to use Pb-free solder containing Sb and having high tensile strength.

  Furthermore, in the power semiconductor module 100 of the second embodiment, Pb-free solder 10a containing Sb (see FIG. 12B) is used as the solders 10e1 and 10e1 ′ (see FIGS. 13B and 13C). Pb-free solder that does not contain Sb is used, but in the modification of the power semiconductor module 100 of the second embodiment, instead of the solder 10e1, 10e1 ′ (FIG. 13B ) And FIG. 13 (C)), it is also possible to use Pb-free solder containing Sb having a high tensile strength as with the solder 10a (see FIG. 12 (B)).

  Hereinafter, a third embodiment of the power semiconductor module of the present invention will be described. FIG. 20 is a view showing the metal heat sink 1 constituting a part of the power semiconductor module 100 of the third embodiment. Specifically, FIG. 20A is a plan view of the metal heat sink 1, and FIG. 20B is a vertical cross-sectional view along the line A2-A2 of FIG. FIG. 21 is a view showing an insulating substrate 2 constituting a part of the power semiconductor module 100 of the third embodiment. Specifically, FIG. 21A is a plan view of the insulating substrate 2, FIG. 21B is a vertical sectional view taken along line B2-B2 of FIG. 21A, and FIG. It is a bottom view. FIG. 22 is a diagram showing a state where the insulating substrate 2 and the like are mounted on the metal heat sink 1. Specifically, in FIG. 22A, an insulating substrate 2 is mounted on a metal heat sink 1, and an anode electrode plate 4a ′ such as an anode PCM (pig iron) plate, an anode molybdenum plate, or the like is mounted on the insulating substrate 2. Is mounted on the anode electrode plate 4a ′, and the power semiconductor chip (thyristor chip) 3a is mounted on the upper surface electrode (cathode electrode) for large current flow formed on the upper surface of the power semiconductor chip (diode chip) 3a. For example, a cathode electrode plate 4a such as a cathode PCM (pig iron) plate or a cathode molybdenum plate is mounted, and a connection member 8 is mounted on the gate electrode formed on the upper surface of the power semiconductor chip (diode chip) 3a. It is the top view which showed the state. FIG. 22B is an exploded sectional view taken along line C2-C2 of FIG.

  FIG. 23 is a view showing a state in which the connection members 5a and 5a 'are mounted on the assembly shown in FIG. Specifically, FIG. 23A is a plan view showing a state in which the connection members 5a and 5a 'are mounted on the assembly shown in FIG. 23B is a schematic exploded sectional view taken along line E2-E2 in FIG. 23A, and FIG. 23C is a schematic exploded view taken along line F2-F2 in FIG. FIG. FIG. 24 and FIG. 25 are diagrams showing how the external lead-out terminals 6a and 6b are mounted on the assembly shown in FIG. Specifically, FIG. 24 is a plan view showing a state where the external lead-out terminals 6a and 6b are mounted on the assembly shown in FIG. 25A is a schematic exploded sectional view taken along line G2-G2 in FIG. 24, and FIG. 25B is a schematic exploded sectional view taken along line H2-H2 in FIG. 26 and 27 are component diagrams of the enclosing case 6 that covers the assembly shown in FIG. Specifically, FIG. 26A is a plan view of the outer case 6, and FIG. 26B is a front view of the outer case 6. 27A is a vertical cross-sectional view taken along line K2-K2 of FIG. 26A, and FIG. 27B is a bottom view of the outer case 6. As shown in FIG.

  FIG. 28 is a component diagram of the lid 7 that covers the outer casing 6 shown in FIGS. 26 and 27 that covers the assembly shown in FIG. Specifically, FIG. 28A is a plan view of the lid 7, FIG. 28B is a front view of the lid 7, and FIG. 28C is a bottom view of the lid 7. FIG. 29 is a diagram showing a power semiconductor module 100 according to the third embodiment. Specifically, in FIG. 29A, the outer casing 6 shown in FIGS. 26 and 27 is put on the assembly shown in FIG. 24, and then the lid 7 shown in FIG. 28 is put. It is a top view of the power semiconductor module 100 of 3rd Embodiment obtained by these. FIG. 29B is a schematic vertical sectional view of the power semiconductor module 100 of the third embodiment. FIG. 29C is an equivalent circuit diagram of the power semiconductor module 100 of the third embodiment.

  In the power semiconductor module 100 of the third embodiment, as shown in FIG. 22B, a metal heat radiating plate 1 (for dissipating heat generated by the power semiconductor chip (thyristor chip) 3a (see FIG. 22)) ( 20 and 22) and the lower surface side conductor pattern 2c (see FIG. 21B) formed on the lower surface side of the insulating layer 2a (see FIGS. 21 and 22) of the insulating substrate 2 (see FIGS. 21 and 22). ) And FIG. 21C and FIG. 22B), the solder 10a (see FIG. 22B) is arranged. Further, as shown in FIG. 22B, the upper surface side conductor pattern 2b1 (see FIGS. 21A, 22A, and 22B) of the insulating substrate 2 (see FIGS. 21 and 22) and Solder 10c1 ′ (see FIG. 22B) is disposed between the lower surface of the anode electrode plate 4a ′ (see FIG. 22B). Further, as shown in FIG. 22B, the upper surface of the anode electrode plate 4a ′ (see FIG. 22B) and the power semiconductor chip (thyristor chip) 3a (see FIGS. 22A and 22B). The solder 10b1 (see FIG. 22B) is disposed between the lower electrode (anode electrode) of the first electrode and the lower electrode.

  In the power semiconductor module 100 of the third embodiment, as shown in FIG. 22B, the large current of the power semiconductor chip (thyristor chip) 3a (see FIGS. 22A and 22B) is large. Solder 10c1 (see FIG. 22B) is disposed between the flowing upper surface electrode (cathode electrode) and the lower surface of the cathode electrode plate 4a (see FIGS. 22A and 22B). Further, as shown in FIG. 22 (B), the gate electrode formed on the upper surface of the power semiconductor chip (thyristor chip) 3a (see FIGS. 22 (A) and 22 (B)) and the connecting member 8 (FIG. 22 (B)). A solder 10g1 (see FIG. 22B) is disposed between the lower surface of A) and FIG. 22B).

  Furthermore, in the power semiconductor module 100 of the third embodiment, as shown in FIG. 23, connection members 5a and 5a 'formed by, for example, pressing a metal material are provided. Specifically, as shown in FIG. 23 (B), the upper surface of the cathode electrode plate 4a (see FIGS. 23 (A) and 23 (B)) and the connecting member 5a (FIGS. 23 (A) and 23 (B)). The solder 10e1 (see FIG. 23B) is arranged between the lower surface of the left lower end portion 5a2 (see FIG. 23A and FIG. 23B). Further, as shown in FIG. 23C, the upper surface of the cathode electrode plate 4a (see FIGS. 23A and 23C) and the connecting member 5a ′ (see FIGS. 23A and 23C). The solder 10e1 ′ (see FIG. 23C) is disposed between the lower end of the left lower end 5a2 ′ (see FIG. 23A and FIG. 23C).

  In the power semiconductor module 100 of the third embodiment, as shown in FIG. 23B, the upper surface side conductor pattern 2b2 (see FIGS. 23A and 23B) of the insulating substrate 2 (see FIG. 23). Between the lower end 5a1 of the right side of the connecting member 5a (see FIGS. 23A and 23B) (see FIGS. 23A and 23B) and the solder 10d1 (see FIG. 23). (See (B)). Furthermore, as shown in FIG. 23C, the upper surface side conductor pattern 2b2 (see FIGS. 23A and 23C) of the insulating substrate 2 (see FIG. 23) and the connection member 5a ′ (see FIG. 23A). ) And FIG. 23 (C)), the solder 10d1 ′ (see FIG. 23 (B)) is disposed between the lower surface of the right lower end 5a1 ′ (see FIG. 23 (A) and FIG. 23 (C)). Yes.

  Furthermore, in the power semiconductor module 100 of the third embodiment, as shown in FIGS. 24 and 25, an upper end 6a1 extending in the vertical direction (the vertical direction in FIG. 25), and a branch from the upper end 6a1 and bending. The external lead-out terminals 6a having the center portions 6a2 and 6a2 'and the lower end portions 6a4 and 6a4' extending in the horizontal direction (left-right direction in FIG. 25) are formed by, for example, pressing a metal material. . Further, in the power semiconductor module 100 of the third embodiment, as shown in FIGS. 24 and 25, an upper end 6b1 extending in the up-down direction (up-down direction in FIG. 25), a branch from the upper end 6b1, and bending The outer lead-out terminals 6b having the center portions 6b2 and 6b2 ′ and the lower end portions 6b4 and 6b4 ′ extending in the horizontal direction (left and right direction in FIG. 25) are formed by, for example, pressing a metal material. .

  In the power semiconductor module 100 of the third embodiment, as shown in FIGS. 24 and 25A, the upper surface side conductor pattern 2b2 (see FIG. 24) of the insulating substrate 2 (see FIGS. 24 and 25A). And the solder 10f1 (see FIG. 25A) between the lower end portion 6a4 (see FIG. 25A) of the external lead-out terminal 6a (see FIG. 24 and FIG. 25A). )) Is arranged. Further, as shown in FIGS. 24 and 25B, the upper surface side conductor pattern 2b2 (see FIGS. 24 and 25B) of the insulating substrate 2 (see FIGS. 24 and 25B) and external derivation Solder 10f1 ′ (see FIG. 25B) is disposed between the lower surface of the lower end portion 6a4 ′ (see FIG. 25B) of the terminal 6a (see FIG. 24 and FIG. 25B). As a result, the upper surface side conductor pattern 2b2 (see FIGS. 24 and 25) and the external lead-out terminal 6a (see FIGS. 24 and 25) are electrically connected.

  Furthermore, in the power semiconductor module 100 of the third embodiment, as shown in FIGS. 24 and 25A, the upper surface side conductor pattern 2b1 (see FIG. 24) of the insulating substrate 2 (see FIGS. 24 and 25A). And the solder 10f2 (see FIG. 25 (A)) between the lower surface of the lower end portion 6b4 (see FIG. 25 (A)) of the external lead-out terminal 6b (see FIG. 24 and FIG. 25 (A)). )) Is arranged. Further, as shown in FIGS. 24 and 25B, the upper surface side conductor pattern 2b1 (see FIGS. 24 and 25B) of the insulating substrate 2 (see FIGS. 24 and 25B) and external derivation Solder 10f2 ′ (see FIG. 25 (B)) is disposed between the lower surface of the lower end 6b4 ′ (see FIG. 25 (B)) of the terminal 6b (see FIG. 24 and FIG. 25 (B)). As a result, the upper surface side conductor pattern 2b1 (see FIGS. 24 and 25) and the external lead-out terminal 6b (see FIGS. 24 and 25) are electrically connected.

  In the power semiconductor module 100 of the third embodiment, as shown in FIGS. 26 and 27, the right side wall 6d (see FIGS. 27A and 27B) and the left side wall 6e (see FIG. 27A). ) And FIG. 27 (B)), a front side wall 6f (see FIG. 26 (B) and FIG. 27 (B)), and a rear side wall 6g (see FIG. 27 (A) and FIG. 27 (B)), An enclosing case 6 (see FIGS. 26 and 27) formed by molding an electrically insulating resin material is provided. More specifically, the outer case 6 (see FIGS. 26, 27, 29A and 29B) is placed on the assembly shown in FIG.

  That is, the power of the first embodiment in which the external lead-out terminals 6a and 6b (see FIGS. 5 and 6A) are inserted and formed integrally with the outer case 6 (see FIGS. 5 and 6). Unlike the semiconductor module 100 (see FIG. 9), in the power semiconductor module 100 of the third embodiment, as shown in FIGS. 24 to 27, external lead-out terminals 6a and 6b (see FIGS. 24 and 25) It is not inserted in the surrounding case 6 (see FIG. 26 and FIG. 27), and is configured as a separate member from the surrounding case 6 (see FIG. 26 and FIG. 27).

  In the power semiconductor module 100 of the third embodiment, the signal terminal 6d (see FIGS. 29A, 29B, and 29C) is connected to the connecting member 8 (FIG. 22) via the signal line. As a result, the signal terminal 6d (see FIGS. 29A, 29B, and 29C) and the power semiconductor chip (diode chip) 3a (see FIGS. 29B and 29) are connected. The gate electrode formed on the upper surface of (C) is electrically connected. Further, the signal terminal 6e (see FIGS. 29A, 29B, and 29C) is connected to the upper surface side conductor of the insulating substrate 2 (see FIGS. 22 and 29B) via the signal line. As a result, the signal terminal 6e (see FIGS. 29A, 29B and 29C) and the power semiconductor chip (diode chip) 3a (see FIG. 29) are connected to the pattern 2b2 (see FIG. 22). B) and the upper surface electrode (cathode electrode) of FIG. 29C) are electrically connected.

  Furthermore, in the power semiconductor module 100 according to the third embodiment, a gel-like resin (not shown) is filled inside the outer casing 6 that covers the assembly shown in FIG. Specifically, a gel-like resin (not shown) is filled up to a height HT indicated by a broken line in FIG. That is, the insulating substrate 2 (see FIG. 29B), the power semiconductor chip (thyristor chip) 3a (see FIG. 29B), and the electrode plates 4a and 4a ′ (by gel resin (not shown)). 22 (B) and 29 (B)), connecting members 5a and 5a ′ (see FIGS. 23 and 29B), and external lead-out terminals 6a and 6b (FIGS. 24, 25, and 29 (). B))) and lower ends 6a4, 6a4 ′, 6b4, 6b4 ′ (see FIGS. 25A and 25B) and central portions 6a2, 6a2 ′, 6b2, 6b2 ′ (FIG. 25A and FIG. 25 (B)). Further, an epoxy resin (not shown) is placed on the inner side of the enclosing case 6 covered on the assembly shown in FIG. 24 and above the height HT indicated by a broken line in FIG. Filled. Further, as shown in FIGS. 29 (A) and 29 (B), the cover body 7 shown in FIG. 28 is put on the outer casing 6 (see FIGS. 29 (A) and 29 (B)). ing. Specifically, when the lid 7 (see FIGS. 28, 29A, and 29B) is attached, as shown in FIG. 29A, the external lead-out terminal 6a (FIGS. 24, 25, and FIG. 29 (A) and FIG. 29 (B)) is provided at the upper end 6a1 (see FIG. 25) of the lead hole 7a (see FIG. 28 (see FIG. 28, FIG. 29 (A) and FIG. 29 (B)). A), see FIG. 28 (C) and FIG. 29 (A)). Further, the upper end portion 6b1 (see FIG. 25) of the external lead-out terminal 6b (see FIGS. 24, 25, 29A and 29B) is the lid body 7 (see FIGS. 28, 29A and 29). 29 (B)) through the lead-out hole 7b (see FIG. 28 (A), FIG. 28 (C) and FIG. 29 (A)). Next, a nut (not shown) is inserted into the recess 7f (see FIGS. 28A and 29A) on the upper surface of the lid 7 (see FIGS. 28, 29A and 29B). Is done. Next, the upper end portions 6a1 and 6b1 (see FIG. 25) of the external lead-out terminals 6a and 6b (see FIGS. 24, 25, 29A and 29B) are bent, and the power of the third embodiment The semiconductor module 100 is completed.

  That is, in the power semiconductor module 100 of the third embodiment, as shown in FIGS. 29B and 29C, the upper surface electrode (cathode electrode) through which a large current flows and the lower surface electrode (anode) through which a large current flows. A power semiconductor chip (thyristor chip) 3a having an electrode) is provided. As shown in FIG. 22A, a power semiconductor chip (thyristor chip) 3a is mounted on the upper surface side conductor pattern 2b1 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Further, as shown in FIG. 22B, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrode (anode electrode) of the power semiconductor chip (thyristor chip) 3a are electrically connected.

  Further, in the power semiconductor module 100 of the third embodiment, as shown in FIG. 23, the connection member 5a (see FIGS. 23A and 23B) and the electrode plate 4a (FIG. 23A and FIG. 23 (B)) through the upper surface electrode (cathode electrode) of the power semiconductor chip (thyristor chip) 3a (see FIG. 23 (A)) and the upper surface side conductor pattern 2b2 (see FIG. 23). 23 (A) and FIG. 23 (B)) are electrically connected. Further, the power semiconductor chip (thyristor chip) 3a is connected via the connecting member 5a ′ (see FIGS. 23A and 23C) and the electrode plate 4a (see FIGS. 23A and 23C). The upper surface electrode (cathode electrode) of (see FIG. 23 (A)) and the upper surface side conductor pattern 2b2 (see FIGS. 23 (A) and 23 (C)) of the insulating substrate 2 (see FIG. 23) are electrically connected. Has been.

  Specifically, in the power semiconductor module 100 of the third embodiment, the lower surface side conductor pattern 2c (FIG. 21) of the metal heat sink 1 (see FIGS. 20 and 22) and the insulating substrate 2 (see FIGS. 21 and 22). (B), joining by solder 10a (see FIG. 22 (B)) between FIG. 21 (C) and FIG. 22 (B)), upper surface of insulating substrate 2 (see FIG. 21, FIG. 24 and FIG. 25) Solder 10f2 between the side conductor pattern 2b1 (see FIG. 21A, FIG. 24 and FIG. 25) and the lower end portions 6b4 and 6b4 ′ (see FIG. 25) of the external lead terminal 6b (see FIG. 24 and FIG. 25) 10f2 ′ (see FIG. 25), the upper surface side conductor pattern 2b2 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead-out terminal 6a (see FIG. 21). See FIG. 24 and FIG. The lower end portions 6a4 and 6a4 ′ (see FIG. 25) of the solder joints 10f1 and 10f1 ′ (see FIG. 25) and the right lower end portions 5a1 and 5a1 ′ (see FIG. 23) of the connecting members 5a and 5a ′ (see FIG. 23). 23) and the solder 10d1, 10d1 ′ (see FIGS. 23B and 23) between the upper surface side conductor pattern 2b2 (see FIGS. 21A and 23) of the insulating substrate 2 (see FIGS. 21 and 23). (See (C)), the lower left ends 5a2, 5a2 '(see FIG. 23) and the electrode plate 4a (see FIGS. 22A, 22B) and FIG. 23) (see FIG. 23), the electrode plate 4a (see FIGS. 22A and 22B) and the power semiconductor chip (thyristor chip) 3a (see FIG. 22). A) and FIG. 22 (B And the lower surface of the power semiconductor chip (thyristor chip) 3a (see FIG. 22A and FIG. 22B) with the solder 10c1 (see FIG. 22B). Bonding between electrode (anode electrode) and electrode plate 4a ′ (see FIG. 22B) by solder 10b1 (see FIG. 22B), electrode plate 4a ′ (see FIG. 22B) and insulating substrate 2 (refer to FIG. 22) and the upper surface side conductor pattern 2b1 (refer to FIG. 22 (A) and FIG. 22 (B)) by the solder 10c1 ′ (refer to FIG. 22 (B)) and the power semiconductor chip ( Thyristor chip) Solder 10g1 between the gate electrode formed on the upper surface of 3a (see FIGS. 22A and 22B) and connection member 8 (see FIGS. 22A and 22B) (See Fig. 22 (B)) The combination is executed by batch processing. Further, at the time of performing the solder bonding, the metal follows the concave upper surface of the basing jig (not shown) like the power semiconductor module described in FIG. 3 of Patent Document 1 (Japanese Patent Laid-Open No. 2010-199251). The metal heat sink 1 (see FIGS. 20, 24 and 25) is a basing jig (not shown) so that the lower surface of the heat sink 1 (see FIGS. 20, 24 and 25) is deformed into a convex shape. Fixed against.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have made the lower surface side conductor pattern 2c (see FIG. 22) of the metal heat sink 1 (see FIG. 22) and the insulating substrate 2 (see FIG. 22). 22 (B)) was subjected to a temperature cycle test of solder bonding. Specifically, in the research by the present inventors, between the metal heat sink 1 (see FIG. 22) and the lower surface side conductor pattern 2c (see FIG. 22B) of the insulating substrate 2 (see FIG. 22). A temperature cycle test was performed using Pb (lead) -free solder having a low tensile strength and containing no Sb (antimony) for solder bonding. As a result, after the temperature cycle test, Pb not containing Sb between the metal heat sink 1 (see FIG. 22) and the lower conductor pattern 2c (see FIG. 22B) of the insulating substrate 2 (see FIG. 22). It was confirmed that the free solder was peeled off.

  The present inventors have insufficient solder tensile strength between the metal heat sink 1 (see FIG. 22) and the lower surface side conductor pattern 2c (see FIG. 22B) of the insulating substrate 2 (see FIG. 22). In the research conducted by the present inventors, between the metal radiator plate 1 (see FIG. 22) and the lower surface side conductor pattern 2c (see FIG. 22B) of the insulating substrate 2 (see FIG. 22). A temperature cycle test was carried out using Pb-free solder (alloy composition such as Sn-3.9Ag-0.6Cu-3.0Sb) containing Sb and having high tensile strength for solder bonding. As a result, after the temperature cycle test, Pb containing Sb between the metal heat sink 1 (see FIG. 22) and the lower surface side conductor pattern 2c (see FIG. 22B) of the insulating substrate 2 (see FIG. 22). It was confirmed that the free solder did not peel off.

  Furthermore, in order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b1 (FIG. 21A), FIG. 21A, FIG. 24 and 25) and a temperature cycle test of the solder joint between the lower end portions 6b4 and 6b4 ′ (see FIG. 25) of the external lead-out terminal 6b (see FIGS. 24 and 25). Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and external derivation. A temperature cycle test was performed using Pb-free solder containing Sb with high tensile strength for solder joint between the lower ends 6b4 and 6b4 ′ (see FIG. 25) of the terminal 6b (see FIGS. 24 and 25). It was. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead-out terminal 6b (see FIG. 24). And Pb-free solder containing Sb between the lower end portions 6b4 and 6b4 ′ (see FIG. 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25). It was confirmed that the upper surface side conductor pattern 2b1 (see FIGS. 21A, 24, and 25) was damaged.

  External lead-out terminal 6b (see FIG. 29B) covered with a gel-like resin (not shown) in the surrounding case 6 (see FIGS. 26, 27, 29A and 29B) ) In the vertical direction during the temperature cycle test (the vertical direction in FIG. 29B) and the vertical direction during the temperature cycle test of the gel resin (not shown) (see FIG. 29B). ) Of the upper surface side conductor pattern 2b1 (FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25). When a Pb-free solder containing high tensile strength and containing Sb is used for solder joining between the lower end portions 6b4 and 6b4 ′ (see FIG. 25) of the external lead-out terminal 6b (see FIG. 24 and FIG. 25). In the temperature cycle test, the external lead-out terminal 6b (see FIG. 29B) The amount of thermal expansion and heat shrinkage in the vertical direction (vertical direction in FIG. 29B) and the amount of thermal expansion and heat in the vertical direction (vertical direction in FIG. 29B) of the gel resin (not shown). The difference from the shrinkage amount cannot be sufficiently absorbed by the deformation of the Pb-free solder containing Sb. As a result, the upper surface side conductor pattern 2b1 (see FIG. 21, FIG. 24 and FIG. 25) of the insulating substrate 2 The upper surface side conductor pattern 2b1 (FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) due to the thermal stress applied to FIGS. 21A, 24, and 25). The present inventors considered that it was damaged.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead-out terminal 6b (see FIG. Pb-free solder having a low tensile strength and not containing Sb (alloy composition is Sn-0.3Ag-, for example) for solder joints with lower end portions 6b4 and 6b4 '(see FIG. 25) of FIG. 24 and FIG. 0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead-out terminal 6b (see FIG. 24). And Pb-free solder that does not contain Sb between the lower end portions 6b4 and 6b4 ′ (see FIG. 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25). It was confirmed that the conductor pattern 2b1 (see FIGS. 21A, 24, and 25) was not damaged.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b2 (FIG. 21 (A), FIG. 21A) of the insulating substrate 2 (see FIG. 21, FIG. 24 and FIG. 25). A temperature cycle test of the solder joint between the lower end portions 6a4 and 6a4 ′ (see FIG. 25) of the external lead terminal 6a (see FIG. 24 and FIG. 25) was performed. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and external derivation. A temperature cycle test was performed using Pb-free solder containing Sb having high tensile strength for solder joint with the lower end portions 6a4 and 6a4 ′ (see FIG. 25) of the terminal 6a (see FIGS. 24 and 25). It was. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead-out terminal 6a (see FIG. 24). And Pb-free solder containing Sb between the lower end portions 6a4 and 6a4 ′ (see FIG. 25) of the insulating substrate 2 (see FIGS. 21, 24 and 25). It was confirmed that the upper surface side conductor pattern 2b2 (see FIGS. 21A, 24, and 25) was damaged.

  External lead-out terminal 6a (see FIG. 29B) covered with a gel-like resin (not shown) in the surrounding case 6 (see FIGS. 26, 27, 29A and 29B) ) In the vertical direction during the temperature cycle test (the vertical direction in FIG. 29B) and the vertical direction during the temperature cycle test of the gel resin (not shown) (see FIG. 29B). ) Of the upper surface side conductor pattern 2b2 (FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25). When a Pb-free solder containing high Sb and containing Sb is used for solder joining between the lower end portions 6a4 and 6a4 ′ (see FIG. 25) of the external lead-out terminal 6a (see FIGS. 24 and 25). In the temperature cycle test, the external lead-out terminal 6a (see FIG. 29B) The amount of thermal expansion and heat shrinkage in the vertical direction (vertical direction in FIG. 29B) and the amount of thermal expansion and heat in the vertical direction (vertical direction in FIG. 29B) of the gel resin (not shown). The difference from the shrinkage amount cannot be sufficiently absorbed by deformation of the Pb-free solder containing Sb, and as a result, the upper surface side conductor pattern 2b2 (see FIG. 21, FIG. 24 and FIG. 25) of the insulating substrate 2 The upper surface side conductor pattern 2b2 (FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) due to thermal stress applied to FIGS. 21A, 24, and 25). The present inventors considered that it was damaged.

  Therefore, in the studies by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead terminal 6a (see FIG. Pb-free solder having a low tensile strength and containing no Sb (alloy composition is Sn-0.3Ag-, for example) for solder joints between the lower ends 6a4 and 6a4 '(see FIG. 25) of FIGS. 0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead-out terminal 6a (see FIG. 24). And Pb-free solder that does not contain Sb between the lower ends 6a4 and 6a4 ′ (see FIG. 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25). It was confirmed that the conductor pattern 2b2 (see FIGS. 21A, 24, and 25) was not damaged.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b2 (FIGS. 21A and 21) of the insulating substrate 2 (see FIGS. 21 and 23). B) and FIG. 23) and a temperature cycle test of the solder joint between the right lower ends 5a1 and 5a1 ′ (see FIG. 23) of the connecting members 5a and 5a (see FIG. 23) were performed. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23) and the connection member. A temperature cycle test was performed using Pb-free solder containing Sb with high tensile strength for solder joint between the right lower ends 5a1 and 5a1 ′ (see FIG. 23) of 5a and 5a ′ (see FIG. 23). It was. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23) and the connection members 5a and 5a ′ (see FIG. Although the peeling of Pb-free solder containing Sb between the right lower end portions 5a1, 5a1 ′ (see FIG. 23) of FIG. 23) is not recognized, the upper surface side of the insulating substrate 2 (see FIGS. 21 and 23) It was confirmed that the conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) was damaged.

  Up and down direction (FIG. 29) at the time of a temperature cycle test of the connecting members 5a and 5a ′ (see FIG. 23 and FIG. 29 (B)) covered with the gel-like resin in the outer case 6 (see FIG. 29 (B)). The amount of thermal expansion / shrinkage in the vertical direction (B) differs from the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 29B) during the temperature cycle test of the gel resin. The upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23) and the connecting members 5a and 5a ′ (see FIGS. 23 and 29B) When the Pb-free solder containing Sb and having high tensile strength is used for the solder joint between the right lower end portions 5a1 and 5a1 ′ (see FIG. 23))), the connecting members 5a and 5a are used during the temperature cycle test. '(See Fig. 23 and Fig. 29 (B)) in the vertical direction ( The difference between the thermal expansion amount / heat shrinkage amount in the vertical direction of 29 (B) and the thermal expansion amount / heat shrinkage amount in the vertical direction of the gel resin (vertical direction in FIG. 29B) contains Sb. As a result, the upper surface side conductor pattern 2b2 of the insulating substrate 2 (see FIGS. 21 and 23) (FIGS. 21A, 21B) and FIG. 23), the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23) is damaged. Thought.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23) and the connection members 5a and 5a. Pb-free solder having a low tensile strength and containing no Sb (for example, the alloy composition is low) for solder joints between the right lower ends 5a1 and 5a1 '(see FIG. 23) of' (see FIGS. 23 and 29B) (Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to conduct a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23) and the connection members 5a and 5a ′ (see FIG. Pb-free solder that does not contain Sb between the lower right ends 5a1 and 5a1 ′ (see FIG. 23) of FIG. 23 and FIG. 29B) does not peel off, and the insulating substrate 2 (see FIG. 21 and FIG. 23) It was confirmed that the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) was not damaged.

  In view of the research results of the present inventors, in the power semiconductor module 100 of the third embodiment, the lower surface side of the metal heat sink 1 (see FIGS. 20 and 22) and the insulating substrate 2 (see FIGS. 21 and 22). Pb-free solder 10a containing Sb (see FIG. 22 (B)) is used for solder bonding with the conductor pattern 2c (see FIGS. 21 (B), 21 (C) and 22 (B)). ing.

  Therefore, according to the power semiconductor module 100 of the third embodiment, the lower surface side conductors of the metal heat sink 1 (see FIGS. 20 and 22) and the insulating substrate 2 (see FIGS. 21 and 22) after the temperature cycle test. The peeling of the solder 10a (see FIG. 22B) between the pattern 2c (see FIGS. 21B, 21C, and 22B) can be avoided, and the metal heat sink 1 (See FIGS. 20 and 22) and the lower surface side conductor pattern 2c (see FIGS. 21B, 21C, and 22B) of the insulating substrate 2 (see FIGS. 21 and 22). The reliability of solder joint can be improved.

  Furthermore, in the power semiconductor module 100 of the third embodiment, the upper surface side conductor pattern 2b1 (see FIGS. 21A, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the outside In the solder joint between the lower end portions 6b4 and 6b4 ′ (see FIG. 25) of the lead-out terminal 6b (see FIGS. 24 and 25), it is more tensioned than the Pb-free solder 10a containing Sb (see FIG. 22 (B)). Pb-free solders 10f2 and 10f2 ′ (see FIG. 25) that have low strength and do not contain Sb are used.

  Therefore, according to the power semiconductor module 100 of the third embodiment, the upper surface side conductor pattern 2b1 (FIGS. 21A and 24) of the insulating substrate 2 (see FIGS. 21, 24, and 25) after the temperature cycle test. And the peeling of the solder 10f2, 10f2 ′ (see FIG. 25) between the lower end portions 6b4 and 6b4 ′ (see FIG. 25) of the external lead-out terminal 6b (see FIGS. 24 and 25) and the insulating substrate 2 Damage to the upper surface side conductor pattern 2b1 (see FIG. 21A, FIG. 24, and FIG. 25) of the insulating substrate 2 (see FIG. 21, FIG. 24) can be avoided at the same time. 25) (see FIGS. 21A, 24, and 25) and lower end portions 6b4 and 6b4 ′ of the external lead-out terminal 6b (see FIGS. 24 and 25) (see FIG. 25). ) Can improve the reliability of the solder joint between.

  In the power semiconductor module 100 of the third embodiment, the upper surface side conductor pattern 2b2 (FIGS. 21A, 21B, 24, and 24) of the insulating substrate 2 (see FIGS. 21, 24, and 25) is used. Pb-free solder 10a containing Sb (see FIG. 22B) for solder joint between the lower end portions 6a4 and 6a4 ′ (see FIG. 25) of the external lead-out terminal 6a (see FIG. 25 and FIG. 25). Pb-free solders 10f1 and 10f1 ′ (see FIG. 25) that do not contain Sb and have a tensile strength lower than that of (see FIG. 25) are used.

  Therefore, according to the power semiconductor module 100 of the third embodiment, the upper surface side conductor pattern 2b2 (FIGS. 21A and 21) of the insulating substrate 2 (see FIGS. 21, 24, and 25) after the temperature cycle test. (B), see FIG. 24 and FIG. 25) and solder 10f1, 10f1 ′ (see FIG. 25) between the lower end portions 6a4 and 6a4 ′ (see FIG. 25) of the external lead-out terminal 6a (see FIG. 24 and FIG. 25). And simultaneous damage to the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) The upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, 24, and 25) of the insulating substrate 2 (see FIGS. 21, 24, and 25) and the external lead terminal 6a (see FIG. 24 and FIG. Lower end 6a4,6a4 reference) '(it is possible to improve the reliability of the solder joint between the see Figure 25).

  Further, in the power semiconductor module 100 of the third embodiment, it is connected to the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23). It is more tensioned than the Pb-free solder 10a containing Sb (see FIG. 22 (B)) in the solder joint between the members 5a, 5a '(see FIG. 23) and the lower right ends 5a1, 5a1' (see FIG. 23). Pb-free solders 10d1 and 10d1 ′ having low strength and containing no Sb (see FIGS. 23B and 23C) are used.

  Therefore, according to the power semiconductor module 100 of the third embodiment, the upper surface side conductor pattern 2b2 (FIGS. 21A and 21B) of the insulating substrate 2 (see FIGS. 21 and 23) after the temperature cycle test. And FIG. 23) and solders 10d1, 10d1 ′ (see FIG. 23B and FIG. 23C) between the right lower ends 5a1, 5a1 ′ (see FIG. 23) of the connecting members 5a, 5a ′ (see FIG. 23). )) And the damage of the upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23) of the insulating substrate 2 (see FIGS. 21 and 23) can be avoided at the same time, The upper surface side conductor pattern 2b2 (see FIGS. 21A, 21B, and 23C) of the insulating substrate 2 (see FIGS. 21 and 23) and the connection members 5a and 5a ′ (see FIG. 23). Right lower edge 5a1,5 1 'can improve the reliability of the solder joint between the (see FIG. 23).

  In the power semiconductor module 100 of the third embodiment, the solders 10b1, 10c1, 10c1 ′, and 10g1 (see FIG. 22B) are pulled more than the Pb-free solder 10a containing Sb (see FIG. 22B). Pb-free solder having low strength and containing no Sb is used, but in the modification of the power semiconductor module 100 of the third embodiment, instead of the solders 10b1, 10c1, 10c1 ′, 10g1 (FIG. 22B )), It is also possible to use Sb-containing Pb-free solder having a high tensile strength in the same manner as the solder 10a (see FIG. 22B).

  Furthermore, in the power semiconductor module 100 of the third embodiment, Pb-free solder 10a containing Sb (see FIG. 22B) as the solders 10e1 and 10e1 ′ (see FIGS. 23B and 23C). Pb-free solder that does not contain Sb is used, but in the modification of the power semiconductor module 100 of the third embodiment, instead of the solder 10e1, 10e1 ′ (FIG. 23B ) And FIG. 23 (C)), it is also possible to use Sb-containing Pb-free solder having high tensile strength like the solder 10a (see FIG. 22 (B)).

  Hereinafter, a fourth embodiment of the power semiconductor module of the present invention will be described. FIG. 30 is a view showing a metal heat sink 1 constituting a part of the power semiconductor module 100 of the fourth embodiment. Specifically, FIG. 30 (A) is a plan view of the metal heat sink 1 and FIG. 30 (B) is a vertical sectional view taken along line A3-A3 of FIG. 30 (A). FIG. 31 is a view showing an insulating substrate 2 constituting a part of the power semiconductor module 100 of the fourth embodiment. Specifically, FIG. 31A is a plan view of the insulating substrate 2, FIG. 31B is a vertical sectional view taken along line B3-B3 in FIG. 31A, and FIG. It is a bottom view. FIG. 32 is a diagram showing a state in which the power semiconductor chips 3a, 3b, 3c are mounted on the insulating substrate 2. Specifically, FIG. 32A is a plan view showing a state in which a power semiconductor chip (IGBT chip) 3 a and power semiconductor chips (diode chips) 3 b and 3 c are mounted on the insulating substrate 2. 32B is an exploded sectional view taken along line C3-C3 in FIG. 32A, and FIG. 32C is an exploded sectional view taken along line D3-D3 in FIG. FIG. 32D is a plan view of an assembly obtained by performing wire bonding on the assembly shown in FIG.

  FIG. 33 and FIG. 34 are component diagrams of the enclosing case 6 that covers the assembly shown in FIG. Specifically, FIG. 33A is a plan view of the outer case 6, FIG. 33B is a front view of the outer case 6, and FIG. 33C is a bottom view of the outer case 6. FIG. 34 is a front view of the external lead-out terminals 6a, 6b, 6c as seen through a resin material constituting a part of the outer case 6.

  FIG. 35 shows a state where the assembly shown in FIG. 32 (D) is mounted on the metal heat radiating plate 1 shown in FIG. 30 and the outer case 6 shown in FIGS. 33 and 34 is covered. It is a figure. More specifically, FIG. 35A shows that the assembly shown in FIG. 32D is mounted on the metal heat radiating plate 1 shown in FIG. 30, and the outer case shown in FIGS. It is the top view which showed the state in which 6 was covered. FIG. 35 (B) is a schematic exploded sectional view in a vertical section including the lower end portion 6a4 of the external lead-out terminal 6a, and FIG. 35 (C) is a lower end portion 6b4 of the external lead-out terminal 6b and a lower end portion of the external lead-out terminal 6c. FIG. 6 is a schematic exploded sectional view in a vertical section including 6c4. FIG. 36 is a component diagram of the lid 7 that covers the assembly shown in FIG. Specifically, FIG. 36A is a plan view of the lid 7, FIG. 36B is a front view of the lid 7, and FIG. 36C is a bottom view of the lid 7. FIG. 37 is a diagram showing a power semiconductor module 100 according to the fourth embodiment. Specifically, FIG. 37A is a plan view of the power semiconductor module 100 of the fourth embodiment obtained by covering the assembly shown in FIG. 35A with the lid 7 shown in FIG. FIG. FIG. 37B is a schematic vertical sectional view of the power semiconductor module 100 of the fourth embodiment obtained by bending the upper end portions of the external lead-out terminals 6a, 6b, 6c shown in FIG. is there. FIG. 37C is an equivalent circuit diagram of the power semiconductor module 100 of the fourth embodiment.

  In the power semiconductor module 100 of the fourth embodiment, as shown in FIGS. 35 (B) and 35 (C), a power semiconductor chip (IGBT chip) 3a (see FIGS. 32 and 35) and a power semiconductor chip (diode). Chips) 3b, 3c (see FIG. 32 and FIG. 35), the upper surface of the metal heat sink 1 (see FIG. 30 and FIG. 35) for radiating the heat, and the insulating substrate 2 (see FIG. 31 and FIG. 35). Lower surface side conductor pattern 2c (FIGS. 31B, 31C, and 35B) formed on the lower surface side of the insulating layer 2a (see FIGS. 31, 35B, and 35C). ) And FIG. 35C), the solder 10a (see FIG. 35B and FIG. 35C) is disposed. Further, as shown in FIG. 32B, the upper surface side conductor pattern 2b1 (FIGS. 31A, 31B, 32A, and 32) of the insulating substrate 2 (see FIGS. 31 and 32). Solder 10b1 (see FIG. 32B) is provided between the lower electrode (collector electrode) of the power semiconductor chip (IGBT chip) 3a (see FIG. 32A and FIG. 32B) and the power semiconductor chip (IGBT chip) 3a. Is arranged. Further, as shown in FIG. 32B, the upper surface side conductor pattern 2b3 (FIGS. 31A, 31B, 32A, and 32) of the insulating substrate 2 (see FIGS. 31 and 32). Solder 10b2 (see FIG. 32B) is provided between the lower electrode (cathode electrode) of the power semiconductor chip (diode chip) 3b (see FIGS. 32A and 32B) and the power semiconductor chip (diode chip) 3b. Is arranged. Further, as shown in FIG. 32C, the upper surface side conductor pattern 2b1 (FIGS. 31A, 31B, 32A, and 32) of the insulating substrate 2 (see FIGS. 31 and 32). (See (C)) and a solder 10b3 (see FIG. 32C) between the power semiconductor chip (diode chip) 3c (see FIG. 32A and FIG. 32C) and the lower electrode (cathode electrode). Has been placed.

  Further, in the power semiconductor module 100 of the fourth embodiment, as shown in FIG. 32D, the upper surface electrode (emitter electrode) for large current of the power semiconductor chip (IGBT chip) 3a and the insulating substrate 2 (FIG. 31 and FIG. 31). The upper surface side conductor pattern 2b2 (see FIG. 31A and FIG. 32D) of FIG. 32D is connected by a bonding wire. Furthermore, the gate electrode formed on the upper surface of the power semiconductor chip (IGBT chip) 3a and the upper surface side conductor pattern 2b4 (see FIGS. 31A and 32D) of the insulating substrate 2 (see FIGS. 31 and 32D). Are connected by a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3b and the upper surface side conductor pattern 2b1 (see FIGS. 31A and 32D) of the insulating substrate 2 (see FIGS. 31 and 32D). Are connected by a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c and the upper surface side conductor pattern 2b2 (see FIGS. 31A and 32D) of the insulating substrate 2 (see FIGS. 31 and 32D). Are connected by a bonding wire.

  Furthermore, in the power semiconductor module 100 of the fourth embodiment, as shown in FIGS. 33 and 34, the right side wall 6d (see FIG. 33C), the left side wall 6e (see FIG. 33C), and the front side wall. 6f (refer to FIG. 33) and rear side wall 6g (refer to FIG. 33 (A) and FIG. 33 (C)), and an outer case 6 (FIGS. 33 and 34) formed by molding an electrically insulating resin material. Reference) is provided.

  Further, in the power semiconductor module 100 of the fourth embodiment, as shown in FIG. 34, the upper end portion 6 a 1 protruding upward from the front side wall 6 f (see FIG. 33) of the outer case 6, and the outer case 6 An external lead-out terminal 6a having a central portion 6a2 embedded in the front side wall 6f (see FIG. 33) and a lower end portion 6a4 protruding downward from the front side wall 6f (see FIG. 33) of the outer casing 6 is provided. For example, it is formed by pressing a metal material.

  Furthermore, in the power semiconductor module 100 of the fourth embodiment, as shown in FIG. 34, the upper end portion 6 b 1 protruding upward from the front side wall 6 f (see FIG. 33) of the outer case 6, and the outer case 6 An external lead-out terminal 6b having a central portion 6b2 embedded in the front side wall 6f (see FIG. 33) and a lower end portion 6b4 protruding downward from the front side wall 6f (see FIG. 33) of the outer casing 6 is provided. For example, it is formed by pressing a metal material.

  Further, in the power semiconductor module 100 of the fourth embodiment, as shown in FIG. 34, the upper end portion 6c1 protruding upward from the front side wall 6f (see FIG. 33) of the outer case 6 and the outer case 6 An external lead-out terminal 6c having a central portion 6c2 embedded in the front side wall 6f (see FIG. 33) and a lower end portion 6c4 protruding downward from the front side wall 6f (see FIG. 33) of the outer casing 6 is provided. For example, the metal material is formed by press working.

  That is, in the power semiconductor module 100 of the fourth embodiment, the external lead-out terminal 6a is insert-molded on the front side wall 6f of the outer case 6 as shown in FIGS. An external lead-out terminal 6 b is insert-molded on the front side wall 6 f of the outer case 6. Further, the external lead-out terminal 6 c is insert-molded on the front side wall 6 f of the outer case 6.

  In the power semiconductor module 100 of the fourth embodiment, as shown in FIG. 35 (B), the upper surface side conductor pattern 2b2 (FIG. 35) of the insulating substrate 2 (see FIGS. 35 (A) and 35 (B)). (See (A) and FIG. 35 (B)) and the lower end portion 6a4 (see FIG. 35 (A) and FIG. 35 (B)) of the external lead-out terminal 6a (see FIG. 35 (A) and FIG. 35 (B)). Solder 10f1 (see FIG. 35 (B)) is arranged between the lower surface, upper surface side conductor pattern 2b2 (see FIGS. 35 (A) and 35 (B)), and external lead-out terminal 6a (FIG. 35 (A) and (See FIG. 35B). Further, as shown in FIG. 35C, the upper surface side conductor pattern 2b1 (see FIGS. 35A and 35C) of the insulating substrate 2 (see FIGS. 35A and 35C) and The solder 10f2 (see FIG. 35C) between the lower surface of the lower end portion 6b4 (see FIGS. 35A and 35C) of the external lead-out terminal 6b (see FIGS. 35A and 35C). )) Is arranged, and the upper surface side conductor pattern 2b1 (see FIGS. 35A and 35C) and the external lead-out terminal 6b (see FIGS. 35A and 35C) are electrically connected. It is connected. Further, as shown in FIG. 35C, the upper surface side conductor pattern 2b3 (see FIGS. 35A and 35C) of the insulating substrate 2 (see FIGS. 35A and 35C) and The solder 10f3 (see FIG. 35C) between the lower surface of the lower end portion 6c4 (see FIGS. 35A and 35C) of the external lead-out terminal 6c (see FIGS. 35A and 35C). )) Is arranged, and the upper surface side conductor pattern 2b3 (see FIGS. 35A and 35C) and the external lead-out terminal 6c (see FIGS. 35A and 35C) are electrically connected. It is connected.

  In the power semiconductor module 100 of the fourth embodiment, the signal terminal 6j (see FIGS. 33A, 33C, 35A, and 37C) is, for example, solder (not shown). Or the like) to the upper surface side conductor pattern 2b4 (see FIG. 32 (D) and FIG. 35 (A)) of the insulating substrate 2 (see FIG. 32 (D) and FIG. 35 (A)). Signal terminal 6j (see FIGS. 33A, 33C, 35A, and 37C) and power semiconductor chip (IGBT chip) 3a (FIGS. 32D and 35A) And the gate electrode formed on the upper surface of FIG. 37C is electrically connected. Further, the signal terminal 6k (see FIGS. 33 (A), 33 (C), 35 (A), and 37 (C)) is connected to the insulating substrate 2 (FIG. 32) via solder (not shown), for example. (D) and FIG. 35 (A)) are connected to the upper surface side conductor pattern 2b2 (see FIG. 32 (D) and FIG. 35 (A)), and as a result, the signal terminal 6k (FIG. 33 (A), FIG. 33). (C), FIG. 35 (A) and FIG. 37 (C)) and power semiconductor chip (IGBT chip) 3a (see FIG. 32 (D), FIG. 35 (A) and FIG. 37 (C)) The upper surface electrode (emitter electrode) is electrically connected.

  Furthermore, in the power semiconductor module 100 of the fourth embodiment, a gel resin (not shown) is filled inside the outer casing 6 of the assembly shown in FIG. At least the insulating substrate 2 (see FIG. 35), the power semiconductor chip (IGBT chip) 3a (see FIG. 35), the power semiconductor chips (diode chips) 3b and 3c (see FIG. 35), and the bonding wire (see FIG. 35). 35 (A)) and lower end portions 6a4, 6b4, 6c4 (FIGS. 33A, 33C, and 34) of the external lead-out terminals 6a, 6b, and 6c (see FIGS. 33, 34, and 35). And FIG. 35). Furthermore, the lid body 7 shown in FIG. 36 is put on the assembly shown in FIG. Specifically, as shown in FIG. 37 (A), when the lid 7 (see FIGS. 36, 37 (A) and 37 (B)) is mounted, the external lead-out terminal 6a (FIG. 35 (A), FIG. 35 (B) and FIG. 37 (A)) upper end portion 6a1 (see FIG. 35 (B)) is the lead-out hole 7a (see FIG. 36, FIG. 37 (A) and FIG. 37 (B)). 36 (A) and 36 (C)), and the upper end 6b1 (see FIG. 35 (B)) of the external lead-out terminal 6b (see FIGS. 35 (A), 35 (C) and 37 (A)). )) Is passed through the lead-out hole 7b (see FIG. 36A and FIG. 36C) of the lid body 7 (see FIG. 36, FIG. 37A and FIG. 37B) and the external lead-out terminal 6c. (See FIGS. 35A, 35C, and 37A) The upper end 6c1 (see FIG. 35B) is the lid 7 (see FIGS. 36, 37A). Deriving hole 7c beauty Figure 37 (B) refer) is passed through (Fig. 36 (A) and FIG. 36 (C) see). Next, a nut (not shown) is inserted into the recess 7f (see FIGS. 36A and 37A) on the upper surface of the lid 7 (see FIGS. 36, 37A and 37B). Is done. Next, the upper end portions 6a1, 6b1, 6c1 (see FIGS. 34 and 37B) of the external lead-out terminals 6a, 6b, 6c (see FIGS. 35, 37A and 37B) are bent, The power semiconductor module 100 of the fourth embodiment shown in FIG. 37B is completed.

  That is, in the power semiconductor module 100 of the fourth embodiment, as shown in FIGS. 35A and 37C, the upper surface electrode (emitter electrode) through which a large current flows and the lower electrode (collector) through which a large current flows. Power semiconductor chip (IGBT chip) 3a having a large current, and a power semiconductor chip (diode chip) 3b having a top electrode (anode electrode) through which a large current flows and a bottom electrode (cathode electrode) through which a large current flows , 3c are provided. As shown in FIG. 32A, a power semiconductor chip (IGBT chip) 3a is mounted on the upper surface side conductor pattern 2b1 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Furthermore, as shown in FIG. 32B, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrode (collector electrode) of the power semiconductor chip (IGBT chip) 3a are electrically connected. As shown in FIG. 32A, a power semiconductor chip (diode chip) 3b is mounted on the upper surface side conductor pattern 2b3 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Furthermore, as shown in FIG. 32B, the upper surface side conductor pattern 2b3 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3b are electrically connected. As shown in FIG. 32A, a power semiconductor chip (diode chip) 3c is mounted on the upper surface side conductor pattern 2b1 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Furthermore, as shown in FIG. 32C, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3c are electrically connected.

  In the power semiconductor module 100 of the fourth embodiment, as shown in FIG. 32D, the upper surface electrode (emitter electrode) of the power semiconductor chip (IGBT chip) 3a and the insulating substrate 2 are connected via bonding wires. The upper surface side conductor pattern 2b2 is electrically connected. Furthermore, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3b and the upper surface side conductor pattern 2b1 of the insulating substrate 2 are electrically connected via a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c and the upper surface side conductor pattern 2b2 of the insulating substrate 2 are electrically connected via a bonding wire.

  Specifically, in the power semiconductor module 100 of the fourth embodiment, first, as shown in FIGS. 32B and 32C, the power semiconductor chip (IGBT chip) 3a (FIG. 32A). And the solder 10b1 between the lower surface electrode (collector electrode) in FIG. 32B and the upper surface side conductor pattern 2b1 (see FIG. 32A and FIG. 32B) of the insulating substrate 2 (see FIG. 32). (Refer to FIG. 32 (B)), the lower electrode (cathode electrode) of the power semiconductor chip (diode chip) 3b (refer to FIG. 32 (A) and FIG. 32 (C)) and the insulating substrate 2 (refer to FIG. 32). Joining with the upper surface side conductor pattern 2b3 (see FIGS. 32A and 32B) by solder 10b2 (see FIG. 32B), and a power semiconductor chip (diode chip) 3c (FIG. 3) (A) and FIG. 32 (C)) between the lower surface electrode (cathode electrode) and the upper surface side conductor pattern 2b1 (see FIG. 32 (A) and FIG. 32 (C)) of the insulating substrate 2 (see FIG. 32). Bonding with the solder 10b3 (see FIG. 32C) is performed. Next, wire bonding shown in FIG. 32D is performed. Next, as shown in FIGS. 35B and 35C, the lower surface side conductor pattern 2c (see FIG. 31 and FIG. 35) of the metal heat sink 1 (see FIGS. 30 and 35) and the insulating substrate 2 (see FIGS. 31 and 35). 31B, FIG. 31C, FIG. 35B, and FIG. 35C)) are joined by the solder 10a (see FIG. 35B and FIG. 35C), an insulating substrate 2 (see FIG. 31 and FIG. 35) and the upper conductor pattern 2b1 (see FIG. 31A, FIG. 35A and FIG. 35C) and the external lead-out terminal 6b (FIG. 35A and FIG. 35). C)) to the lower end 6b4 (see FIG. 35A and FIG. 35C), the soldering board 10f2 (see FIG. 35C), and the insulating substrate 2 (see FIG. 31 and FIG. 35). Of the upper surface side conductor pattern 2b2 (FIG. 31A, FIG. 35A and FIG. )) And the lower end 6a4 (see FIGS. 35A and 35B) of the external lead-out terminal 6a (see FIGS. 35A and 35B) (see FIG. 35 (1)). B)), and the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead-out terminal 6c. Joining is performed by solder 10f3 (see FIG. 35C) between the lower end portion 6c4 (see FIGS. 35A and 35C) of (see FIGS. 35A and 35C). Is done. Further, when performing the solder bonding shown in FIGS. 35B and 35C, a basing jig (such as the power semiconductor module described in FIG. 3 of Patent Document 1 (Japanese Patent Laid-Open No. 2010-199251)) ( The metal heat dissipating plate 1 (see FIG. 35) becomes a basing jig (not shown) so that the lower surface of the metal heat dissipating plate 1 (see FIG. 35) is deformed into a convex shape following the concave upper surface of the not shown. It is fixed against. Specifically, in the power semiconductor module 100 of the fourth embodiment, a screw (not shown) for fixing the metal heat radiating plate 1 (see FIG. 35) to a base jig (not shown), The outer case 6 (see FIGS. 33 and 35A) is also fastened together. That is, the assembly in the state shown in FIG. 35A is fixed to a basing jig (not shown) with screws (not shown).

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have made the lower surface side conductor pattern 2c (see FIG. 35) of the metal heat sink 1 (see FIG. 35) and the insulating substrate 2 (see FIG. 35). 35 (B) and FIG. 35 (C)) were subjected to a temperature cycle test of solder bonding. Specifically, in the study by the present inventors, the lower surface side conductor pattern 2c (FIGS. 35B and 35C) of the metal heat sink 1 (see FIG. 35) and the insulating substrate 2 (see FIG. 35). A temperature cycle test was performed using Pb (lead) -free solder having a low tensile strength and containing no Sb (antimony). As a result, after the temperature cycle test, between the metal heat sink 1 (see FIG. 35) and the lower surface side conductor pattern 2c (see FIG. 35B and FIG. 35C) of the insulating substrate 2 (see FIG. 35). It was confirmed that the Pb-free solder containing no Sb was peeled off.

  The present inventors have soldered between the metal heat sink 1 (see FIG. 35) and the lower surface side conductor pattern 2c (see FIGS. 35B and 35C) of the insulating substrate 2 (see FIG. 35). In the study by the present inventors, the lower surface side conductor pattern 2c (see FIG. 35B) of the metal heat sink 1 (see FIG. 35) and the insulating substrate 2 (see FIG. 35) is considered. And Pb-free solder containing Sb with high tensile strength (alloy composition is Sn-3.9Ag-0.6Cu-3.0Sb, for example) A temperature cycle test was conducted. As a result, after the temperature cycle test, between the metal heat sink 1 (see FIG. 35) and the lower surface side conductor pattern 2c (see FIG. 35B and FIG. 35C) of the insulating substrate 2 (see FIG. 35). It was confirmed that the Pb-free solder containing Sb was not peeled off.

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b1 (FIG. 31A, FIG. 35) of the insulating substrate 2 (see FIGS. 31 and 35). A) and FIG. 35 (C)) and the lower end portion 6b4 (see FIGS. 35 (A) and 35 (C) of the external lead-out terminal 6b (see FIGS. 33, 34, 35 (A) and 35 (C))). The temperature cycle test of the solder joint was conducted between Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35). And a lower end portion 6b4 (see FIGS. 35A and 35C) of the external lead terminal 6b (see FIGS. 33, 34, 35A, and 35C). A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead-out terminal 6b. The Pb-free solder containing Sb between the lower end 6b4 (see FIGS. 35 (A) and 35 (C)) of FIG. 33, FIG. 34, FIG. 35 (A) and FIG. 35 (C)) Although peeling is not recognized, the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) is damaged. Was confirmed.

  Vertical direction at the time of a temperature cycle test of the external lead-out terminal 6b (see FIGS. 33, 34, 35A and 35C) insert-molded in the outer case 6 (see FIGS. 33 and 34) The amount of thermal expansion / contraction in the vertical direction (FIG. 33B) and the vertical direction during the temperature cycle test of the outer case 6 (see FIGS. 33 and 34) made of resin material (FIG. 33). Since the amount of thermal expansion / contraction in the vertical direction (B) is different, the upper surface side conductor pattern 2b1 (FIGS. 31A, 35A) and 35A of the insulating substrate 2 (see FIGS. 31 and 35) and 35C) and the lower end 6b4 of the external lead-out terminal 6b (see FIGS. 33, 34, 35A and 35C) (see FIGS. 35A and 35C) Pb containing Sb with high tensile strength for solder joint When lead solder is used, the heat in the vertical direction (the vertical direction in FIG. 33B) of the external lead-out terminal 6b (see FIGS. 33, 34, 35A and 35C) during the temperature cycle test. The difference between the expansion amount / heat shrinkage amount and the thermal expansion amount / heat shrinkage amount in the vertical direction (vertical direction in FIG. 33 (B)) of the surrounding case 6 (see FIGS. 33 and 34) contains Sb. As a result, the Pb-free solder cannot be sufficiently absorbed, and as a result, the upper surface side conductor pattern 2b1 (FIGS. 31A, 35A, and 35) of the insulating substrate 2 (see FIGS. 31 and 35). The upper surface side conductor pattern 2b1 (see FIGS. 31 (A), 35 (A), and 35 (C)) of the insulating substrate 2 (see FIGS. 31 and 35) is damaged by the thermal stress applied to (C). The present inventors thought.

  Therefore, in the study by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external derivation. Tensile strength is applied to the solder joint between the lower end 6b4 (see FIGS. 35A and 35C) of the terminal 6b (see FIGS. 33, 34, 35A, and 35C). The Pb-free solder (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) having a low Sb content was subjected to a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead-out terminal 6b. Pb-free solder containing no Sb between the lower end 6b4 (see FIGS. 35 (A) and 35 (C)) of FIG. 33, FIG. 34, FIG. 35 (A) and FIG. 35 (C)) It was confirmed that the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) was not damaged without peeling.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b2 (FIGS. 31A and 35) of the insulating substrate 2 (see FIGS. 31 and 35). A) and FIG. 35 (B)) and the lower end 6a4 (FIG. 35 (A) and FIG. 35 (B) of the external lead-out terminal 6a (see FIG. 33, FIG. 34, FIG. 35 (A) and FIG. 35 (B))). The temperature cycle test of the solder joint was conducted between Specifically, in the research conducted by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35). And the external lead-out terminal 6a (see FIGS. 33, 34, 35 (A) and 35 (B)) at the lower end 6a4 (see FIGS. 35 (A) and 35 (B)) A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead terminal 6a. Pb-free solder containing Sb between the lower end 6a4 (see FIGS. 35 (A) and 35 (B)) of FIG. 33, FIG. 34, FIG. 35 (A) and FIG. 35 (B)) Although peeling is not recognized, the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35) is damaged. Was confirmed.

  Vertical direction at the time of the temperature cycle test of the external lead-out terminal 6a (see FIGS. 33, 34, 35A and 35B) insert-molded in the outer case 6 (see FIGS. 33 and 34) The amount of thermal expansion / contraction in the vertical direction (FIG. 33B) and the vertical direction during the temperature cycle test of the outer case 6 (see FIGS. 33 and 34) made of a resin material (FIG. 33). Since the amount of thermal expansion / contraction in the vertical direction of (B) is different, the upper surface side conductor pattern 2b2 (FIGS. 31A, 35A) and 35A of the insulating substrate 2 (see FIGS. 31 and 35) and 35B) and the lower end 6a4 of the external lead-out terminal 6a (see FIGS. 33, 34, 35A, and 35B) (see FIGS. 35A and 35B) Pb containing Sb with high tensile strength for solder joint When lead solder is used, the heat in the vertical direction (the vertical direction in FIG. 33B) of the external lead-out terminal 6a (see FIGS. 33, 34, 35A and 35B) during the temperature cycle test. The difference between the expansion amount / heat shrinkage amount and the thermal expansion amount / heat shrinkage amount in the vertical direction (vertical direction in FIG. 33 (B)) of the surrounding case 6 (see FIGS. 33 and 34) contains Sb. As a result, the Pb-free solder cannot be sufficiently absorbed, and as a result, the upper surface side conductor pattern 2b2 (FIGS. 31A, 35A, and 35) of the insulating substrate 2 (see FIGS. 31 and 35). The upper surface side conductor pattern 2b2 (see FIGS. 31 (A), 35 (A), and 35 (B)) of the insulating substrate 2 (see FIGS. 31 and 35) is damaged by the thermal stress applied to (B). The present inventors thought.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35) and external derivation. Tensile strength is applied to the solder joint between the lower end 6a4 (see FIGS. 35A and 35B) of the terminal 6a (see FIGS. 33, 34, 35A, and 35B). The Pb-free solder (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) having a low Sb content was subjected to a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead terminal 6a. Pb-free solder containing no Sb between the lower end portion 6a4 (see FIGS. 35 (A) and 35 (B)) of (see FIGS. 33, 34, 35 (A) and 35 (B)). It was confirmed that the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35) was not damaged without peeling.

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b3 (FIGS. 31A and 35) of the insulating substrate 2 (see FIGS. 31 and 35). A) and FIG. 35 (C)) and the lower end portion 6c4 (FIG. 35 (A) and FIG. 35 (C) of the external lead-out terminal 6c (see FIG. 33, FIG. 34, FIG. 35 (A) and FIG. 35 (C))). The temperature cycle test of the solder joint was conducted between Specifically, in the research conducted by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35). And the outer lead terminal 6c (see FIGS. 33, 34, 35A, and 35C) at the lower end 6c4 (see FIGS. 35A and 35C)) A temperature cycle test was performed using a Pb-free solder containing Sb having a high tensile strength. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead terminal 6c. Pb-free solder containing Sb between the lower end 6c4 (see FIGS. 35 (A) and 35 (C)) of FIG. 33, FIG. 34, FIG. 35 (A) and FIG. 35 (C)) Although peeling is not recognized, the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) is damaged. Was confirmed.

  Vertical direction at the time of a temperature cycle test of the external lead-out terminal 6c (see FIGS. 33, 34, 35A, and 35C) insert-molded in the outer case 6 (see FIGS. 33 and 34) The amount of thermal expansion / contraction in the vertical direction (FIG. 33B) and the vertical direction during the temperature cycle test of the outer case 6 (see FIGS. 33 and 34) made of a resin material (FIG. 33). Since the amount of thermal expansion / contraction in the vertical direction of (B) is different, the upper surface side conductor pattern 2b3 (FIGS. 31A, 35A) and 35A of the insulating substrate 2 (see FIGS. 31 and 35) and 35C) and the lower end 6c4 of the external lead-out terminal 6c (see FIGS. 33, 34, 35A, and 35C) (see FIGS. 35A and 35C) Pb containing Sb with high tensile strength for solder joint When lead solder is used, the heat in the vertical direction (vertical direction in FIG. 33B) of the external lead-out terminal 6c (see FIGS. 33, 34, 35A and 35C) during the temperature cycle test. The difference between the expansion amount / heat shrinkage amount and the thermal expansion amount / heat shrinkage amount in the vertical direction (vertical direction in FIG. 33 (B)) of the surrounding case 6 (see FIGS. 33 and 34) contains Sb. As a result, the Pb-free solder cannot be sufficiently absorbed, and as a result, the upper surface side conductor pattern 2b3 (FIGS. 31A, 35A, and 35) of the insulating substrate 2 (see FIGS. 31 and 35). The upper surface side conductor pattern 2b3 (see FIGS. 31 (A), 35 (A), and 35 (C)) of the insulating substrate 2 (see FIGS. 31 and 35) is damaged by the thermal stress applied to (C). The present inventors thought.

  Therefore, in the study by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and external derivation. Tensile strength is applied to the solder joint between the lower end 6c4 (see FIGS. 35 (A) and 35 (C)) of the terminal 6c (see FIGS. 33, 34, 35 (A) and 35 (C)). The Pb-free solder (alloy composition such as Sn-0.3Ag-0.7Cu-0.035Ni, Sn-0.7Cu-0.05Ni, etc.) having a low Sb content was subjected to a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead terminal 6c. Pb-free solder containing no Sb between the lower end portion 6c4 (see FIGS. 35 (A) and 35 (C)) of FIG. 33, FIG. 34, FIG. 35 (A) and FIG. 35 (C)) It was confirmed that the upper surface side conductor pattern 2b3 (see FIGS. 31 (A), 35 (A) and 35 (C)) of the insulating substrate 2 (see FIGS. 31 and 35) was not damaged without peeling.

  In view of the research results of the present inventors, in the power semiconductor module 100 of the fourth embodiment, the lower surface side of the metal heat sink 1 (see FIGS. 30 and 35) and the insulating substrate 2 (see FIGS. 31 and 35). Pb-free solder 10a containing Sb (see FIG. 35B) for solder joint with the conductor pattern 2c (see FIG. 31B, FIG. 31C, FIG. 35B, and FIG. 35C). ) And FIG. 35 (C)).

  Therefore, according to the power semiconductor module 100 of the fourth embodiment, the lower surface side conductors of the metal heat sink 1 (see FIGS. 30 and 35) and the insulating substrate 2 (see FIGS. 31 and 35) after the temperature cycle test. Separation of solder 10a (see FIGS. 35B and 35C) between pattern 2c (see FIGS. 31B, 31C, 35B, and 35C) The lower surface conductor pattern 2c (FIGS. 31B and 31C) of the metal heat sink 1 (see FIGS. 30 and 35) and the insulating substrate 2 (see FIGS. 31 and 35). , See FIG. 35B and FIG. 35C), the reliability of the solder joint can be improved.

  Furthermore, in the power semiconductor module 100 of the fourth embodiment, the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35). ) And the lower end portion 6b4 (see FIGS. 35A and 35C) of the external lead-out terminal 6b (see FIGS. 35A and 35C) contains Sb. A Pb-free solder 10f2 (see FIG. 35C) that does not contain Sb and has a tensile strength lower than that of the Pb-free solder 10a (see FIGS. 35B and 35C) is used.

  Therefore, according to the power semiconductor module 100 of the fourth embodiment, the upper surface side conductor pattern 2b1 (FIGS. 31A and 35A) of the insulating substrate 2 (see FIGS. 31 and 35) after the temperature cycle test. And the solder between the lower end portion 6b4 (see FIGS. 35 (A) and 35 (C)) of the external lead-out terminal 6b (see FIGS. 35 (A) and 35 (C)). 10f2 (see FIG. 35C) and the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35). Damage can be avoided at the same time, and the upper surface side conductor pattern 2b1 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead-out terminal 6b (FIG. 35 (A) and FIG. 35 ( ) Reference) the lower end 6b4 (it is possible to improve the solder joint reliability between the FIG. 35 (A) and see FIG. 35 (C)) of.

  In the power semiconductor module 100 of the fourth embodiment, the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35). ) And the lower end portion 6a4 (see FIGS. 35A and 35B) of the external lead-out terminal 6a (see FIGS. 35A and 35B) contains Sb. Pb-free solder 10f1 (see FIG. 35B) that does not contain Sb and has a lower tensile strength than Pb-free solder 10a (see FIGS. 35B and 35C) is used.

  Therefore, according to the power semiconductor module 100 of the fourth embodiment, the upper surface side conductor pattern 2b2 (FIGS. 31A and 35A) of the insulating substrate 2 (see FIGS. 31 and 35) after the temperature cycle test. And the solder between the lower end portion 6a4 (see FIGS. 35 (A) and 35 (B)) of the external lead-out terminal 6a (see FIGS. 35 (A) and 35 (B)). 10f1 (see FIG. 35 (B)) and the upper surface side conductor pattern 2b2 (see FIGS. 31 (A), 35 (A), and 35 (B)) of the insulating substrate 2 (see FIGS. 31 and 35). Damage can be avoided at the same time, and the upper surface side conductor pattern 2b2 (see FIGS. 31A, 35A, and 35B) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead-out terminal 6a (FIG. 35 (A) and FIG. 35 ( ) Reference) the lower end 6a4 (it is possible to improve the solder joint reliability between the FIG. 35 (A) and FIG. 35 (B) refer) of.

  Furthermore, in the power semiconductor module 100 of the fourth embodiment, the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35). ) And an external lead terminal 6c (see FIGS. 35A and 35C), Sb is contained in the solder joint between the lower end portion 6c4 (see FIGS. 35A and 35C). A Pb-free solder 10f3 (see FIG. 35C) that does not contain Sb and has a tensile strength lower than that of the Pb-free solder 10a (see FIGS. 35B and 35C) is used.

  Therefore, according to the power semiconductor module 100 of the fourth embodiment, the upper surface side conductor pattern 2b3 (FIGS. 31A and 35A) of the insulating substrate 2 (see FIGS. 31 and 35) after the temperature cycle test. And the solder between the lower end portion 6c4 (see FIGS. 35A and 35C) of the external lead-out terminal 6c (see FIGS. 35A and 35C). 10f3 (see FIG. 35C) and the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35). Damage can be avoided at the same time, and the upper surface side conductor pattern 2b3 (see FIGS. 31A, 35A, and 35C) of the insulating substrate 2 (see FIGS. 31 and 35) and the external lead-out terminal 6c (FIG. 35A and FIG. ) Reference) the lower end 6c4 (it is possible to improve the solder joint reliability between the FIG. 35 (A) and see FIG. 35 (C)) of.

  In the power semiconductor module 100 of the fourth embodiment, as the solders 10b1 and 10b2 (see FIG. 32B), the Pb-free solder 10a containing Sb (see FIGS. 35B and 35C) is used. Pb-free solder having low tensile strength and containing no Sb is used, but in the modified example of the power semiconductor module 100 of the fourth embodiment, instead of solders 10b1 and 10b2 (see FIG. 32 (B)). Similarly to the solder 10a (see FIGS. 35B and 35C), it is also possible to use Pb-free solder containing Sb and having high tensile strength.

  In the power semiconductor module 100 of the fourth embodiment, the solder 10b3 (see FIG. 32C) is more than the Pb-free solder 10a containing Sb (see FIGS. 35B and 35C). Pb-free solder having a low tensile strength and containing no Sb is used. However, in the modified example of the power semiconductor module 100 of the fourth embodiment, instead of the solder 10b3 (see FIG. 32C), the solder is used. Similarly to 10a (see FIGS. 35B and 35C), it is also possible to use Pb-free solder containing Sb having high tensile strength.

  Hereinafter, a fifth embodiment of the power semiconductor module of the present invention will be described. FIG. 38 is a view showing the metal heat sink 1 constituting a part of the power semiconductor module 100 of the fifth embodiment. Specifically, FIG. 38A is a plan view of the metal heat sink 1, and FIG. 38B is a vertical cross-sectional view along the line A4-A4 of FIG. FIG. 39 is a view showing an insulating substrate 2 constituting a part of the power semiconductor module 100 of the fifth embodiment. Specifically, FIG. 39A is a plan view of the insulating substrate 2, FIG. 39B is a vertical sectional view taken along line B4-B4 of FIG. 39A, and FIG. It is a bottom view. FIG. 40 is a diagram illustrating a state in which the power semiconductor chips 3a, 3b, 3c, and 3d are mounted on the insulating substrate 2. Specifically, FIG. 40A is a plan view showing a state where power semiconductor chips (IGBT chips) 3 a and 3 b and power semiconductor chips (diode chips) 3 c and 3 d are mounted on the insulating substrate 2. FIG. 40 (B) is an exploded sectional view taken along line C4-C4 of FIG. 40 (A). FIG. 40C is a plan view of an assembly obtained by performing wire bonding on the assembly shown in FIG.

  FIG. 41 is a component diagram of the lid 7 constituting a part of the power semiconductor module 100 of the fifth embodiment. Specifically, FIG. 41A is a plan view of the lid 7, FIG. 41B is a right side view of the lid 7, FIG. 41C is a front view of the lid 7, and FIG. FIG. 6 is a bottom view of the lid body 7. FIG. 42 is a view showing an assembly obtained by attaching the external lead terminals 6a, 6b, 6c and the signal terminals 6j, 6k, 6m, 6n to the lid 7. Specifically, FIG. 42A is a plan view of an assembly obtained by attaching the external lead-out terminals 6a, 6b, and 6c and the signal terminals 6j, 6k, 6m, and 6n to the lid body 7, and FIG. FIG. 42C is a front view of the assembly obtained by attaching the external lead terminals 6a, 6b, 6c and the signal terminals 6j, 6k, 6m, 6n to the lid body 7, and FIG. FIG. 6 is a right side view of an assembly obtained by attaching terminals 6j, 6k, 6m, and 6n to the lid body 7.

  43 is a view of the external lead-out terminals 6a, 6b, and 6c as seen through the lid body 7 of the assembly shown in FIG. Specifically, FIG. 43A is a plan view of the external lead-out terminals 6a, 6b, and 6c, FIG. 43B is a front view of the external lead-out terminals 6a, 6b, and 6c, and FIG. 43C is the external lead-out terminal 6c. It is a right view of (6a, 6b). FIG. 44 is a diagram of signal terminals 6j, 6k, 6m, and 6n as seen through the lid body 7 of the assembly shown in FIG. Specifically, FIG. 44A is a plan view of the signal terminals 6j, 6k, 6m, and 6n, FIG. 44B is a front view of the signal terminals 6m (6j, 6k, and 6n), and FIG. It is a right view of terminal 6j, 6k, 6m, 6n. FIG. 45 is a diagram showing a state in which the assembly shown in FIG. 40C is mounted on the metal heat sink 1 shown in FIG. 38 and the assembly shown in FIG. 42 is mounted thereon. is there. More specifically, in FIG. 45 (A), the assembly shown in FIG. 40 (C) is mounted on the metal heat sink 1 shown in FIG. 38, and the assembly shown in FIG. 42 is mounted thereon. It is the top view which showed the state. FIG. 45 (B) shows a state in which the assembly shown in FIG. 40 (C) is mounted on the metal heat sink 1 shown in FIG. 38, and the assembly shown in FIG. FIG. 3 is a schematic exploded view showing the lid body 7 seen through.

  FIG. 46 is a component diagram of the enclosing case 6 that covers the assembly shown in FIG. Specifically, FIG. 46A is a plan view of the outer case 6, FIG. 46B is a vertical sectional view taken along the line K4-K4 of FIG. 46A, and FIG. 46C is an outer case. 6 is a bottom view of FIG. FIG. 47 is a diagram showing a power semiconductor module 100 according to the fifth embodiment. Specifically, FIG. 47A shows a power semiconductor module 100 of the fifth embodiment obtained by covering the assembly shown in FIG. 45A with the outer case 6 shown in FIG. It is a top view. FIG. 47B is a schematic vertical sectional view of the power semiconductor module 100 according to the fifth embodiment. FIG. 47C is an equivalent circuit diagram of the power semiconductor module 100 of the fifth embodiment.

  In the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 45B, power semiconductor chips (IGBT chips) 3a, 3b (see FIG. 40) and power semiconductor chips (diode chips) 3c, 3d (see FIG. 45). 40) and the insulating layer 2a (FIGS. 39 and 45) of the insulating substrate 2 (see FIGS. 39 and 45) and the upper surface of the metal heat radiating plate 1 (see FIGS. 38 and 45) for radiating the heat generated. Solder 10a (see FIG. 45B) between the lower surface side conductor pattern 2c (see FIG. 39B, FIG. 39C and FIG. 45B) formed on the lower surface side of FIG. ) Is arranged. As shown in FIG. 40B, the upper surface side conductor pattern 2b1 (FIGS. 39A, 39B, 40A, and 40) of the insulating substrate 2 (see FIGS. 39 and 40). Solder 10b1 (see FIG. 40B) is provided between the lower electrode (collector electrode) of the power semiconductor chip (IGBT chip) 3a (see FIGS. 40A and 40B) and the power semiconductor chip (IGBT chip) 3a. Has been placed. Further, the upper surface side conductor pattern 2b3 (see FIGS. 39A, 39B, 40A, and 40B) of the insulating substrate 2 (see FIGS. 39 and 40) and the power semiconductor chip (see FIG. 39). Solder 10b2 (see FIG. 40B) is arranged between the lower surface electrode (collector electrode) of IGBT chip) 3b (see FIGS. 40A and 40B). As shown in FIG. 40B, the upper surface side conductor pattern 2b1 (FIGS. 39A, 39B, 40A, and 40) of the insulating substrate 2 (see FIGS. 39 and 40). Solder 10b3 (see FIG. 40B) is placed between the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3c (see FIGS. 40A and 40B) and the power semiconductor chip (diode chip) 3c. Has been placed. Further, as shown in FIG. 40B, the upper surface side conductor pattern 2b3 (FIGS. 39A, 39B, 40A, and 40) of the insulating substrate 2 (see FIGS. 39 and 40). Solder 10b4 (see FIG. 40 (B)) is provided between the lower electrode (cathode electrode) of the power semiconductor chip (diode chip) 3d (see FIG. 40 (A) and FIG. 40 (B)) and the power semiconductor chip (diode chip) 3d. Has been placed.

  Further, in the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 40C, the upper surface electrode (emitter electrode) for large current of the power semiconductor chip (IGBT chip) 3a and the insulating substrate 2 (FIG. 39 and FIG. 39). The upper surface side conductor pattern 2b2 (see FIG. 39A and FIG. 40C) in FIG. 40C is connected by a bonding wire. Furthermore, the gate electrode formed on the upper surface of the power semiconductor chip (IGBT chip) 3a and the upper surface side conductor pattern 2b4 (see FIGS. 39A and 40C) of the insulating substrate 2 (see FIGS. 39 and 40C). Are connected by a bonding wire. Further, the upper electrode (emitter electrode) for large current of the power semiconductor chip (IGBT chip) 3b and the upper surface side conductor pattern 2b1 (see FIGS. 39A and 40) of the insulating substrate 2 (see FIGS. 39 and 40C). (See (C)) is connected by a bonding wire. Furthermore, the gate electrode formed on the upper surface of the power semiconductor chip (IGBT chip) 3b and the upper surface side conductor pattern 2b5 (see FIGS. 39A and 40C) of the insulating substrate 2 (see FIGS. 39 and 40C). Are connected by a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c and the upper surface side conductor pattern 2b2 (see FIGS. 39A and 40C) of the insulating substrate 2 (see FIGS. 39 and 40C). Are connected by a bonding wire. Furthermore, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3d and the upper surface side conductor pattern 2b1 (FIGS. 39A and 40C) of the insulating substrate 2 (see FIGS. 39 and 40C). Are connected by a bonding wire.

  Furthermore, in the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 41, an electrically insulating lid 7 formed by molding a resin material, for example, is provided. Specifically, in the power semiconductor module 100 of the fifth embodiment, the positioning hole 2h (see FIGS. 39A and 39C) of the insulating substrate 2 (see FIG. 39) and the metal heat sink 1 (see FIG. 39). 38), the leg portion 7g (see FIGS. 41B, 41C, and 41D) having a tip inserted into the positioning hole 1h (see FIG. 38A) is a lid. 7 (see FIG. 41).

  Further, in the power semiconductor module 100 of the fifth embodiment, as shown in FIGS. 43A and 43B, an upper end 6a1 extending in the vertical direction (the vertical direction in FIG. 43B) and The external lead-out terminal 6a having the bent central portion 6a2 and the lower end portion 6a4 extending in the horizontal direction is formed by, for example, pressing a metal material. Further, in the power semiconductor module 100 of the fifth embodiment, as shown in FIGS. 43A and 43B, the upper end portion 6b1 extending in the vertical direction (the vertical direction in FIG. 43B) and The external lead-out terminal 6b having the bent center part 6b2 and the lower end part 6b4 extending in the horizontal direction is formed into the external lead-out terminal 6a (FIG. 43A and FIG. It is formed in the same shape as B). Furthermore, in the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 43, the upper end portion 6c1 extending in the vertical direction (the vertical direction in FIGS. 43B and 43C) and the bent portion are bent. The external lead-out terminal 6c having a central portion 6c2 and a lower end portion 6c4 extending in the horizontal direction (left-right direction in FIG. 43C) is, for example, formed by pressing a metal material. (See (A) and FIG. 43 (B)).

  At the time of manufacturing the power semiconductor module 100 of the fifth embodiment, the upper end portion 6a1 (see FIG. 42) of the external lead-out terminal 6a (see FIGS. 42A, 42B, 43A, and 43B). 42 (B), FIG. 43 (A), and FIG. 43 (B)) are lead-out holes 7a (FIGS. 41A, 41C, and 42) of the lid body 7 (see FIGS. 41 and 42). A), and the external lead-out terminal 6a is attached to the lid body 7 as shown in FIG. Further, the upper end portion 6b1 (FIGS. 42B, 43A and 43) of the external lead-out terminal 6b (see FIGS. 42A, 42B, 43A and 43B) is shown. 43 (B)) is passed through the lead-out hole 7b (see FIGS. 41 (A), 41 (C) and 42 (A)) of the lid 7 (see FIGS. 41 and 42), and is shown in FIG. As described above, the external lead-out terminal 6 b is attached to the lid body 7. Further, the upper end portion 6c1 (see FIGS. 42B, 42C, and 43) of the external lead-out terminal 6c (see FIGS. 42 and 43) is a lead-out hole of the lid body 7 (see FIGS. 41 and 42). 7c (see FIGS. 41 (A), 41 (C) and 42 (A)), and the external lead-out terminal 6c is attached to the lid 7 as shown in FIG.

  Further, at the time of manufacturing the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 42, the signal terminal 6j (FIGS. 42A, 42C, 44A, and 44C). Is attached to the lid 7. Furthermore, the signal terminal 6k (see FIGS. 42A and 42) formed in the same shape as the signal terminal 6j (see FIGS. 42A, 42C, 44A, and 44C). (C), FIG. 44 (A) and FIG. 44 (C)) are attached to the lid body 7. Further, a signal terminal 6m (see FIGS. 42 and 44) formed in the same shape as the signal terminal 6j (see FIGS. 42A, 42C, 44A, and 44C) is provided. Attached to the lid 7. Further, the signal terminal 6n (see FIGS. 42A and 42) formed in the same shape as the signal terminal 6j (see FIGS. 42A, 42C, 44A, and 44C). (C), FIG. 44 (A) and FIG. 44 (C)) are attached to the lid body 7.

  In the power semiconductor module 100 of the fifth embodiment, external lead terminals 6a, 6b, 6c (see FIG. 43) and signal terminals 6j, 6k, 6m, 6n formed separately from the lid 7 (see FIG. 41). (See FIG. 44) is attached to the lid body 7 (see FIG. 41), and the assembly shown in FIG. 42 is formed. In the modification of the power semiconductor module 100 of the fifth embodiment, The external lead-out terminals 6a, 6b, and 6c and the signal terminals 6j, 6k, 6m, and 6n are inserted into the lid body 7 formed by molding the resin material and integrally molded, so that the same assembly as shown in FIG. It is also possible to form an assembly.

  In the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 45 (B), the upper surface side conductor pattern 2b2 (FIG. 40) of the insulating substrate 2 (see FIGS. 45 (A) and 45 (B)). (See (A) and FIG. 45 (B)) and the lower end portion 6a4 (see FIG. 43 (A) and FIG. 45 (B)) of the external lead-out terminal 6a (see FIG. 45 (A) and FIG. 45 (B)). Solder 10f1 (see FIG. 45 (B)) is arranged between the lower surface, upper surface side conductor pattern 2b2 (see FIGS. 40 (A) and 45 (B)), and external lead-out terminal 6a (FIG. 45 (A) and (See FIG. 45B). Further, as shown in FIG. 45B, the upper surface side conductor pattern 2b1 (see FIGS. 40A and 45B) of the insulating substrate 2 (see FIGS. 45A and 45B) and The solder 10f2 (see FIG. 45 (B) between the lower surface of the lower end portion 6b4 (see FIGS. 43 (A) and 45 (B)) of the external lead-out terminal 6b (see FIGS. 45 (A) and 45 (B)). )) Is arranged, and the upper surface side conductor pattern 2b1 (see FIGS. 40A and 45B) and the external lead-out terminal 6b (see FIGS. 45A and 45B) are electrically connected. It is connected. Further, as shown in FIG. 45B, the upper surface side conductor pattern 2b3 (see FIGS. 40A and 45B) of the insulating substrate 2 (see FIGS. 45A and 45B) and The solder 10f3 (see FIG. 45 (B) between the lower surface of the lower end portion 6c4 (see FIGS. 43 (A) and 45 (B)) of the external lead-out terminal 6c (see FIGS. 45 (A) and 45 (B)). )) Is arranged, and the upper surface side conductor pattern 2b3 (see FIGS. 40A and 45B) and the external lead-out terminal 6c (see FIGS. 45A and 45B) are electrically connected. It is connected.

  Specifically, in the power semiconductor module 100 of the fifth embodiment, the leg portion 7g (see FIGS. 41B and 41) of the lid body 7 (see FIG. 41) during the manufacturing process shown in FIG. (C) and the tip of FIG. 41 (D) are the positioning holes 2h (see FIG. 39 (A) and FIG. 39 (C)) of the insulating substrate 2 (see FIG. 39) and the metal heat sink 1 (see FIG. 38) is inserted into the positioning hole 1h (see FIG. 38A), and as a result, the lower end 6a4 (see FIG. 43A) of the external lead-out terminal 6a (see FIGS. 45A and 45B). And FIG. 45 (B)) are positioned on the upper surface side conductor pattern 2b2 (see FIG. 40 (A) and FIG. 45 (B)) of the insulating substrate 2 (see FIG. 45 (A) and FIG. 45 (B)), Lower end portion 6b4 (see FIG. 45 (A) and FIG. 45 (B)) of external lead-out terminal 6b 43 (A) and FIG. 45 (B)) is the upper surface side conductor pattern 2b1 of the insulating substrate 2 (see FIG. 45 (A) and FIG. 45 (B)) (see FIG. 40 (A) and FIG. 45 (B)). The lower end portion 6c4 (see FIGS. 43A and 45B) of the external lead-out terminal 6c (see FIGS. 45A and 45B) is the insulating substrate 2 (see FIG. 45A). And the upper side conductor pattern 2b3 (see FIGS. 40A and 45B) of FIG. 45B).

  In the power semiconductor module 100 of the fifth embodiment, the signal terminal 6j (see FIGS. 42A, 42C, 44A, 44C, and 47C) is provided. For example, on the upper surface side conductor pattern 2b4 (see FIGS. 40C and 45A) of the insulating substrate 2 (see FIGS. 40C and 45A) via solder (not shown) or the like. As a result, the signal terminal 6j (see FIGS. 42A, 42C, 44A, 44C, and 47C) and the power semiconductor chip (IGBT chip) 3a are connected. The gate electrode formed on the upper surface of (see FIGS. 40C and 47C) is electrically connected. Further, the signal terminal 6k (see FIGS. 42A, 42C, 44A, 44C, and 47C) is connected via, for example, solder (not shown) or the like. It is connected to the upper surface side conductor pattern 2b2 (see FIG. 40C) of the insulating substrate 2 (see FIGS. 40C and 45A), and as a result, the signal terminal 6k (see FIGS. 42A and 42). (C), FIG. 44 (A), FIG. 44 (C) and FIG. 47 (C)) and the power semiconductor chip (IGBT chip) 3a (see FIG. 40 (C) and FIG. 47 (C)) The upper surface electrode (emitter electrode) is electrically connected.

  Further, in the power semiconductor module 100 of the fifth embodiment, the signal terminal 6m (see FIGS. 42, 44, and 47C) is connected to the insulating substrate 2 (FIG. 40) via, for example, solder (not shown). (C) and FIG. 45 (A)) are connected to the upper surface side conductor pattern 2b5 (see FIG. 40 (C)), and as a result, the signal terminal 6m (see FIGS. 42, 44 and 47 (C)) and A gate electrode formed on the upper surface of the power semiconductor chip (IGBT chip) 3b (see FIGS. 40C and 47C) is electrically connected. Further, the signal terminal 6n (see FIG. 42A, FIG. 42C, FIG. 44A, FIG. 44C, and FIG. 47C) is connected via, for example, solder (not shown) or the like. It is connected to the upper surface side conductor pattern 2b1 (see FIG. 40C) of the insulating substrate 2 (see FIGS. 40C and 45A), and as a result, the signal terminal 6n (see FIGS. 42A and 42). (C), FIG. 44 (A), FIG. 44 (C) and FIG. 47 (C)) and the power semiconductor chip (IGBT chip) 3b (see FIG. 40 (C) and FIG. 47 (C)) The upper surface electrode (emitter electrode) is electrically connected.

  Further, in the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 46, the right side wall 6d (see FIG. 46), the left side wall 6e (see FIG. 46), the front side wall 6f (FIG. 46A) and FIG. 46 (C)) and a rear side wall 6g (see FIG. 46), and an enclosing case 6 (see FIG. 46) formed by molding an electrically insulating resin material is provided. Specifically, the outer casing 6 (see FIGS. 46, 47A, and 47B) is placed on the assembly shown in FIG.

  That is, the power of the first embodiment in which the external lead-out terminals 6a and 6b (see FIGS. 5 and 6A) are inserted and formed integrally with the outer case 6 (see FIGS. 5 and 6). Unlike the semiconductor module 100 (see FIG. 9), in the power semiconductor module 100 of the fifth embodiment, as shown in FIGS. 42, 43, and 46, external lead-out terminals 6a, 6b, 6c (FIG. 42 and FIG. 43) is not inserted into the outer case 6 (see FIG. 46), and is configured as a separate member from the outer case 6 (see FIG. 46).

  Furthermore, in the power semiconductor module 100 of the fifth embodiment, a gel-like resin (not shown) is filled inside the enclosing case 6 that covers the assembly shown in FIG. Specifically, gel resin (not shown) is filled up to the height HT shown by the broken line in FIG. That is, the insulating substrate 2 (see FIG. 47 (B)), the power semiconductor chips (IGBT chips) 3a and 3b (see FIG. 40 (C)), and the power semiconductor chip (diode) by gel-like resin (not shown). Chips) 3c, 3d (see FIG. 40C), bonding wires (see FIG. 40C), and external lead terminals 6a, 6b, 6c (FIGS. 42, 43, 47A and 47). (See FIG. 42B)) and lower ends 6a4, 6b4, 6c4 (see FIGS. 42B, 43A, 43B, and 47B) and the central portions 6a2, 6b2, 6c2 (see FIG. 42). (B), FIG. 43 (A) and FIG. 43 (B)) are covered. Also, an epoxy resin (not shown) is placed on the inner side of the surrounding case 6 covered on the assembly shown in FIG. 45 (A) and above the height HT shown by a broken line in FIG. 47 (B). Z). At the time of manufacturing the power semiconductor module 100 of the fifth embodiment, the concave portion 7f (FIG. 41A) on the upper surface of the lid body 7 (see FIGS. 41, 42, 47A and 47B), FIG. 42 (A) and FIG. 47 (A)), a nut (not shown) is inserted. Next, upper end portions 6a1, 6b1, 6c1 (FIGS. 42B and 47B) of external lead-out terminals 6a, 6b, and 6c (see FIGS. 42, 43, 47A, and 47B). The power semiconductor module 100 of the fifth embodiment is completed.

  That is, in the power semiconductor module 100 of the fifth embodiment, as shown in FIGS. 40C and 47C, the upper surface electrode (emitter electrode) through which a large current flows and the lower surface electrode (collector) through which a large current flows. Power semiconductor chips (IGBT chips) 3a and 3b having a large current, and a power semiconductor chip (diode chip) having a top electrode (anode electrode) through which a large current flows and a bottom electrode (cathode electrode) through which a large current flows. ) 3c and 3d are provided. Further, as shown in FIG. 40C, a power semiconductor chip (IGBT chip) 3a and a power semiconductor chip (diode chip) 3c are formed on the upper surface side conductor pattern 2b1 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Is installed. Furthermore, as shown in FIG. 40B, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrode (collector electrode) of the power semiconductor chip (IGBT chip) 3a are electrically connected. As shown in FIG. 40B, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3c are electrically connected. Further, as shown in FIG. 40C, a power semiconductor chip (IGBT chip) 3b and a power semiconductor chip (diode chip) 3d are formed on the upper surface side conductor pattern 2b3 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Is installed. As shown in FIG. 40B, the upper surface side conductor pattern 2b3 of the insulating substrate 2 and the lower surface electrode (collector electrode) of the power semiconductor chip (IGBT chip) 3b are electrically connected. As shown in FIG. 40B, the upper surface side conductor pattern 2b3 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3d are electrically connected.

  In the power semiconductor module 100 of the fifth embodiment, as shown in FIG. 40C, the upper surface electrode (emitter electrode) of the power semiconductor chip (IGBT chip) 3a and the insulating substrate 2 are connected via bonding wires. The upper surface side conductor pattern 2b2 is electrically connected. Furthermore, the upper surface electrode (emitter electrode) of the power semiconductor chip (IGBT chip) 3b and the upper surface side conductor pattern 2b1 of the insulating substrate 2 are electrically connected via a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c and the upper surface side conductor pattern 2b2 of the insulating substrate 2 are electrically connected via a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3d and the upper surface side conductor pattern 2b1 of the insulating substrate 2 are electrically connected via a bonding wire.

  Specifically, in the power semiconductor module 100 of the fifth embodiment, first, as shown in FIG. 40B, the power semiconductor chip (IGBT chip) 3a (FIGS. 40A and 40B). The solder 10b1 (see FIG. 40 (B)) between the lower surface electrode (collector electrode) of FIG. 40 and the upper surface side conductor pattern 2b1 (see FIG. 40 (A) and FIG. 40 (B)) of the insulating substrate 2 (see FIG. 40). (See FIG. 40), the lower surface electrode (collector electrode) of the power semiconductor chip (IGBT chip) 3b (see FIGS. 40A and 40B) and the upper surface side conductor pattern 2b3 (see FIG. 40). 40 (A) and FIG. 40 (B)) joining by solder 10b2 (see FIG. 40 (B)), power semiconductor chip (diode chip) 3c (FIG. 40 (A) and FIG. 40 (B)) three ) And the upper surface side conductor pattern 2b1 (see FIGS. 40A and 40B) of the insulating substrate 2 (see FIG. 40), solder 10b3 (see FIG. 40B). ), And the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3d (see FIGS. 40A and 40B) and the upper surface side conductor pattern 2b3 of the insulating substrate 2 (see FIG. 40). Joining with the solder 10b4 (see FIG. 40 (B)) is performed (see FIG. 40 (A) and FIG. 40 (B)). Next, wire bonding shown in FIG. 40C is performed. Next, as shown in FIG. 45 (B), the lower surface side conductor pattern 2c (FIG. 39 (B),) of the metal heat sink 1 (see FIGS. 38 and 45) and the insulating substrate 2 (see FIGS. 39 and 45), Joining by solder 10a (see FIG. 45 (B)) between FIG. 39 (C) and FIG. 45 (B)), upper surface side conductor pattern 2b1 (see FIG. 39) of insulating substrate 2 (see FIG. 39 and FIG. 45) (A), FIG. 39 (B) and FIG. 45 (B)) and the lower end portion 6b4 (see FIG. 45 (B)) of the external lead-out terminal 6b (see FIG. 45 (A) and FIG. 45 (B)). Bonding by solder 10f2 (see FIG. 45 (B)), upper surface side conductor pattern 2b2 (see FIGS. 39 (A) and 45 (B)) of the insulating substrate 2 (see FIGS. 39 and 45) and external lead-out terminals 6a (see FIG. 45 (A) and FIG. 45 (B)) at the lower end 6a4 ( 45 (see FIG. 45 (B)) and the upper surface side conductor pattern 2b3 (see FIGS. 39 (A) and 39) of the insulating substrate 2 (see FIGS. 39 and 45). (B) and FIG. 45 (B)) and the solder 10f3 (see FIG. 45) between the lower end portion 6c4 (see FIG. 45 (B)) of the external lead-out terminal 6c (see FIG. 45 (A) and FIG. 45 (B)). 45 (B)) is performed. Furthermore, when the solder bonding shown in FIG. 45 (B) is performed, a concave shape of a basing jig (not shown) is formed as in the power semiconductor module described in FIG. 3 of Patent Document 1 (Japanese Patent Laid-Open No. 2010-199251). The metal heat radiating plate 1 (see FIG. 45) is fixed to a basing jig (not shown) so that the lower surface of the metal heat radiating plate 1 (see FIG. 45) is deformed in a convex manner following the upper surface.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have made the lower side conductor pattern 2c (see FIG. 45) of the metal heat sink 1 (see FIG. 45) and the insulating substrate 2 (see FIG. 45). 45 (B)) was performed. Specifically, in the research by the present inventors, between the metal heat sink 1 (see FIG. 45) and the lower surface side conductor pattern 2c (see FIG. 45B) of the insulating substrate 2 (see FIG. 45). A temperature cycle test was performed using Pb (lead) -free solder having a low tensile strength and containing no Sb (antimony) for solder bonding. As a result, Pb not containing Sb between the metal heat sink 1 (see FIG. 45) and the lower conductor pattern 2c (see FIG. 45B) of the insulating substrate 2 (see FIG. 45) after the temperature cycle test. It was confirmed that the free solder was peeled off.

  The present inventors have insufficient solder tensile strength between the metal heat sink 1 (see FIG. 45) and the lower surface side conductor pattern 2c (see FIG. 45B) of the insulating substrate 2 (see FIG. 45). In the research conducted by the present inventors, between the metal heat sink 1 (see FIG. 45) and the lower surface side conductor pattern 2c (see FIG. 45B) of the insulating substrate 2 (see FIG. 45). A temperature cycle test was carried out using Pb-free solder (alloy composition such as Sn-3.9Ag-0.6Cu-3.0Sb) containing Sb and having high tensile strength for solder bonding. As a result, after the temperature cycle test, Pb containing Sb between the metal heat sink 1 (see FIG. 45) and the lower surface side conductor pattern 2c (see FIG. 45B) of the insulating substrate 2 (see FIG. 45). It was confirmed that the free solder did not peel off.

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b1 (FIG. 39A and FIG. 45) of the insulating substrate 2 (see FIG. 39 and FIG. 45). B)) and the soldering temperature cycle between the lower end portion 6b4 (see FIG. 45B) of the external lead-out terminal 6b (see FIGS. 42, 43, 45A and 45B). A test was conducted. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal 6b (see FIG. 39A). Pb-free containing Sb with high tensile strength for solder joint with the lower end 6b4 (see FIG. 45B) of FIGS. 42, 43, 45A and 45B) A temperature cycle test was performed using solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6b (see FIGS. 42 and 43). 45 (A) and FIG. 45 (B)), the Pb-free solder containing Sb between the lower end 6b4 (see FIG. 45 (B)) is not peeled off, but the insulating substrate 2 (FIG. 39 and FIG. 45), it was confirmed that the upper surface side conductor pattern 2b1 (see FIG. 39A and FIG. 45B) was damaged.

  The temperature of the external lead-out terminal 6b (see FIG. 47B) covered with the gel-like resin (not shown) in the outer case 6 (see FIGS. 46, 47A and 47B) Thermal expansion / contraction amount in the vertical direction during the cycle test (vertical direction in FIG. 47B) and vertical direction during the temperature cycle test for the gel-like resin (not shown) (in the vertical direction in FIG. 47B) Direction) thermal expansion amount and thermal contraction amount are different, so that the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal When a Pb-free solder containing Sb and having a high tensile strength is used for solder joint with the lower end 6b4 (see FIG. 45B) of 6b (see FIG. 45), an external lead terminal is used during a temperature cycle test. 6b (see FIG. 45B) up and down direction (up and down in FIG. 45B) ) And the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 45 (B)) of the gel resin (not shown), and the difference between Pb containing Sb As a result of the deformation of the free solder, it cannot be sufficiently absorbed, and as a result, the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) is applied. The present inventors considered that the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) was damaged by the thermal stress.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6b (see FIG. 45). Pb-free solder (with an alloy composition of Sn-0.3Ag-0.7Cu-0...) Having a low tensile strength and not containing Sb, for solder joint with the lower end 6b4 (see FIG. 45B) of 035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal 6b (see FIG. 45). The Pb-free solder containing no Sb between the lower end portion 6b4 (see FIG. 45B) does not peel off, and the upper surface side conductor pattern 2b1 (see FIG. 39A) of the insulating substrate 2 (see FIGS. 39 and 45). It was also confirmed that no damage occurred (see FIG. 45B).

  Further, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b2 (FIG. 39A and FIG. 45) of the insulating substrate 2 (see FIG. 39 and FIG. 45). B)) and the soldering temperature cycle between the lower end portion 6a4 (see FIG. 45 (B)) of the external lead-out terminal 6a (see FIGS. 42, 43, 45A and 45B). A test was conducted. Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6a (see FIG. Pb-free containing Sb with high tensile strength for solder joint with the lower end 6a4 (see FIG. 45B) of FIGS. 42, 43, 45A and 45B) A temperature cycle test was performed using solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6a (see FIGS. 42 and 43). 45 (A) and FIG. 45 (B)), the Pb-free solder containing Sb between the lower end 6a4 (see FIG. 45 (B)) is not peeled off, but the insulating substrate 2 (FIG. 39 and FIG. 45), it was confirmed that the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) was damaged.

  The temperature of the external lead-out terminal 6a (see FIG. 47B) covered with the gel-like resin (not shown) in the outer case 6 (see FIGS. 46, 47A and 47B) Thermal expansion / contraction amount in the vertical direction during the cycle test (vertical direction in FIG. 47B) and vertical direction during the temperature cycle test for the gel-like resin (not shown) (in the vertical direction in FIG. 47B) Direction) thermal expansion amount and thermal contraction amount are different, so that the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal When Pb-free solder containing Sb and having high tensile strength is used for solder joint with the lower end 6a4 (see FIG. 45B) of 6a (see FIG. 45), an external lead terminal is used during a temperature cycle test. 6a (see FIG. 45B) up and down direction (up and down in FIG. 45B) ) And the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 45 (B)) of the gel resin (not shown), and the difference between Pb containing Sb As a result, it cannot be sufficiently absorbed by the deformation of the free solder, and as a result, is applied to the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45). The present inventors considered that the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) was damaged by the thermal stress.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6a (see FIG. 45). Pb-free solder (with an alloy composition of Sn-0.3Ag-0.7Cu-0 .., for example) having a low tensile strength and containing no Sb for solder joint with the lower end 6a4 (see FIG. 45 (B)). 035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to conduct a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6a (see FIG. 45) The Pb-free solder containing no Sb between the lower end 6a4 (see FIG. 45B) does not peel off, and the upper surface side conductor pattern 2b2 (see FIG. 39A) of the insulating substrate 2 (see FIGS. 39 and 45). It was also confirmed that no damage occurred (see FIG. 45B).

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b3 (FIG. 39A and FIG. 45) of the insulating substrate 2 (see FIG. 39 and FIG. 45). B)) and the soldering temperature cycle between the lower end portion 6c4 (see FIG. 45B) of the external lead-out terminal 6c (see FIGS. 42, 43, 45A and 45B). A test was conducted. Specifically, in the study by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal 6c (see FIG. 39). 42, 43, 45 (A) and 45 (B)), the solder joint between the lower end portion 6c4 (see FIG. 45 (B)) is high in tensile strength and Pb-free containing Sb. A temperature cycle test was performed using solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6c (see FIGS. 42 and 43). 45 (A) and FIG. 45 (B)), the Pb-free solder containing Sb between the lower end 6c4 (see FIG. 45 (B)) is not peeled off, but the insulating substrate 2 (FIG. 39 and FIG. 45), it was confirmed that the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) was damaged.

  Temperature of external lead-out terminal 6c (see FIG. 47 (B)) covered with gel-like resin (not shown) in outer case 6 (see FIGS. 46, 47 (A) and 47 (B)) Thermal expansion / contraction amount in the vertical direction during the cycle test (vertical direction in FIG. 47B) and vertical direction during the temperature cycle test for the gel-like resin (not shown) Direction) thermal expansion amount and thermal contraction amount are different, so that the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal When Pb-free solder containing Sb and having high tensile strength is used for solder joint with the lower end portion 6c4 (see FIG. 45B) of 6c (see FIG. 45), an external lead terminal is used during a temperature cycle test. 6c (see FIG. 45B) up and down direction (up and down in FIG. 45B) ) And the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 45 (B)) of the gel resin (not shown), and the difference between Pb containing Sb It cannot be sufficiently absorbed by the deformation of the free solder, and as a result, is applied to the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45). The present inventors considered that the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) was damaged by the thermal stress.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead terminal 6c (see FIG. 45). Pb-free solder having a low tensile strength and containing no Sb (alloy composition is Sn-0.3Ag-0.7Cu-0.), For example, at a solder joint between the lower end 6c4 (see FIG. 45B). 035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal 6c (see FIG. 45). The Pb-free solder containing no Sb between the lower end portion 6c4 (see FIG. 45B) does not peel off, and the upper surface side conductor pattern 2b3 (see FIG. 39A) of the insulating substrate 2 (see FIGS. 39 and 45). It was also confirmed that no damage occurred (see FIG. 45B).

  In view of the research results of the present inventors, in the power semiconductor module 100 of the fifth embodiment, the lower surface side of the metal heat sink 1 (see FIGS. 38 and 45) and the insulating substrate 2 (see FIGS. 39 and 45). Pb-free solder 10a containing Sb (see FIG. 45 (B)) is used for solder joint with the conductor pattern 2c (see FIGS. 39 (B), 39 (C) and 45 (B)). ing.

  Therefore, according to the power semiconductor module 100 of the fifth embodiment, the lower surface side conductors of the metal heat sink 1 (see FIGS. 38 and 45) and the insulating substrate 2 (see FIGS. 39 and 45) after the temperature cycle test. Peeling of the solder 10a (see FIG. 45B) between the pattern 2c (see FIGS. 39B, 39C, and 45B) can be avoided, and the metal heat sink 1 (See FIGS. 38 and 45) and the lower surface side conductor pattern 2c (see FIGS. 39B, 39C, and 45B) of the insulating substrate 2 (see FIGS. 39 and 45). The reliability of solder joint can be improved.

  Furthermore, in the power semiconductor module 100 of the fifth embodiment, the upper surface side conductor pattern 2b1 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal 6b. Sb having a lower tensile strength than the Pb-free solder 10a containing Sb (see FIG. 45B) is used for solder joint with the lower end 6b4 (see FIG. 45B) of (see FIG. 45). Pb-free solder 10f2 (see FIG. 45B) that does not contain is used.

  Therefore, according to the power semiconductor module 100 of the fifth embodiment, the upper surface side conductor pattern 2b1 (FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) after the temperature cycle test. The solder 10f2 (see FIG. 45B) between the lower end 6b4 (see FIG. 45B) of the external lead-out terminal 6b (see FIG. 45) and the insulating substrate 2 (see FIGS. 39 and 45). The upper surface side conductor pattern 2b1 (see FIG. 39A and FIG. 45B) of the upper surface side conductor pattern 2b1 (see FIG. 39A and FIG. 45B) can be avoided at the same time. 39 (A) and 45 (B)) and the solder joint reliability between the lower end portion 6b4 (see FIG. 45 (B)) of the external lead-out terminal 6b (see FIG. 45) can be improved. .

  In the power semiconductor module 100 of the fifth embodiment, the upper surface side conductor pattern 2b2 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal 6a. Sb having a lower tensile strength than the Pb-free solder 10a containing Sb (see FIG. 45B) for solder joint with the lower end 6a4 (see FIG. 45B) of (see FIG. 45). Pb-free solder 10f1 (see FIG. 45B) that does not contain is used.

  Therefore, according to the power semiconductor module 100 of the fifth embodiment, the upper surface side conductor pattern 2b2 (FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) after the temperature cycle test. The solder 10f1 (see FIG. 45B) between the lower end 6a4 (see FIG. 45B) of the external lead-out terminal 6a (see FIG. 45) and the insulating substrate 2 (see FIGS. 39 and 45). Damage to the upper surface side conductor pattern 2b2 (see FIG. 39A and FIG. 45B) can be avoided at the same time, and the upper surface side conductor pattern 2b2 (see FIG. 39 and FIG. 45) of the insulating substrate 2 (see FIG. 39). The reliability of the solder joint between the lower end portion 6a4 (see FIG. 45B) of the external lead-out terminal 6a (see FIG. 45) can be improved. .

  Furthermore, in the power semiconductor module 100 of the fifth embodiment, the upper surface side conductor pattern 2b3 (see FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) and the external lead-out terminal 6c. Sb having a lower tensile strength than the Pb-free solder 10a containing Sb (see FIG. 45B) for solder joint with the lower end portion 6c4 (see FIG. 45B) of (see FIG. 45). Pb-free solder 10f3 (see FIG. 45B) that does not contain is used.

  Therefore, according to the power semiconductor module 100 of the fifth embodiment, the upper surface side conductor pattern 2b3 (FIGS. 39A and 45B) of the insulating substrate 2 (see FIGS. 39 and 45) after the temperature cycle test. The solder 10f3 (see FIG. 45B) between the lower end 6c4 (see FIG. 45B) of the external lead-out terminal 6c (see FIG. 45) and the insulating substrate 2 (see FIGS. 39 and 45). (See FIG. 39A and FIG. 45B) can be avoided at the same time, and the upper surface side conductor pattern 2b3 (see FIG. 39 and FIG. 45) of the insulating substrate 2 can be avoided. 39 (A) and 45 (B)) and the solder joint reliability between the lower end portion 6c4 (see FIG. 45 (B)) of the external lead-out terminal 6c (see FIG. 45) can be improved. .

  In the power semiconductor module 100 of the fifth embodiment, the tensile strength of the solder 10b1, 10b2, 10b3, 10b4 (see FIG. 40B) is higher than that of the Pb-free solder 10a containing Sb (see FIG. 45B). Pb-free solder that does not contain Sb is used, but in the modification of the power semiconductor module 100 of the fifth embodiment, instead of the solders 10b1, 10b2, 10b3, and 10b4 (see FIG. 40B) ), It is also possible to use a Pb-free solder containing Sb having a high tensile strength like the solder 10a (see FIG. 45B).

  Hereinafter, a sixth embodiment of the power semiconductor module of the present invention will be described. FIG. 48 is a view showing the metal heat sink 1 constituting a part of the power semiconductor module 100 of the sixth embodiment. Specifically, FIG. 48 (A) is a plan view of the metal heat sink 1 and FIG. 48 (B) is a vertical sectional view taken along line A5-A5 of FIG. 48 (A). FIG. 49 is a view showing the insulating substrate 2 constituting a part of the power semiconductor module 100 of the sixth embodiment. Specifically, FIG. 49A is a plan view of the insulating substrate 2, FIG. 49B is a vertical sectional view taken along line B5-B5 of FIG. 49A, and FIG. It is a bottom view. 50, power semiconductor chips 3a, 3a ′, 3b, 3b ′, 3c, 3c ′, 3d, 3d ′, 3e, 3f and gate resistor chips R1, R1 ′, R2, R2 ′ are mounted on an insulating substrate 2. FIG. More specifically, FIG. 50A shows power semiconductor chips (MOSFET chips) 3a, 3a ′, 3b, 3b ′ and power semiconductor chips (diode chips) 3c, 3c ′, 3d, 3d ′, 3e on the insulating substrate 2. , 3f and gate resistor chips R1, R1 ′, R2, R2 ′ are mounted in a plan view. FIG. 50B is an exploded assembly sectional view showing a state in which power semiconductor chips (MOSFET chips) 3a, 3a ′, 3b, 3b ′ and a power semiconductor chip (diode chip) 3f are mounted on the insulating substrate 2. . FIG. 50C is an exploded assembly sectional view showing a state in which power semiconductor chips (diode chips) 3 c, 3 c ′, 3 d, 3 d ′ are mounted on the insulating substrate 2. FIG. 50D is an exploded assembly sectional view showing a state in which the power semiconductor chip (diode chip) 3e and the gate resistor chips R1, R1 ', R2, and R2' are mounted on the insulating substrate 2. FIG. 51 is a plan view of an assembly obtained by performing wire bonding on the assembly shown in FIG.

  FIG. 52 is a component diagram of the lid 7 constituting a part of the power semiconductor module 100 of the sixth embodiment. Specifically, FIG. 52A is a plan view of the lid 7, FIG. 52B is a right side view of the lid 7, FIG. 52C is a front view of the lid 7, and FIG. FIG. 6 is a bottom view of the lid body 7. FIG. 53 is a view showing an assembly obtained by attaching external lead-out terminals 6a, 6b, 6c and signal terminals 6j, 6k, 6m, 6n to the lid 7. Specifically, FIG. 53A is a plan view of an assembly obtained by attaching the external lead-out terminals 6a, 6b, and 6c and the signal terminals 6j, 6k, 6m, and 6n to the lid body 7, and FIG. FIG. 53C is a front view of an assembly obtained by attaching the external lead terminals 6a, 6b, 6c and the signal terminals 6j, 6k, 6m, 6n to the lid body 7, and FIG. FIG. 5 is a right side view of an assembly obtained by attaching terminals 6j, 6k, 6m, and 6n to the lid body 7.

  54 is a view of the external lead-out terminals 6a, 6b, and 6c as seen through the lid body 7 in the assembly shown in FIG. Specifically, FIG. 54A is a plan view of the external lead-out terminals 6a, 6b, and 6c, FIG. 54B is a front view of the external lead-out terminals 6a, 6b, and 6c, and FIG. 54C is the external lead-out terminal 6c. It is a right view of (6a, 6b). FIG. 55 is a view of signal terminals 6j, 6k, 6m, and 6n as seen through the lid body 7 of the assembly shown in FIG. Specifically, FIG. 55A is a plan view of the signal terminals 6j, 6k, 6m, and 6n, FIG. 55B is a front view of the signal terminals 6m (6j, 6k, and 6n), and FIG. It is a right view of terminal 6j, 6k, 6m, 6n. FIG. 56 is a diagram showing a state where the assembly shown in FIG. 51 is mounted on the metal heat sink 1 shown in FIG. 48 and the assembly shown in FIG. 53 is mounted thereon. Specifically, FIG. 56 (A) shows a state in which the assembly shown in FIG. 51 is mounted on the metal heat sink 1 shown in FIG. 48 and the assembly shown in FIG. 53 is mounted thereon. It is the shown top view. FIG. 56B shows the state in which the assembly shown in FIG. 51 is mounted on the metal heat sink 1 shown in FIG. 48 and the assembly shown in FIG. FIG.

  FIG. 57 is a component diagram of the enclosing case 6 that covers the assembly shown in FIG. 56 (A). Specifically, FIG. 57 (A) is a plan view of the enclosing case 6, FIG. 57 (B) is a vertical sectional view taken along line K5-K5 in FIG. 57 (A), and FIG. 57 (C) is the enclosing case. 6 is a bottom view of FIG. FIG. 58 is a diagram showing a power semiconductor module 100 according to the sixth embodiment. Specifically, FIG. 58A shows a power semiconductor module 100 of the sixth embodiment obtained by covering the assembly shown in FIG. 56A with the enclosing case 6 shown in FIG. It is a top view. FIG. 58B is a schematic vertical sectional view of the power semiconductor module 100 of the sixth embodiment. FIG. 58C is an equivalent circuit diagram of the power semiconductor module 100 of the sixth embodiment.

  In the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 56B, power semiconductor chips (MOSFET chips) 3a, 3a ′, 3b, 3b ′ (see FIG. 50), power semiconductor chips (diode chips). 3c, 3c ′, 3d, 3d ′, 3e, 3f (see FIG. 50) and the metal heat sink for radiating the heat generated by the gate resistor chips R1, R1 ′, R2, R2 ′ (see FIG. 50) 1 (see FIG. 48 and FIG. 56) and the lower surface side conductor pattern formed on the lower surface side of the insulating layer 2a (see FIG. 49 and FIG. 56B) of the insulating substrate 2 (see FIG. 49 and FIG. 56). Solder 10a (see FIG. 56 (B)) is disposed between 2c (see FIG. 49 (B), FIG. 49 (C) and FIG. 56 (B)). Further, as shown in FIG. 50B, the upper surface side conductor pattern 2b1 (FIGS. 49A, 49B, 50A and 50) of the insulating substrate 2 (see FIGS. 49 and 50). Solder 10b1 (see FIG. 50 (B)) is provided between the lower electrode (drain electrode) of the power semiconductor chip (MOSFET chip) 3a (see FIGS. 50 (A) and 50 (B)) and the power semiconductor chip (MOSFET chip) 3a. Has been placed. Furthermore, as shown in FIG. 50B, the upper surface side conductor pattern 2b1 (FIGS. 49A, 49B, 50A, and 50) of the insulating substrate 2 (see FIGS. 49 and 50). Solder 10b1 ′ (see FIG. 50B) between the lower electrode (drain electrode) of the power semiconductor chip (MOSFET chip) 3a ′ (see FIGS. 50A and 50B) and the power semiconductor chip (MOSFET chip) 3a ′. ) Is arranged. Further, as shown in FIG. 50B, the upper surface side conductor pattern 2b3 (FIGS. 49A, 49B, 50A, and 50) of the insulating substrate 2 (see FIGS. 49 and 50). Solder 10b2 (see FIG. 50B) is placed between the lower electrode (drain electrode) of the power semiconductor chip (MOSFET chip) 3b (see FIGS. 50A and 50B) and the power semiconductor chip (MOSFET chip) 3b. Has been placed. Further, as shown in FIG. 50B, the upper surface side conductor pattern 2b3 (FIGS. 49A, 49B, 50A, and 50) of the insulating substrate 2 (see FIGS. 49 and 50). (See (B)) and the lower surface electrode (drain electrode) of the power semiconductor chip (MOSFET chip) 3b ′ (see FIGS. 50A and 50B), solder 10b2 ′ (see FIG. 50B) ) Is arranged. Further, as shown in FIG. 50B, the upper surface side conductor pattern 2b7 (FIGS. 49A, 49B, 50A, and 50) of the insulating substrate 2 (see FIGS. 49 and 50). Solder 10b6 (see FIG. 50B) is placed between the lower electrode (cathode electrode) of the power semiconductor chip (diode chip) 3f (see FIGS. 50A and 50B) and the power semiconductor chip (diode chip) 3f. Has been placed.

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 50C, the upper surface side conductor pattern 2b1 (FIGS. 49A and 49) of the insulating substrate 2 (see FIGS. 49 and 50). (B), between FIG. 50 (A) and FIG. 50 (C)) and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3c (see FIG. 50 (A) and FIG. 50 (C)). Solder 10b3 (see FIG. 50C) is disposed on the surface. As shown in FIG. 50C, the upper surface side conductor pattern 2b1 (FIGS. 49A, 49B, 50A and 50) of the insulating substrate 2 (see FIGS. 49 and 50). (See (C)) and the solder 10b3 ′ (see FIG. 50C) between the power semiconductor chip (diode chip) 3c ′ (see FIG. 50A and FIG. 50C) and the lower electrode (cathode electrode). ) Is arranged. Further, as shown in FIG. 50C, the upper surface side conductor pattern 2b3 (FIGS. 49A, 49B, 50A and 50) of the insulating substrate 2 (see FIGS. 49 and 50). (See (C)) and a solder 10b4 (see FIG. 50C) between the power semiconductor chip (diode chip) 3d (see FIG. 50A and FIG. 50C) and the lower electrode (cathode electrode). Has been placed. Further, as shown in FIG. 50C, the upper surface side conductor pattern 2b3 (FIGS. 49A, 49B, 50A, and 50) of the insulating substrate 2 (see FIGS. 49 and 50). (See (C)) and the solder 10b4 ′ (see FIG. 50C) between the power semiconductor chip (diode chip) 3d ′ (see FIG. 50A and FIG. 50C) and the lower electrode (cathode electrode). ) Is arranged.

  In the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 50D, the upper surface side conductor pattern 2b6 (see FIGS. 49A and 49) of the insulating substrate 2 (see FIGS. 49 and 50). (B), between FIG. 50 (A) and FIG. 50 (D)) and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3e (see FIG. 50 (A) and FIG. 50 (D)). Solder 10b5 (see FIG. 50D) is disposed on the surface. Further, as shown in FIG. 50D, the upper surface side conductor pattern 2b4 (see FIGS. 49A, 50A, and 50D) of the insulating substrate 2 (see FIGS. 49 and 50) and Solder 10b7 (see FIG. 50D) is arranged between the lower electrode of the gate resistor chip R1 (see FIGS. 50A and 50D). Further, as shown in FIG. 50D, the upper surface side conductor pattern 2b4 (see FIGS. 49A, 50A, and 50D) of the insulating substrate 2 (see FIGS. 49 and 50) and Solder 10b7 ′ (see FIG. 50D) is arranged between the lower electrode of the gate resistor chip R1 ′ (see FIGS. 50A and 50D). Furthermore, as shown in FIG. 50D, the upper surface side conductor pattern 2b5 (see FIGS. 49A, 50A, and 50D) of the insulating substrate 2 (see FIGS. 49 and 50) and Solder 10b8 (see FIG. 50 (D)) is disposed between the lower electrode of the gate resistor chip R2 (see FIGS. 50 (A) and 50 (D)). Further, as shown in FIG. 50D, the upper surface side conductor pattern 2b5 (see FIGS. 49A, 50A, and 50D) of the insulating substrate 2 (see FIGS. 49 and 50) and Solder 10b8 ′ (see FIG. 50D) is disposed between the lower electrode of the gate resistor chip R2 ′ (see FIGS. 50A and 50D).

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 51, the upper surface electrode (source electrode) for large current of the power semiconductor chip (MOSFET chip) 3a and the insulating substrate 2 (see FIGS. 49 and 51). ) Of the upper surface side conductor pattern 2b2 (see FIG. 49A and FIG. 51) is connected by a bonding wire. As shown in FIG. 51, the gate electrode formed on the upper surface of the power semiconductor chip (MOSFET chip) 3a and the upper electrode of the gate resistor chip R1 are connected by a bonding wire. Further, as shown in FIG. 51, the upper surface electrode (source electrode) for large current of the power semiconductor chip (MOSFET chip) 3a ′ and the upper surface side conductor pattern 2b2 (see FIG. 49 (FIG. 49)) of the insulating substrate 2 (see FIGS. 49 and 51). A) and FIG. 51) are connected by a bonding wire. As shown in FIG. 51, the gate electrode formed on the upper surface of the power semiconductor chip (MOSFET chip) 3a 'and the upper electrode of the gate resistor chip R1' are connected by a bonding wire.

  Further, in the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 51, the upper surface electrode (source electrode) for large current of the power semiconductor chip (MOSFET chip) 3b and the insulating substrate 2 (see FIGS. 49 and 51). ) Of the upper surface side conductor pattern 2b6 (see FIG. 49A and FIG. 51) is connected by a bonding wire. Further, as shown in FIG. 51, the gate electrode formed on the upper surface of the power semiconductor chip (MOSFET chip) 3b and the upper electrode of the gate resistor chip R2 are connected by a bonding wire. Further, as shown in FIG. 51, the upper surface electrode (source electrode) for large current of the power semiconductor chip (MOSFET chip) 3b ′ and the upper surface side conductor pattern 2b6 (see FIG. 49 (FIG. 49)) of the insulating substrate 2 (see FIGS. 49 and 51). A) and FIG. 51) are connected by a bonding wire. Further, as shown in FIG. 51, the gate electrode formed on the upper surface of the power semiconductor chip (MOSFET chip) 3b 'and the upper electrode of the gate resistor chip R2' are connected by a bonding wire.

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 51, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c and the upper surface of the insulating substrate 2 (see FIGS. 49 and 51). Side conductor pattern 2b6 (see FIGS. 49A and 51) is connected by a bonding wire. Further, as shown in FIG. 51, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c ′ and the upper surface side conductor pattern 2b6 (see FIG. 49A) of the insulating substrate 2 (see FIG. 49 and FIG. 51). Are connected by a bonding wire. Further, as shown in FIG. 51, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3d and the upper surface side conductor pattern 2b7 (see FIG. 49A) and FIG. 51) is connected by a bonding wire. Further, as shown in FIG. 51, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3d ′ and the upper surface side conductor pattern 2b7 (see FIG. 49A) of the insulating substrate 2 (see FIGS. 49 and 51) Are connected by a bonding wire. Further, as shown in FIG. 51, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3e and the upper surface side conductor pattern 2b2 of the insulating substrate 2 (see FIGS. 49 and 51) (FIG. 49A) and FIG. 51) is connected by a bonding wire. Also, as shown in FIG. 51, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3f and the upper surface side conductor pattern 2b6 (see FIG. 49A) and FIG. 51) is connected by a bonding wire.

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 52, an electrically insulating lid 7 formed by molding a resin material, for example, is provided. Specifically, in the power semiconductor module 100 of the sixth embodiment, the positioning hole 2h (see FIGS. 49A and 49C) of the insulating substrate 2 (see FIG. 49) and the metal heat sink 1 (see FIG. 49). 48), the leg portion 7g (see FIGS. 52 (B), 52 (C) and 52 (D)) having a tip portion inserted into the positioning hole 1h (see FIG. 48 (A)) is a lid. 7 (see FIG. 52).

  Further, in the power semiconductor module 100 of the sixth embodiment, as shown in FIGS. 54 (A) and 54 (B), an upper end 6a1 extending in the vertical direction (the vertical direction in FIG. 54 (B)) and The external lead-out terminal 6a having the bent central portion 6a2 and the lower end portion 6a4 extending in the horizontal direction is formed by, for example, pressing a metal material. Further, in the power semiconductor module 100 of the sixth embodiment, as shown in FIGS. 54 (A) and 54 (B), an upper end 6b1 extending in the vertical direction (vertical direction in FIG. 54 (B)) and The external lead-out terminal 6b having the bent center part 6b2 and the lower end part 6b4 extending in the horizontal direction is formed into the external lead-out terminal 6a (FIG. 54 (A) and FIG. It is formed in the same shape as B). Furthermore, in the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 54, the upper end portion 6c1 extending in the vertical direction (the vertical direction in FIG. 54B and FIG. 54C) and the bent portion are bent. The external lead-out terminal 6c having the central part 6c2 and the lower end part 6c4 extending in the horizontal direction (left-right direction in FIG. 54C) is, for example, formed by pressing a metal material. (See (A) and FIG. 54 (B)).

  At the time of manufacturing the power semiconductor module 100 of the sixth embodiment, the upper end portion 6a1 (see FIG. 53) of the external lead-out terminal 6a (see FIGS. 53A, 53B, 54A, and 54B). 53 (B), FIG. 54 (A) and FIG. 54 (B)) is the lead-out hole 7a (FIG. 52 (A), FIG. 52 (C) and FIG. A)) and the external lead-out terminal 6a is attached to the lid body 7 as shown in FIG. Further, the upper end portion 6b1 (FIGS. 53B, 54A and 54A) of the external lead-out terminal 6b (see FIGS. 53A, 53B, 54A and 54B) and FIG. 54 (B)) is passed through the lead-out hole 7b (see FIG. 52 (A), FIG. 52 (C) and FIG. 53 (A)) of the lid 7 (see FIG. 52 and FIG. 53) and shown in FIG. As described above, the external lead-out terminal 6 b is attached to the lid body 7. Further, the upper end portion 6c1 (see FIGS. 53B, 53C, and 54) of the external lead-out terminal 6c (see FIGS. 53 and 54) is a lead-out hole of the lid body 7 (see FIGS. 52 and 53). 7c (see FIGS. 52 (A), 52 (C) and 53 (A)), and the external lead-out terminal 6c is attached to the lid 7 as shown in FIG.

  Further, when the power semiconductor module 100 of the sixth embodiment is manufactured, as shown in FIG. 53, the signal terminal 6j (FIGS. 53A, 53C, 55A and 55C). Is attached to the lid 7. Further, the signal terminal 6k (see FIGS. 53A and 53) formed in the same shape as the signal terminal 6j (see FIGS. 53A, 53C, 55A, and 55C). (C), FIG. 55 (A) and FIG. 55 (C)) are attached to the lid body 7. Further, a signal terminal 6m (see FIGS. 53 and 55) formed in the same shape as the signal terminal 6j (see FIGS. 53A, 53C, 55A and 55C) is provided. Attached to the lid 7. Further, the signal terminal 6n (see FIGS. 53A and 53) formed in the same shape as the signal terminal 6j (see FIGS. 53A, 53C, 55A, and 55C). (C), FIG. 55 (A) and FIG. 55 (C)) are attached to the lid body 7.

  In the power semiconductor module 100 of the sixth embodiment, external lead-out terminals 6a, 6b, 6c (see FIG. 54) and signal terminals 6j, 6k, 6m, 6n formed separately from the lid 7 (see FIG. 52). (See FIG. 55) is attached to the lid body 7 (see FIG. 52), and the assembly shown in FIG. 53 is formed. In the modification of the power semiconductor module 100 of the sixth embodiment, The external lead-out terminals 6a, 6b, 6c and the signal terminals 6j, 6k, 6m, 6n are inserted into the lid body 7 formed by molding the resin material and are integrally molded, so that the same assembly as shown in FIG. It is also possible to form an assembly.

  In the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 56 (B), the upper surface side conductor pattern 2b2 (FIG. 50) of the insulating substrate 2 (see FIGS. 56 (A) and 56 (B)). (See (A) and FIG. 56 (B)) and the lower end portion 6a4 (see FIG. 54 (A) and FIG. 56 (B)) of the external lead-out terminal 6a (see FIG. 56 (A) and FIG. 56 (B)). Solder 10f1 (see FIG. 56 (B)) is arranged between the lower surface, upper surface side conductor pattern 2b2 (see FIGS. 50 (A) and 56 (B)) and external lead-out terminal 6a (FIG. 56 (A) and 56B) is electrically connected. Furthermore, as shown in FIG. 56 (B), the upper surface side conductor pattern 2b6 (see FIGS. 50 (A) and 56 (B)) of the insulating substrate 2 (see FIGS. 56 (A) and 56 (B)) and The solder 10f2 (see FIG. 56 (B) between the lower surface of the lower end portion 6b4 (see FIGS. 54 (A) and 56 (B)) of the external lead-out terminal 6b (see FIGS. 56 (A) and 56 (B)). )) Is arranged, and the upper surface side conductor pattern 2b6 (see FIGS. 50A and 56B) and the external lead-out terminal 6b (see FIGS. 56A and 56B) are electrically connected to each other. It is connected. Further, as shown in FIG. 56 (B), the upper surface side conductor pattern 2b7 (see FIGS. 50 (A) and 56 (B)) of the insulating substrate 2 (see FIGS. 56 (A) and 56 (B)) and The solder 10f3 (see FIG. 56 (B) between the lower surface of the lower end portion 6c4 (see FIGS. 54 (A) and 56 (B)) of the external lead-out terminal 6c (see FIGS. 56 (A) and 56 (B)). )) Is arranged, and the upper surface side conductor pattern 2b7 (see FIGS. 50A and 56B) and the external lead-out terminal 6c (see FIGS. 56A and 56B) are electrically connected to each other. It is connected.

  Specifically, in the power semiconductor module 100 of the sixth embodiment, the leg portion 7g (FIGS. 52B and 52) of the lid body 7 (see FIG. 52) during the manufacturing process shown in FIG. The tip of (C) and FIG. 52 (D)) is positioned at the positioning hole 2h (see FIG. 49 (A) and FIG. 49 (C)) of the insulating substrate 2 (see FIG. 49) and the metal heat sink 1 (see FIG. 48) is inserted into the positioning hole 1h (see FIG. 48A), and as a result, the lower end 6a4 (see FIG. 54A) of the external lead-out terminal 6a (see FIGS. 56A and 56B). And FIG. 56 (B)) are positioned on the upper surface side conductor pattern 2b2 (see FIG. 50 (A) and FIG. 56 (B)) of the insulating substrate 2 (see FIG. 56 (A) and FIG. 56 (B)), Lower end 6b4 (see FIG. 56 (A) and FIG. 56 (B)) of the external lead-out terminal 6b 54 (A) and FIG. 56 (B)) is the upper surface side conductor pattern 2b6 of the insulating substrate 2 (see FIG. 56 (A) and FIG. 56 (B)) (see FIG. 50 (A) and FIG. 56 (B)). The lower end portion 6c4 (see FIGS. 54A and 56B) of the external lead-out terminal 6c (see FIGS. 56A and 56B) is the insulating substrate 2 (see FIG. 56A). And the upper surface side conductor pattern 2b7 (see FIGS. 50A and 56B) of FIG. 56B).

  In the power semiconductor module 100 of the sixth embodiment, the signal terminal 6j (see FIGS. 53A, 53C, 55A, 55C, and 58C) is provided. For example, it is connected to the upper surface side conductor pattern 2b4 (see FIG. 51) of the insulating substrate 2 (see FIG. 51) via solder (not shown) or the like. As a result, the signal terminal 6j (FIG. 53A, FIG. 53) is connected. (C), FIG. 55 (A), FIG. 55 (C) and FIG. 58 (C)) and the gate formed on the upper surface of the power semiconductor chip (MOSFET chip) 3a (see FIG. 51 and FIG. 58 (C)). The electrodes are electrically connected to each other through the gate resistor chip R1 (see FIGS. 51 and 58C) and the signal terminals 6j (FIGS. 53A, 53C, and 55A). ), FIG. 55 (C) and FIG. 58 (C)) and a power semiconductor The gate electrode formed on the upper surface of the chip (MOSFET chip) 3a ′ (see FIGS. 51 and 58C) is electrically connected via the gate resistor chip R1 ′ (see FIGS. 51 and 58C). Connected. Further, the signal terminal 6k (see FIGS. 53 (A), 53 (C), 55 (A), 55 (C), and 58 (C)) is connected via, for example, solder (not shown) or the like. It is connected to the upper surface side conductor pattern 2b2 (see FIG. 51) of the insulating substrate 2 (see FIG. 51), and as a result, the signal terminal 6k (FIGS. 53A, 53C, 55A and 55). (C) and FIG. 58 (C)) and the upper electrode (source electrode) for large current of the power semiconductor chip (MOSFET chip) 3a (see FIG. 51 and FIG. 58 (C)) are electrically connected. , The signal terminal 6k (see FIGS. 53A, 53C, 55A, 55C, and 58C) and the power semiconductor chip (MOSFET chip) 3a ′ (see FIGS. The upper electrode (source electrode) for large current shown in FIG. It is connected.

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, the signal terminal 6m (see FIGS. 53, 55 and 58C) is connected to the insulating substrate 2 (FIG. 51) via, for example, solder (not shown). As a result, the signal terminal 6m (see FIGS. 53, 55 and 58C) and the power semiconductor chip (MOSFET chip) 3b (see FIG. 51 and FIG. 51) are connected to the upper surface side conductor pattern 2b5 (see FIG. 51). The gate electrode formed on the upper surface of FIG. 58 (C) is electrically connected via the gate resistor chip R2 (see FIG. 51 and FIG. 58 (C)) and the signal terminal 6m (FIG. 53). 55 and FIG. 58 (C)) and the gate electrode formed on the upper surface of the power semiconductor chip (MOSFET chip) 3b ′ (see FIG. 51 and FIG. 58 (C)) are the gate resistance chip R2. It is electrically connected via a (FIGS. 51 and 58 (C) see). Further, the signal terminal 6n (see FIGS. 53 (A), 53 (C), 55 (A), 55 (C) and 58 (C)) is connected via, for example, solder (not shown) or the like. It is connected to the upper surface side conductor pattern 2b6 (see FIG. 51) of the insulating substrate 2 (see FIG. 51), and as a result, the signal terminal 6n (FIGS. 53A, 53C, 55A and 55). (C) and FIG. 58 (C)) and the upper electrode (source electrode) for large current of the power semiconductor chip (MOSFET chip) 3b (see FIG. 51 and FIG. 58 (C)) are electrically connected. , The signal terminal 6n (see FIGS. 53A, 53C, 55A, 55C, and 58C) and the power semiconductor chip (MOSFET chip) 3b ′ (see FIGS. The upper electrode (source electrode) for large current shown in FIG. It is connected.

  In the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 57, the right side wall 6d (see FIG. 57), the left side wall 6e (see FIG. 57), the front side wall 6f (FIG. 57 (A) and FIG. 57 (see FIG. 57) and a rear side wall 6g (see FIG. 57), and an enclosing case 6 (see FIG. 57) formed by molding an electrically insulating resin material is provided. Specifically, the outer case 6 (see FIGS. 57, 58A, and 58B) is put on the assembly shown in FIG. 56A.

  That is, the power of the first embodiment in which the external lead-out terminals 6a and 6b (see FIGS. 5 and 6A) are inserted and formed integrally with the outer case 6 (see FIGS. 5 and 6). Unlike the semiconductor module 100 (see FIG. 9), in the power semiconductor module 100 of the sixth embodiment, as shown in FIGS. 53, 54, and 57, external lead-out terminals 6a, 6b, 6c (FIG. 53 and FIG. 54) is not inserted into the outer case 6 (see FIG. 57), and is configured as a separate member from the outer case 6 (see FIG. 57).

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, a gel-like resin (not shown) is filled inside the enclosing case 6 that covers the assembly shown in FIG. 56 (A). Specifically, gel resin (not shown) is filled up to the height HT indicated by the broken line in FIG. That is, the insulating substrate 2 (see FIG. 58B), the power semiconductor chips (MOSFET chips) 3a, 3a ′, 3b, 3b ′ (see FIG. 51), and the power semiconductor are made of gel resin (not shown). Chips (diode chips) 3c, 3c ′, 3d, 3d ′, 3e, 3f (see FIG. 51), gate resistor chips R1, R1 ′, R2, R2 ′ (see FIG. 51), and bonding wires (see FIG. 51) ) And the lower end portions 6a4, 6b4, 6c4 (FIGS. 53B, 54A) of the external lead-out terminals 6a, 6b, 6c (see FIGS. 53, 54, 58A and 58B). ), FIG. 54 (B) and FIG. 58 (B)) and the central portions 6a2, 6b2, 6c2 (see FIG. 53 (B), FIG. 54 (A) and FIG. 54 (B)). In addition, an epoxy resin (not shown) is placed on the inner side of the surrounding case 6 covered on the assembly shown in FIG. 56 (A) and above the height HT shown by a broken line in FIG. 58 (B). Z). At the time of manufacturing the power semiconductor module 100 of the sixth embodiment, the concave portion 7f (FIG. 52 (A), FIG. 52) on the upper surface of the lid body 7 (see FIGS. 52, 53, 58 (A) and 58 (B)). 53 (A) and FIG. 58 (A)), a nut (not shown) is inserted. Next, upper end portions 6a1, 6b1, 6c1 (FIGS. 53B and 58B) of external lead-out terminals 6a, 6b, and 6c (see FIGS. 53, 54, 58A, and 58B). The power semiconductor module 100 of the sixth embodiment is completed.

  That is, in the power semiconductor module 100 of the sixth embodiment, as shown in FIGS. 51 and 58C, the upper surface electrode (source electrode) through which a large current flows, and the lower surface electrode (drain electrode) through which a large current flows. Power semiconductor chip (MOSFET chip) 3a, 3a ', 3b, 3b' having a top surface electrode (anode electrode) through which a large current flows and a bottom surface electrode (cathode electrode) through which a large current flows (Diode chips) 3c, 3c ′, 3d, 3d ′, 3e, 3f are provided. Further, as shown in FIG. 50A, power semiconductor chips (MOSFET chips) 3a and 3a ′ and power semiconductor chips (diodes) are formed on the upper surface side conductor pattern 2b1 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Chips) 3c and 3c ′ are mounted. Further, as shown in FIG. 50B, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrodes (drain electrodes) of the power semiconductor chips (MOSFET chips) 3a and 3a ′ are electrically connected. Yes. Further, as shown in FIG. 50C, the upper surface side conductor pattern 2b1 of the insulating substrate 2 and the lower surface electrodes (cathode electrodes) of the power semiconductor chips (diode chips) 3c, 3c ′ are electrically connected. Yes. Further, as shown in FIG. 50A, power semiconductor chips (MOSFET chips) 3b and 3b ′ and power semiconductor chips (diodes) are formed on the upper surface side conductor pattern 2b3 formed on the upper surface side of the insulating layer 2a of the insulating substrate 2. Chips) 3d and 3d ′ are mounted. Further, as shown in FIG. 50B, the upper surface side conductor pattern 2b3 of the insulating substrate 2 and the lower surface electrodes (drain electrodes) of the power semiconductor chips (MOSFET chips) 3b and 3b ′ are electrically connected. Yes. Further, as shown in FIG. 50C, the upper surface side conductor pattern 2b3 of the insulating substrate 2 and the lower surface electrodes (cathode electrodes) of the power semiconductor chips (diode chips) 3d and 3d ′ are electrically connected. Yes. Further, as shown in FIG. 50D, the upper surface side conductor pattern 2b6 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3e are electrically connected. As shown in FIG. 50B, the upper surface side conductor pattern 2b7 of the insulating substrate 2 and the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3f are electrically connected.

  Further, in the power semiconductor module 100 of the sixth embodiment, as shown in FIG. 51, the upper surface electrode (source electrode) of the power semiconductor chip (MOSFET chip) 3a and the upper surface side conductor of the insulating substrate 2 through bonding wires. The pattern 2b2 is electrically connected. Furthermore, the upper surface electrode (source electrode) of the power semiconductor chip (MOSFET chip) 3a 'and the upper surface side conductor pattern 2b2 of the insulating substrate 2 are electrically connected via a bonding wire. Further, the upper surface electrode (source electrode) of the power semiconductor chip (MOSFET chip) 3b and the upper surface side conductor pattern 2b6 of the insulating substrate 2 are electrically connected via a bonding wire. Furthermore, the upper surface electrode (source electrode) of the power semiconductor chip (MOSFET chip) 3b 'and the upper surface side conductor pattern 2b6 of the insulating substrate 2 are electrically connected via a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c and the upper surface side conductor pattern 2b6 of the insulating substrate 2 are electrically connected via a bonding wire. Furthermore, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3c 'and the upper surface side conductor pattern 2b6 of the insulating substrate 2 are electrically connected via a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3d and the upper surface side conductor pattern 2b7 of the insulating substrate 2 are electrically connected via a bonding wire. Furthermore, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3d 'and the upper surface side conductor pattern 2b7 of the insulating substrate 2 are electrically connected via a bonding wire. Further, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3e and the upper surface side conductor pattern 2b2 of the insulating substrate 2 are electrically connected via the bonding wires. Furthermore, the upper surface electrode (anode electrode) of the power semiconductor chip (diode chip) 3f and the upper surface side conductor pattern 2b6 of the insulating substrate 2 are electrically connected via a bonding wire.

  Specifically, in the power semiconductor module 100 of the sixth embodiment, first, as shown in FIGS. 50B, 50C, and 50D, the power semiconductor chip (MOSFET chip) 3a is used. (Refer to FIG. 50 (A) and FIG. 50 (B)) The lower surface electrode (drain electrode) and the upper surface side conductor pattern 2b1 of the insulating substrate 2 (refer to FIG. 50) (refer to FIG. 50 (A) and FIG. 50 (B)) And a bottom electrode (drain electrode) of the power semiconductor chip (MOSFET chip) 3a ′ (see FIGS. 50A and 50B) and an insulating substrate 2 (see FIG. 50) between the upper surface side conductor pattern 2b1 (see FIG. 50 (A) and FIG. 50 (B)) by solder 10b1 ′ (see FIG. 50 (B)), a power semiconductor chip (MOSFET ) 3b (see FIG. 50A and FIG. 50B) the lower electrode (drain electrode) and the upper surface side conductor pattern 2b3 of the insulating substrate 2 (see FIG. 50) (FIG. 50A and FIG. 50). B)) and a lower surface electrode (drain electrode) of the power semiconductor chip (MOSFET chip) 3b ′ (see FIG. 50A and FIG. 50B) with the solder 10b2 (see FIG. 50B) ) And the upper surface side conductor pattern 2b3 (see FIGS. 50A and 50B) of the insulating substrate 2 (see FIG. 50) by solder 10b2 ′ (see FIG. 50B), a power semiconductor The lower surface electrode (cathode electrode) of the chip (diode chip) 3c (see FIGS. 50A and 50C) and the upper surface side conductor pattern 2b1 of the insulating substrate 2 (see FIG. 50) (FIG. 50A and FIG. See 50 (C) And a bottom electrode (cathode electrode) of the power semiconductor chip (diode chip) 3c ′ (see FIGS. 50A and 50C) and an insulating substrate 2 (refer to FIG. 50), bonding with the upper surface side conductor pattern 2b1 (refer to FIG. 50 (A) and FIG. 50 (C)) by solder 10b3 ′ (refer to FIG. 50 (C)), power semiconductor chip (diode chip) ) 3d (refer to FIG. 50A and FIG. 50C) the lower surface electrode (cathode electrode) and the upper surface side conductor pattern 2b3 of the insulating substrate 2 (refer to FIG. 50) (FIG. 50A and FIG. 50C) And a lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3d ′ (see FIGS. 50A and 50C) and the solder 10b4 (see FIG. 50C) Insulation Bonding by solder 10b4 ′ (see FIG. 50C) between the upper surface side conductor pattern 2b3 (see FIGS. 50A and 50C) of the substrate 2 (see FIG. 50), a power semiconductor chip (diode) Chip) 3e (see FIG. 50A and FIG. 50D) lower surface electrode (cathode electrode) and upper surface side conductor pattern 2b6 of insulating substrate 2 (see FIG. 50) (FIG. 50A and FIG. 50D) )) And the lower surface electrode (cathode electrode) of the power semiconductor chip (diode chip) 3f (see FIGS. 50A and 50B) and the solder 10b5 (see FIG. 50D) Bonding with the upper surface side conductor pattern 2b7 (see FIGS. 50A and 50B) of the insulating substrate 2 (see FIG. 50) by solder 10b6 (see FIG. 50B), the gate resistance chip R1 (see FIG. 50B) FIG. And the solder 10b7 (see FIG. 50 (D)) between the lower electrode of FIG. 50 (D) and the upper surface side conductor pattern 2b4 (see FIG. 50 (A) and FIG. 50 (D)) of the insulating substrate 2 (see FIG. 50). D)), the lower electrode of the gate resistor chip R1 ′ (see FIGS. 50A and 50D) and the upper conductor pattern 2b4 of the insulating substrate 2 (see FIG. 50) (FIG. 50A). And the bottom electrode of the gate resistor chip R2 (see FIGS. 50 (A) and 50 (D)) and the insulating substrate 2 (see FIG. 50) and the upper surface side conductor pattern 2b5 (see FIG. 50 (A) and FIG. 50 (D)) by the solder 10b8 (see FIG. 50 (D)) and the gate resistance chip R2 ′ (See Figure 50 (A) and Figure 50 (D). ) And the upper surface side conductor pattern 2b5 (see FIG. 50 (A) and FIG. 50 (D)) of the insulating substrate 2 (see FIG. 50) by the solder 10b8 ′ (see FIG. 50 (D)). Is executed. Next, wire bonding shown in FIG. 51 is performed. Next, as shown in FIG. 56 (B), the lower surface side conductor pattern 2c (FIG. 49B) of the metal heat sink 1 (see FIGS. 48 and 56) and the insulating substrate 2 (see FIGS. 49 and 56), 49 (C) and FIG. 56 (B)) joining by solder 10a (see FIG. 56 (B)), upper surface side conductor pattern 2b6 (see FIG. 49) of insulating substrate 2 (see FIGS. 49 and 56). (A), FIG. 49 (B) and FIG. 56 (B)) and the lower end portion 6b4 (see FIG. 56 (B)) of the external lead-out terminal 6b (see FIG. 56 (A) and FIG. 56 (B)). Bonding by solder 10f2 (see FIG. 56 (B)), upper surface side conductor pattern 2b2 (see FIGS. 49 (A) and 56 (B)) of the insulating substrate 2 (see FIGS. 49 and 56) and external lead-out terminals 6a (see FIG. 56 (A) and FIG. 56 (B)), the lower end 6a4 ( 56 (B)) and the upper surface side conductor pattern 2b7 (FIGS. 49 (A) and 49) of the insulating substrate 2 (see FIGS. 49 and 56). (B) and FIG. 56 (B)) and the solder 10f3 (see FIG. 56) between the lower end portion 6c4 (see FIG. 56 (B)) of the external lead-out terminal 6c (see FIG. 56 (A) and FIG. 56 (B)). 56 (B)) is performed. Further, at the time of performing the solder joining shown in FIG. 56 (B), a concave shape of a basing jig (not shown) like the power semiconductor module shown in FIG. 3 of Patent Document 1 (Japanese Patent Laid-Open No. 2010-199251). The metal heat dissipating plate 1 (see FIG. 56) is fixed to a basing jig (not shown) so that the lower surface of the metal heat dissipating plate 1 (see FIG. 56) is deformed into a convex shape following the upper surface.

  In recent years, high reliability is required for power semiconductor modules. Specifically, it is required to withstand severe temperature cycle tests.

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have made the lower surface side conductor pattern 2c (see FIG. 56) of the metal heat sink 1 (see FIG. 56) and the insulating substrate 2 (see FIG. 56). 56 (B)) was subjected to a temperature cycle test of soldering. Specifically, in the research by the present inventors, between the metal heat sink 1 (see FIG. 56) and the lower surface side conductor pattern 2c (see FIG. 56B) of the insulating substrate 2 (see FIG. 56). A temperature cycle test was performed using Pb (lead) -free solder having a low tensile strength and containing no Sb (antimony) for solder bonding. As a result, after the temperature cycle test, Pb not containing Sb between the metal heat sink 1 (see FIG. 56) and the lower surface side conductor pattern 2c (see FIG. 56B) of the insulating substrate 2 (see FIG. 56). It was confirmed that the free solder was peeled off.

  The present inventors have insufficient solder tensile strength between the metal heat sink 1 (see FIG. 56) and the lower conductor pattern 2c (see FIG. 56B) of the insulating substrate 2 (see FIG. 56). In the research conducted by the present inventors, between the metal heat sink 1 (see FIG. 56) and the lower surface side conductor pattern 2c (see FIG. 56B) of the insulating substrate 2 (see FIG. 56). A temperature cycle test was carried out using Pb-free solder (alloy composition such as Sn-3.9Ag-0.6Cu-3.0Sb) containing Sb and having high tensile strength for solder bonding. As a result, after the temperature cycle test, Pb containing Sb between the metal heat sink 1 (see FIG. 56) and the lower surface side conductor pattern 2c (see FIG. 56B) of the insulating substrate 2 (see FIG. 56). It was confirmed that the free solder did not peel off.

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b6 (FIG. 49A and FIG. 56) of the insulating substrate 2 (see FIG. 49 and FIG. 56). B)) and the soldering temperature cycle between the lower end portion 6b4 (see FIG. 56B) of the external lead-out terminal 6b (see FIGS. 53, 54, 56A and 56B). A test was conducted. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead terminal 6b (see FIG. 53, 54, 56 (A) and 56 (B)), the solder joint between the lower end 6b4 (see FIG. 56 (B)) has a high tensile strength and Pb free containing Sb. A temperature cycle test was performed using solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead terminal 6b (see FIGS. 53 and 54). 56 (A) and FIG. 56 (B)), the Pb-free solder containing Sb between the lower end 6b4 (see FIG. 56 (B)) is not peeled off, but the insulating substrate 2 (FIG. 49 and FIG. 56), it was confirmed that the upper surface side conductor pattern 2b6 (see FIG. 49A and FIG. 56B) was damaged.

  Temperature of the external lead-out terminal 6b (see FIG. 58 (B)) covered with the gel-like resin (not shown) in the surrounding case 6 (see FIGS. 57, 58 (A) and 58 (B)). Thermal expansion / contraction amount in the vertical direction during the cycle test (vertical direction in FIG. 58B), and vertical direction during the temperature cycle test for the gel-like resin (not shown) (in the vertical direction in FIG. 58B) Direction) thermal expansion amount and thermal contraction amount are different, so that the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal When Pb-free solder containing Sb and having high tensile strength is used for solder joint with the lower end 6b4 (see FIG. 56B) of 6b (see FIG. 56), an external lead terminal is used during a temperature cycle test. 6b (see FIG. 56B) up and down direction (up and down in FIG. 56B) ) And the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 56 (B)) of the gel-like resin (not shown), and the difference between Pb containing Sb It cannot be sufficiently absorbed by the deformation of the free solder, and as a result, is applied to the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56). The present inventors considered that the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) was damaged by the thermal stress.

  Therefore, in the studies by the present inventors, the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead terminal 6b (see FIG. 56). Pb-free solder that has a low tensile strength and does not contain Sb (alloy composition is, for example, Sn-0.3Ag-0.7Cu-0.) For solder joint with the lower end 6b4 (see FIG. 56B) of 035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6b (see FIG. 56). The Pb-free solder containing no Sb between the lower end 6b4 (see FIG. 56B) does not peel off, and the upper surface side conductor pattern 2b6 (see FIG. 49A) of the insulating substrate 2 (see FIGS. 49 and 56). It was also confirmed that no damage occurred (see FIG. 56B).

  In order to meet the recent high reliability requirements for the power semiconductor module, the present inventors have provided the upper surface side conductor pattern 2b2 (FIG. 49A) and FIG. 56 (FIG. 56) of the insulating substrate 2 (see FIG. 49 and FIG. 56). B)) and the temperature cycle of the solder joint between the external lead terminal 6a (see FIGS. 53, 54, 56A and 56B) and the lower end 6a4 (see FIG. 56B). A test was conducted. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6a (see FIG. 53, 54, 56 (A) and 56 (B)), the solder joint between the lower end 6a4 (see FIG. 56 (B)) has a high tensile strength and Pb free containing Sb. A temperature cycle test was performed using solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead terminal 6a (see FIGS. 53 and 54). 56 (A) and FIG. 56 (B)), the Pb-free solder containing Sb between the lower ends 6a4 (see FIG. 56 (B)) is not peeled off, but the insulating substrate 2 (FIG. 49 and FIG. 56), it was confirmed that the upper surface side conductor pattern 2b2 (see FIG. 49A and FIG. 56B) was damaged.

  The temperature of the external lead-out terminal 6a (see FIG. 58 (B)) covered with the gel-like resin (not shown) in the outer case 6 (see FIGS. 57, 58 (A) and 58 (B)). Thermal expansion / contraction amount in the vertical direction during the cycle test (vertical direction in FIG. 58B), and vertical direction during the temperature cycle test for the gel-like resin (not shown) (in the vertical direction in FIG. 58B) Direction) thermal expansion amount and thermal contraction amount are different, so that the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal When Pb-free solder containing Sb and having high tensile strength is used for solder joint with the lower end 6a4 (see FIG. 56B) of 6a (see FIG. 56), an external lead-out terminal is used during a temperature cycle test. 6a (see FIG. 56B) up and down direction (up and down in FIG. 56B) ) And the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 56 (B)) of the gel-like resin (not shown), and the difference between Pb containing Sb It cannot be sufficiently absorbed by deformation of the free solder, and as a result, is applied to the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56). The present inventors considered that the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) was damaged by the thermal stress.

  Therefore, in the research by the present inventors, the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6a (see FIG. 56). Pb-free solder having a low tensile strength and containing no Sb (alloy composition is Sn-0.3Ag-0.7Cu-0.), For example, at the lower end 6a4 (see FIG. 56B). 035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6a (see FIG. 56). The Pb-free solder containing no Sb between the lower end 6a4 (see FIG. 56B) does not peel off, and the upper surface side conductor pattern 2b2 (see FIG. 49A) of the insulating substrate 2 (see FIGS. 49 and 56). It was also confirmed that no damage occurred (see FIG. 56B).

  Furthermore, in order to meet the recent high reliability requirement for the power semiconductor module, the present inventors have made the upper surface side conductor pattern 2b7 (FIG. 49A and FIG. 56) of the insulating substrate 2 (see FIG. 49 and FIG. 56). B)) and the temperature cycle of the solder joint between the external lead terminal 6c (see FIGS. 53, 54, 56A and 56B) and the lower end 6c4 (see FIG. 56B). A test was conducted. Specifically, in the research by the present inventors, the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6c (see FIG. 53, 54, 56 (A) and 56 (B)), the solder joint between the lower end portion 6c4 (see FIG. 56 (B)) has a high tensile strength and is free of Pb containing Sb. A temperature cycle test was performed using solder. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead terminal 6c (see FIGS. 53 and 54). 56 (A) and FIG. 56 (B)), the Pb-free solder containing Sb between the lower end 6c4 (see FIG. 56 (B)) is not peeled off, but the insulating substrate 2 (FIG. 49 and FIG. 56), it was confirmed that the upper surface side conductor pattern 2b7 (see FIG. 49A and FIG. 56B) was damaged.

  The temperature of the external lead-out terminal 6c (see FIG. 58 (B)) covered with the gel-like resin (not shown) in the outer case 6 (see FIGS. 57, 58 (A) and 58 (B)). Thermal expansion / contraction amount in the vertical direction during the cycle test (vertical direction in FIG. 58B), and vertical direction during the temperature cycle test for the gel-like resin (not shown) (in the vertical direction in FIG. 58B) Direction) thermal expansion amount and thermal contraction amount are different, so that the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal When Pb-free solder containing Sb and having high tensile strength is used for solder joint with the lower end portion 6c4 (see FIG. 56B) of 6c (see FIG. 56), an external lead terminal is used during a temperature cycle test. 6c (see FIG. 56B) up and down direction (up and down in FIG. 56B) ) And the amount of thermal expansion / shrinkage in the vertical direction (vertical direction in FIG. 56 (B)) of the gel-like resin (not shown), and the difference between Pb containing Sb It cannot be sufficiently absorbed by the deformation of the free solder, and as a result, is applied to the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56). The present inventors considered that the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) was damaged by the thermal stress.

  Therefore, in the study by the present inventors, the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead terminal 6c (see FIG. 56). Pb-free solder having a low tensile strength and containing no Sb (alloy composition is, for example, Sn-0.3Ag-0.7Cu-0.) For solder joint with the lower end 6c4 (see FIG. 56B) of 035Ni, Sn-0.7Cu-0.05Ni, etc.) were used to perform a temperature cycle test. As a result, after the temperature cycle test, the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6c (see FIG. 56). The Pb-free solder containing no Sb between the lower end 6c4 (see FIG. 56B) does not peel off, and the upper surface side conductor pattern 2b7 (see FIG. 49A) of the insulating substrate 2 (see FIGS. 49 and 56). It was also confirmed that no damage occurred (see FIG. 56B).

  In view of the research results of the present inventors, in the power semiconductor module 100 of the sixth embodiment, the lower surface side of the metal heat sink 1 (see FIGS. 48 and 56) and the insulating substrate 2 (see FIGS. 49 and 56). Pb-free solder 10a containing Sb (see FIG. 56 (B)) is used for solder joint with the conductor pattern 2c (see FIGS. 49 (B), 49 (C) and 56 (B)). ing.

  Therefore, according to the power semiconductor module 100 of the sixth embodiment, the lower surface side conductors of the metal heat sink 1 (see FIGS. 48 and 56) and the insulating substrate 2 (see FIGS. 49 and 56) after the temperature cycle test. Separation of the solder 10a (see FIG. 56 (B)) between the pattern 2c (see FIGS. 49 (B), 49 (C) and 56 (B)) can be avoided, and the metal heat sink 1 (See FIGS. 48 and 56) and the lower surface side conductor pattern 2c (see FIGS. 49B, 49C, and 56B) of the insulating substrate 2 (see FIGS. 49 and 56). The reliability of solder joint can be improved.

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, the upper surface side conductor pattern 2b6 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6b. Sb having a tensile strength lower than that of the Pb-free solder 10a containing Sb (see FIG. 56B) for solder joint with the lower end portion 6b4 (see FIG. 56B) of (see FIG. 56). Pb-free solder 10f2 (see FIG. 56B) that does not contain is used.

  Therefore, according to the power semiconductor module 100 of the sixth embodiment, the upper surface side conductor pattern 2b6 (FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) after the temperature cycle test. The solder 10f2 (see FIG. 56B) between the lower end portion 6b4 (see FIG. 56B) of the external lead-out terminal 6b (see FIG. 56) and the insulating substrate 2 (see FIGS. 49 and 56). Damage to the upper surface side conductor pattern 2b6 (see FIG. 49A and FIG. 56B) can be avoided simultaneously, and the upper surface side conductor pattern 2b6 (see FIG. 49 and FIG. 56) of the insulating substrate 2 can be avoided. 49 (A) and 56 (B)) and the reliability of solder bonding between the lower end portion 6b4 (see FIG. 56 (B)) of the external lead-out terminal 6b (see FIG. 56) can be improved. .

  In the power semiconductor module 100 of the sixth embodiment, the upper surface side conductor pattern 2b2 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6a. Sb having a tensile strength lower than that of the Pb-free solder 10a containing Sb (see FIG. 56B) for solder joint with the lower end portion 6a4 (see FIG. 56B) of (see FIG. 56). Pb-free solder 10f1 (see FIG. 56B) that does not contain is used.

  Therefore, according to the power semiconductor module 100 of the sixth embodiment, the upper surface side conductor pattern 2b2 (FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) after the temperature cycle test. The solder 10f1 (see FIG. 56B) between the lower end 6a4 (see FIG. 56B) of the external lead-out terminal 6a (see FIG. 56) and the insulating substrate 2 (see FIGS. 49 and 56). (See FIG. 49A and FIG. 56B) can be avoided at the same time, and the upper surface side conductor pattern 2b2 (see FIG. 49 and FIG. 56) of the insulating substrate 2 can be avoided. 49A and 56B) and the solder joint reliability between the lower end portion 6a4 of the external lead-out terminal 6a (see FIG. 56) (see FIG. 56B) can be improved. .

  Furthermore, in the power semiconductor module 100 of the sixth embodiment, the upper surface side conductor pattern 2b7 (see FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) and the external lead-out terminal 6c. Sb, which has a lower tensile strength than the Pb-free solder 10a containing Sb (see FIG. 56B), is used for solder joint with the lower end portion 6c4 (see FIG. 56B) of (see FIG. 56). Pb-free solder 10f3 (see FIG. 56B) that does not contain is used.

  Therefore, according to the power semiconductor module 100 of the sixth embodiment, the upper surface side conductor pattern 2b7 (FIGS. 49A and 56B) of the insulating substrate 2 (see FIGS. 49 and 56) after the temperature cycle test. The solder 10f3 (see FIG. 56B) between the lower end portion 6c4 (see FIG. 56B) of the external lead-out terminal 6c (see FIG. 56) and the insulating substrate 2 (see FIGS. 49 and 56). (See FIG. 49A and FIG. 56B) can be avoided at the same time, and the upper surface side conductor pattern 2b7 (see FIG. 49 and FIG. 56) of the insulating substrate 2 can be avoided. 49 (A) and 56 (B)) and the solder joint reliability between the lower end portion 6c4 (see FIG. 56 (B)) of the external lead-out terminal 6c (see FIG. 56) can be improved. .

  In the power semiconductor module 100 of the sixth embodiment, solders 10b1, 10b1 ′, 10b2, 10b2 ′, 10b3, 10b3 ′, 10b4, 10b4 ′, 10b5, 10b6, 10b7, 10b7 ′, 10b8, 10b8 ′ (FIG. 50 ( B), as shown in FIGS. 50C and 50D), a Pb-free solder that does not contain Sb and has a lower tensile strength than the Pb-free solder 10a containing Sb (see FIG. 56B) is used. However, in the modification of the power semiconductor module 100 of the sixth embodiment, instead of the solders 10b1, 10b1 ′, 10b2, 10b2 ′, 10b3, 10b3 ′, 10b4, 10b4 ′, 10b5, 10b6, 10b7, 10b7 ′, 10b8, 10b8 ′ (see FIGS. 50B, 50C, and 50D) and Te solder 10a (FIG. 56 (B) refer) as well as high tensile strength, it is also possible to use Pb-free solder containing combined with Sb.

  In the seventh embodiment, the first to sixth embodiments and their modifications can be combined as appropriate, or the number of chips can be arbitrarily changed.

DESCRIPTION OF SYMBOLS 1 Metal heat sink 1h Hole 2 Insulating board 2a Insulating layer 2b1, 2b2, 2b3, 2b4 Upper surface side conductor pattern 2b5, 2b6, 2b7 Upper surface side conductor pattern 2c Lower surface side conductor pattern 2h Hole 3a, 3a ', 3b, 3b', 3c, 3c 'Power semiconductor chips 3d, 3d', 3e, 3f Power semiconductor chips 4a, 4b Electrode plates 5a, 5b Connection members 5a1, 5a2, 5b1, 5b2 Lower end 6 Enclosure cases 6a, 6b, 6c External lead-out terminals 6a1 6b1, 6c1 Upper end 6a2, 6b2, 6c2 Center 6a4, 6b4, 6c4 Lower end 6d, 6e, 6f, 6g Side wall 7 Lid 7a, 7b, 7c Hole 7f Recess 7g Leg 10a, 10b1, 10b1 'Solder 10b2 , 10b2 ', 10b3, 10b3' Solder 10b4, 10b4 ', 10b5, 10b6 Solder 10b7, 10b7', 0B8,10b8 'solder 10c1,10c2,10d1,10d2 solder 10e1,10e2 solder 10f1,10f2,10f3 solder 10g1 solder 100 power semiconductor module R1, R1', R2, R2 'gate resistor chips

Claims (4)

A power semiconductor chip (3a) having a top electrode through which a large current flows and a bottom electrode through which a large current flows;
A first insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the power semiconductor chip (3a) and is electrically connected to the lower surface electrode of the power semiconductor chip (3a). An upper surface side conductor pattern (2b1), a second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a); An insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat radiating plate (1) for radiating the heat generated by the power semiconductor chip (3a) is provided,
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
A first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2) is insert-molded into the outer case (6);
A second outer lead-out terminal (6b) having a lower end (6b4) electrically connected to the first upper surface side conductor pattern (2b1) is insert-molded in the outer case (6);
Solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the second external lead terminal ( 6b) between the lower end (6b4) of the solder and between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). By fixing the metal heat radiating plate (1) to the basing jig so that the lower surface of the metal heat radiating plate (1) is deformed into a convex shape following the concave upper surface of the basing jig during the soldering of In the manufactured power semiconductor module (100),
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
More than the Pb-free solder (10a) containing Sb in the solder joint between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end (6b4) of the second external lead-out terminal (6b). Using a Pb-free solder (10f2) having a low tensile strength and containing no Sb,
More than the Pb-free solder (10a) containing Sb in the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). A power semiconductor module (100) using Pb-free solder (10f1) having low tensile strength and containing no Sb. A power semiconductor chip (3a) having a top electrode through which a large current flows and a bottom electrode through which a large current flows;
A first insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the power semiconductor chip (3a) and is electrically connected to the lower surface electrode of the power semiconductor chip (3a). An upper surface side conductor pattern (2b1), a second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a); An insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat radiating plate (1) for radiating the heat generated by the power semiconductor chip (3a) is provided,
A first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2);
A second external lead terminal (6b) having a lower end (6b4) electrically connected to the first upper surface side conductor pattern (2b1) is provided,
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
Solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the second external lead terminal ( 6b) between the lower end (6b4) of the solder and between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). At the time of performing the solder joining, the metal heat radiating plate (1) is fixed to the basing jig so that the lower surface of the metal heat radiating plate (1) deforms into a convex shape following the concave upper surface of the basing jig,
The outer casing (6) disposed on the metal heat sink (1) is filled with a gel resin, and the gel semiconductor allows the power semiconductor chip (3a) and the center of the first external lead-out terminal (6a). In the power semiconductor module (100) covering the part (6a2) and the lower end part (6a4) and the central part (6b2) and the lower end part (6b4) of the second external lead-out terminal (6b),
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
More than the Pb-free solder (10a) containing Sb in the solder joint between the first upper surface side conductor pattern (2b1) of the insulating substrate (2) and the lower end (6b4) of the second external lead-out terminal (6b). Using a Pb-free solder (10f2) having a low tensile strength and containing no Sb,
More than the Pb-free solder (10a) containing Sb in the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). A power semiconductor module (100) using Pb-free solder (10f1) having low tensile strength and containing no Sb. A power semiconductor chip (3a) having a top electrode through which a large current flows and a bottom electrode through which a large current flows;
A first insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the power semiconductor chip (3a) and is electrically connected to the lower surface electrode of the power semiconductor chip (3a). An upper surface side conductor pattern (2b1), a second upper surface side conductor pattern (2b2) formed on the upper surface side of the insulating layer (2a) and electrically connected to the upper surface electrode of the power semiconductor chip (3a); An insulating substrate (2) having a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat radiating plate (1) for radiating the heat generated by the power semiconductor chip (3a) is provided,
A connection member (5a) for electrically connecting the upper surface electrode of the power semiconductor chip (3a) and the second upper surface side conductor pattern (2b2) of the insulating substrate (2);
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
Solder joint between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), and one lower end (5a1) of the connecting member (5a) and the insulating substrate (2) When performing solder joining with the second upper surface side conductor pattern (2b2), a metal heat radiating plate (1) is formed so that the lower surface of the metal heat radiating plate (1) deforms into a convex shape following the concave upper surface of the basing jig. 1) is fixed to the basing jig,
A power semiconductor module in which an enclosing case (6) disposed on a metal heat sink (1) is filled with a gel resin and the power semiconductor chip (3a) and the connection member (5a) are covered with the gel resin. (100)
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
The solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and one lower end portion (5a1) of the connection member (5a) is pulled more than the Pb-free solder (10a) containing Sb. A power semiconductor module (100) characterized by using Pb-free solder (10d1) having low strength and containing no Sb. Providing a first power semiconductor chip (3a) having a top electrode through which a large current flows and a bottom electrode through which a large current flows;
Providing a second power semiconductor chip (3c) having a top electrode through which a large current flows and a bottom electrode through which a large current flows;
An insulating layer (2a) is formed on the upper surface side of the insulating layer (2a) for mounting the first power semiconductor chip (3a) and the second power semiconductor chip (3c), and the first power semiconductor chip (3a) ) And the first upper surface side conductor pattern (2b1) electrically connected to the lower surface electrode of the second power semiconductor chip (3c), and the first upper surface side conductor pattern (2a). The second upper surface side conductor pattern (2b2) electrically connected to the upper surface electrode of the power semiconductor chip (3a), the upper surface side of the insulating layer (2a), and the second power semiconductor chip (3c) Providing an insulating substrate (2) having a third upper surface side conductor pattern (2b6) electrically connected to the upper surface electrode and a lower surface side conductor pattern (2c) formed on the lower surface side of the insulating layer (2a);
A metal heat dissipating plate (1) for dissipating heat generated by the first power semiconductor chip (3a) and the second power semiconductor chip (3c);
A first external lead terminal (6a) having a lower end (6a4) electrically connected to the second upper surface side conductor pattern (2b2);
A second external lead terminal (6b) having a lower end (6b4) electrically connected to the third upper surface side conductor pattern (2b6);
An outer case (6) having a right side wall (6d), a left side wall (6e), a front side wall (6f), and a rear side wall (6g), formed by molding an electrically insulating resin material;
Solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2), the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the second external lead terminal ( 6b) between the lower end (6b4) of the solder and between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). At the time of performing the solder joining, the metal heat radiating plate (1) is fixed to the basing jig so that the lower surface of the metal heat radiating plate (1) deforms into a convex shape following the concave upper surface of the basing jig,
The outer casing (6) disposed on the metal heat sink (1) is filled with a gel resin, and the first power semiconductor chip (3a) and the second power semiconductor chip (3c) are filled with the gel resin. And a power semiconductor covering the central part (6a2) and the lower end part (6a4) of the first external lead-out terminal (6a) and the central part (6b2) and the lower end part (6b4) of the second external lead-out terminal (6b) In module (100),
Pb-free solder (10a) containing Sb is used for solder bonding between the metal heat sink (1) and the lower surface side conductor pattern (2c) of the insulating substrate (2).
More than the Pb-free solder (10a) containing Sb in the solder joint between the third upper surface side conductor pattern (2b6) of the insulating substrate (2) and the lower end portion (6b4) of the second external lead-out terminal (6b). Using a Pb-free solder (10f2) having a low tensile strength and containing no Sb,
More than the Pb-free solder (10a) containing Sb in the solder joint between the second upper surface side conductor pattern (2b2) of the insulating substrate (2) and the lower end (6a4) of the first external lead-out terminal (6a). A power semiconductor module (100) using Pb-free solder (10f1) having low tensile strength and containing no Sb.

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