JP2015101059A - Optical writing device, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical writing device that is able to reduce variations in quantity of light emitted by respective light emitting elements, resulting from a voltage decrease, while decreasing cost without requiring many power supply points.SOLUTION: In each of dot circuits 100 having an OLED 101, a drive circuit 102, a sample hold circuit 103 and a forcible shut-off switch 106, the forcible shut-off switch 106 is opened during a charging period in which a luminance signal SG is written in a hold element 105 of the sample hold circuit 103, thereby preventing a current from a common power source 180 from flowing into the OLED 101 via a power source line 192 and a drive circuit 102. When a charge period for all the dot circuits is over, all the forcible shut-off switches 106 are closed to start a light emission period, thereby allowing a transition in which current from the common power source 180 flows in the OLED 101.

Description

  The present invention relates to an optical writing device and an image forming apparatus including the same.

2. Description of the Related Art Some image forming apparatuses such as printers use an optical writing unit that arranges minute light emitting elements in a line and irradiates a photosensitive member with a light beam emitted from each light emitting element.
Patent Document 1 discloses a line head in which a large number of organic EL elements, which are light emitting elements, are arranged on a substrate in the main scanning direction as an optical writing unit.
In the line head, a parallel circuit in which each of the plurality of organic EL elements is connected to the power supply line A on the power supply side and the cathode side is connected to the power supply line B on the ground side is disposed on the substrate. It is configured. Further, a moisture-proof plate is arranged at a distance from the substrate, and an auxiliary power line C on the power source side and an auxiliary power line D on the ground side are separately wired on the moisture-proof plate.

The power line A on the substrate and the auxiliary power line C on the moisture barrier plate are electrically connected at a plurality of locations, and the power line B on the substrate and the auxiliary power line D on the moisture barrier plate are electrically connected at a plurality of locations. Thus, the circuit configuration is such that the number of feeding points for each organic EL element is increased.
With this configuration in which the number of feeding points is increased, the wiring distance of the power supply line from one feeding point to each organic EL element can be shortened as compared with a configuration with a small number of feeding points. The drop is small, the difference in the supply current to each organic EL element due to the potential drop is reduced, and it becomes possible to suppress the variation in the light emission amount.

JP 2005-144686 A

In the configuration of Patent Document 1, in order to increase the number of feeding points, two auxiliary power lines are arranged on the moisture-proof plate in addition to the two power lines on the substrate, and the power lines and auxiliary power lines A mechanism for electrically connecting the two is required.
In addition, as the number of feeding points is increased, the variation in the amount of light emission due to the potential drop due to the wiring distance can be suppressed. However, taking a larger number of feeding points means that the power supply line on the substrate, The number of locations where the auxiliary power supply line on the moisture-proof plate separate from the substrate is electrically connected increases and the mechanism becomes complicated, resulting in a problem that the cost of the line head is increased.

  The present invention has been made in view of the above-described problems, and can suppress variations in the amount of light emitted from each light-emitting element due to a potential drop while suppressing cost without increasing the number of feeding points. It is an object of the present invention to provide an optical writing device and an image forming apparatus including the same.

  In order to achieve the above object, an optical writing device according to the present invention is an optical writing device in which a plurality of light emitting elements are connected in parallel via a drive driver to a power supply line extended from a common power supply. An apparatus, wherein a shut-off means for disconnecting each light-emitting element from the power line, a holding element provided corresponding to each of the plurality of light-emitting elements, and power supply to each light-emitting element are shut off Writing means for writing an index value indicating a voltage difference between the voltage corresponding to the amount of light to be emitted and the voltage of the common power supply to each holding element corresponding to each of the light emitting elements, Each of the drive drivers has an index value held in a holding element corresponding to the light emitting element, the current supplied from the power line when the interruption of the power supply by the interruption means is released. Voltage In response to control and supplying to the light emitting element.

Further, the writing means sequentially writes the index value to each of the plurality of holding elements, and the blocking means starts from the start of writing to the holding element to which the index value is written first, and finally The power supply may be shut off over a writing period until the writing is completed for the holding element to which the index value is written.
Further, the writing means sequentially writes the index value to each of the plurality of holding elements, and the blocking means has N light emitting elements, corresponding to the N light emitting elements. When each of the N holding elements is numbered in the order of writing, all the light emitting elements corresponding to the Q (where 1 <Q <N) and subsequent holding elements from the first to the Nth are displayed. In the case of non-light emission, the writing period from the start of writing to the holding element to which the index value is first written to the end of writing to the holding element to which the index value is written (Q-1) th is described. The power supply may be shut off.

Further, the blocking unit may release the blocking for the plurality of light emitting elements at the same time when the writing period ends.
Further, the blocking means may be a switch provided in each column in a circuit in which the plurality of light emitting elements are connected in parallel to the power supply line, and opens and closes a path of a current flowing through the column.

Here, the switch may be provided between the light emitting element and the drive driver.
The drive driver is a P-type or N-type field effect transistor, the holding element is a capacitor, one end of the capacitor is connected to the gate of the field effect transistor, and the other end of the capacitor is It may be connected to the source of the field effect transistor.

Furthermore, the light emitting element may be an organic LED, and the driving driver and the holding element may be formed of thin film transistors.
An image forming apparatus according to the present invention is an image forming apparatus that writes an image on an image carrier with a light beam from an optical writing unit, and includes the optical writing device as the optical writing unit. And

  With the above-described configuration, since the reference voltage for determining the index value written in the holding element corresponding to the light emitting element can be used as the common power supply voltage for each of the plurality of light emitting elements. Even if such an auxiliary power line is not separately provided to increase the number of feeding points, variations in the amount of light emission due to a potential drop in the power line can be suppressed.

1 is a diagram illustrating a configuration of an image forming apparatus according to Embodiment 1. FIG. It is a figure which shows schematic structure of the print head contained in an exposure part. FIG. 2 is a schematic plan view and a cross-sectional view of an OLED panel in a print head. It is a figure which shows typically the relationship between OLED provided in the TFT substrate in an OLED panel, a drive circuit, an S / H circuit, etc. It is a figure which shows the mode of a charge period in the circuit structure of an Example. It is a figure which shows the mode of the light emission period in the circuit structure of an Example. It is a figure which shows the timing chart of the light extinction period and light emission period in each dot circuit. It is a figure which shows the mode of the charge period of one dot circuit. It is a figure which shows the mode of the holding period A (standby) of one dot circuit. It is a figure which shows the mode of the holding period B (light emission period) of one dot circuit. It is a block diagram which shows the circuit structure of a comparative example. It is a timing chart which shows the mode of the charge period and light emission period in the structure of a comparative example. It is a figure for demonstrating the dispersion | variation in the light emission amount by the potential drop of a power supply line generate | occur | produces in the structure of a comparative example. It is a figure which shows graphs, such as the relationship between the wiring distance from a common power supply, and the electric potential on a power supply line. It is a figure which shows the mode of the presence or absence of the brightness | luminance change of each OLED resulting from the electric potential drop of the power source line in the case of all lighting about an Example and a comparative example. FIG. 10 is a diagram illustrating a timing chart of an extinguishing period and a light emitting period in each dot circuit according to the second embodiment. FIG. 5 is a diagram schematically illustrating a relationship between a sheet width, a photosensitive drum, and N OLEDs on a print head. It is a schematic diagram which shows the difference in the light emission period with respect to large size paper and small size paper. It is a flowchart which shows the content of the control which switches a light emission period according to paper width. It is a figure which shows the circuit structure which concerns on a modification. It is a figure which shows another circuit structure which concerns on a modification.

Hereinafter, embodiments of an optical writing device and an image forming apparatus according to the present invention will be described by taking a tandem type color printer (hereinafter simply referred to as “printer”) as an example.
<Embodiment 1>
FIG. 1 is a schematic diagram illustrating the overall configuration of a printer 1 according to the present embodiment.
As shown in FIG. 1, the printer 1 forms an image by an electrophotographic method, and includes an image processing unit 10, an intermediate transfer unit 20, a feeding unit 30, a fixing unit 40, and a control unit 50. Color image formation (printing) is executed based on a job execution request from an external terminal device (not shown) via a network (for example, LAN).

The image processing unit 10 includes image forming units 10Y, 10M, 10C, and 10K corresponding to development colors of yellow (Y), magenta (M), cyan (C), and black (K).
The image forming unit 10Y includes a photosensitive drum 11 as an image carrier, a charging unit 12, an exposure unit 13, a developing unit 14, a cleaner 15 and the like disposed around the photosensitive drum 11.
The charging unit 12 charges the peripheral surface of the photosensitive drum 11 that rotates in the direction indicated by the arrow A.

The exposure unit (optical writing unit) 13 exposes the charged photosensitive drum 11 with the light beam L to form an electrostatic latent image on the photosensitive drum 11. In this embodiment, since a so-called reversal development method is employed, an electrostatic latent image is formed by exposing a portion where a toner image is to be formed in a charged area on the peripheral surface of the photosensitive drum 11. It is formed.
In the exposure unit 13, a current-driven organic EL element (hereinafter referred to as “OLED”), which is a light emitting element, extends along the drum axis direction (hereinafter referred to as “main direction”) of the photosensitive drum 11. A number of printheads arranged on a substrate are included. The configuration of this print head will be described later.

  The developing unit 14 develops the electrostatic latent image on the photosensitive drum 11 with Y toner. As a result, a Y-color toner image is formed on the photosensitive drum 11, and the formed Y-color toner image is primarily transferred onto the intermediate transfer belt 21 of the intermediate transfer unit 20. The cleaner 15 cleans residual toner on the photosensitive drum 11. The other image forming units 10M to 10K have the same configuration as the image forming unit 10Y, and the reference numerals are omitted in FIG.

The intermediate transfer unit 20 is stretched around a driving roller 24 and a driven roller 25 and circulated in the direction of the arrow, and the photosensitive drums 11 of the image forming units 10Y to 10K across the intermediate transfer belt 21. A primary transfer roller 22 disposed opposite to the drive roller 24 and a secondary transfer roller 23 disposed opposite to the drive roller 24.
The feeding unit 30 includes a sheet 31, in this case, a cassette 31 that stores the paper S, a feeding roller 32 that feeds the paper S from the cassette 31 one by one to the transport path 39, a transport roller 33 that transports the fed paper S, 34 is provided.

The fixing unit 40 includes a fixing roller 41 and a pressure roller 42 pressed against the fixing roller 41.
The control unit 50 comprehensively controls the operations of the image processing unit 10 to the fixing unit 40 to execute a smooth job. When the job is executed, the control unit 50 executes the following operation.
That is, drive data for causing a plurality of OLEDs disposed in the exposure units 13 of the image forming units 10Y to 10K to emit light is generated based on the print image data included in the received job.

Since this driving data is a digital signal here, the luminance signal output unit 51 (FIG. 3) of the control unit 50 converts the driving data into an analog luminance signal indicating the light emission amount for each OLED and sends it to the exposure unit 13. It is done. Each OLED of the exposure unit 13 emits a light beam L having a light amount based on the analog luminance signal.
A light beam L is emitted from each OLED of the exposure unit 13 for each of the image forming units 10Y to 10K, and when the charged photosensitive drum 11 is exposed to the light beam L, the photosensitive drum 11 is electrostatically exposed. A latent image is formed, and the electrostatic latent image formed on the photosensitive drum 11 is developed with toner to form a toner image.

The toner images formed on the respective photosensitive drums 11 are primarily transferred onto the intermediate transfer belt 21 by the electrostatic action of the primary transfer roller 22 disposed on the photosensitive drum 11 via the intermediate transfer belt 21. The
In the image forming operation of each color by the image forming units 10Y to 10K, the timing is shifted from the upstream side to the downstream side so that the toner images of the respective colors are superimposed and transferred at the same position on the traveling intermediate transfer belt 21. Executed.

In synchronization with this image formation timing, the sheet S is conveyed from the cassette 31 toward the secondary transfer roller 23 from the feeding unit 30, and the sheet is transferred between the secondary transfer roller 23 and the intermediate transfer belt 21. When S passes, the color toner images transferred onto the intermediate transfer belt 21 are secondarily transferred onto the sheet S by electrostatic action of the secondary transfer roller 23.
The sheet S after each color toner image is secondarily transferred is conveyed to the fixing unit 40 and heated and pressed when passing through the nip between the fixing roller 41 and the pressure roller 42 of the fixing unit 40. The toner on the paper S is fused and fixed to the paper S. The paper S that has passed through the fixing unit 40 is discharged (output) onto the paper discharge tray 36 by the paper discharge roller 35.

FIG. 2 is a diagram showing a schematic configuration of the print head 60 included in the exposure unit 13.
As shown in the figure, the print head 60 includes an OLED panel 61, a rod lens array 62, and a housing 63 for housing them.
The OLED panel 61 has a plurality of OLEDs 101 arranged in a line, and each of the plurality of OLEDs 101 individually emits a light beam L.

The rod lens array 62 focuses the light beam L emitted from each OLED 101 on the surface of the photosensitive drum 11.
FIG. 3 is a schematic plan view of the OLED panel 61, which also shows a cross-sectional view taken along the line AA ′ and a cross-sectional view taken along the line CC ′.
As shown in the figure, the OLED panel 61 includes a TFT (thin film transistor) substrate 71, a sealing plate 72, and a source IC 73.

On the TFT substrate 71, a plurality of OLEDs 101 are arranged so as to be aligned along the main direction, and a drive circuit, a holding element, a forced cutoff switch, and the like described later are provided for each OLED 101. The circuit configuration is formed on the same TFT substrate 71.
The sealing plate 72 seals the arrangement area of the OLED 101 on the TFT substrate 71 so as not to be exposed to the outside air.

  The source IC 73 is mounted on an area other than the arrangement area of the sealing plate 72 on the TFT substrate 71, and the digital luminance signal output from the luminance signal output unit 51 of the control unit 50 is output for each OLED 101. It includes a digital / analog converter (hereinafter referred to as “DAC”) that converts it into an analog luminance signal indicating the light emission amount and a shift register described later, and also has a function of outputting a forced turn-off signal described later at a predetermined timing.

FIG. 4 is a diagram schematically showing the relationship among the OLED 101, the drive circuit 102, the S / H (sample / hold) circuit 103, the forced cutoff switch 106, and the source IC 73 provided on the TFT substrate 71.
As shown in the figure, the S / H circuit 103 includes a switch 104 and a holding element (capacitor, etc.) 105 connected in series, and one S / H circuit 103 corresponds to one drive circuit 102. The drive circuit 102 has a relationship corresponding to one OLED 101 via one forced cutoff switch 106.

On the other hand, the source IC 73 includes a plurality of DACs 74, and one DAC 74 is provided corresponding to the plurality of S / H circuits 103, and each S / H circuit 103 is connected to the corresponding OLED 101. The luminance signal SG is sequentially output.
For example, in a state in which all the switches 104 of the plurality of S / H circuits 103 corresponding to one DAC 74 are turned off (non-conducting), luminance signals SG1, SG2,. Assuming the case of outputting one by one, it is as follows.

  That is, when the luminance signal SG1 is output from the DAC 74, in synchronization with the timing, only the switch 104 of one S / H circuit 103a corresponding to the luminance signal SG1 among the plurality of S / H circuits 103 is turned on from off. Switching to (conduction), the luminance signal SG1 is written to the holding element 105 of the S / H circuit 103a. Since the switches 104 of the other S / H circuits 103 remain off, the luminance signal SG1 is not written to the other holding elements 105.

When the writing of the luminance signal SG1 to the holding element 105 in the S / H circuit 103a is completed, the switch 104 of the S / H circuit 103a is turned off, but the luminance signal SG1 is held in the holding element 105 of the S / H circuit 103a. Maintained.
Thereafter, when the next luminance signal SG2 is output from the DAC 74, in synchronization with the timing, only the switch 104 of the S / H circuit 103b corresponding to the luminance signal SG2 is switched from OFF to ON, and the luminance signal SG2 is changed. The data is written in the holding element 105.

When the writing of the luminance signal SG2 to the holding element 105 is completed, the switch 104 of the S / H circuit 103b is turned off, but the state where the luminance signal SG2 is held in the holding element 105 of the S / H circuit 103b is maintained. .
For each S / H circuit 103, the switch 104 is switched according to the input timing of the luminance signal SG, and the writing operation of the luminance signal SG is executed in order of time. This switching is performed using the shift register 109 (FIG. 5).

The forced cutoff switch 106 is a switch that opens and closes the path of the current flowing through the OLED 101 based on the forced turn-off signal SV from the source IC 73.
In the present embodiment, the forced cutoff switch 106 is closed (on) only during a predetermined light emission period, and is open (off) during other extinction periods. The reason for opening and closing at such timing will be described later.

  Each drive circuit 102 receives a current input from a common power source (not shown) during the light emission period of the OLED 101 in a state where the corresponding holding element 105 holds the luminance signal SG. The current is controlled and output to a current corresponding to the voltage of the signal SG, and supplied to the OLED 101 via the forced cutoff switch 106 in the on state. With this current supply, each OLED 101 emits light with the light emission amount indicated by the luminance signal SG. Note that the image data also includes data indicating a non-exposed area (such as a background portion of a document) where a toner image is not formed, and the luminance signal SG for this non-exposed area is a signal indicating that the light emission amount is 0 (zero). Therefore, no current is supplied from the driving circuit 102 to the OLED 101 even during the light emission period, and the OLED 101 remains off.

In accordance with the output timing of the luminance signals SG1, SG2,... From the DAC 74, the on / off switching timing of the switch 104 in each S / H circuit 103 is determined in advance. The photosensitive drum 11 is exposed by writing, holding, and emitting the luminance signal SG to the OLED 101.
FIG. 5 is a diagram showing a circuit configuration of an embodiment in which a plurality of dot circuits 100 including an OLED 101, a drive circuit 102, an S / H circuit 103, and a forced cutoff switch 106 are provided. FIG. 3 shows a state in which the luminance signal SG is written in the holding element 105 within the extinguishing period (charge period).

As shown in the figure, each of the plurality of OLEDs 101 is connected in parallel via a forced cutoff switch 106 and a drive circuit 102 between two power supply lines (power supply line 192 and cathode electrode line 194) extending from a common power supply 180. It is connected. The potential of the common power supply 180 is the reference potential Vc.
The drive circuit 102 is a voltage input type drive circuit having a gate terminal 121, an input terminal 222, and an output terminal 123. Here, the drive circuit 102 is composed of a P-type field effect transistor (FET), and the input terminal 122 The source and output terminal 123 corresponds to the drain.

The input terminal 122 of the drive circuit 102 is connected to a power supply line (wiring) 192 (corresponding to a plus-side power supply line) connected to the common power supply 180, and current from the common power supply 180 passes through the power supply line 192. Entered.
In the figure, the leftmost dot circuit 100 has the shortest wiring distance from the common power supply 180 (the length of the power supply line 192 between the common power supply 180 and the dot circuit 100), and the dot circuit 100 on the right is the same. Secondly, a circuit configuration example is shown in which the wiring distance is short and the wiring distance to each dot circuit 100 becomes longer as the wiring distance is further moved to the right side.

The drive circuit 102 outputs a current from the common power supply 180 that is input to the input terminal 122, and outputs a current having a magnitude corresponding to the difference between the voltage at the gate terminal 121 and the voltage at the input terminal 122 to the output terminal 123. Output from.
The gate terminal 121 of the driving circuit 102 is connected to the signal line 191 through the switch 104.

The signal line 191 is a signal line for transmitting the luminance signals SG1, SG2,... Output from the one DAC 74 in time order.
Here, the holding element 105 is formed of a capacitor, one terminal 151 of which is connected to the gate terminal 121 of the drive circuit 102, and the other terminal 152 is connected to the power supply line 192. Since the input terminal 122 of the drive circuit 102 is connected to the power supply line 192, the other terminal 152 of the holding element 105 is connected to the input terminal 122 of the drive circuit 102 through a part of the wiring portion of the power supply line 192. Will be connected.

  The holding element 105 holds the luminance signal SG input from the signal line 191 via the switch 104. The luminance signal SG is held by the voltage Vdac of the luminance signal SG applied to the terminal 151 of the holding element 105 (corresponding to the voltage applied to the gate terminal 121 of the driving circuit 102) and the voltage applied to the terminal 152, for example, In the dot circuit 100 at the left end, the charge corresponding to the magnitude of the voltage Vg, which is the difference from the voltage Vd1 (corresponding to the voltage applied to the input terminal 122 of the drive circuit 102 from the common power supply 180 via the power supply line 192), is held by the holding element. It is performed by being injected into 105 and stored.

Charge injection into the holding element 105 corresponds to writing of the luminance signal SG, and a writing period of the luminance signal SG is a charging period of the luminance signal SG.
An output terminal 123 of the drive circuit 102 is connected to one terminal 161 of the forced cutoff switch 106.
The forced cut-off switch 106 is a switch that opens and closes based on the on / off of the forced extinction signal SV output from the source IC 73. The figure shows an example in which all the forced cutoff switches 106 in each dot circuit 100 are in an open (off) state because the forced extinction signal SV is turned on to indicate extinction during the charging period. Yes.

  The other terminal 162 of the forced cutoff switch 106 is connected to the anode 111 of the OLED 101, and the cathode 112 of the OLED 101 is connected to the cathode electrode line 194. The cathode electrode line 194 is an earth line whose one end is connected to the earth terminal 195 common to the dot circuits 100, and corresponds to a minus-side power line with respect to the plus-side power line 192 connected to the common power supply 180. To do.

For each dot circuit 100, one of the pulse signals φ1, φ2,... Output from the shift register 109 is input to the switch 104 of the S / H circuit 103.
The pulse signals φ1, φ2,... Are signals in which the output timings of the pulse waveforms appearing at regular intervals are shifted from each other (FIG. 7), and the output timings of the luminance signals SG1, SG2,. It is determined in advance so as to be synchronized with the output timing.

  For example, when the luminance signal SG1 for the leftmost dot circuit 100 is output from the DAC 74, the pulse signal φ1 is input to the leftmost dot circuit 100, and then the luminance signal SG2 for the second dot circuit 100 from the left end. The output timing of the pulse signals φ1, φ2,... Is shifted so that the pulse signal φ2 is input to the second dot circuit 100 at the timing when is output from the DAC 74.

The switch 104 is closed (ON) only when the pulse waveform from the shift register 109 is output, and is open (OFF) when the pulse waveform is not output. In the example, only the switch 104 of the dot circuit 100 at the left end is closed, and the switches 104 of all other dot circuits 100 are open.
Thus, when the luminance signal SG to be input to each dot circuit 100 is output from the DAC 74, the switch 104 of the dot circuit 100 is turned on only at the same timing as the output, and the luminance signal SG is It is input to the holding element 105 via the switch 104 (writing of a luminance signal).

  When the writing of the luminance signal SG1 in the leftmost dot circuit 100 is completed, the switch 104 of the dot circuit 100 is turned off. Next, when the switch 104 of the second dot circuit 100 from the left end is turned on, 2 from the left end. Writing of the luminance signal SG2 to the second dot circuit 100 is started. In synchronization with the output period of the luminance signals SG1, SG2,..., The writing of the luminance signal SG is executed for each dot circuit 100 with a time order shift.

For each dot circuit 100, the period during which the luminance signal SG is written is the charge period, and the period from the end of writing the luminance signal SG to the start of the next charge period holds the written luminance signal SG. It becomes the retention period.
Since a plurality of (in the example, n) dot circuits 100 correspond to one DAC 74, one shift register 109 and one signal line 191 correspond to one DAC 74 for each DAC 74. Is provided. When a plurality of dot circuits 100 corresponding to one DAC 74 are regarded as one circuit 100Z, one circuit 100Z corresponds to one DAC 74, and a plurality of dot circuits belonging to the circuit 100Z are provided for each circuit 100Z. The writing of the luminance signal SG to 100 is executed in parallel.

If the number of dot circuits 100 (OLED 101) corresponding to one DAC 74 is n and the number of DACs 74 is M, the number (total) of all dot circuits 100 (OLED 101) provided in the OLED panel 61 is , (N × M).
In this case, the number of signal lines 191 for the luminance signal SG is M, which is the same as the number M of DACs 74. In the present embodiment, power is supplied to all dot circuits 100 using one power supply line 192 in order to reduce the number of power supply points. Therefore, the wiring distance of the signal line 191 and the wiring distance of the power supply line 192 on the TFT substrate 71 is significantly longer in one power supply line 192 than in one signal line 191.

  During the period in which the luminance signal SG is written to the holding element 105 of each dot circuit 100 (charge period), all the forced cutoff switches 106 are opened (off). As a result, the output terminals 123 of all the drive circuits 102 are opened, that is, all the OLEDs 101 are disconnected from the power supply line 192, and the current supplied from the common power supply 180 and the current from the signal line 191 are reduced. The current does not flow to the OLED 101 via each drive circuit 102 (cut off of the current flowing to the OLED 101).

On the other hand, in the light emission period, as shown in FIG. 6, all the forced shut-offs are performed by turning off the forced turn-off signal SV output from the source IC 73 while the switches 104 in all the dot circuits 100 are off. The switch 106 is closed (ON).
As a result, in each dot circuit 100, the above-described interruption of current is released, and in the drive circuit 102, the magnitude corresponding to the voltage (source-gate voltage) Vg of the difference between the voltage at the gate terminal 121 and the voltage at the input terminal 122 is obtained. This current is output from the output terminal 123, and the OLED 101 emits light with a light emission amount corresponding to the output current.

This voltage Vg corresponds to the voltage difference between one terminal 151 and the other terminal 152 of the holding element 105, that is, the amount of charge stored in the holding element 105 during the charge period.
Since the light emission amount of the OLED 101 that is a light emitting element can be set for each dot circuit 100 based on the luminance signal SG, one dot circuit 100 constitutes one light emitting unit.

  FIG. 7 is a diagram showing a timing chart of the extinguishing period and the light emitting period in each dot circuit 100. Here, in order to make the explanation easier to understand, when the number of all the dot circuits 100 is N, luminance signals SG1, SG2,... SGN for the N dot circuits 100 are sequentially output. In this example, pulse signals φ1, φ2,... ΦN corresponding to are sequentially output.

In the figure, a dot circuit 100a corresponds to the leftmost dot circuit shown in FIG. 5 among N, 100b corresponds to the second dot circuit from the left end, and 100c corresponds to the third dot circuit from the left end. Correspondingly, 100N corresponds to the Nth (last) dot circuit.
As shown in the figure, the luminance signal SG1 is output to the holding element 105 of the dot circuit 100a only while the luminance signal SG1 is output in synchronization with the timing at which the pulse waveform of the pulse signal φ1 is output from the shift register 109. Written. The writing period of the luminance signal SG1 is a charging period for the dot circuit 100a.

When the writing of the luminance signal SG1 is completed, the pulse waveform of the pulse signal φ2 is output from the shift register 109, and the luminance signal SG2 is output from the dot circuit 100b while the luminance signal SG2 is output in synchronization therewith. It is written in the holding element 105. The writing period of the luminance signal SG2 is a charging period for the dot circuit 100b.
Thereafter, writing of the corresponding luminance signals SG3,... SGN is performed in a time sequence with respect to the holding elements 105 of the dot circuits 100c,.

  The period during which the luminance signals SG1 to SGN are output is the extinguishing period Tb, and the period during which the luminance signals SG1 to SGN are not output is the light emission period Ta. In the figure, for the sake of illustration, an example is shown in which the turn-off period Tb is slightly longer than the light emission period Ta, but actually the light emission period Ta is longer than the turn-off period Tb. In most cases, the length is long. For example, one light emission period Ta is several tens to 100 times as long as one light extinction period Tb.

During the extinguishing period Tb, all the forced cutoff switches 106 are opened as described above, and the current from the common power supply 180 does not flow to the OLED 101, and during the light emission period Ta, all the forced cutoff switches 106 are closed. A current supply path from the common power supply 180 to the OLED 101 is formed.
Hereinafter, a hold period in which the luminance signal SG written in the holding element 105 in the charge period is held until the next charge period is referred to as a hold period A corresponding to a period other than the charge period in the extinguishing period. In some cases, the hold period B corresponding to the light emission period is described separately.

One light emission period Ta (time points t2 to t3) follows one light extinction period Tb (time points t1 to t2), and from the start of the light extinction period Tb (time point t1) to the end of the subsequent light emission period Ta ( A period (time points t1 to t3) extending to time point t3) is one main scanning period (Hsync).
This one main scanning period corresponds to a time for forming an electrostatic latent image for one line in the main direction (drum axis direction) on the photosensitive drum 11. In accordance with the length of this one main scanning period, the ratio of the length of one light emitting period Ta to one light extinguishing period Tb is determined in advance by experiments or the like according to the apparatus configuration.

  In one main scanning period, the start of output of the luminance signal SG1 (time t1: equivalent to the rise of the pulse waveform of the pulse signal φ1 output from the shift register 109) is the start of the extinction period Tb, and the luminance signal SGN The end of output (time t2: corresponding to the fall of the pulse waveform of the pulse signal φN output from the shift register 109) is the end of the extinguishing period Tb. The end of the turn-off period Tb (time t2) is equal to the start of the light emission period Ta, and the end of light emission period Ta (time t3) is equal to the start of output of the luminance signal SG1 for the next main scanning period.

  The forced turn-off signal SV for opening and closing the forced cutoff switch 106 is turned on in synchronization with the start of output of the luminance signal SG1 (time point t1 or t3), and all the forced cutoff switches 106 are thereby opened. Further, the forced turn-off signal SV is turned “off” in synchronization with the end of the output of the luminance signal SGN (time point t2), whereby all the forced cutoff switches 106 are closed. That is, the interruption of the power supply to all the OLEDs 101 is released at the same time.

In this way, the on / off switching of the forced extinction signal SV is executed at a predetermined timing in the DAC 74 so as to be performed in synchronization with the output timings of the luminance signals SG1 and SGN for each main scanning period. The
When one main scanning period ends, the transition to the next main scanning period is repeatedly executed, and an electrostatic latent image for one line along the main direction is formed on the rotating photosensitive drum 11 for each main scanning period. Will be formed. Thereby, an electrostatic latent image corresponding to an image for one page is formed in the rotation direction (sub-scanning direction) of the photosensitive drum 11. A graph 80 showing the reference potentials Vd1, Vd2,... VdN is shown below the timing chart in FIG.

  In the timing chart shown in FIG. 7, an example in which the luminance signals SG1, SG2,... SGN are sequentially output to all N dot circuits 100 has been described, but as shown in FIG. ) In a configuration in which one dot circuit 100 is one circuit 100Z and one DAC 74 corresponds to one circuit 100Z, for each circuit 100Z, processing in the turn-off period Tb and light emission period Ta for each main scanning period. Each process is executed in parallel.

  As described above, all the forced cutoff switches 106 are opened during the extinguishing period Tb to enter a cutoff state in which the current supply path from the common power supply 180 to each OLED 101 is forcibly cut off. The reason for adopting a configuration in which the current supply state in which the cutoff is released and the interruption is released is to prevent variation in the light emission amount of each OLED 101 due to the wiring resistance of the power supply line 192. Hereinafter, this reason will be specifically described with reference to FIGS.

8 to 10 show one dot circuit 100 rewritten so that the circuit configuration can be easily explained, and portions not necessary for the explanation are omitted. 8 shows the state of the charge period, FIG. 9 shows the state of the hold period A, and FIG. 10 shows the state of the hold period B.
8 to 10, wiring resistances of the power supply line 192 and the cathode electrode line 194 are shown as 198 and 199, respectively.

  8 to 10, the wiring resistance of the signal line 191 is not shown. This is due to the following reason. That is, since the signal line 191 is connected to the terminal 151 of the holding element 105 and the gate terminal 121 of the driving circuit 102, the holding element 105 is made of a capacitor, and the driving circuit 102 is made of FET, the DC voltage flowing through the signal line 191 is reduced. The luminance signal SG hardly flows through the holding element 105 to the power supply line 192 or from the gate terminal 121 to the input terminal 122 and the output terminal 123.

Therefore, the voltage Vdac of the luminance signal SG hardly occurs due to the wiring resistance of the signal line 191, and the signal line 191 has a negligible magnitude even if there is a potential drop due to the wiring resistance. It is.
8 to 10 also show graphs showing the relationship between the wiring distance from the common power supply 180 and the potential drop on the power supply line 192 below the circuit configuration diagram.

  As shown in FIG. 8, since the forced cutoff switch 106 is turned off during the charging period, the current from the common power supply 180 does not flow to the OLED 101 via the drive circuit 102. As a result, a potential drop due to the wiring resistance 198 of the power supply line 192 does not occur, and the voltage Vd having the same magnitude as the reference potential Vc of the common power supply 180 is applied to the input terminal 122 of the drive circuit 102.

Since the forced cutoff switch 106 is also turned off for all other dot circuits 100, the same potential Vd (on the power supply line 192 regardless of the wiring distance from the common power supply 180, as shown by the graph 81 in FIG. = Reference potential Vc).
That is, the input (applied) voltage Vd1 to the input terminal 122 of each drive circuit 102 is either a dot circuit provided at a short (close) position or a dot circuit provided at a long (far) position where the wiring distance from the common power supply 180 is short. , Vd2 ·· Vdn (FIG. 5) are equal to the reference potential Vc (the voltage of the common power supply 180) (OLED reference potential) except for a minute voltage drop due to a negligible leakage current.

As described above, the switch 104 is turned on while the voltage Vd having the same magnitude as the reference potential Vc is applied to the input terminal 122 of the drive circuit 102 during the charge period, whereby the luminance signal SG (voltage Vdac <Vc) is input to one terminal 151 of the holding element 105 through the switch 104.
The other terminal 152 of the holding element 105 is connected to the input terminal 122 of the driving circuit 102 via the power supply line 192, but on the power supply line 192, regardless of the wiring distance from the common power supply 180, the same voltage Vd (= Vc).

  Therefore, the holding element 105 stores a charge corresponding to a voltage Vg that is a difference between the signal voltage Vdac of the luminance signal SG applied to the terminal 151 and the input voltage Vd (= Vc) applied to the terminal 152. Become. This voltage Vg corresponds to the amount of light emission of the OLED 101 indicated by the luminance signal SG, and the accumulated amount of charge becomes an index value indicating the voltage Vg, and the writing of this index value to the holding element 105 is the luminance signal. SG is written to the holding element 105.

  The writing of the luminance signal SG to the holding element 105 is performed in the same manner in the other dot circuits 100. If the voltage Vdac of the luminance signal SG is the same (the same amount of light emission) for each dot circuit 100, the voltage at the input terminal 122 of the dot circuit 100 is the same Vc. As shown, the voltage Vg indicating the difference between the voltage Vc of the input terminal 122 of the drive circuit 102 and the voltage Vdac of the gate terminal 121 is the same in any dot circuit 100 regardless of the wiring distance from the common power supply 180. become.

That is, the luminance signals SG1, SG2,..., Under the same condition that the voltage of the input terminal 122 of the drive circuit 102 serving as a reference for taking the difference from the voltage Vdac of the luminance signal SG is the same for each dot circuit 100. Can be written to the holding element 105.
Writing the luminance signal SG to the holding element 105 means that an amount of electric charge corresponding to the amount of light emission indicated by the luminance signal SG is stored in the holding element 105, so that it is the same for each dot circuit 100. When the luminance signal SG indicating the light emission amount is input, the same amount of charge is accumulated in each holding element 105.

When the charging period ends, each dot circuit 100 moves to a holding period A (standby) shown in FIG. 9, and when the charging period starts, the switch 104 is turned off.
Since the forced cutoff switch 106 remains off even when the hold period A is started, the current from the common power supply 180 does not flow through the OLED 101, and the voltage Vd of the input terminal 122 of the drive circuit 102 does not change from the charge period. (Vd = Vc).

  Further, since the switch 104 is turned off, the gate terminal 121 of the driver circuit 102, that is, the terminal 151 of the holding element 105 is opened, and the applied voltage Vf of the gate terminal 121 (terminal 151 of the holding element 105) is also changed from the charge period. There is no change (Vf = Vdac). As a result, the charge accumulated in the charge period is held in the holding element 105 as it is during the hold period A.

Therefore, as shown in the graphs 81 and 82 in the figure, the hold period A is applied to the input terminal 122 of the drive circuit 102 for each dot circuit 100 regardless of the wiring distance from the common power supply 180, similarly to the charge period. The voltage Vg indicating the difference between the voltage Vc to be applied and the voltage Vf applied to the gate terminal 121 is maintained at the same level.
When the hold period A shifts to the hold period B (light emission period) shown in FIG. 10, for each dot circuit 100, the forcible cut-off switch 106 is turned on with the switch 104 turned off (release of the current cut-off state), and driving. A current corresponding to the voltage Vg of the difference between the voltage at the gate terminal 121 of the circuit 102 and the voltage at the input terminal 122 is output from the output terminal 123 of the drive circuit 102. This current flows through the OLED 101 and the OLED 101 emits light.

In this light emission period, the current from the common power supply 180 flows to the OLED 101 via the power supply line 192 and the drive circuit 102, so that the wiring distance from the common power supply 180, that is, the magnitude of the wiring resistance 198 is different for each dot circuit 100. A difference occurs in the voltage Vd applied to the input terminal 122 of the drive circuit 102 due to the potential drop due to the difference.
Specifically, as shown in the graph 81a of FIG. 8, as the wiring distance from the common power supply 180 becomes longer, the voltage Vd at the input terminal 122 of the drive circuit 102 gradually decreases due to the potential drop. Note that the graph 81a shows an example in which all the OLEDs 101 are all lit to emit light simultaneously based on the luminance signal SG indicating the same light emission amount.

  As the wiring distance from the common power supply 180 becomes longer, the voltage Vd at the input terminal 122 of the drive circuit 102 gradually decreases. As shown in FIG. 7, the dot circuits are 100a, 100b,. Then, at the time of full lighting, the reference potentials Vd1, Vd2,... VdN of the voltage at the input terminal 122 of the drive circuit 102 are the highest as shown in the graph 80 of FIG. 7, and the VdN is the lowest. .

As described above, the voltage Vd at the input terminal 122 of the drive circuit 102 decreases as the wiring distance from the common power supply 180 increases for each dot circuit 100, but it accumulates in the holding element 105 of each dot circuit 100. The amount of charge that is being held is held as it is until the next charge period.
That is, if the voltage Vd of the input terminal 122 of the driver circuit 102 decreases, the potential of the gate terminal 121 of the driver circuit 102 decreases by the voltage Vg corresponding to the amount of charge accumulated in the holding element 105 (the switch 104 is The voltage of the difference between the voltage of the input terminal 122 of the drive circuit 102 and the voltage of the gate terminal 121 is maintained at the original Vg.

This is the same in any dot circuit 100 regardless of the wiring distance from the common power supply 180 in the light emission period Tb, and the voltage Vf of the gate terminal 121 is different from the input voltage Vd to the potential difference Vg as shown in the graph 82a of FIG. As the wiring distance from the common power supply 180 increases, the value gradually decreases.
As described above, the drive circuit 102 is a circuit that outputs from the output terminal 123 a current having a magnitude corresponding to the magnitude of the voltage Vg that is the difference between the voltage at the gate terminal 121 and the voltage at the input terminal 122.

  Therefore, by adopting the configuration of the above embodiment, even if the voltage Vd of the input terminal 122 varies due to a potential drop due to a difference in wiring distance from the common power source 180 for each dot circuit 100, for each dot circuit 100. If the voltage Vg is the same, currents of the same magnitude are supplied to each OLED 101, so that variation in the light emission amount of each OLED 101 due to potential drop due to a difference in wiring distance can be prevented. become.

FIG. 11 is a block diagram illustrating a configuration (comparative example) in which each of the plurality of dot circuits 900 is not provided with a forced cutoff switch.
As shown in the figure, each of the plurality of dot circuits 900 includes an OLED 901, a drive circuit 902, and a hold circuit 903, and the hold circuit 903 includes a switch 904 and a holding element 905. The OLED 901 corresponds to the OLED 101, the drive circuit 902 corresponds to the drive circuit 102, and the hold circuit 903 corresponds to the hold circuit 103.

  Similarly to the above, one DAC 974 corresponds to a plurality of dot circuits 900, and luminance signals SG1, SG2,... Indicating light emission amounts are output from one DAC 974 to each of the plurality of dot circuits 900. In synchronization with this, pulse signals φ1, φ2,... (Not shown) are output from a shift register (not shown), whereby the luminance signal SG is sequentially written in each holding element 905.

  FIG. 12 is a timing chart showing the state of the charging period and the light emitting period of the luminance signal SG by the rolling drive in the configuration of the comparative example. In the figure, in order to distinguish the respective dot circuits 900, the dot circuits are denoted by reference numerals 900a, 900b,... 900N. The circuit 900 is assumed.

As shown in FIG. 7, the charge period of each dot circuit 900 is shifted in time, and the hold period continues after the charge period, which is the same as the timing chart shown in FIG.
However, in the comparative example, since the forced cutoff switch is not provided as described above, the current supply path from the common power source to the OLED 901 of each dot circuit 900 is always formed. For this reason, each dot circuit 900 is in a light emission period regardless of a charge period or a hold period, and a current flows through the OLED 901 during the charge period, that is, during writing of the luminance signal SG to the holding element 905. The current flowing through the OLED 901 during this charging period also causes the variation in the amount of light emission due to the potential drop. This will be specifically described with reference to FIG.

FIG. 13 is a diagram for explaining a variation in the amount of light emission due to a potential drop in the power supply line 920 in the configuration of the comparative example. Here, in the figure, among the N dot circuits 900, the m-th (m is an integer of 2 or more), the (m−1) th, and the (m + 1) -th counted from the leftmost dot circuit. Three dot circuits are shown.
In each dot circuit 900, the hold circuit 903 shown in FIG. 11 is omitted, but for each dot circuit 900, the voltage of the luminance signal SG held in the hold circuit 903 is the drive circuit 902, here the gate terminal of the FET. A voltage corresponding to the difference between the voltage at the gate terminal G and the voltage at the input terminal 931 corresponding to the source flows from the drive circuit 902 to the OLED 901.

  Each dot circuit 900 has a current supply path from the common power supply 950 to the OLED 901 via the power supply line 920 and the drive circuit 902 even during the charge period, which is caused by a potential drop due to the wiring resistance 921 of the power supply line 920. Thus, the voltage applied to the input terminal 931 of the drive circuit 902 differs between the dot circuit 900 (m−1) and the far dot circuit 900 (m + 1) that have a short wiring distance from the common power source 950.

On the other hand, the potential drop hardly occurs on the signal line 930 for transmitting the luminance signal SG output from the DAC 974 for each dot circuit 900.
Therefore, if the luminance signals SG1, SG2,... Indicating the same light emission amount are output from the DAC 974, the charge corresponding to the voltage Vdac of the same luminance signal SG is supplied to the holding element 905 for each dot circuit 900 (FIG. 11). Will be charged.

  For example, in FIG. 13, the voltage at the gate terminal G of each dot circuit 900 is Vdac, and the voltage applied to the input terminal 931 of the drive circuit 902 in the dot circuit 900 (m−1) with the shortest wiring distance from the common power source 950 is Vd ( m−1), the voltage of the difference between the voltage of the input terminal 931 and the voltage of the gate terminal G is Vg (m−1), and the application of the input terminal 931 of the drive circuit 902 in the dot circuit 900 (m + 1) with the longest wiring distance is applied. The voltage is Vd (m + 1), the voltage of the difference between the voltage of the input terminal 931 and the voltage of the gate terminal G is Vg (m + 1), and the voltage applied to the input terminal 931 of the drive circuit 902 of the dot circuit 900m having an intermediate wiring distance is If Vd (m), the voltage of the difference between the voltage at the input terminal 931 and the voltage at the gate terminal G is Vg (m), the following relationship between (Expression 1) and (Expression 2) may occur. That.

Vd (m−1)> Vd (m)> Vd (m + 1) (Formula 1)
Vg (m-1)> Vg (m + 1)> Vg (m + 1) (Formula 2)
That is, even when a luminance signal indicating the same light emission amount is output for each dot circuit due to a potential drop in the power supply line 920, the voltage Vg decreases as the wiring distance from the common power supply 950 increases. .

FIG. 14 is a graph 911 showing the relationship between the wiring distance from the common power source 950 and the potential on the power supply line 920, and the graph 914 showing the relationship between the wiring distance from the common power source 950 and the potential on the signal line 930. It is.
Here, the graph 911 shows an example in which the luminance signals SG1, SG2,... Showing the same light emission amount are output to all the dot circuits 900a, 900b,.

A graph 912 shows an example in which only the OLED 901 of one dot circuit 900m emits light (single point lighting), and a graph 913 shows an example in which the OLED 901 of all dot circuits 900 does not light up (non-extinguishing). Is shown.
As shown in the graph 911, as the wiring distance from the common power supply 950 becomes longer, the potential on the power supply line 920 decreases, and accordingly, the applied voltage Vd of the input terminal 931 of the drive circuit 902, that is, the voltage The reference voltage for determining the magnitude of Vg also decreases.

On the other hand, as shown in the graph 914, the potential on the signal line 930 is substantially constant regardless of the wiring distance from the common power source 950. Therefore, it can be seen from these graphs 911 and 914 that the voltage Vg decreases as the wiring distance from the common power source 950 becomes longer, as shown in the above (Formula 1) and (Formula 2).
Note that in the case of non-lighting as shown in the graph 913, the current from the common power source 950 does not flow to the OLED 901 via the drive circuit 902 in all the dot circuits 900, so that no potential drop occurs.

  Further, as shown in the graph 912, in the case of one-point lighting, the dot circuit 900m is connected between the common power supply 950 and the connection position with the input terminal 931 of the drive circuit 902 of the mth dot circuit 900m on the power supply line 920. A potential drop occurs due to the current flowing in the OLED 901. On the other hand, the portion of the power supply line 920 that is farther from the common power supply 950 than the dot circuit 900m does not cause a potential drop because no current flows through the OLED 901 of each of the (m + 1) th and subsequent dot circuits 900. The applied voltage Vc of the input terminal 931 of the driving circuit 902 is maintained substantially constant.

In addition, although the example in the case of all lighting or one point lighting was shown above, depending on the image to be reproduced, in one main scanning period, for example, the number of OLEDs 901 that should emit light is within a range of 2 or more and less than N. In many cases, the amount of light to be emitted may be different because the density of the reproduced image is different for each OLED 901.
In this case, the potential distribution of the applied voltage Vd is a graph having a shape different from the graphs 911 and 912 shown in FIG.

This means that the magnitude of the potential drop of the power supply line 920 changes due to the combination of the OLEDs 901 that should emit light depending on the difference in the reproduced image.
That is, the configuration in which the current supply path from the common power source 950 to the OLED 901 of each dot circuit 900 is always formed as in the comparative example should emit light not only due to the inherent wiring resistance of the power line 920 but also due to the difference in the reproduced image. Since the combination of the OLEDs 901 is also affected by the change in potential drop, it can be said that the variation in the light emission amount of each OLED 901 easily occurs.

FIG. 15 is a graph showing the presence or absence of a change in luminance of each OLED due to the potential drop of the power supply line in the case of full lighting in the above embodiment and the comparative example, and the solid line graph 915 is an embodiment. A dashed-dotted line graph 916 shows a comparative example.
A graph 916 showing a comparative example shows that the luminance (light emission amount) of each OLED decreases as the distance from the common power source increases. As shown in the graph 911 in FIG. 14, the voltage Vg decreases as the dot circuit 900 has a longer wiring distance from the common power source 950, that is, farther from the common power source 950, among the plurality of dot circuits 900. This is because the current flowing through the OLED 901 is reduced accordingly.

On the other hand, when the graph 915 showing the embodiment is seen, it can be seen that the luminance (light emission amount) of each OLED is substantially constant regardless of the distance from the common power source. As shown in the graphs 81a and 81b in FIG. 10, the voltage Vg is the same for each dot circuit 100, regardless of whether the wiring distance from the common power source 950 is long or short, that is, near or far from the common power source 950.
For this reason, the currents that flow through the OLEDs 101 of the dot circuits 100 are substantially the same, and each OLED 101 can emit light with the same luminance when fully lit.

Further, in the circuit configuration of the embodiment, since the luminance signal SG is written in the charge period other than the light emission period, the potential drop is caused by the combination of the OLEDs that should emit light depending on the reproduction image as in the above comparative example. It will not be affected by changes.
As described above, in the present embodiment, the current from the common power supply 180 is prevented from flowing (cut off) to the OLED 101 during the charging period for each dot circuit 100.

Thus, during the charging period, the drive circuit 102 serving as a reference for taking the difference from the voltage of the luminance signal SG for each dot circuit 100 due to a potential drop due to a difference in wiring distance from the common power supply 180 or the like. A difference does not occur in the voltage Vd of the input terminal 122, and variation in the light emission amount of each OLED 101 can be prevented.
<Embodiment 2>
In the first embodiment, as shown in FIG. 7, the luminance signal SGN is written (charged) to the N-th dot circuit 100N whose output order is last among the luminance signals SG1, SG2,... SGN in one main scanning period. ) Is completed (time t2), the light emission periods for all N dot circuits 100a to 100N are started simultaneously.

  On the other hand, in the second embodiment, the light emission period is started prior to the end of writing of the luminance signal SGN to the Nth dot circuit 100N in accordance with the presence or absence of light emission of the OLED 101. This is different from the first embodiment. Hereinafter, in order to avoid duplication of description, the description of the same contents as those of Embodiment 1 is omitted, and the same components are denoted by the same reference numerals.

FIG. 16 is a diagram illustrating a timing chart of the light-off period and the light emission period in each dot circuit 100 according to the second embodiment.
As shown in the figure, the end of writing of the luminance signal SGN to the Nth dot circuit 100N is time t2, but prior to this, the (N-2) th dot circuit 100 (N-2) is written. When the writing of the luminance signal SG (N-2) is completed (time t4), the forced turn-off signal SV is turned off, and all the forced cutoff switches 106 are turned on (on), and the light emission period starts. For the dot circuit 100 (N-1) and the dot circuit 100N, the luminance signals SG (N-1) and SGN are written (charged) in order after the light emission period starts. That is, in the dot circuit 100 (N-1) and the dot circuit 100N, the control is performed so that the switch 104 is turned on only during the charging period for charging the luminance signal in a state where the forced cutoff switch 106 is closed (on). Is done.

The reason for starting the light emission period (preceding light emission control) without waiting for the end of writing of the luminance signal SGN to the Nth dot circuit 100N in this way is as follows.
That is, in the example shown in the drawing, both the luminance signal SG (N-1) for the dot circuit 100 (N-1) and the luminance signal SGN for the dot circuit 100N are signals indicating that they are turned off (non-light emission) in one main scanning period. ing.

When the dot circuit 100 (N−1) and 100 N are in the off state, no current flows between the source and drain of the drive circuit 102 in each of the dot circuits 100 (N−1) and 100 N. Therefore, the forced cutoff switch 106 is closed during the writing of the signal. Even when turned on, the amount of light emission does not vary due to the potential drop in the power supply line 192.
On the other hand, if the light emission period can be made longer within one main scanning period determined in advance by the apparatus configuration, the exposure time to the peripheral surface of the photosensitive drum 11 in one main scanning period can be made longer.

For example, if the exposure time in one main scanning period can only be short, it is necessary to increase the supply current per unit time for the OLED 101 to cause the OLED 101 to emit light with higher luminance, and the burden on the OLED 101 increases. It becomes easy to affect the life.
On the other hand, if the exposure time in one main scanning period can be made longer as in the second embodiment, it is necessary to form an electrostatic latent image having the same density as compared with the case where the exposure time is short. It is possible to reduce an exposure amount (a light emission amount of the OLED 101) in one exposure.

If the light emission amount (luminance) of the OLED 101 can be reduced, the burden on the OLED 101 can be reduced accordingly, and the life can be extended.
Among the luminance signals SG1, SG2,... SGN in one main scanning period, the output order includes the last luminance signal SGN, and there are two or more consecutive signals indicating non-light emission from the last luminance signal SGN to the output order. A timing at which the forced turn-off signal SV is switched from on to off at the start of writing of the first luminance signal (SG (N-1) in the example in the figure) of the non-light-emitting signal sequence (time t4 in the example in the figure); That is, the start timing of the prior light emission control is set.

The above is an example of a non-light-emitting dot circuit in which two of 100 (N-1) and 100N are continuous among the N dot circuits 100a, 100b,... 100N. The same can be applied to the case.
Specifically, the first, second, and Nth numbers are assigned to the N dot circuits 100 in the order in which the luminance signals SG1, SG2,. , Q (where 1 <Q <N) and subsequent dot circuits 100q to 100N are in a non-light emitting signal sequence and emit no light, the following occurs.

  That is, while the luminance signals SG1, SG2,... SG (Q-1) are sequentially output to the first to (Q-1) th dot circuits 100 in one main scanning period. The dot circuits 100 from the first to the (Q-1) th are in a light extinction period (a cutoff state in which the forced cutoff switch 106 is opened), and the luminance signal SG (Q (Q-1) in the (Q-1) th dot circuit 100 When the writing of (-1) is completed, all the dot circuits 100a to 100N including the first to (Q-1) th shift to the light emission period.

Whether or not a non-emission signal sequence is included in one main scanning period is determined by referring to image data used for exposure in the one main scanning period, that is, the voltages of the luminance signals SG1 to SGN for each main scanning period. To be judged. For example, if there is a voltage other than 0V in the case of no light emission and 0V in the case of light emission, the presence / absence of a signal indicating 0V is determined.
If the luminance signal SG (N−1) output immediately before the last luminance signal SGN is a signal indicating light emission, and the last luminance signal SGN is a signal indicating non-light emission, The start of writing of the luminance signal SGN may be set as the start timing of the preceding light emission control.

  In contrast to the preceding light emission control in the second embodiment, when the control for starting the light emission period after the writing of the last luminance signal SGN in one main scanning period as in the first embodiment is the normal light emission control, the preceding light emission is performed. When executing the control, in order to reduce the light emission amount of each OLED 101 compared to when performing the normal light emission control, for example, a configuration in which the light emission amount indicated by the luminance signals SG1, SG2,.

Specifically, for each main scanning period, when the light emission amount in the light emission period Ta (FIG. 7) in one main scanning period in the normal light emission control is used as a reference value, the light emission in one main scanning period in the preceding light emission control. The period Ta1 (FIG. 16) is longer than Ta.
Therefore, a method is considered in which correction control is performed to uniformly reduce the light emission amounts of the luminance signals SG1, SG2,... For the OLED 101 to emit light by an amount corresponding to the difference ΔTa (= Ta1-Ta) of the light emission period. It is done.

  Table showing data indicating beforehand how much the light emission amount of the OLED 101 can be reduced according to the magnitude of the difference ΔTa in the light emission period to make the exposure amount on the photosensitive drum 11 the same as in the case of the normal light emission control. This can be realized by storing it in a format. A storage unit such as this table is provided in the source IC 73, for example, and after the correction necessary for the luminance signals SG1, SG2,... Luminance signals SG1, SG2,... Are output from each DAC 74.

  As described above, when there is a non-light emitting OLED 101 among the N OLEDs 101 in one main scanning period, for example, the control for taking a longer light emitting period is performed for each sheet S to be conveyed (sheet) width (conveyance). When the direction length orthogonal to the direction (corresponding to the main direction) is different, it can be applied when printing is performed on paper (small size paper) having a paper width (sheet width) smaller than that of large paper (large size paper).

  FIGS. 17 to 19 are diagrams for explaining the control for making the light emission period of the OLED 101 different between large size paper and small size paper. FIG. 17 is a diagram schematically showing the relationship between the paper width, the photosensitive drum 11, and the N OLEDs 101 on the print head 60. FIG. 18 shows the difference in the light emission period between the large size paper and the small size paper. FIG. 19 is a flowchart showing the content of the control for switching the light emission period in accordance with the paper width.

  As shown in FIG. 17, the paper width of the large size paper Sa (maximum paper width: first sheet width) is Wa, and the paper width (second sheet width) of the small size paper Sb is Wb (<Wa). When printing on the paper Sa, the N OLEDs 101a, 101b,... 101N are arranged in the main direction so that an electrostatic latent image having a size corresponding to the maximum paper width Wa can be formed on the photosensitive drum 11 in the main direction. Are arranged in a row.

  When printing on a large size paper Sa, a maximum of N OLEDs 101 are used, and when printing on a small size paper Sb having a paper width shorter than that of the large size paper Sa, the number of N OLEDs 101 is set. Of these, only the OLED 101 corresponding to the paper width Wb of the small size paper Sb is used. For example, if the OLED corresponding to the small size paper Sb is 101a to 101α, the remaining OLEDs from 101β to 101N are not emitting light.

Since non-light emission of the OLED 101 is performed by outputting a signal indicating non-light emission as the luminance signal SG, the luminance signals SGβ to SGN to the OLEDs 101β to 101N for the small size paper are all non-luminous as shown in FIG. A non-light-emission signal sequence indicating light emission is obtained.
When there is a non-emission signal sequence within one main scanning period, when the writing of the first luminance signal of the non-emission signal sequence starts as described above, the forced extinction signal SV is turned on at time t5 in the example of FIG. If the preceding light emission control is started after switching to off, the light emission period Ta2 in one main scanning period can be lengthened accordingly.

  In FIG. 18, regardless of whether large-size paper or small-size paper is used, the length of one main scanning period is the same, and the output timings (cycles) of the luminance signals SG1, SG2,. Since the charging period (light-out period) of the luminance signal SG is the same for each circuit 100, the light emission period in one main scanning period for large size paper is Ta, the light emission period is Tb, and the light emission period in one main scanning period for small size paper is Ta2. Assuming that the extinguishing period is Tb2, it is understood that the relationship of Tb2 <Tb and Ta <Ta2 is satisfied, and that the light emission period in one main scanning period can be made longer for small size paper than for large size paper.

For example, when the small-size paper includes papers having a plurality of different paper widths, the number of luminance signals SG constituting the non-light emitting signal sequence changes for each paper width.
Specifically, if the paper width is medium size paper smaller than the large size paper and larger than the small size paper, the non-light emitting signal sequence when the number of luminance signals SG constituting the non-light emitting signal sequence is the small size paper For example, if the time t6 is the start of writing of the first luminance signal SG in the non-light emitting signal sequence, the light emission period is started at the time t6.

Switching between the normal light emission control and the preceding light emission control is performed by executing the processing shown in the flowchart of FIG. 19 for each print on one sheet S.
As shown in FIG. 19, the paper width is first detected (step S1).
The detection of the paper width is performed by, for example, obtaining the length in the width direction from the paper size (A4 size or the like) detected by a paper size detection sensor (not shown) or the like disposed in the feeding unit 30. Alternatively, the paper width may be extracted and determined from information indicating the paper size selected by the user in the print execution instruction.

It is determined whether or not the detected paper width is equal to a predetermined maximum width (step S2). If it is determined that the width is equal to the maximum width (“YES” in step S2), the control to be executed for each main scanning period is set to the normal light emission control (step S3), and the process is terminated.
On the other hand, if it is determined that it is not equal to the maximum width (“NO” in step S2), the control to be executed for each main scanning period is set to the preceding light emission control (step S4), and the detected paper width is detected. Accordingly, execution of correction control for reducing the light emission amount of each OLED 101 from the reference value is set (step S5), and the process ends.

As described above, the exposure amount necessary for forming the electrostatic latent image on the photosensitive drum 11 by switching between the normal light emission control and the preceding light emission control according to the size of the paper width for each print on one sheet of paper. It is possible to extend the life of the OLED 101 while ensuring the above.
The present invention is not limited to the optical writing device, and may be an optical writing method for writing a light beam on a photosensitive member, for example. The method may be a program executed by a computer. Furthermore, the program according to the present invention can be read by a computer such as a magnetic disk such as a magnetic tape or a flexible disk, an optical recording medium such as a DVD-ROM, DVD-RAM, CD-ROM, CD-R, MO, or PD. It can be recorded on various recording media, and may be produced, transferred, etc. in the form of the recording medium, or in the form of a program, including wired and wireless networks including the Internet, broadcasting, telecommunications lines, In some cases, the data is transmitted and supplied via satellite communication or the like.

(Modification)
As described above, the present invention has been described based on the embodiment. However, the present invention is not limited to the above-described embodiment, and the following modifications may be considered.
(1) In the above embodiment, the drive circuit 102 and the OLED 101 are intermittently switched by switching the open / close of the forced cutoff switch 106 as a cutoff means provided between the drive circuit 102 and the OLED 101 for each dot circuit 100. However, it is not limited to this.

Each dot circuit 100 may be configured to be switchable so that a current is not supplied to the OLED 101 during the extinguishing period and a supply state where current is supplied by releasing the interruption during the light emission period.
FIG. 20 is a diagram illustrating a circuit configuration according to a modification.
As shown in the figure, the circuit according to this modification is not provided with a forced cut-off switch between the drive circuit 102 and the OLED 101 for each dot circuit 100, and the common ground terminal 195 (GND) with the cathode electrode line 194. Is provided with a forced cutoff switch 201, which differs from the circuit configuration according to the embodiment (FIG. 7) in these respects.

  In the circuit according to this modification, the forced cutoff switch 201 is opened by turning on the forced extinction signal SV during the extinguishing period (charging period), and the OLED 101 in all the dot circuits 100 is connected to the ground terminal 195. The cathode electrode line 194 is substantially disconnected from the cathode electrode line 194, and the current from the common power supply 180 does not flow to all the OLEDs 101.

On the other hand, when the forced turn-off signal SV is turned off during the light emission period, the forced cutoff switch 201 is closed and the cutoff is released, so that a current flows through the OLED 101 in all the dot circuits 100.
By adopting the circuit configuration as shown in FIG. 20, variation in the light emission amount of the OLED 101 is prevented for each dot circuit 100, as in the embodiment. In addition, the configuration of the dot circuit 100 can be simplified because it is not a configuration in which one forcible cutoff switch is provided for each of the plurality of dot circuits 100.

(2) In the above embodiment, for each dot circuit 100, the drive circuit 102, the forced cutoff switch 106, and the OLED 101 are arranged in this order from upstream to downstream in the direction in which the current from the common power supply 180 flows. Not limited to. For example, the order of the OLED 101 and the forced cutoff switch 106 can be changed.
(3) In the above embodiment, the configuration example using the drive circuit 102 made of a P-type FET has been described. However, the present invention is not limited to this. For example, a configuration using a drive circuit made of an N-type FET may be used.

FIG. 21 is a diagram illustrating an example of a circuit configuration of the present modification.
As shown in the figure, the dot circuit 100 is arranged in the order of the forced cutoff switch 106, the OLED 101, and the drive circuit 102 from the upstream to the downstream in the direction in which the current from the common power supply 180 flows, and the gate terminal 121 of the drive circuit 102. The output terminal 123 (source) is connected via the holding element 105.

  In this configuration, in one dot circuit 100, during the charging period, the forced cutoff switch 106 is turned off (solid line state) and the switch 104 is turned on (solid line state), and each OLED 101 is disconnected from the power supply line 192. Then, the writing of the luminance signal SG to the holding element 105 is executed in a state where the current from the common power supply 180 does not flow to the OLED 101 and the drive circuit 102.

  On the other hand, during the light emission period Tb, the forced cutoff switch 106 is turned on (broken line state) and the switch 104 is turned off (broken line state), and the current from the common power supply 180 is output to the gate terminal 121 in the drive circuit 102. The current flows through the OLED 101 under the control of a current having a magnitude corresponding to the magnitude of the voltage (source-gate voltage) Vg between the terminals 123 (source), and the OLED 101 emits light.

Even in the case of the circuit configuration described above, variation in the light emission amount of the OLED 101 can be suppressed by turning off (opening) the forced cutoff switch 106 during the charge period.
That is, if the forced cutoff switch 106 is turned on (closed) during the charging period, the current from the common power supply 180 flows to the ground terminal 195 via the OLED 101, the drive circuit 102, and the cathode electrode line 194.

  Each of the dot circuits 100 is connected to the ground terminal 195 by the cathode electrode line 194. However, since the wiring distance from the ground terminal 195 is different, a current flows from the common power source 180 to the cathode electrode line 194 through the OLED 101. When the luminance signal SG is written, the voltage of the output terminal 123 (source) of the drive circuit 102 is connected to the wiring from the ground terminal 195 for each dot circuit 100 under the influence of the potential drop due to the wiring resistance of the cathode electrode line 194. It depends on the length of the distance. In the case of the circuit configuration shown in the figure, the voltage at the output terminal 123 (source) of the drive circuit 102 is a reference voltage for determining a difference from the voltage of the luminance signal SG, that is, a reference voltage for determining the voltage Vg.

If the voltage of the output terminal 123 (source) serving as a reference for determining the voltage Vg is different for each dot circuit 100, even if the luminance signals SG1, SG2,. Thus, the magnitude of the voltage Vg is different for each dot circuit 100, and the light emission amount of the OLED 101 of each dot circuit 100 varies.
Therefore, the forced cut-off switch 106 is turned off (opened) during the charging period so that the current from the power supply line 192 does not flow to the cathode electrode line 194 via each dot circuit 100, so The luminance signal SG can be written in a state where the influence of the potential drop when the current flows through the cathode electrode line 194 is eliminated.

When the driving circuit 102 made of an N-type FET as in this modification is used, the voltage at the output terminal 123 is used as a reference voltage for taking the difference from the voltage of the luminance signal SG, and during the charging period, the driving is performed. A configuration in which the current path upstream of the circuit 102 (on the input terminal 122 side) is interrupted can be employed.
On the other hand, when the drive circuit 102 made of a P-type FET is used as in the embodiment, the voltage at the input terminal 122 is used as a reference voltage for taking the difference from the voltage of the luminance signal SG as shown in FIG. In the charging period, the current path on the downstream side (output terminal 123 side) of the drive circuit 102 in the direction in which the current from the common power supply 180 flows can be cut off.

In any case, by disconnecting the OLED 101 from the power supply line connected to the common power supply 180 during the charge period, the voltage of the common power supply 180 (plus Vc or minus 0 V) is changed to the voltage of the luminance signal SG. It is possible to adopt a circuit configuration that can be used as a reference voltage for taking the difference between the two.
In FIG. 21, for example, the arrangement of the OLED 101 and the drive circuit 102 may be changed.

(4) In the above embodiment, the OLED 101 is formed on the same TFT substrate 71 as the drive circuit 102, the S / H circuit 103, the forced cutoff switch 106, and the like made of thin film transistors (TFTs). A circuit configuration may be adopted.
In addition, the configuration example in which the source IC 73 including the DAC 74 is in charge of the signal output unit that sequentially outputs the luminance signal SG (signal indicating the light emission amount) to the OLED 101 for each of the plurality of OLEDs 101 has been described. However, other circuit configurations may be used.

In addition, a holding element made of a capacitor having an amount of electric charge corresponding to the magnitude of the voltage Vg as a difference between the voltage Vdac of the signal indicating the amount of light emission and the voltage Vd of the input terminal of the driving circuit 102 as an index value indicating the voltage Vg. Although it was set as the structure which inject | pours into 105 and hold | maintains, it is not restricted to this.
Any sample and hold circuit (writing means) that can write and hold an index value corresponding to the voltage Vg in each holding element may be used.

For example, a storage unit such as a RAM is used as the holding element 105, and a value indicating the voltage Vg (for example, information indicating the voltage value) is written and held in the storage unit during the charge period, and is stored in the storage unit during the light emission period. It is also possible to adopt a configuration in which a drive circuit capable of supplying a current corresponding to the magnitude of the voltage Vg indicated by the held information to the OLED 101 is arranged.
In the above description, the example using the OLED 101, which is a current-driven light-emitting element that changes the amount of light emission according to the amount of flowing current (the magnitude of the current), has been described. However, the present invention is not limited to this. A thing, for example, LED etc. can also be used as a light emitting element. In addition, although the configuration example in which the drive circuit 102 as an example of the drive driver is a field effect transistor (FET) has been described, a circuit other than this may be used.

Further, the present invention is not limited to each circuit configuration and each circuit element described above, and a circuit that can be in a cut-off state in which no current flows to the light emitting element of the dot circuit 100 (light emitting unit) during the charging period of the luminance signal SG. Can be applied to.
(5) In the above embodiment, the configuration example in which the optical writing device is used in the printer 1 has been described. However, the present invention is not limited to this. For example, an optical writing device used in an image forming apparatus such as a copying machine or a multifunction peripheral (MFP) having an image carrier such as a photosensitive drum 11 on which an image such as an electrostatic latent image is written by a light beam. Applicable to. In addition, the present invention can be applied to any apparatus other than an image forming apparatus that writes on a photosensitive member or the like with a light beam.

  Further, the contents of the above embodiment and the above modification may be combined as much as possible.

  The present invention can be widely applied to an optical writing device and an image forming apparatus including the same.

1 Printer (image forming device)
11 Photosensitive drum 11 (image carrier)
13 Exposure unit (optical writing device)
50 Control unit 60 Print head 73 Source IC
100 dot circuit 101 OLED (light emitting element)
102 Drive circuit (drive driver)
103 Sample / hold circuit (writing means)
104 switch 105 holding element 106, 201 forced cutoff switch (shut-off means)
109 Shift register 180 Common power supply 192 Power supply line 194 Cathode electrode line 195 Ground terminal 198, 199 Wiring resistance Ta, Ta1, Ta2 Light emission period Tb, Tb2 Light-off period Wa, Wb Paper width

Claims (9)

An optical writing device in which each of a plurality of light emitting elements is connected in parallel via a drive driver to a power line extended from a common power source,
A blocking means for disconnecting each light emitting element from the power line;
A holding element provided corresponding to each of the plurality of light emitting elements;
When power supply to each light emitting element is cut off, each holding element corresponding to each light emitting element has a voltage corresponding to a difference between the voltage corresponding to the amount of light to be emitted and the voltage of the common power supply. Writing means for writing an index value to be indexed;
With
Each drive driver is
When the interruption of the power supply by the interruption means is released, the current supplied from the power supply line is controlled according to the voltage indicated by the index value held in the holding element corresponding to the light emitting element. An optical writing device, wherein the optical writing device is supplied to a light emitting element. The writing means includes
Sequentially writing the index value to each of the plurality of holding elements;
The blocking means is
The power supply is cut off during a writing period from the start of writing to the holding element to which the index value is written first to the end of writing to the holding element to which the index value is written last. The optical writing device according to claim 1. The writing means includes
Sequentially writing the index value to each of the plurality of holding elements;
The blocking means is
When the number of the light emitting elements is N, and each of the N holding elements corresponding to the N light emitting elements is numbered in the order of writing, Q among the first to the Nth (however, When all the light emitting elements corresponding to the 1 <Q <N) and subsequent holding elements are non-light emitting,
The power supply is cut off over a writing period from the start of writing to the holding element to which the index value is written first until the end of writing to the holding element to which the index value is written (Q-1). The optical writing device according to claim 1. The blocking means is
4. The optical writing device according to claim 2, wherein when the writing period ends, the blocking is simultaneously released for the plurality of light emitting elements. The blocking means is
5. The switch according to claim 1, wherein each of the plurality of light emitting elements is a switch provided in each column in a circuit connected in parallel to the power supply line, and opens and closes a path of a current flowing through the column. The optical writing device according to claim 1. The switch
The optical writing device according to claim 5, wherein the optical writing device is provided between the light emitting element and the driving driver. The drive driver is
A P-type or N-type field effect transistor,
The holding element is
A capacitor,
The one end of the capacitor is connected to the gate of the field effect transistor, and the other end of the capacitor is connected to the source of the field effect transistor. Optical writing device. The light emitting element is an organic LED,
The optical writing device according to claim 1, wherein the driving driver and the holding element are formed of thin film transistors. An image forming apparatus that writes an image on an image carrier with a light beam from an optical writing unit,
An image forming apparatus comprising the optical writing device according to claim 1 as the optical writing unit.

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