JP2015097332A - Calibration method of sample/hold circuit, calibration device, and sample/hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement calibration of a sample/hold circuit while further reducing noise and improving analog/digital conversion accuracy.SOLUTION: In an SADC (sub-A/D converter) circuit 102, a threshold value of the SADC circuit 102 is varied by a random variable PN, and an output signal Vout obtained by performing digital conversion on an input signal Vin through a pipelined A/D converter 1 including an MDAC (multiple D/A converter) 110 using SPM (summing point monitoring) is multiplied by the random variable PN. An LUT output value corresponding to a coupling signal obtained by coupling a digital signal Digital1 outputted from an ADC 102a of the SADC circuit 102 and the random variable PN through a coupler 61 is acquired from an LUT 62, the acquired LUT output value is added to a multiplication result of the output signal Vout and the random variable PN and on the basis of an integration result of integrating an addition result as an error signal Verr', a gain of a Gain-AMP 12 included in the MDAC 110 is adjusted.

Description

  The present invention relates to calibration of a sample and hold circuit, and more specifically, a circuit for converting an input signal to output using amplification by an operational amplifier (for example, a pipelined A / D converter or a ΔΣ A / D converter). Further, the present invention relates to a calibration method, a calibration apparatus, and a sample hold circuit of a sample hold circuit and a multiple DAC (MDAC: multiplication digital analog converter) included therein.

An example of the sample and hold circuit is a pipeline A / D converter. As this pipeline type A / D converter 10, for example, a circuit shown in FIG. 20 is known (see, for example, Patent Document 1).
FIG. 20 is a schematic configuration diagram illustrating an example of the pipeline type A / D converter 10.
As shown in FIG. 20, the pipeline type A / D converter 10 includes N-stage unit blocks 100 (1) to 100 (N) cascaded from Stage1 to StageN.

Since the unit blocks 100 (1) to 100 (N) have the same configuration, the configuration of StageI (unit block 100 (I)) will be described here.
As shown in FIG. 20, Stage I includes an SSH (subsample hold) circuit 101, a SADC (sub AD converter) circuit 102, a DAC (D / A converter) circuit 103, and an adder 104. Is done.

The Stage I SSH circuit 101 takes in the analog output signal Residue I-1 output from the previous unit block Stage I-1.
The SADC circuit 102 performs A / D conversion of the analog output signal ResidueI-1 captured by the SSH circuit 101 into a digital signal DigitalI. This digital signal DigitalI is output as an output signal (DigitalI) of StageI. The digital signal DigitalI output from the SADC circuit 102 is added together with the digital signals DigitalI output from the SADC circuits 102 of Stage1 to StageN according to a predetermined rule, and the result represents the result of A / D conversion. Output as a digital output signal.

The DAC circuit 103 generates an analog signal corresponding to the digital signal DigitalI from the SADC circuit 102 and outputs the analog signal to the adder 104.
The adder 104 subtracts the analog signal generated by the DAC circuit 103 from the analog signal captured by the SSH circuit 101, and outputs the analog signal as a subtraction result to the next unit block Stage I + 1 as Residue I as a residual signal. It has become. At this time, the analog signal (Residue I) as a residual signal obtained by subtracting by the adder 104 is amplified by a predetermined factor, so that the required accuracy of the next unit block Stage I + 1 is not increased and the same unit block (Stage I) is amplified. ) A / D conversion is possible depending on the configuration, and high-precision A / D conversion is realized.

Incidentally, the SSH circuit 101, the DAC circuit 103, and the adder 104 are generally configured by a combination of one operational amplifier and a capacitor CAP. A circuit configured by combining the operational amplifier and the capacitor CAP is referred to as a multiple DAC (MDAC: multiplication type digital analog converter) 105.
FIG. 21 is a schematic configuration diagram illustrating an example of the MDAC 105.

  In FIG. 21, (a) shows a circuit configuration in the sample phase (SamplingPhase), and (b) shows a circuit configuration in the hold phase (HoldingPhase). The MDAC 105 realizes the circuit of FIG. 21A in the sample phase and the circuit of FIG. 21B in the hold phase by switching a switch or the like (not shown) according to the converted clock signal CLK. Note that the variable I of CsI in FIG. 21A means Cs constituting StageI.

  As shown in FIG. 21, the MDAC 105 includes a sampling capacitor CsI in which unit capacitors of the same size are combined in parallel, an MDAC-AMP11 formed of an operational amplifier, and a parasitic capacitor Cp existing at the input terminal of the MDAC-AMP11. Is done. The MDAC 105 operates so as to alternately realize the sample phase (FIG. 21A) and the hold phase (FIG. 21B) in accordance with the input conversion clock signal CLK.

  In the sample phase (FIG. 21A), the sampling output CsI is charged with the analog output signal ResidueI-1 of the previous unit block StageI-1. That is, the analog output signal ResidueI-1 is input to one end of the sampling capacitor CsI, and the other end is connected to the inverting input terminal of the MDAC-AMP11. At this time, the input end and output end of the MDAC-AMP 11 are short-circuited to the ground level. The parasitic capacitance Cp is similarly shorted to the ground level.

  On the other hand, in the hold phase (FIG. 21B), the output terminal and the inverting input terminal of the MDAC-AMP 11 are connected via the capacitor Cf. In addition, the capacitor Cr is set to any one of “+ Vr”, “0”, and “−Vr” for each of a plurality of unit capacitors constituting the capacitor Cr according to the digital signal DigitalI output from the SADC circuit 102 of FIG. Connect to. That is, one end of the capacitor Cr is connected to any one of “+ Vr”, “0”, and “−Vr”, and the other end is connected to the inverting input terminal of the MDAC-AMP 11. Each of the capacitor Cf and the capacitor Cr is constituted by a part of a plurality of unit capacitors constituting the sampling capacitor CsI. That is, in the hold phase, the sampling capacitor CsI uses a part of the unit capacitance constituting the sampling capacitor CsI as the capacitance Cf connecting the output terminal and the inverting input terminal of the MDAC-AMP 11 and the remaining unit capacitance as the capacitance Cr. Used. Here, the case where a part of the plurality of unit capacitors constituting the sampling capacitor CsI is used as the capacitor Cf and the capacitor Cr has been described, but the present invention is not limited to this. For example, a plurality of unit capacitors constituting the sampling capacitor CsI may be used as they are as the capacitor Cr, and the capacitor Cf may be provided separately.

  The output of the MDAC-AMP 11 is connected to the sampling capacitor CsI + 1 of the MDAC 105 constituting the unit block StageI + 1 of the next stage, and the output of the MDAC-AMP 11 of Stage I is output to the sampling capacitor CsI + 1 of the next stage as an analog output signal ResidueI. . Further, the non-inverting input terminal of the MDAC-AMP 11 is maintained at the ground level.

At this time, when the DC (direct current) gain of the MDAC-AMP 11 is “a0”, the voltage Va at the inverting input terminal of the MDAC-AMP 11 is expressed by the following equation (1) using the voltage Vout at the output terminal of the MDAC-AMP 11. Can be represented.
Va = − (1 / a0) × Vout (1)

For example, when the voltages connected to the unit capacitors constituting the capacitor Cr are all zero, the following equation (2) is established from the charge conservation law stored in the capacitors in the sample phase and the hold phase.
CsI × Vin
= Cf (Vout-Va) + Cr (0-Va) + Cp (0-Va) (2)

From the expressions (1) and (2), the output Residue I of the MDAC-AMP 11 in the hold phase, that is, the output Vout of the MDAC 105 can be expressed by the following expression (3).
Vout
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))} × Vin
...... (3)

Here, “a0” in the expression (3) represents the DC (direct current) gain of the MDAC-AMP 11 as described above. “F” is called a feedback factor of the MDAC-AMP 11 and can be expressed by the following equation (4) using the respective capacitances Cr, Cf, and Cp.
f = Cf / (Cr + Cf + Cp) (4)

In the transfer function represented by Expression (3), when input / output characteristics are ideal, Expression (3) can be expressed as the following Expression (5).
Vout = (CsI / Cf) × Vin (5)
From formulas (3) and (5), it can be seen that DCGain “a0” of MDAC-AMP11 needs to be large to infinity in order to obtain ideal input / output characteristics.

In practice, DCGain “a0” is increased according to the required accuracy.
In general, in order to increase the DCGain of AMP, it is necessary to make it multistage or cascode. Therefore, it becomes a problem that it is difficult to maintain good stability or the output amplitude is limited.
In order to solve this problem, a method called Summing Point Monitoring (hereinafter referred to as SPM) has been devised as a method of obtaining MDAC-AMP 11 having high gain characteristics without increasing DCGain “a0”.

FIG. 22 is an example of a specific circuit of the multiplying DA converter 105 using the SPM method of FIG.
FIGS. 22A and 22B are examples of specific circuits for realizing the SPM. FIG. 22A shows a circuit configuration in the sample phase, and FIG. 22B shows a circuit configuration in the hold phase.

This circuit corrects an error occurring in the MDAC-AMP 11 by taking out the summing point voltage “−Δs” of the MDAC-AMP 11 in FIG. 22B by the Gain-AMP 12.
FIG. 22C is another example of a specific circuit for realizing the SPM (see, for example, Non-Patent Document 1).
This circuit is a discrete SC (switched capacitor) circuit that samples with the capacitor Ce1 and then transfers with the capacitor Ce2.

JP 2012-60519 A

“A 16-bit 250-MS / s IF Sampling Pipelined ADC With Background Calibration”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010, p. 2602-p. 2612

However, when a new capacitor is added as described above, there is a problem that the characteristics of the entire ADC deteriorate due to noise caused by the newly added capacitor.
Further, in order to keep the MDAC-AMP 11 in a high gain characteristic even when the DCGain “a0” of the MDAC-AMP 11 is low, for example, in the case of the configuration shown in FIG. 22, the Gain-AMP 12 has a high gain. Must have characteristics. However, in practice, there is a problem that such high accuracy cannot be realized due to variations in operating environment and manufacturing process.

  The present invention has been made in view of such a problem, and a sample-and-hold circuit calibration method capable of realizing higher gain characteristics in a sample-and-hold circuit having a relatively low gain characteristic of a DA conversion amplifier. A calibration device and a sample hold circuit are provided.

  In one embodiment of the present invention, the amplitude of an analog signal to be converted is changed by a random variable, and the changed analog signal to be converted is converted into a digital signal by a sample hold circuit (for example, a stage unit 41 shown in FIG. 17). Then, the converted digital signal is multiplied by the random variable, and the analog signal to be converted is A / D converted by a system different from the sample-and-hold circuit into the digital signal after the A / D conversion and the random variable. A digital signal corresponding to the size of the digital signal after the A / D conversion and the value of the random variable is generated, and the digital signal after the conversion by the sample hold circuit and the random variable are generated to the generated digital signal. Are added to each other, and the addition result is integrated, and the integration result is added to the analog signal to be converted as the sample signal. Calibration method of the sample-and-hold circuit, characterized in that the error signal when converted by the hold circuit into a digital signal is.

The sample hold circuit may have an amplifier (for example, Gain-AMP 12 shown in FIG. 17), and the gain of the amplifier may be adjusted based on the error signal.
The amplifier may be a gain amplifier.
The sample and hold circuit includes a multiplying digital-analog converter having an amplifier (for example, MDAC 110 shown in FIG. 17), and adjusts the gain of the amplifier included in the multiplying digital-analog converter based on the error signal. Good.

The gain of the main amplifier among the amplifiers included in the sample and hold circuit may be adjusted based on the error signal.
In another aspect of the present invention, the amplitude is varied by a random variation unit (for example, the multiplier 102c and the computing unit 102d shown in FIG. 17) that varies the amplitude of the analog signal to be converted by a random variable, and the random variation unit. Further, a multiplier (for example, a multiplier 35 shown in FIG. 17) that multiplies the conversion result obtained by converting the analog signal to be converted into a digital signal by a sample and hold circuit by the random variable, and the analog signal to be converted is sampled. Based on the digital signal after A / D conversion that is A / D converted by a system different from the hold circuit and the random variable, the magnitude of the digital signal after the A / D conversion and the value of the random variable are represented. A combining unit (for example, a combiner 61 shown in FIG. 17) that generates a combined signal composed of digital signals, and the combined signal generated by the combining unit. A lookup table (for example, LUT 62 shown in FIG. 17) that generates a digital signal, and an addition unit (for example, FIG. 17) that adds the multiplication result in the multiplication unit and the generation result of the digital signal in the lookup table. A calibration device comprising an adder 63) and an accumulator (for example, accumulator 21 shown in FIG. 17) for accumulating the addition results of the adder.

The sample hold circuit includes an A / D conversion circuit (for example, ADC 12a shown in FIG. 17) that converts the analog signal to be converted into a digital signal, and the coupling unit is an A / D conversion circuit of the sample hold circuit. The combined signal may be generated based on the converted digital signal and the random variable.
In addition to the sample-and-hold circuit, an A / D conversion circuit (for example, a level determination circuit 217 shown in FIG. 15) that converts the analog signal to be converted into a digital signal is included, and the coupling unit includes the A / D conversion The combined signal may be generated based on the digital signal converted by the circuit and the random signal.

The sample hold circuit includes an amplifier (for example, Gain-AMP 12 shown in FIG. 17), and the gain of the amplifier is adjusted based on the integration result by using the integration result of the integration unit as an error signal in the sample hold circuit. An adjustment unit (for example, DAC 23 shown in FIG. 17) may be provided.
The amplifier may be a gain amplifier.

The sample and hold circuit includes a multiplying digital-to-analog converter having an amplifier (for example, MDAC 110 shown in FIG. 17), and the adjusting unit determines the gain of the amplifier included in the multiplying-type digital to analog converter based on the error signal. It may be adjusted.
The adjustment unit may adjust a gain of a main amplifier among amplifiers included in the sample and hold circuit based on the error signal.

  Another aspect of the present invention is a sample and hold circuit including the calibration device according to any one of the above aspects.

  According to one embodiment of the present invention, analog-digital conversion can be performed with higher accuracy without newly adding a capacitor. In particular, since the signals obtained by amplifying the analog signals are integrated only when the input signal has a predetermined amplitude and the calibration is performed using this as an error signal, the calibration can be performed efficiently. Furthermore, since integration is performed only when the analog signal to be converted is within a predetermined error integration region, efficient integration can be performed, and as a result, the calibration time can be shortened.

It is a schematic block diagram which shows an example of a pipeline type A / D converter. It is a conceptual diagram which shows an example of the multiplication type DA converter using SPM. It is a conceptual diagram which shows an example of Gain-AMP. It is a conceptual diagram which shows the other example of Gain-AMP. It is a schematic block diagram which shows an example of the calibration apparatus of a random signal addition system. It is a schematic block diagram which shows an example of the calibration apparatus of a threshold value fluctuation system. It is a conceptual diagram which shows an example of a more detailed structure of the calibration apparatus of a threshold value fluctuation system. It is a figure which shows typically a part of ADC contained in a SADC circuit. It is a figure which shows the transfer function (input / output characteristic) of a SADC circuit when not adding a random signal. It is a figure which shows typically a part of ADC contained in the SADC circuit of Stage1 in the case of 2.5-bit MDAC. It is a figure which shows an example of the transfer function (input / output characteristic) of a SADC circuit in the case of adding a random signal. (A) is a figure which shows an example of the transfer function (input / output characteristic) of Stage1 and Stage2 in the ideal case where there is no Offset in the comparator of the SADC circuit, and (b) is a Stage1 in the case where there is Offset. It is a figure which shows an example of the transfer function (input / output characteristic) of Stage2. It is a conceptual diagram which shows an example of a more detailed structure of the calibration apparatus of a random signal addition system. It is a figure which shows an example of the input signal and transfer function (input / output characteristic) of a SADC circuit when adding a random signal. It is a conceptual diagram which shows an example of the detailed structure which shows the other application example of the calibration apparatus of a random signal addition system. It is a figure which shows an example of the transfer function (input / output characteristic) of Stage1 and Stage2 in the calibration apparatus of the threshold value fluctuation system when there is a general error. It is a conceptual diagram which shows an example of a more detailed structure of the calibration apparatus of the threshold value fluctuation system in this invention. (A) is a diagram showing the transfer function (input / output characteristics) and LUT output value of Stage 1 when the random variable PN = 1 shown in FIG. 17 when the MDAC has a 2.5-bit configuration, and (b), FIG. 18 is a diagram showing a transfer function (input / output characteristics) of Stage 1 and an LUT output value when the random variable PN = −1 shown in FIG. 17 when the MDAC has a 2.5-bit configuration. It is a conceptual diagram which shows an example of a more detailed structure of the calibration apparatus of a random signal addition system. It is a schematic block diagram which shows an example of a pipeline type A / D converter. It is a schematic block diagram which shows an example of a multiplication type DA converter. It is an example of the specific circuit of a multiplication type DA converter.

Embodiments of the present invention will be described below.
In the following description, a pipeline type A / D converter in which each stage has a 2.5 bit configuration will be described as an example. However, the present invention is not limited to this, and may not be 2.5 bit. It does not have to be a / D converter.
FIG. 1 is a conceptual diagram showing an example of a pipelined A / D converter 1 to which a sample and hold circuit calibration method according to the present invention is applied.

The pipeline type A / D converter 1 is different from the pipeline type A / D converter 10 shown in FIG. 20 in that an MDAC 110 is provided instead of the MDAC 105. Components having the same functions as those of the pipeline type A / D converter 10 shown in FIG.
Next, the concept of SPM in the present invention will be described.

FIG. 2 is a schematic configuration diagram illustrating an example of the MDAC 110 using the SPM.
As shown in FIG. 2, the SPM includes a gain amplifier AMP12 which is a gain amplifier for monitoring the voltage Va at the input terminal of the MDAC-AMP 11 called a summing point (summing point) Psum with respect to a normal DAC. There is a feature in the point to use.

  The gain-AMP 12 has an input / output terminal shorted to the ground level in the sample phase, an input terminal connected to the summing point Psum in the hold phase, and an output terminal connected to the sampling capacitor of the MDAC 110 constituting the next stage unit block StageI + 1. Connected to CsI + 1. That is, by alternately repeating the sample phase (FIG. 2A) and the hold phase (FIG. 2B), a signal obtained by amplifying the voltage Va at the summing point Psum by the Gain-AMP 12, that is, (1 / f ′) XVa is stored in the next stage sampling capacitor CsI + 1.

The output Vout (MDAC) of the MDAC-AMP 11 in the MDAC 110 using the SPM shown in FIG. 2 is the same as the output Vout of the MDAC-AMP 11 in the MDAC 105 shown in FIG. ) Expression can be expressed by the following expression (6).
Vout (MDAC)
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))} × Vin
...... (6)

On the other hand, the output Vout (SPM) of the Gain-AMP 12 can be expressed by the following equation (7), where the gain of the Gain-AMP 12 is 1 / f ′.
Vout (SPM)
= (1 / f ') x Va
= -1 / (a0 * f ') * Vout (MDAC) (7)

In the MDAC 110 using the SPM shown in FIG. 2, the difference between the output Vout (MDAC) of the MDAC-AMP 11 and the output Vout (SPM) of the Gain-AMP 12 is the total output of the unit block StageI. Can be expressed by the following equation (8).
Vout
= Vout (MDAC) -Vout (SPM)
= Vout (MDAC) + 1 / (a0 * f ') * Vout (MDAC)
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))}
× {1 + 1 / (a0 × f ′)} × Vin (8)

Here, when “f ′” is equal to “f”, the equation (8) can be expressed as the following equation (9).
Vout = (CsI / Cf) × Vin (9)
From Expression (9), it can be seen that the output Vout of the unit block StageI in the SPM does not depend on the DCGain “a0” of the MDAC-AMP11. That is, it is possible to maintain high gain characteristics even when DCGain “a0” is low.

<Conceptual diagram of Gain-AMP12>
FIG. 3 is a conceptual diagram showing an example of the Gain-AMP 12 constituting the pipeline type A / D converter 1 (FIG. 1) in the present invention.
The pipeline type A / D converter 1 according to the present invention is equipped with the MDAC 110 shown in FIG. 2 as the MDAC for the Stage 1 (100 (1)), and the Gain-AMP 12 shown in FIG. Is used. For Stage2 (100 (2)) to StageN (100 (N)), an MDAC having no Gain-AMP 12 shown in FIG. 21 is mounted.

  That is, in the pipeline type A / D converter 1, DCGain “a0” having the highest Stage1 (100 (1)) is required. Therefore, in the present embodiment, only for Stage 1 (100 (1)), the MDAC 110 shown in FIG. 2 is mounted as the MDAC, and the Gain-AMP shown in FIG. 3 is used as the Gain-AMP 12. The present invention is not limited to this. For all Stage 1 (100 (1)) to Stage N (100 (N)) or any of a plurality of Stages, the MDAC 110 shown in FIG. 2 is mounted as an MDAC, and the Gain-AMP 12 is illustrated. It is also possible to use the Gain-AMP shown in FIG.

In each of the above drawings, the case where the circuit is configured with a single-ended circuit has been described for the sake of simplification of the description, but FIG.
As shown in FIG. 3, the Gain-AMP 12 in the present invention has differential MOS transistors Mx1 and Mx2 composed of N-channel MOS transistors connected to a summing point Psum, and is connected to an output. This is a non-discrete type gain-adjustable gain amplifier that includes transistors My1 and My2 and current sources I1, I2, and I3 of variable current values, and is a capless gain amplifier. The non-discrete type gain amplifier here refers to an amplifier that continuously amplifies an input signal to an output without switching operation.

The MOS transistors Mx1, Mx2, My1, and My2 are composed of MOS transistors having the same functional configuration.
That is, in the Gain-AMP 12, as shown in FIG. 3, the MOS transistors My2 and Mx2 connected in series and the MOS transistors My1 and Mx1 connected in series are connected in parallel between the power supply VDD and the ground GND. Further, a current source I3 is interposed between the MOS transistors Mx1 and Mx2 and the ground GND.

  The connection point between the MOS transistors My1 and Mx1 is one output terminal Pout of the Gain-AMP 12, and the current source I1 is connected in parallel with the MOS transistor My1. Similarly, the connection point of the MOS transistors My2 and Mx2 becomes the other output terminal Nout of the Gain-AMP 12, and the current source I2 is connected in parallel with the MOS transistor My2.

The gate of the MOS transistor Mx2 is connected to one input terminal Pin of the Gain-AMP12, and the gate of the MOS transistor Mx1 is connected to the other input terminal Nin of the Gain-AMP12. These input terminals Pin / Nin correspond to the input terminals of the Gain-AMP 12 in FIG. 2 and are connected to the summing point Psum.
The gates of the MOS transistors My1 and My2 are connected to fixed voltages Vb1 and Vb2 sufficient for the MOS transistors to enter the saturation region, respectively.

Furthermore, the output terminals Pout and Nout correspond to the output terminal of the Gain-AMP 12 in FIG. 2, and are connected to the sampling capacitor CsI + 1 at the next stage.
The gain of the Gain-AMP 12 shown in FIG. 3 can be expressed by the following equation (10), where the mutual conductance of the MOS transistors Mx1 and Mx2 is gmx, and the mutual conductance of the MOS transistors My1 and My2 is gmy, respectively.
1 / f '= gmx / gmy (10)

  The Gain-AMP12 MOS transistors Mx1, Mx2, My1, and My2 are all composed of the same type of MOS transistors and have the same functional configuration. Therefore, the characteristics of Gain-AMP 12 are characterized by being hardly affected by process variations. Note that each of the current sources I1, I2, and I3 can be composed of MOS transistors. In addition, when the current source I3 is configured by a MOS transistor, a simple amplifier connected by three MOS transistors from the power supply voltage of the power supply VDD to the ground GND is configured. It also has the effect that it is difficult to receive such restrictions.

Here, generally, the mutual conductance gm of a MOS transistor is expressed as follows: the size of the MOS transistor is W / L (W is the gate width of the MOS transistor, L is the gate length of the MOS transistor), and the current flowing through the MOS transistor is i. It can represent with following Formula (11). In the equation (11), K is a constant depending on the process.
gm = 2 × {K × (W / L) × i} ^1/2 (11)

  That is, the value of the mutual conductance gm of the MOS transistor is proportional to the 1/2 power of the current i flowing through the MOS transistor. From this, it is possible to change the gain 1 / f ′ of the Gain-AMP 12 by changing the value of the mutual conductance gm by finely adjusting the current values of the current sources I1, I2, and I3. Recognize.

<Conceptual diagram of other example of Gain-AMP12>
In the above embodiment, the case where the Gain-AMP 12 is configured by an N-channel MOS transistor has been described. However, the Gain-AMP 12 may be configured by a P-channel MOS transistor.

FIG. 4 is a conceptual diagram showing another example of Gain-AMP 12 in the present invention.
The Gain-AMP 12 shown in FIG. 4 is connected to the summing point Psum and is composed of P-channel MOS transistors, differential MOS transistors Mx1 and Mx2, MOS transistors My1 and My2 connected to the output, and variable current value. Current sources I1, I2, and I3. The MOS transistors Mx1, Mx2, My1, and My2 are P-channel MOS transistors having the same functional configuration.

That is, as shown in FIG. 4, the Gain-AMP 12 includes MOS transistors Mx2 and My2 connected in series, and MOS transistors Mx1 and My1 connected in series, connected in parallel between the power supply VDD and the ground GND. Further, a current source I3 is interposed between the MOS transistors Mx1 and Mx2 and the power supply VDD.
The connection point between the MOS transistors Mx1 and My1 is one output terminal Pout of the Gain-AMP 12, and the current source I1 is connected in parallel with the MOS transistor My1. Similarly, the connection point of the MOS transistors Mx2 and My2 becomes the other output terminal Nout of the Gain-AMP 12, and the current source I2 is connected in parallel with the MOS transistor My2.

The gate of the MOS transistor Mx2 is connected to one input terminal Pin of the Gain-AMP12, and the gate of the MOS transistor Mx1 is connected to the other input terminal Nin of the Gain-AMP12.
These input terminals Pin / Nin correspond to the input terminals of the Gain-AMP 12 in FIG. 2 and are connected to the summing point Psum.

The gates of the MOS transistors My1 and My2 are connected to fixed voltages Vb3 and Vb4 sufficient for the MOS transistors to enter the saturation region, respectively.
Further, the output terminals Pout and Nout correspond to the output terminal of the Gain-AMP 12 in FIG. 2 and are connected to the next-stage sampling capacitor CsI + 1.
With the above configuration, it is possible to obtain the same operational effects as when the Gain-AMP 12 is configured with an N-channel MOS transistor.
3 and 4, each of the current sources I1 to I3 can be configured by a MOS transistor.

<Calibration device>
Next, a circuit for adjusting the gain 1 / f ′ of the Gain-AMP 12 in the pipeline A / D converter 1 including the MDAC 110 having the Gain-AMP 12 shown in FIG. 3, that is, the pipeline A / D. A calibration apparatus for adjusting the gain of the converter 1 will be described.

<Random signal addition type calibration device>
FIG. 5 is a schematic configuration diagram illustrating an example of a calibration apparatus that performs gain adjustment of the pipelined A / D converter 1 having the Gain-AMP 12. The calibration apparatus shown in FIG. 5 performs calibration by adding a random signal to an input signal Vin. A method of performing calibration by adding a random signal to the input signal Vin in this way is called a random signal addition method.

  In the calibration apparatus using the random signal addition method shown in FIG. 5, the pipeline type A / D converter 1 is stage 1 in the MDAC 110 that constitutes the pipeline type A / D converter 1 shown in FIG. Then, the MDAC shown in FIG. 2 is mounted as the MDAC 110, and the gain-AMP 12 having a simple configuration shown in FIG.

In FIG. 3, the gain “1 / f ′” of the Gain-AMP 12 is different from the reciprocal “1 / f” of the feedback factor of the MDAC 11, and therefore the input / output characteristics of the pipeline type A / D converter 1 are nonlinear. Then, the input / output characteristics in this case can be assumed as shown in the following equation (12).
Vout (ADC) = (1−α) × Vin (ADC) (12)

Α in the equation (12) can be expressed as follows using the gain “1 / f ′” of Gain-AMP 12 and the reciprocal “1 / f” of the feedback factor of MDAC 110.
α = Cf / Cs × (1 / a0) × (1 / f−1 / f ′) (13)

  Here, a random variable PN composed of “1” or “−1” is added to a signal PN × Vcal obtained by multiplying a certain voltage Vcal to the input signal Vin, and the added analog signal Vin (ADC) is added to the pipeline type A / Input to D converter 1. The voltage Vcal may be set based on, for example, a necessary input amplitude and a time required for correction.

Here, although the random variable PN is set to “1” or “−1”, it is not limited to this, and is a value that is changed by a value in the plus direction and the minus direction with reference to 0. Thus, it is sufficient that the average value of the random variables is zero.
After analog-to-digital conversion through the pipeline type A / D converter 1, the digital signal Vout (ADC) corresponding to the analog signal Vin (ADC) output from the pipeline type A / D converter 1 is converted into an input signal Vin. When a digital signal corresponding to the added analog signal (PN × Vcal) is subtracted, the subtraction result, that is, the output Vout can be expressed by the following equation (14).
Vout = Vin−α × (Vin + PN × Vcal) (14)

Here, when the random variable PN used when calculating the analog signal (PN × Vcal) added to the input signal Vin is multiplied by the output Vout represented by the equation (14), as described above, the random variable PN Is “1” or “−1” and PN × PN = 1, and can be expressed by the following equation (15).
PN x Vout
= PN × Vin (1-α) −αVcal (15)

Since PN × Vin obtained by multiplying the input signal Vin by the random variable PN becomes zero when averaged over a long period of time, the equation (15) can be expressed as the equation (16) after all.
PN × Vout = −αVcal (16)
Here, an accumulator 21, an up / down counter (up / dn counter) 22 for detecting a signal PN × Vout (= −α × Vcal = Verr) in the long term, a DAC (D / A converter) 23, , The gain of the Gain-AMP 12 of each MDAC 110 constituting the pipeline type A / D converter 1 is adjusted so that Verr (error signal) becomes zero.

  That is, the accumulator 21 accumulates the input error signal Verr, and the up / down counter 22 can consider that 1 / f ′ is greater than 1 / f from the equation (13) when the accumulated value is smaller than zero. A command signal for reducing the gain of the Gain-AMP 12 is output. On the contrary, when the integrated value in the accumulator 21 is larger than zero, it can be considered that 1 / f ′ is smaller than 1 / f from the equation (13), so that a command signal for increasing the gain of the Gain-AMP 12 is output.

  The DAC 23 adjusts the current values of the current sources I1 to I3 according to the command signal of the up / down counter 22. For example, when 1 / f ′ is decreased, the current amount of the current sources I1, I2 and I3 is decreased, and 1 / f ′ is decreased by decreasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2. Conversely, 1 / f ′ is increased by increasing the current amount of the current sources I1, I2, and I3 and increasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2.

When the gain of Gain-AMP 12 is adjusted as described above, α = 0.
Therefore, if α = 0 is substituted into the equation (14), the equation (14) becomes Vout = Vin. That is, this is equivalent to ideal analog-digital conversion of the input signal Vin.
In the calibration apparatus using the random signal addition method shown in FIG. 5, 31 is a computing unit that multiplies a random variable PN generated by a random signal generation circuit (not shown) and the like, and a preset voltage Vcal, 32 Is the addition result Vin (ADC) obtained by adding the input signal Vin to the pipeline type A / D converter 1 and the calculation result PN × Vcal of the multiplier 31 to the pipeline type A / D converter 1. A multiplier 33 multiplies the negative value (−PN) of the random variable PN generated by the random signal generation circuit and the like with a preset voltage Vcal, and 34 indicates an operation result (−PN) of the multiplier 33. × Vcal) and the output Vout (ADC) of the pipeline A / D converter 1 are added and output as an output Vout, 35 is the random signal This is a multiplier that multiplies the random variable PN generated by the generation circuit or the like and the output Vout output from the adder 34.

In the calibration device of FIG. 5, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 of FIG. 2 may be adjusted. In this case, what is necessary is just to adjust the gain of MDAC-AMP11 in the procedure similar to the case where the gain adjustment of Gain-AMP12 is performed.
As described above, by using the calibration apparatus based on the random signal addition method shown in FIG. 5, the pipeline type A / D converter 1 performs accurate analog-digital conversion without adding a new capacity. Even if the DCgain “a0” of MDAC-AMP11 is low, accurate analog-to-digital conversion can be performed. Therefore, accurate analog-to-digital conversion can be realized while suppressing an increase in noise.

  Further, for example, the gain is adjusted by feeding back the output of the MDAC-AMP 11 to produce the gain “1 / f ′” of the Gain-AMP 12 like the circuit of the multiplying DA converter that realizes the SPM of FIG. Compared to the method, the gain-AMP 12 in this embodiment has a simple circuit configuration as shown in FIG. Therefore, power consumption can be kept small.

  Further, even if the DCgain “a0” of the MDAC-AMP11 is relatively small, the analog-digital conversion can be performed accurately, so that the DCgain “a0” of the MDAC-AMP11 can be kept small. Therefore, the configuration of the MDAC-AMP 11 can be made simple, that is, the power supply voltage can be reduced, so that power consumption can be further suppressed.

  In the calibration apparatus of FIG. 5, the case of adjusting the Gain-AMP 12 of the MDAC 110 included in the Stage 1 of the pipeline A / D converter 1 has been described. When the Stage includes the MDAC 110 having the Gain-AMP 12, the gain of each Gain-AMP 12 may be adjusted in each Stage, and whether or not the Gain-AMP 12 is included is included in each Stage. You may make it adjust the gain of MDAC-AMP11 contained in.

<Threshold variation calibration device>
Next, another example of the calibration apparatus that performs gain adjustment of the pipeline type A / D converter 1 including the Gain-AMP 12 as a calibration apparatus will be described.
FIG. 6 is a schematic configuration diagram illustrating another example of a calibration apparatus that adjusts the gain 1 / f ′ of the Gain-AMP 12 in the pipelined A / D converter 1 including the Gain-AMP 12 illustrated in FIG. 3. It is.

  The calibration apparatus shown in FIG. 6 performs calibration by changing the threshold value of the SADC circuit 102 included in the pipeline type A / D converter 1. A method of performing calibration by changing the threshold value of the SADC circuit 102 in this way is called a threshold value changing method.

As shown in FIG. 6, the calibration device using the threshold variation method does not require the multipliers 31 and 33 and the adders 32 and 34 that are included in the calibration device shown in FIG.
In the case of the calibration apparatus using the random signal addition method shown in FIG. 5, since a random signal irrelevant to the input signal is added and then AD conversion is performed, it is necessary to subtract a signal corresponding to the random signal added from the output signal. On the other hand, in the case of the calibration apparatus based on the threshold value variation method shown in FIG. 6, only the threshold value of the SADC circuit 102 is varied, and no random signal is added, so that a portion for subtracting the random signal is unnecessary. .

  That is, as shown in FIG. 6, the calibration device using the threshold variation method includes a multiplier 35 that multiplies the output Vout output from the pipeline A / D converter 1 and the random variable PN, An accumulator 21 for adding outputs, an up / down counter (up / dn counter) 22 for detecting a signal PN × Vout (= −α × Vcal = Verr) in the long term, and a DAC (D / A converter) 23 The gain of each MDAC 110 constituting the pipeline A / D converter 1 is adjusted so that the error signal Verr (error signal) becomes zero by using the output of the DAC 23.

In FIG. 3, the gain “1 / f ′” of the Gain-AMP 12 is different from the reciprocal “1 / f” of the feedback factor of the MDAC 11, and therefore the input / output characteristics of the pipeline type A / D converter 1 are nonlinear. Then, the input / output characteristics in this case can be assumed as shown in the following equation (17).
Vout = (1−α) × Vin (17)
Α in the equation (17) can be expressed as the following equation (18) using the gain “1 / f ′” of the Gain-AMP 12 and the reciprocal “1 / f” of the feedback factor of the MDAC 110.
α = Cf / Cs × (1 / a0) × (1 / f−1 / f ′) (18)

Here, a signal PN × Vcal obtained by multiplying a random voltage PN consisting of “1” or “−1” by a certain voltage Vcal is added to the output of the ADC in the SADC circuit 102. The voltage Vcal may be set based on, for example, a necessary input amplitude and a time required for correction.
A digital signal Vout corresponding to the analog signal Vin output from the pipeline A / D converter 1 after being converted from analog to digital through the pipeline A / D converter 1 can be expressed by the following equation (19).
Vout = Vin−α × (Vin + PN × Vcal)
= (1-α) Vin−α (PN × Vcal) (19)

Here, when the random variable PN is multiplied by the output Vout represented by the equation (19), as described above, the random variable PN is “1” or “−1” and PN × PN = 1. Can be represented by the following formula (20).
PN x Vout
= PN × Vin (1-α) −αVcal (20)

Since PN × Vin obtained by multiplying the input signal Vin by the random variable PN becomes zero when averaged over a long period of time, the equation (20) can be expressed as the equation (21).
PN × Vout = −αVcal (21)
Here, using the accumulator 21, the up / down counter 22, and the DAC (D / A converter) 23, it is included in the pipeline type A / D converter 1 so that Verr (error signal) becomes zero. The gain of the Gain-AMP 12 of the MDAC 110 to be adjusted is adjusted.

  That is, the accumulator 21 integrates the input error signal Verr, and when the integrated value is smaller than zero, the up / down counter 22 can consider that 1 / f 'is larger than 1 / f, so that the gain of the Gain-AMP 12 is reduced. Command signal to be output. Conversely, when the integrated value in the accumulator 21 is larger than zero, it can be considered that 1 / f ′ is smaller than 1 / f, so that a command signal for increasing the gain of the Gain-AMP 12 is output. The DAC 23 adjusts the current values of the current sources I1 to I3 according to the command signal of the up / down counter 22. For example, when 1 / f ′ is decreased, the current amount of the current sources I1, I2 and I3 is decreased, and 1 / f ′ is decreased by decreasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2. Conversely, 1 / f ′ is increased by increasing the current amount of the current sources I1, I2, and I3 and increasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2.

When the gain of Gain-AMP 12 is adjusted as described above, α = 0.
Therefore, if α = 0 is substituted into the equation (19), the equation (19) becomes Vout = Vin. That is, this is equivalent to ideal analog-digital conversion of the input signal Vin.
In FIG. 6, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 in FIG. 2 may be adjusted by the same procedure as described above.

  Also in this case, when the pipeline type A / D converter 1 includes not only the Stage 1 but also other stages including the MDAC 110 having the Gain-AMP 12, the gain of each Gain-AMP 12 is adjusted in each Stage. The gain of the MDAC-AMP 11 included in each stage may be adjusted regardless of whether the Gain-AMP 12 is included or not.

<Detailed configuration diagram showing an example of a calibration apparatus using a threshold variation method>
Next, a detailed configuration of the calibration apparatus using the threshold variation method will be described.
FIG. 7 shows a detailed configuration of a calibration apparatus based on a threshold variation method that performs adjustment using the calibration method that varies the threshold of the SADC circuit 102 described in FIG. 6. In the case of performing background calibration, FIG. It is a block diagram which shows an example of a calibration apparatus.

  As shown in FIG. 7, the pipeline A / D converter 1 includes a stage unit 41 including Stage I (for example, Stage 1 (unit block 100 (1))), and units from Stage I + 1 to Stage N (for example, Stage 2 to Stage N). Backend ADC 42 including blocks 100 (2) to 100 (N)).

The stage unit 41 includes an MDAC 110 and a SADC circuit 102.
The SADC circuit 102 includes an ADC 102a and a DAC 102b to which the input signal Vin is input, and further includes a multiplier 102c that multiplies the voltage Vcal and the random variable PN, an output of the ADC 102a, and an output of the multiplier 102c. And an arithmetic unit 102d for adding.

Then, as described above, the calibration apparatus shown in FIG. 7 performs calibration by changing the threshold of the SADC circuit 102 and changing the input / output function.
The MDAC 110 has the same configuration as the MDAC 110 shown in FIG.
Further, the output signal Vout obtained as a result of processing the input signal Vin by the stage unit 41 and the Backend ADC 42, that is, the output signal Vout which is a conversion result obtained by A / D converting the input signal Vin, and the random variable PN are multiplied by the multiplier 35. And the calculation result in the multiplier 35 is used as an error signal Verr. Then, the error signal Verr is integrated by the accumulator 21, and the up / down counter 22 outputs a command signal depending on whether the integrated value is smaller than zero, that is, 1 / f 'can be regarded as larger than 1 / f. In response to the command signal from the up / down counter 22, the DAC 23 adjusts the current values of the current sources I1 to I3 of the Gain-AMP 12.

Here, the method of performing calibration by changing the threshold value of the SADC circuit 102 has an advantage that a high Feedback Gain can be obtained because a capacitor (CAP) for inserting a Dither signal is not added.
Also, in this method, an error generated by AD conversion is extracted on the assumption that a signal obtained by superimposing a Dither signal on an input signal is accumulated for a long period, and an optimum value is searched by feeding back this error.

  In FIG. 7, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 may be adjusted, and the capacitance value of sampling capacitor CsI may be adjusted. You can do it.

<Comparison with conventional calibration method>
Here, as in this embodiment, a method for adjusting the gain of the pipelined A / D converter 1 by adding a random signal to the input signal Vin or changing the threshold value of the SADC circuit 102. In order to clarify the difference from the conventional calibration method, a case where gain adjustment is performed without using a conventional random signal will be described.

FIG. 8 is a diagram schematically showing a part of the ADC 102a included in the SADC circuit 102 of Stage 1 when the MDAC 110 shown in FIG. 7 is a 2.5-bit MDAC, for example, and when a conventional calibration method is used. 2 shows a part of the ADC included in the SADC circuit 102.
A SADC circuit (hereinafter referred to as a conventional SADC circuit) in the case of using a conventional calibration method includes comparators 151 to 156 as shown in FIG.

  The comparators 151 to 156 include the input signal Vin and the reference voltages (5/8) · Vr, (3/8) · Vr, (1/8) · Vr, (−1/8) · Vr, (−3/8). ) · Vr and (−5/8) · Vr. Vr is the maximum input range of the input signal Vin.

FIG. 9 is a diagram illustrating a transfer function (input / output characteristics) of a conventional SADC circuit that does not add a random signal. In FIG. 9, the horizontal axis is input, and the vertical axis is output. Further, a value indicated by “Δ” in FIG. 9 represents a threshold value of a conventional SADC circuit that does not add a random signal.
As shown in FIG. 9, in the case of a conventional SADC circuit that does not add a random signal, the value of the reference voltage to be compared does not change, so that an output signal with a transfer function adapted to the input signal is output.

Next, a case where random signals are added in the SADC circuit 102 as in this embodiment will be described.
FIG. 10 is a diagram schematically illustrating a part of the ADC included in the SADC circuit 102 of Stage 1 illustrated in FIG. 7 when the MDAC 110 is a 2.5-bit MDAC.
The SADC circuit 102 includes comparators 161 to 168.

  The comparators 161 to 168 exchange voltages to be compared with random signals. That is, when the random variable PN = 1, the input signal Vin and the reference voltages (15/16) · Vr, (11/16) · Vr, (7/16) · Vr, (3/16) · Vr, ( −1/16) · Vr, (−5/16) · Vr, (−9/16) · Vr, and (−13/16) · Vr. On the other hand, when the random variable PN = −1, the input signal Vin and the reference voltages (13/16) · Vr, (9/16) · Vr, (5/16) · Vr, (1/16) · Vr, (−3/16) · Vr, (−7/16) · Vr, (−11/16) · Vr, and (−15/16) · Vr are respectively compared. Vr is the maximum input range of the input signal Vin.

FIG. 11 is a diagram illustrating a transfer function (input / output characteristics) of the SADC circuit 102 in the present embodiment, in which the random variable PN is added. In FIG. 11, the horizontal axis represents the input to the SADC circuit 102, and the vertical axis represents the output. Further, the value indicated by “Δ” in FIG. 11 represents the threshold value of the SADC circuit 102 to which the random variable PN is added.
In FIG. 11, the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = 1, and the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = −1. Is also written.

When an input signal as in Example 1 enters from the input side, the output signal changes depending on the value of the random variable PN. For example, when PN = 1, the transfer function of the SADC circuit 102 when adding the random variable PN = 1 is applied, and the input signal of Example 1 becomes an output signal (PN = 1) according to Example 1. When PN = −1, the transfer function of the SADC circuit 102 when adding the random variable PN = −1 is applied, and the input signal of Example 1 becomes the output signal (PN = −1) according to Example 1. As a result, as shown in FIG. 11, the output result varies depending on the random variable PN.
In this case, since the output changes even with the same input depending on the random variable PN, if it is added over a long period, an error component remains as a result.

  On the other hand, when an input signal such as Example 2 is input from the input side, the output signal is not changed by the random variable PN. For example, when PN = 1, the transfer function of the SADC circuit 102 when adding the random variable PN = 1 is applied. When PN = −1, the transfer function of the SADC circuit 102 when adding the random variable PN = −1. Although the function is applied, since both transfer functions are the same, the input signal of Example 2 is an output signal (PN = 1 / −1) according to Example 2.

In this case, even if the random variable PN fluctuates, the output is always the same, so even if added for a long time, it is canceled out and no error remains.
By the way, whether or not errors are integrated, the accumulator 21 integrates all output signals.
Therefore, in order to shorten the calibration time, it is necessary to make the integration time of the accumulator 21 efficient, and as described above, the error signal in the multiplier 35 becomes zero by the input signal Vin. Since there are cases where the error signal does not become zero, a region that the input signal Vin can take when the error signal does not become zero is set as an error integration region, and it is determined whether or not the input signal Vin is a value within the error integration region. Perform efficient integration.

<Description of calibration method using threshold fluctuation method>
Next, a calibration method using a threshold variation method will be described.
In the present embodiment, for example, the back-end ADC 42 shown in FIG. 7 is used to distinguish the input signal Vin into a region (time) in which the error signal is integrated and a region (time) in which the error signal is not integrated, The error signal is integrated by the accumulator 21 only when the value of the area where the error signal is integrated, that is, the value within the error integration area.

  The accumulator 21 may simply hold the previous integration result when the input signal Vin is a value in a region (time) in which the error signal is not integrated, or may add “0” to the previous integration result. Alternatively, both ends of the accumulator 21 may be bypassed.

  FIG. 12A shows the transfer functions (input / output characteristics) of Stage 1 and Stage 2 in the ideal case where there is no offset in the comparators 161 to 168 of the SADC circuit 102 that adds the random variable PN shown in FIG. It is. In the diagram showing the transfer function of Stage 1 (the diagram on the left side of FIG. 12A), the horizontal axis represents the input to the SADC circuit 102, the vertical axis represents the output, and the value indicated by “Δ” on the horizontal axis is This represents the threshold value of the SADC circuit 102 of Stage1. The solid line represents the transfer characteristic when PN = 1, and the alternate long and short dash line represents the transfer characteristic when PN = -1.

  In the diagram showing the transfer function of Stage 2 (the diagram on the right side of FIG. 12A), the horizontal axis represents the output of the SADC circuit 102 of Stage 2, the vertical axis represents the input of the SADC circuit 102 of Stage 2, and the vertical axis The value indicated by “Δ” indicates the threshold value of the SADC circuit 102 of Stage2. Further, for each of the cases of PN = 1 and PN = −1, the input signal to the SADC circuit 102 and each segment seg. 0 to seg. 7 is represented.

  In FIG. 12A, the region not affected by the random variable PN corresponds to (−1/4) · Vr to (1/4) · Vr of Stage 2 input (= Output of Stage 1). A determination circuit (not shown) determines that this area is an error integrated area (time), and distinguishes an error integrated area (time) from an unintegrated area (time). Only the accumulator 21 is integrated.

As described above, since only the areas where errors are integrated are integrated, it is not necessary to integrate as much as possible the input signals unnecessary for error integration, and the integration ratio of the error signals that are relatively necessary increases. That is, since the ratio of error components in the integrated signal increases, it is easy to extract error components even if the integration time is relatively short.
Here, the stage 2 input (= stage 1 output) is (−1/4) · Vr to (1/4) · Vr as shown in FIG. 12 (a) when the input signal inputted to Stage2 is In each segment divided into a plurality of segments, segment Seg. 3 and segment Seg. 2 when the output is 0 or more, the segment Seg. 4 when the output is 0 or less.

  Whether the output is 0 or more or 0 or less can be determined from the AD conversion result of the back-end ADC 42, and the accumulator 21 does not perform integration if it corresponds to these. As described above, instead of adding a new determination circuit, the AD conversion result in the back-end ADC 42 can be used for the determination.

  FIG. 12B is a diagram illustrating transfer functions (input / output characteristics) of Stage 1 and Stage 2 when the comparator of the SADC circuit 102 has Offset. In the diagram showing the transfer function of Stage 1 (the diagram on the left side of FIG. 12B), the horizontal axis represents the input to the SADC circuit 102, the vertical axis represents the output, and the value indicated by “Δ” on the horizontal axis is: This represents the threshold value of the SADC circuit 102 of Stage1. The solid line represents the transfer characteristic when PN = 1, and the alternate long and short dash line represents the transfer characteristic when PN = -1. In the diagram showing the transfer function of Stage 2 (the diagram on the right side of FIG. 12B), the horizontal axis represents the output of the SADC circuit 102 of Stage 2, and the vertical axis represents the input of the SADC circuit 102 of Stage 2. The value indicated by “Δ” on the vertical axis represents the threshold value of the SADC circuit 102 of Stage2.

  As shown in FIG. 12B, when the offsets are present in the comparators 161 to 168 of the SADC circuit 102, the area to be integrated is widened for the back-end ADC 42. Therefore, it is preferable to determine a region where error signals are not integrated in consideration of the offset of the comparator of the SADC circuit 102. For example, assuming that Offset is (1/32) · Vr, the area where the error signal is not integrated becomes 1/8 of the entire back-end ADC 42, and the time reduction effect is expected.

<Detailed configuration diagram showing an example of a calibration apparatus using a random signal addition method>
Next, a detailed configuration of the calibration apparatus using the random signal addition method will be described.
FIG. 13 is a conceptual diagram of a detailed configuration showing an example of a calibration apparatus using a random signal addition method that adds a random signal to the input signal described in FIG.
Compared with the calibration apparatus based on the threshold value variation system shown in FIG. 7, the calibration apparatus based on the random signal addition system shown in FIG. 13 further includes multipliers 31 and 33, an adder 34, and addition for adding random signals. The place provided with the capacity as the container 32 is different. Components having the same functions as those of the calibration apparatus shown in FIG.

As shown in FIG. 13, the pipeline A / D converter 1 includes a stage unit 51 including Stage I (for example, Stage 1 (unit block 100 (1))) and a unit from Stage I + 1 to Stage N (for example, Stage 2 to Stage N). Backend ADC 52 including blocks (100 (2) to 100 (N)).
The stage unit 51 includes an MDAC 110 and a SADC circuit 102 ′, a multiplier 31 that multiplies the voltage Vcal and the random variable PN, and an addition for adding the multiplication result of the multiplier 31 to the input signal Vin. And the capacity of the container 32.

The SADC circuit 102 ′ includes an ADC 102a and a DAC 102b to which the input signal Vin is input.
The calibration apparatus shown in FIG. 13 adds a random signal to the input signal Vin, and performs calibration by changing the amplitude of the input signal Vin.
The MDAC 110 has the same configuration as the MDAC 110 shown in FIG.

  Further, an output signal Vout (ADC) obtained as a result of processing the input signal Vin by the stage unit 51 and the Backend ADC 52, that is, the calculation result of the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN”, that is, An output signal Vout (ADC), which is a result of A / D conversion of a signal obtained by adding a random signal to the input signal Vin, is added by an adder 34, and an output which is a digital signal obtained by A / D converting the input signal Vin. A signal Vout is obtained. Then, the multiplier 35 multiplies the output signal Vout and the random variable PN. The calculation result in the multiplier 35 is used as an error signal Verr, and the error signal Verr is integrated by the accumulator 21. In the up / down counter 22, the integrated value is smaller than zero, that is, 1 / f ′ is larger than 1 / f. A command signal is output to the DAC 23 according to whether it can be considered, and the DAC 23 adjusts the current values of the current sources I1 to I3 of the Gain-AMP 12 according to the command signal of the up / down counter 22.

In FIG. 13, the addition of the analog unit is realized by charging the capacitor as the adder 32 with a voltage of (Vcal × PN). However, the present invention is not limited to this. A vessel may be used.
Further, instead of the voltage Vcal, the reference voltage Vr used in the comparator of the ADC 102a included in the SADC circuit 102 ′ can be used, and the ratio can be realized by the ratio with the capacitance (CAP) CsI connected to the input terminal of the input signal Vin. For example, when Vcal = (1/4) · Vr, instead of setting the voltage Vcal in FIG. 13 to (1/4) · Vr, Vcal may be set to Vr and the CAP ratio may be set to 1: 4. .

In FIG. 13, the gain of Gain-AMP 12 is adjusted. However, the gain is not limited to this. For example, the gain of MDAC-AMP 11 may be adjusted.
FIG. 14 is a diagram showing an input signal and a transfer function (input / output characteristics) of the SADC circuit 102 ′ when the random variable PN is added to the input signal Vin in the random signal addition type calibration apparatus of FIG. is there. In FIG. 14, the horizontal axis represents the input signal to the SADC circuit 102 ', and the vertical axis represents the output.

In FIG. 14, the input signal when adding the random variable PN = 1 and the input signal when adding the random variable PN = −1 are shown together. Note that the position indicated by “Δ” in FIG. 14 represents the threshold value of the SADC circuit 102, and the transfer function is the same and the threshold value is the same when PN = 1 and PN = −1.
Even if the transfer function is the same, if the output varies depending on the random variable PN, an error component remains as a result if they are added over a long period of time.

On the other hand, even if the random variable PN fluctuates, if the output is the same, even if it is added over a long period, it is canceled out and no error remains.
In the calibration apparatus shown in FIG. 13, similarly to the calibration apparatus shown in FIG. 7, an area (time) in which error signals are integrated by using the back-end ADC 52 and an area in which error signals are not integrated. By distinguishing from (time) and accumulating only the area where error signals are accumulated by the accumulator 21, the calibration time can be shortened.

  As described above, according to the present invention, even when the circuit for extracting the voltage at the summing point Psum is realized by the gain-AMP 12 having a simple configuration, a high-accuracy gain is realized regardless of variations in the operating environment and the manufacturing process. it can.

<Configuration diagram showing another application example of calibration apparatus using random signal system>
Next, another application example of the calibration apparatus will be described.
FIG. 15 is a detailed configuration diagram illustrating another application example of the calibration apparatus using the random signal addition method.
The calibration apparatus shown in FIG. 15 performs gain adjustment in the sample hold circuit of the A / D converter, not in the pipeline type A / D converter. In FIG. 15, the input described in FIG. Calibration is performed by adding a random signal to the signal Vin.

  That is, the calibration apparatus shown in FIG. 15 uses an ADC (A / D converter 1) instead of the pipeline A / D converter 1 including the stage unit 51 including Stage 1 and the Backend ADC 52 including Stages thereafter. / D converter) 212 is for adjusting the gain of the sample hold circuit 211. This calibration apparatus is further provided with a level determination circuit 217 in the calibration apparatus shown in FIG.

Note that components having the same functions as those of the calibration apparatus shown in FIG. 13 are denoted by the same reference numerals and description thereof is omitted.
FIG. 15 is a block diagram illustrating an example of a calibration device for performing background calibration on the sample hold circuit 211.
As shown in FIG. 15, the sample hold circuit 211 includes an AMP 221, a gain-AMP 12, a capacitor 222 that connects the output terminal and the inverting input terminal of the AMP 221, one end connected to the input terminal of the input signal Vin, and the other end. Includes a sampling capacitor 223 connected to the inverting input terminal of the AMP 221 and the input terminal of the Gain-AMP 12, and further, a capacity as a multiplier 31 and an adder 32 that multiplies the voltage Vcal and the random variable PN. And comprising. A capacitor 213 for connecting the sample hold circuit 211 and the ADC 212 is connected between the output terminal of the AMP 221 and the output terminal of the Gain-AMP 12.

The calibration apparatus illustrated in FIG. 15 includes a multiplier 33 that multiplies the voltage Vcal and the random variable “−PN” after the ADC 212, and an addition that adds the output Vout (ADC) of the ADC 212 and the output of the multiplier 33. Instrument 34.
Then, the output from the ADC 212 is added to the calculation result of the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN” by the adder 34 to obtain an output signal Vout that is a digital signal of the input signal Vin. The output signal Vout and the random variable PN are multiplied by the multiplier 35, and the calculation result is integrated by the accumulator 21 as the error signal Verr. The up / down counter 22 outputs a command signal to the DAC 23 according to whether the integrated value is smaller than zero, that is, 1 / f ′ can be regarded as larger than 1 / f. The current values of the current sources I1 to I3 of the Gain-AMP 12 are adjusted according to the command signal.

In FIG. 15, the gain of Gain-AMP 12 is adjusted. However, the gain is not limited to this. For example, the gain of AMP 221 of sample hold circuit 211 may be adjusted, or a capacitor included in sample hold circuit 211 may be used. It is also possible to adjust.
Further, the level determination circuit 217 is configured by, for example, an ADC, and distinguishes between a region (time) in which error signals are integrated and a region (time) in which error signals are not integrated, similarly to the back-end ADC 52 in FIG.

If the input signal Vin corresponds to a region (time) in which the error signal is not integrated from the determination result of the level determination circuit 217, the accumulator 21 does not integrate.
In this way, the calibration apparatus shown in FIG. 15 also uses the level determination circuit 217 and the area (time) where error signals are integrated and the area (time) where integration is not performed, similarly to the calibration apparatus shown in FIG. And the accumulator 21 accumulates only the area where the error signal is accumulated, so that the calibration time can be shortened.
As described above, even when applied to the sample-and-hold circuit 211, a high-accuracy gain can be realized regardless of variations in operating environment and manufacturing process.

<Improvement of calibration method>
<Examination of improved error insertion method for all input ranges>
The present inventor further studied improvements on the above-described calibration method.
That is, in the calibration method by the calibration apparatus using the threshold fluctuation method shown in FIG. 7 described above, as shown in FIG. 12A, errors are integrated regardless of the voltage input at any voltage in the entire input range. It is constituted so that.
FIG. 16 shows an example of the transfer function (input / output characteristics) of the calibration device using the threshold variation method when there is a general error, and the characteristic line L1 in the figure is the actual transfer function when there is an error. (Input / output characteristics). The characteristic line L2 is a transfer function (input / output characteristics) when there is no error. The solid line represents the transfer function when PN = 1, and the broken line represents the transfer function when PN = -1.

In FIG. 16, for example, when the input signal is Example 3, the error signal to be extracted is a voltage corresponding to the error (Example 3) shown in the figure. When the input signal is Example 4, the error signal to be extracted is a voltage corresponding to the error (Example 4) shown in the figure. That is, it can be seen that the error amount is constant regardless of the input signal when the output signal has the same voltage. On the other hand, the signal accumulated by the accumulator 21 can be expressed by the following equation.
(Error amount to be integrated) = Σ [(Error signal) / (Input signal)]

  For this reason, when errors are accumulated over the entire input range, when the input signal is large, the signal that can be accumulated by the accumulator 21 is relative even though the magnitude of the error signal is the same as when the input signal is small. Will become smaller. If the signal accumulated by the accumulator 21 becomes smaller, the accumulated time must be lengthened accordingly.

<Circuit configuration / transfer function configuration diagram of calibration device for shortening calibration time>
<Improvement of calibration method by threshold fluctuation method>
In view of the above, a more efficient calibration method will be described below.
FIG. 17 is a detailed configuration diagram showing an example of a calibration apparatus using a threshold variation method that performs adjustment using the calibration method for varying the threshold of the SADC circuit 102 described in FIG. 2 is an example of a calibration device for realizing the calibration.

The calibration device using the threshold variation method according to the present invention illustrated in FIG. 17 is compared with the digital signal Digital1 that is the calculation result of the ADC 102a of the SADC circuit 102, as compared with the calibration device using the general threshold variation method illustrated in FIG. A coupler 61 that couples the random variable PN, a LookUpTable (hereinafter referred to as LUT) 62 that changes an output value according to the value of the operation result of the coupler 61, and an adder 63. Is different. The adder 63 outputs the output signal Vout, that is, the output signal Vout, which is a digital signal obtained by A / D-converting the input signal Vin, obtained as a result of processing the input signal Vin in the stage unit 41 and the Backend ADC 42, and the random variable PN. The output of the LUT 62 is added to the error signal Verr multiplied by the multiplier 35. In FIG. 17, components having the same functions as those of the calibration apparatus shown in FIG. Is omitted.

As shown in FIG. 17, the pipeline type A / D converter 1 includes a stage unit 41 including Stage I (for example, Stage 1 (unit block 100 (1))), and unit blocks from Stage I + 1 to Stage N (for example, Stage 2 to Stage N). Backing ADC42 including (100 (2) to 100 (N))).
The stage unit 41 includes an MDAC 110 and a SADC circuit 102.

  The SADC circuit 102 includes an ADC 102a and a DAC 102b to which the input signal Vin is input, a multiplier 102c that multiplies the voltage Vcal and the random variable PN, an arithmetic unit 102d that adds the output of the ADC 102a and the output of the multiplier 102c, Is included. The multiplier 102c and the computing unit 102d correspond to a random variation unit. The MDAC 110 has the same configuration as the MDAC 110 shown in FIG.

Also, the output signal Vout, which is a digital signal of the input signal Vin, obtained as a result of processing the input signal Vin by the stage unit 41 and the Backing ADC 42 is multiplied by the random variable PN, and an error signal Verr is obtained.
On the other hand, the output result of the ADC 102a and the result of the random signal PN are combined by a combiner 61, and a digital value is output from a LUT (LookUpTable) 62 prepared in advance according to this value. This result is added to the error signal Verr previously calculated by the adder 63, and the addition result is integrated by the accumulator 21, and the up / down counter 22 determines whether the integrated value is smaller than zero, that is, 1 / f 'is A command signal is output to the DAC 23 according to whether it can be regarded as greater than 1 / f, and the DAC 23 adjusts the current values of the current sources I1 to I3 of the Gain-AMP 12 according to the command signal of the up / down counter 22. . The accumulator 21 integrates over the entire input range, but it is more efficient by adding the LUT output prepared in advance with the added LUT 62 and the error signal Verr, and subtracting the equivalent of the input signal Vin unnecessary for error integration. Integration is possible.

In FIG. 17, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 may be adjusted.
The combiner 61 is, for example, a predetermined bit, for example, an x-bit digital signal (for example, “010” representing “0”) output from the ADC 102 a and the value of the random signal PN (that is, 1 or −1). And a y-bit digital signal representing the random signal PN as a high-order bit, and an x-bit bit string representing a digital value output from the ADC 102a as a low-order bit. For example, when the bit string of x bits is “010” and the bit string representing the random signal PN = 1 is “1”, the combined signal is “1010”, and the bit string representing the random signal PN = −1 is “−1”. The combined signal is “−1010”.

In the LUT 62, an LUT output value corresponding to the input signal Vin corresponding to the digital signal output from the ADC 102a and the random signal PN is set in association with the combined signal generated by the combiner 61. The LUT 62 receives the combined signal from the combiner 61 and outputs it as an LUT output value corresponding to the input combined signal.
For example, when the x-bit bit string output from the ADC 102a is “010” representing “0”, the y-bit bit string is “1” representing the random signal PN = 1, and the combined signal is “1010” The LUT output value is a digital value representing “0” as shown in FIG.

For example, when the digital value output from the ADC 102a is an x-bit bit string representing “(3/4) Vr” and the random signal PN is a y-bit bit string representing PN = −1, The LUT output value is a digital value representing “(−3/4) Vr” as shown in FIG.
18A and 18B show the transfer function of Stage 1 when the random variable PN shown in FIG. 17 is PN = 1 and PN = −1 when the MDAC 110 shown in FIG. 17 has a 2.5-bit configuration. And an output result of the LUT 62 (hereinafter also referred to as an LUT output value). In the characteristic diagram showing the transfer function, the horizontal axis represents input and the vertical axis represents output. In the lower part of the horizontal axis, the value indicated by “Δ” represents the threshold value of the SADC circuit 102. In addition, Seg. 0 to 7 represent Segments obtained by dividing the input signal input to Stage1 into a plurality of parts.

The LUT output value varies depending on the sign of the random variable PN and the calculation result of the ADC included in the SADC circuit 102 shown in FIG.
The method of determining the LUT output value corresponding to the combined signal is as follows.
0 is output on the basis of a segment where the input signal Vin is 0 in each of the transfer functions when the random variable PN is PN = 1 and PN = −1, and 1 / segment for each segment as the input signal Vin increases from 0. The value that increases by (2 ⁿ ) is subtracted. Note that n is the stage 1 stage gain. In the example of FIG. 18, since MDAC 110 is 2.5 bits, n = 2. Conversely, when the input signal Vin decreases from 0, a value that increases by 1 / (2 ⁿ ) is added to each Segment as the input signal decreases from 0 with respect to the Segment at which the input signal Vin becomes 0.

Next, the output added by the adder 63 using the case where the input signal is Example 5 (= 0) and the case where Example 6 (= (+ 3/4) Vr) is shown in FIG. That is, the input signal of the accumulator 21 in FIG. 17 will be described.
For example, in the conventional threshold value variation calibration method shown in FIG. 7, when the input signal is Example 5, the error signal is integrated with respect to the input signal (= 0). Similarly, when the input signal is Example 4 , Error signals are integrated with respect to the input signal (= (+ 3/4) Vr), and as a result, error signals of the same magnitude are integrated. In the case of Example 4, the input signal is (+ 3 / 4) Since it is as large as Vr, the relative integrated amount decreased according to the following formula.
(Error amount to be integrated) = Σ [(Error signal) / (Input signal)]

However, in the calibration method of the threshold value fluctuation method in the present invention shown in FIG. 17, the adder 63 adds the LUT output value of the LUT 62 to the output signal Vout, so that the stage to the Stage having the SPM unit 12 in advance is added. A value close to the input signal, that is, the input signal (= Vin) to Stage 1 in the case of FIG. 17 is subtracted from the error signal Verr output from the multiplier 35. That is, in FIG. 18, when the input signal is Example 5, “0” is subtracted, and when the input signal is Example 4, “(+3/4) Vr” is subtracted. Therefore, the signal accumulated by the accumulator 21 is the sum of the same amount of “error signal” in Example 3 and Example 4 and the same amount of “input signal-LUT output value” in Example 3 and Example 4. As a result, In Example 3 and Example 4, the same amount of error signal is integrated. That is, the error amount to be integrated can be expressed according to the following equation.
(Error amount to be integrated) = Σ [(Error signal) / (Input signal−LUT output value)]

The same explanation can be made in FIG. 18B showing the transfer function when the PN signal is “−1”.
Therefore, when errors are integrated over the entire input range, even when the input signal Vin to Stage1 is large, the LUT output having a magnitude equivalent to the input signal Vin having a large value is obtained from the error signal Verr calculated by the multiplier 35. The accumulator 21 accumulates the error signal Verr 'after the LUT output value is subtracted, so that the error signal that can be accumulated by the accumulator 21 can be avoided from becoming relatively small. Become. As a result, the relative ratio of error signals to be integrated can be increased, and the integration time can be shortened accordingly.

  In FIG. 17, as shown in FIGS. 18 (a) and 18 (b), the range of the Segment obtained by dividing the input signal Vin is different depending on the random variable PN, and the LUT output value is different for each Segment. Therefore, the combiner 61 generates a combined signal obtained by synthesizing the random variable PN and the digital signal output from the ADC 102a of Stage 1, and obtains the LUT output value from the LUT 62 based on this combined signal. It is not limited to. For example, when the random variable PN is +1 and when the random variable PN is −1, a lookup table is provided individually, and the lookup table to be referred to is switched according to the value of the random variable PN, thereby outputting from the random variable PN and the ADC 102a of Stage1. The LUT output value corresponding to the digital signal to be output may be obtained. In short, the LUT output value corresponding to the digital signal output from the ADC 102a of Stage 1 and the random variable PN may be obtained. .

The above explanation is made when the MDAC 110 shown in FIG. 17 has a 2.5-bit configuration. It is possible.
In addition, the LUT output value is determined using the output result of Stage 1, but this is not limited to this, and by changing the LUT output value using the Back ADC output values of Stage 2, 3,..., It is closer to the input signal. The value can be subtracted, and the relative ratio of the error amount to be integrated can be further increased.

  That is, the LUT output value is not only the magnitude corresponding to the output value of Stage1, but also the magnitude equivalent to the sum of the outputs of these Stages, based on the output of each Stage included in the Backend ADC 42, such as the output of Stage2 and the output of Stage3. If the LUT output value is set and the error signal Verr from the multiplier 35 is subtracted by the adder 63, the value approximated by the input signal Vin to Stage1 can be subtracted. Therefore, the relative ratio of the error amount accumulated in the accumulator 21 can be increased.

<Improvement of calibration method of random signal addition method>
<Detailed configuration (improvement) of calibration device using random signal addition method>
FIG. 19 is a conceptual diagram illustrating an example of a more detailed configuration of a calibration apparatus using a random signal addition method that adds a random signal to the input signal described in FIG. 5, and is more efficient as described above. It is an example of the calibration apparatus for implement | achieving calibration.

  The calibration device using the random signal addition method shown in FIG. 19 according to the present invention is digital compared to the calibration device using the general random signal addition method shown in FIG. 13, which is the calculation result of the ADC 102a of the SADC circuit 102 ′. A coupler 61 that combines the signal Digital1 and the random variable PN, a LUT (LookUpTable) 62 that changes an output value according to the value of the operation result of the coupler 61, and an adder 63. Different. The adder 63 adds the random variable “−PN” × Vcal to the digital signal Vout (ADC) obtained as a result of processing the signal obtained by adding the random signal to the input signal Vin in the stage unit 51 and the Backend ADC 52 by the adder 34. The error signal Verr obtained by multiplying the random variable PN by the multiplier 35 and the output result of the LUT 62 are added to the output signal Vout which is a digital signal obtained by performing A / D conversion on the input signal Vin.

The coupler 61, LUT 62, and adder 63 have the same functional configuration as the coupler 61, LUT 62, and adder 63 shown in FIG.
In FIG. 19, components having the same functions as those of the calibration apparatus shown in FIG. 13 are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 19, the pipeline type A / D converter 1 includes a stage unit 51 including Stage I (for example, Stage 1 (unit block 100 (1))), and unit blocks from Stage I + 1 to Stage N (for example, Stage 2 to Stage N). Backend ADC 52 including (100 (2) to 100 (N))).

  The stage unit 51 includes an MDAC 110 and a SADC circuit 102 ′, a multiplier 31 that multiplies the voltage Vcal and the random variable PN, and an addition for adding the multiplication result of the multiplier 31 to the input signal Vin. And the capacity of the container 32. Accordingly, the calibration apparatus shown in FIG. 19 performs calibration by changing the amplitude of the input signal Vin. Note that the adder 32 and the adder 34 correspond to a random variation unit.

The SADC circuit 102 ′ includes an ADC 102a and a DAC 102b to which the input signal Vin is input.
The MDAC 110 has the same configuration as the MDAC 110 shown in FIG.
Further, an output Vout obtained as a result of processing a signal obtained by adding a random signal to the input signal Vin to the calculation result of the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN” by the stage unit 51 and the Backend ADC 52. (ADC) is added by the adder 34 to obtain an output signal Vout obtained by A / D converting the input signal Vin. Then, the output signal Vout and the random variable PN are multiplied by the multiplier 35, and the calculation result is used as an error signal Verr. The error signal Verr and an output result including a digital value from the LUT (LookUpTable) 62 are added. In 63, the addition result Verr 'is accumulated by the accumulator 21. The up / down counter 22 outputs a command signal to the DAC 23 according to whether the integrated value in the accumulator 21 is smaller than zero, that is, 1 / f ′ can be regarded as larger than 1 / f. The current values of the current sources I1 to I3 of the Gain-AMP 12 are adjusted according to the command signal of the up / down counter 22.

Also in this case, it is possible to avoid that the error signal that can be integrated by the accumulator 21 is relatively small, so that it is possible to increase the relative ratio of the error signal that is desired to be integrated, and the integration time can be shortened accordingly. .
In FIG. 19, addition in the analog unit is realized by charging the capacitor as the adder 32 with a voltage of Vcal × PN. However, the present invention is not limited to this, and the adder is replaced with a capacitor. It may be used.

  Further, instead of the voltage Vcal, the reference voltage Vr used in the comparator of the ADC included in the SADC circuit 102 can be used, and it can be realized by a ratio with the capacitance (CAP) CsI connected to the input terminal of the input signal Vin. For example, when Vcal = (1/4) · Vr, instead of setting the voltage Vcal in FIG. 19 to (1/4) · Vr, Vcal may be set to Vr and the CAP ratio may be set to 1: 4. .

In FIG. 19, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 may be adjusted.
In the calibration apparatus using the random signal addition method shown in FIG. 19, the error signal is integrated by using the back-end ADC 52, as in the calibration apparatus using the threshold value fluctuation method shown in FIG. 7 having the configuration shown in FIG. It is possible to shorten the calibration time by distinguishing the area (time) in which the error signal is not accumulated and the area (time) in which the error signal is not accumulated, and accumulating only the area where the error signal is accumulated. it can.

  As described above, according to the present invention, even when the circuit for extracting the voltage at the summing point Psum is realized by the gain-AMP 12 having a simple configuration, a high-accuracy gain is realized regardless of variations in the operating environment and the manufacturing process. In addition, the integration time can be shortened by avoiding the error signal that can be integrated by the accumulator 21 from becoming relatively small, the gain adjustment of the Gain-AMP 12 can be performed in a shorter time, and the accuracy is high. A pipeline type A / D converter 1 can be realized.

  17 and 19, the case where the output result of the LUT 62 is obtained based on the output of the ADC 102a has been described. However, the level determination circuit 217 described with reference to FIG. Instead of this, the output of the LUT 62 corresponding to the output of the level determination circuit 217 and the random variable PN may be obtained by using the output of the level determination circuit 217.

In the above embodiment, the case where the sample-and-hold circuit calibration method according to the present invention is applied to a pipeline type A / D converter has been described. However, the present invention is not limited to this. For example, the A / D converter Even a sample hold circuit or a ΔΣ A / D converter can be applied.
For example, in the sample hold circuit of the A / D converter shown in FIG. 15, when calibration is performed, the output of the level determination circuit 217 is used as the output of the ADC 102 a, and the level determination circuit is connected by the coupler 61 and the LUT 62. An output result of the LUT 62 corresponding to the output of 217 and the random variable PN may be obtained.

  In addition, the scope of the present invention is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that provide the same effects as those intended by the present invention. Furthermore, the scope of the invention is not limited to the combinations of features of the invention defined by the claims, but can be defined by any desired combination of particular features among all the disclosed features.

1 Pipeline A / D Converter 11 MDAC-AMP
12 Gain-AMP
21 accumulator
22 Up / Down Counter (up / dn counter)
23 DAC (DA converter)
31, 33, 35 Multiplier 32, 34 Adder 61 Combiner 62 LUT (LookUpTable)
63 Adder 102, 102 ′ SADC (Sub AD Converter) Circuit 102a ADC
110 MDAC (Multiplication type digital analog converter)
171 to 177 Comparator 211 Sample hold circuit 212 A / D converter Mx1, Mx2, My1, My2 MOS transistors I1, I2, I3 Current source

Claims (13)

The amplitude of the analog signal to be converted is changed by a random variable, the changed analog signal to be converted is converted into a digital signal by a sample and hold circuit,
Multiply the converted digital signal by the random variable,
Based on the A / D converted digital signal obtained by A / D converting the analog signal to be converted in a system different from the sample hold circuit and the random variable, the magnitude of the A / D converted digital signal and the Generate a digital signal according to the value of the random variable,
To the generated digital signal, add the multiplication signal of the digital signal after the conversion by the sample and hold circuit and the random variable,
A calibration method for a sample and hold circuit, wherein the addition results are integrated and the integration result is used as an error signal when the analog signal to be converted is converted into a digital signal by the sample and hold circuit. The sample and hold circuit has an amplifier,
2. The calibration method for a sample and hold circuit according to claim 1, wherein the gain of the amplifier is adjusted based on the error signal.   The sample-and-hold circuit calibration method according to claim 2, wherein the amplifier is a gain amplifier. The sample and hold circuit includes a multiplying digital-to-analog converter having an amplifier,
4. The sample-and-hold circuit calibration method according to claim 3, wherein a gain of an amplifier included in the multiplying digital-analog converter is adjusted based on the error signal.   4. The method of calibrating a sample and hold circuit according to claim 3, wherein a gain of a main amplifier among amplifiers included in the sample and hold circuit is adjusted based on the error signal. A random variation section that varies the amplitude of the analog signal to be converted by a random variable;
A multiplying unit that multiplies the random variable by a conversion result obtained by converting the analog signal to be converted whose amplitude has been changed by the random changing unit into a digital signal by a sample and hold circuit;
The magnitude of the digital signal after the A / D conversion based on the digital signal after the A / D conversion in which the analog signal to be converted is A / D converted by a system different from the sample hold circuit and the random variable. And a combining unit that generates a combined signal composed of digital signals representing the values of the random variables,
A lookup table for generating a digital signal corresponding to the combined signal generated by the combining unit;
An addition unit for adding the multiplication result in the multiplication unit and the generation result of the digital signal in the lookup table;
An integration unit for integrating the addition results in the addition unit;
A calibration apparatus comprising: The sample hold circuit includes an A / D conversion circuit that converts the analog signal to be converted into a digital signal,
7. The calibration apparatus according to claim 6, wherein the combining unit generates the combined signal based on the digital signal converted by the A / D conversion circuit of the sample and hold circuit and the random variable. A / D conversion circuit that converts the analog signal to be converted into a digital signal separately from the sample and hold circuit,
The calibration device according to claim 6, wherein the combining unit generates the combined signal based on the digital signal converted by the A / D conversion circuit and the random signal. The sample and hold circuit has an amplifier,
The adjustment part which adjusts the gain of the said amplifier based on the said integration result by making the integration result of the said integration part into an error signal in the said sample-and-hold circuit, The any one of Claim 6-8 characterized by the above-mentioned. The calibration device described in 1.   The calibration apparatus according to claim 9, wherein the amplifier is a gain amplifier. The sample and hold circuit includes a multiplying digital-to-analog converter having an amplifier,
The calibration device according to claim 10, wherein the adjustment unit adjusts a gain of an amplifier included in the multiplying digital-analog converter based on the error signal.   The calibration device according to claim 10, wherein the adjustment unit adjusts a gain of a main amplifier among amplifiers included in the sample and hold circuit based on the error signal.   A sample-and-hold circuit comprising the calibration device according to claim 6.

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