JP2015076732A - Method of calibrating sample-hold circuit, calibration device, and sample-hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To implement calibration of a sample-hold circuit providing lower noise and high analog-digital conversion accuracy.SOLUTION: In an SADC (sub AD converter) circuit for converting an input signal Vin to a digital signal, a threshold of the SADC circuit is varied with a random variable, so that as for an analog signal having a predetermined amplitude (for example, near zero) of the input signal Vin, the amplitude is varied. An output Vout produced by digital conversion of the analog signal thus varied in a pipelined A/D converter 1 including an SPM-based MDAC (multiplying DA converter) for converting the digital signal converted in the SADC circuit to an analog signal is multiplied by the random variable PN, a multiplication result is integrated as an error signal Verr, and a gain of Gain-AMP included in the MDAC is adjusted on the basis of the integrated error signal Verr.

Description

  The present invention relates to calibration of a sample and hold circuit, and more specifically, a circuit for converting an input signal to output using amplification by an operational amplifier (for example, a pipelined A / D converter or a ΔΣ A / D converter). Further, the present invention relates to a calibration method, a calibration apparatus, and a sample hold circuit of a sample hold circuit and a multiple DAC (MDAC: multiplication digital analog converter) included therein.

An example of the sample and hold circuit is a pipeline A / D converter. As the pipeline type A / D converter 10, for example, a circuit shown in FIG. 21 is known (see, for example, Patent Document 1).
FIG. 21 is a schematic configuration diagram illustrating an example of the pipeline type A / D converter 10.
As shown in FIG. 21, the pipeline type A / D converter 10 includes N-stage unit blocks 100 (1) to 100 (N) cascaded from Stage1 to StageN.

Since the unit blocks 100 (1) to 100 (N) have the same configuration, the configuration of StageI (unit block 100 (I)) will be described here.
As shown in FIG. 21, Stage I includes an SSH (subsample hold) circuit 101, a SADC (sub AD converter) circuit 102, a DAC (D / A converter) circuit 103, and an adder 104. Is done.

The Stage I SSH circuit 101 takes in the analog output signal Residue I-1 output from the previous unit block Stage I-1.
The SADC circuit 102 performs A / D conversion of the analog output signal ResidueI-1 captured by the SSH circuit 101 into a digital signal DigitalI. This digital signal DigitalI is output as an output signal (DigitalI) of StageI. The digital signal DigitalI output from the SADC circuit 102 is added together with the digital signals DigitalI output from the SADC circuits 102 of Stage1 to StageN according to a predetermined rule, and the result represents the result of A / D conversion. Output as a digital output signal.

The DAC circuit 103 generates an analog signal corresponding to the digital signal DigitalI from the SADC circuit 102 and outputs the analog signal to the adder 104.
The adder 104 subtracts the analog signal generated by the DAC circuit 103 from the analog signal captured by the SSH circuit 101, and outputs the analog signal as a subtraction result to the next unit block Stage I + 1 as Residue I as a residual signal. It has become. At this time, the analog signal (Residue I) as a residual signal obtained by subtracting by the adder 104 is amplified by a predetermined factor, so that the required accuracy of the next unit block Stage I + 1 is not increased and the same unit block (Stage I) is amplified. ) A / D conversion is possible depending on the configuration, and high-precision A / D conversion is realized.

Incidentally, the SSH circuit 101, the DAC circuit 103, and the adder 104 are generally configured by a combination of one operational amplifier and a capacitor CAP. A circuit configured by combining the operational amplifier and the capacitor CAP is referred to as a multiple DAC (MDAC: multiplication type digital analog converter) 105.
FIG. 22 is a schematic configuration diagram illustrating an example of the MDAC 105.

  22A shows a circuit configuration in the sample phase (SamplingPhase), and FIG. 22B shows a circuit configuration in the hold phase (HoldingPhase). The MDAC 105 realizes the circuit of FIG. 22A in the sample phase and the circuit of FIG. 22B in the hold phase by switching a switch or the like (not shown) according to the converted clock signal CLK. Note that the variable I of CsI in FIG. 22A means Cs constituting StageI.

  As shown in FIG. 22, the MDAC 105 includes a sampling capacitor CsI in which unit capacitors of the same size are combined in parallel, an MDAC-AMP11 formed of an operational amplifier, and a parasitic capacitor Cp present at the input terminal of the MDAC-AMP11. Is done. The MDAC 105 operates so as to alternately realize the sample phase (FIG. 22A) and the hold phase (FIG. 22B) in accordance with the input conversion clock signal CLK.

  In the sample phase (FIG. 22A), the sampling output CsI is charged with the analog output signal ResidueI-1 of the previous unit block StageI-1. That is, the analog output signal ResidueI-1 is input to one end of the sampling capacitor CsI, and the other end is connected to the inverting input terminal of the MDAC-AMP11. At this time, the input end and output end of the MDAC-AMP 11 are short-circuited to the ground level. The parasitic capacitance Cp is similarly shorted to the ground level.

  On the other hand, in the hold phase (FIG. 22B), the output terminal and the inverting input terminal of the MDAC-AMP 11 are connected via the capacitor Cf. In addition, the capacitor Cr is set to any one of “+ Vr”, “0”, and “−Vr” for each of a plurality of unit capacitors constituting the capacitor Cr according to the digital signal DigitalI output from the SADC circuit 102 of FIG. Connect to. That is, one end of the capacitor Cr is connected to any one of “+ Vr”, “0”, and “−Vr”, and the other end is connected to the inverting input terminal of the MDAC-AMP 11. Each of the capacitor Cf and the capacitor Cr is constituted by a part of a plurality of unit capacitors constituting the sampling capacitor CsI. That is, in the hold phase, the sampling capacitor CsI uses a part of the unit capacitance constituting the sampling capacitor CsI as the capacitance Cf connecting the output terminal and the inverting input terminal of the MDAC-AMP 11 and the remaining unit capacitance as the capacitance Cr. Used. Here, the case where a part of the plurality of unit capacitors constituting the sampling capacitor CsI is used as the capacitor Cf and the capacitor Cr has been described, but the present invention is not limited to this. For example, a plurality of unit capacitors constituting the sampling capacitor CsI may be used as they are as the capacitor Cr, and the capacitor Cf may be provided separately.

  The output of the MDAC-AMP 11 is connected to the sampling capacitor CsI + 1 of the MDAC 105 constituting the unit block StageI + 1 of the next stage, and the output of the MDAC-AMP 11 of Stage I is output to the sampling capacitor CsI + 1 of the next stage as an analog output signal ResidueI. . Further, the non-inverting input terminal of the MDAC-AMP 11 is maintained at the ground level.

At this time, when the DC (direct current) gain of the MDAC-AMP 11 is “a0”, the voltage Va at the inverting input terminal of the MDAC-AMP 11 is expressed by the following equation (1) using the voltage Vout at the output terminal of the MDAC-AMP 11. Can be represented.
Va = − (1 / a0) × Vout (1)

For example, when the voltages connected to the unit capacitors constituting the capacitor Cr are all zero, the following equation (2) is established from the charge conservation law stored in the capacitors in the sample phase and the hold phase.
CsI × Vin
= Cf (Vout-Va) + Cr (0-Va) + Cp (0-Va) (2)

From the expressions (1) and (2), the output Residue I of the MDAC-AMP 11 in the hold phase, that is, the output Vout of the MDAC 105 can be expressed by the following expression (3).
Vout
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))} × Vin
...... (3)

Here, “a0” in the expression (3) represents the DC (direct current) gain of the MDAC-AMP 11 as described above. “F” is called a feedback factor of the MDAC-AMP 11 and can be expressed by the following equation (4) using the respective capacitances Cr, Cf, and Cp.
f = Cf / (Cr + Cf + Cp) (4)
In the transfer function represented by Expression (3), when input / output characteristics are ideal, Expression (3) can be expressed as the following Expression (5).
Vout = (CsI / Cf) × Vin (5)
From formulas (3) and (5), it can be seen that DCGain “a0” of MDAC-AMP11 needs to be large to infinity in order to obtain ideal input / output characteristics.

In practice, DCGain “a0” is increased according to the required accuracy.
In general, in order to increase the DCGain of AMP, it is necessary to make it multistage or cascode. Therefore, it becomes a problem that it is difficult to maintain good stability or the output amplitude is limited.
In order to solve this problem, a method called Summing Point Monitoring (hereinafter referred to as SPM) has been devised as a method of obtaining MADC-AMP 11 having high gain characteristics without increasing DCGain “a0”.

FIG. 23 is an example of a specific circuit of the multiplying DA converter 105 using the SPM method of FIG.
FIGS. 23A and 23B are examples of specific circuits for realizing the SPM. FIG. 23A shows a circuit configuration in the sample phase, and FIG. 23B shows a circuit configuration in the hold phase.

This circuit corrects an error occurring in the MDAC-AMP 11 by extracting the voltage “−Δs” of the summing point of the MDAC-AMP 11 in FIG. 23B by the Gain-AMP 12.
FIG. 23C is another example of a specific circuit for realizing SPM (for example, see Non-Patent Document 1).
This circuit is a discrete SC (switched capacitor) circuit that samples with the capacitor Ce1 and then transfers with the capacitor Ce2.

JP 2012-60519 A

“A 16-bit 250-MS / s IF Sampling Pipelined ADC With Background Calibration”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010, p. 2602-p. 2612

However, when a new capacitor is added as described above, there is a problem that the characteristics of the entire ADC deteriorate due to noise caused by the newly added capacitor.
Further, in order to keep the MDAC-AMP 11 in a high gain characteristic even when the DCGain “a0” of the MDAC-AMP 11 is low, for example, in the case of the configuration shown in FIG. 23, the Gain-AMP 12 has a high gain. Must have characteristics. However, in practice, there is a problem that such high accuracy cannot be realized due to variations in operating environment and manufacturing process.

  The present invention has been made in view of such a problem, and a sample-and-hold circuit calibration method capable of realizing higher gain characteristics in a sample-and-hold circuit having a relatively low gain characteristic of a DA conversion amplifier. A calibration device and a sample hold circuit are provided.

  According to one aspect of the present invention, only an analog signal having a predetermined amplitude among analog signals to be converted is varied with a random variable, and the varied analog signal to be converted is converted into a digital signal by a sample and hold circuit. The sample is characterized in that the converted digital signal is multiplied by the random variable and the multiplied signal is integrated, and the integration result is used as an error signal when the analog signal to be converted is converted into a digital signal. A calibration method for the hold circuit.

The analog signal having the predetermined amplitude may be an analog signal having an amplitude close to zero.
The analog signal having a predetermined amplitude may be an analog signal having a constant amplitude that is periodically input.
It is determined whether or not the analog signal to be converted is a value within a preset error integration region. If it is determined that the analog signal to be converted is not a value within the error integration region, the multiplication signal is integrated. Instead, the multiplication signal may be integrated only when it is determined that the analog signal to be converted is a value within the error integration region.

Whether or not the analog signal to be converted is a value in the error integration region may be determined based on the analog signal to be converted or a digital signal obtained by converting the analog signal to be converted.
If it is determined that the analog signal to be converted is not a value within the error integration region, the previous integration result may be held.

The sample hold circuit may include an amplifier, and the gain of the amplifier may be adjusted based on the error signal.
The amplifier may be a gain amplifier.
The sample and hold circuit may include a multiplying digital-to-analog converter having an amplifier, and adjust the gain of the amplifier included in the multiplying-type digital to analog converter based on the error signal.

The gain of the main amplifier among the amplifiers included in the sample and hold circuit may be adjusted based on the error signal.
In another aspect of the present invention, a random fluctuation unit (for example, an ADC included in the SADC circuit shown in FIG. 17) that changes the amplitude of only an analog signal having a predetermined amplitude among analog signals to be converted with a random variable; A multiplication unit (for example, FIG. 7) that multiplies the random variable by a conversion result obtained by converting the analog signal to be converted whose amplitude has been varied by the random variation unit into a digital signal by a sample and hold circuit (for example, MDAC 110 illustrated in FIG. 7). And a multiplier (for example, an accumulator 21 shown in FIG. 7) that accumulates the multiplication results of the multiplier.

The analog signal having the predetermined amplitude may be an analog signal having an amplitude close to zero.
The analog signal having a predetermined amplitude may be an analog signal having a constant amplitude that is periodically input.
The integration unit determines whether the analog signal to be converted is a value within a preset error integration region, and when it is determined that the analog signal to be converted is not a value within the error region Does not accumulate the multiplication results in the multiplication unit, and only accumulates the multiplication results in the multiplication unit when it is determined that the analog signal to be converted is a value within the error accumulation region. It's okay.

The sample hold circuit includes an amplifier, and an adjustment unit (for example, an up / down adjustment shown in FIG. 7) that adjusts the gain of the amplifier based on the integration result by using the integration result of the integration unit as an error signal in the sample hold circuit. A counter 22 and a DAC 23) may be provided.
The amplifier may be a gain amplifier (for example, Gain-AMP 12 shown in FIG. 7).

The sample and hold circuit includes a multiplying digital-to-analog converter (for example, MDAC 110 shown in FIG. 7) having an amplifier, and the adjusting unit is an amplifier (for example, MDAC− shown in FIG. 7) included in the multiplying-type digital to analog converter. The gain of AMP11) may be adjusted based on the error signal.
The adjustment unit may adjust a gain of a main amplifier among amplifiers included in the sample hold circuit based on the error signal.

  Another aspect of the present invention is a sample and hold circuit including the calibration device according to any one of the above aspects.

  According to one embodiment of the present invention, analog-digital conversion can be performed with higher accuracy without newly adding a capacitor. In particular, since the signals obtained by amplifying the analog signals are integrated only when the input signal has a predetermined amplitude and the calibration is performed using this as an error signal, the calibration can be performed efficiently. Furthermore, since integration is performed only when the analog signal to be converted is within a predetermined error integration region, efficient integration can be performed, and as a result, the calibration time can be shortened.

It is a schematic block diagram which shows an example of a pipeline type A / D converter. It is a conceptual diagram which shows an example of the multiplication type DA converter using SPM. It is a conceptual diagram which shows an example of Gain-AMP. It is a conceptual diagram which shows the other example of Gain-AMP. It is a schematic block diagram which shows an example of the calibration apparatus of a random signal addition system. It is a schematic block diagram which shows an example of the calibration apparatus of a threshold value fluctuation system. It is a detailed block diagram which shows an example of the calibration apparatus of a threshold value fluctuation system. It is a figure which shows typically a part of ADC contained in a SADC circuit. It is a figure which shows the transfer function (input / output characteristic) of a SADC circuit when not adding a random signal. It is a figure which shows typically a part of ADC contained in the SADC circuit of Stage1 in the case of 2.5-bit MDAC. It is a figure which shows an example of the transfer function (input / output characteristic) of a SADC circuit in the case of adding a random signal. (A) is a figure which shows an example of the transfer function (input / output characteristic) of Stage1 and Stage2 in the ideal case where there is no Offset in the comparator of the SADC circuit, and (b) is a Stage1 in the case where there is Offset. It is a figure which shows an example of the transfer function (input / output characteristic) of Stage2. It is a detailed block diagram which shows an example of the calibration apparatus of a random signal addition system. It is a figure which shows an example of the input signal and transfer function (input / output characteristic) of a SADC circuit when adding a random signal. It is a detailed block diagram which shows the other application example of the calibration apparatus of a random signal addition system. It is a figure which shows an example of the transfer function (input / output characteristic) of Stage1 and Stage2 in the calibration apparatus of the threshold value fluctuation system when there is a general error. FIG. 5 is a diagram schematically illustrating a part of an ADC included in a SADC circuit of Stage 1 in the case of a 2.5-bit MDAC in a threshold variation calibration apparatus. (A) is a figure which shows an example of the transfer function (input / output characteristic) of Stage1 and Stage2 in the ideal case where there is no Offset in the comparator of the SADC circuit, and (b) is a Stage1 in the case where there is Offset. It is a figure which shows an example of the transfer function (input / output characteristic) of Stage2. It is a detailed block diagram which shows an example of the calibration apparatus of a random signal addition system. It is a figure which shows an example of the input signal and transfer function (input / output characteristic) of a SADC circuit when adding a random signal. It is a schematic block diagram which shows an example of a pipeline type A / D converter. It is a schematic block diagram which shows an example of a multiplication type DA converter. It is an example of the specific circuit of a multiplication type DA converter.

Embodiments of the present invention will be described below.
In the following description, a pipeline type A / D converter in which each stage has a 2.5 bit configuration will be described as an example. However, the present invention is not limited to this, and may not be 2.5 bit. It does not have to be a / D converter.
FIG. 1 is a conceptual diagram showing an example of a pipelined A / D converter 1 to which a sample and hold circuit calibration method according to the present invention is applied.

  The pipeline type A / D converter 1 is different from the pipeline type A / D converter 10 shown in FIG. 21 in that an MDAC 110 is provided instead of the MDAC 105. In addition, the same code | symbol is attached | subjected to the component which has the same function as the pipeline type A / D converter 10 shown in FIG. 21, and the description is abbreviate | omitted.

Next, the concept of SPM in the present invention will be described.
FIG. 2 is a schematic configuration diagram illustrating an example of the MDAC 110 using the SPM.
As shown in FIG. 2, the SPM includes a gain amplifier AMP12 which is a gain amplifier for monitoring the voltage Va at the input terminal of the MDAC-AMP 11 called a summing point (summing point) Psum with respect to a normal DAC. There is a feature in the point to use.

  The gain-AMP 12 has an input / output terminal shorted to the ground level in the sample phase, an input terminal connected to the summing point Psum in the hold phase, and an output terminal connected to the sampling capacitor of the MDAC 110 constituting the next stage unit block StageI + 1. Connected to CsI + 1. That is, by alternately repeating the sample phase (FIG. 2A) and the hold phase (FIG. 2B), a signal obtained by amplifying the voltage Va at the summing point Psum by the Gain-AMP 12, that is, (1 / f ′) XVa is stored in the next stage sampling capacitor CsI + 1.

The output Vout (MDAC) of the MDAC-AMP 11 in the MDAC 110 using the SPM shown in FIG. 2 is the same as the output Vout of the MDAC-AMP 11 in the MDAC 105 shown in FIG. ) Expression can be expressed by the following expression (6).
Vout (MDAC)
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))} × Vin
...... (6)

On the other hand, the output Vout (SPM) of the Gain-AMP 12 can be expressed by the following equation (7), where the gain of the Gain-AMP 12 is 1 / f ′.
Vout (SPM)
= (1 / f ') x Va
= -1 / (a0 * f ') * Vout (MDAC) (7)

In the MDAC 110 using the SPM shown in FIG. 2, the difference between the output Vout (MDAC) of the MDAC-AMP 11 and the output Vout (SPM) of the Gain-AMP 12 is the total output of the unit block StageI. Can be expressed by the following equation (8).
Vout
= Vout (MDAC) -Vout (SPM)
= Vout (MDAC) + 1 / (a0 * f ') * Vout (MDAC)
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))}
× {1 + 1 / (a0 × f ′)} × Vin (8)

Here, when “f ′” is equal to “f”, the equation (8) can be expressed as the following equation (9).
Vout = (CsI / Cf) × Vin (9)
From Expression (9), it can be seen that the output Vout of the unit block StageI in the SPM does not depend on the DCGain “a0” of the MDAC-AMP11. That is, it is possible to maintain high gain characteristics even when DCGain “a0” is low.

<Conceptual diagram of Gain-AMP12>
FIG. 3 is a conceptual diagram showing an example of the Gain-AMP 12 constituting the pipeline type A / D converter 1 (FIG. 1) in the present invention.
The pipeline type A / D converter 1 according to the present invention is equipped with the MDAC 110 shown in FIG. 2 as the MDAC for the Stage 1 (100 (1)), and the Gain-AMP 12 shown in FIG. Is used. For Stage 2 (100 (2)) to Stage N (100 (N)), an MDAC having no Gain-AMP 12 shown in FIG. 22 is mounted.

  That is, in the pipeline type A / D converter 1, DCGain “a0” having the highest Stage1 (100 (1)) is required. Therefore, in the present embodiment, only for Stage 1 (100 (1)), the MDAC 110 shown in FIG. 2 is mounted as the MDAC, and the Gain-AMP shown in FIG. 3 is used as the Gain-AMP 12. The present invention is not limited to this. For all Stage 1 (100 (1)) to Stage N (100 (N)) or any of a plurality of Stages, the MDAC 110 shown in FIG. 2 is mounted as an MDAC, and the Gain-AMP 12 is illustrated. It is also possible to use the Gain-AMP shown in FIG.

In each of the above drawings, the case where the circuit is configured with a single-ended circuit has been described for the sake of simplification of the description, but FIG.
As shown in FIG. 3, the Gain-AMP 12 in the present invention has differential MOS transistors Mx1 and Mx2 composed of N-channel MOS transistors connected to a summing point Psum, and is connected to an output. This is a non-discrete type gain-adjustable gain amplifier that includes transistors My1 and My2 and current sources I1, I2, and I3 of variable current values, and is a capless gain amplifier. The non-discrete type gain amplifier here refers to an amplifier that continuously amplifies an input signal to an output without switching operation.

The MOS transistors Mx1, Mx2, My1, and My2 are composed of MOS transistors having the same functional configuration.
That is, in the Gain-AMP 12, as shown in FIG. 3, the MOS transistors My2 and Mx2 connected in series and the MOS transistors My1 and Mx1 connected in series are connected in parallel between the power supply VDD and the ground GND. Further, a current source I3 is interposed between the MOS transistors Mx1 and Mx2 and the ground GND.

  The connection point between the MOS transistors My1 and Mx1 is one output terminal Pout of the Gain-AMP 12, and the current source I1 is connected in parallel with the MOS transistor My1. Similarly, the connection point of the MOS transistors My2 and Mx2 becomes the other output terminal Nout of the Gain-AMP 12, and the current source I2 is connected in parallel with the MOS transistor My2.

The gate of the MOS transistor Mx2 is connected to one input terminal Pin of the Gain-AMP12, and the gate of the MOS transistor Mx1 is connected to the other input terminal Nin of the Gain-AMP12. These input terminals Pin / Nin correspond to the input terminals of the Gain-AMP 12 in FIG. 2 and are connected to the summing point Psum.
The gates of the MOS transistors My1 and My2 are connected to fixed voltages Vb1 and Vb2 sufficient for the MOS transistors to enter the saturation region, respectively.

Furthermore, the output terminals Pout and Nout correspond to the output terminal of the Gain-AMP 12 in FIG. 2, and are connected to the sampling capacitor CsI + 1 at the next stage.
The gain of the Gain-AMP 12 shown in FIG. 3 can be expressed by the following equation (10), where the mutual conductance of the MOS transistors Mx1 and Mx2 is gmx, and the mutual conductance of the MOS transistors My1 and My2 is gmy, respectively.
1 / f '= gmx / gmy (10)

  The Gain-AMP12 MOS transistors Mx1, Mx2, My1, and My2 are all composed of the same type of MOS transistors and have the same functional configuration. Therefore, the characteristics of Gain-AMP 12 are characterized by being hardly affected by process variations. Note that each of the current sources I1, I2, and I3 can be composed of MOS transistors. In addition, when the current source I3 is configured by a MOS transistor, a simple amplifier connected by three MOS transistors from the power supply voltage of the power supply VDD to the ground GND is configured. It also has the effect that it is difficult to receive such restrictions.

Here, generally, the mutual conductance gm of a MOS transistor is expressed as follows: the size of the MOS transistor is W / L (W is the gate width of the MOS transistor, L is the gate length of the MOS transistor), and the current flowing through the MOS transistor is i. It can represent with following Formula (11). In the equation (11), K is a constant depending on the process.
gm = 2 × {K × (W / L) × i} ^1/2 (11)

  That is, the value of the mutual conductance gm of the MOS transistor is proportional to the 1/2 power of the current i flowing through the MOS transistor. From this, it is possible to change the gain 1 / f ′ of the Gain-AMP 12 by changing the value of the mutual conductance gm by finely adjusting the current values of the current sources I1, I2, and I3. Recognize.

<Conceptual diagram of other example of Gain-AMP12>
In the above embodiment, the case where the Gain-AMP 12 is configured by an N-channel MOS transistor has been described. However, the Gain-AMP 12 may be configured by a P-channel MOS transistor.
FIG. 4 is a conceptual diagram showing another example of Gain-AMP 12 in the present invention.
The Gain-AMP 12 shown in FIG. 4 is connected to the summing point Psum and is composed of P-channel MOS transistors, differential MOS transistors Mx1 and Mx2, MOS transistors My1 and My2 connected to the output, and variable current value. Current sources I1, I2, and I3. The MOS transistors Mx1, Mx2, My1, and My2 are P-channel MOS transistors having the same functional configuration.

That is, as shown in FIG. 4, the Gain-AMP 12 includes MOS transistors Mx2 and My2 connected in series, and MOS transistors Mx1 and My1 connected in series, connected in parallel between the power supply VDD and the ground GND. Further, a current source I3 is interposed between the MOS transistors Mx1 and Mx2 and the power supply VDD.
The connection point between the MOS transistors Mx1 and My1 is one output terminal Pout of the Gain-AMP 12, and the current source I1 is connected in parallel with the MOS transistor My1. Similarly, the connection point of the MOS transistors Mx2 and My2 becomes the other output terminal Nout of the Gain-AMP 12, and the current source I2 is connected in parallel with the MOS transistor My2.

The gate of the MOS transistor Mx2 is connected to one input terminal Pin of the Gain-AMP12, and the gate of the MOS transistor Mx1 is connected to the other input terminal Nin of the Gain-AMP12.
These input terminals Pin / Nin correspond to the input terminals of the Gain-AMP 12 in FIG. 2 and are connected to the summing point Psum.

The gates of the MOS transistors My1 and My2 are connected to fixed voltages Vb3 and Vb4 sufficient for the MOS transistors to enter the saturation region, respectively.
Further, the output terminals Pout and Nout correspond to the output terminal of the Gain-AMP 12 in FIG. 2 and are connected to the next-stage sampling capacitor CsI + 1.
With the above configuration, it is possible to obtain the same operational effects as when the Gain-AMP 12 is configured with an N-channel MOS transistor.
3 and 4, each of the current sources I1 to I3 can be configured by a MOS transistor.

<Calibration device>
Next, a circuit for adjusting the gain 1 / f ′ of the Gain-AMP 12 in the pipeline A / D converter 1 including the MDAC 110 having the Gain-AMP 12 shown in FIG. 3, that is, the pipeline A / D. A calibration apparatus for adjusting the gain of the converter 1 will be described.

<Random signal addition type calibration device>
FIG. 5 is a schematic configuration diagram illustrating an example of a calibration apparatus that performs gain adjustment of the pipelined A / D converter 1 having the Gain-AMP 12. The calibration apparatus shown in FIG. 5 performs calibration by adding a random signal to an input signal Vin. A method of performing calibration by adding a random signal to the input signal Vin in this way is called a random signal addition method.

  In the calibration apparatus using the random signal addition method shown in FIG. 5, the pipeline type A / D converter 1 is stage 1 in the MADC 110 constituting the pipeline type A / D converter 1 shown in FIG. 2, the MDAC shown in FIG. 2 is mounted as the MADC 110, and the simple configuration Gain-AMP shown in FIG. 3 is used as the Gain-AMP 12.

In FIG. 3, the gain “1 / f ′” of the Gain-AMP 12 is different from the reciprocal “1 / f” of the feedback factor of the MDAC 11, and therefore the input / output characteristics of the pipeline type A / D converter 1 are nonlinear. Then, the input / output characteristics in this case can be assumed as shown in the following equation (12).
Vout (ADC) = (1−α) × Vin (ADC) (12)

Α in the equation (12) can be expressed as follows using the gain “1 / f ′” of Gain-AMP 12 and the reciprocal “1 / f” of the feedback factor of MDAC 110.
α = Cf / Cs × (1 / a0) × (1 / f−1 / f ′) (13)
Here, a random variable PN composed of “1” or “−1” is added to a signal PN × Vcal obtained by multiplying a certain voltage Vcal to the input signal Vin, and the added analog signal Vin (ADC) is added to the pipeline type A / Input to D converter 1. The voltage Vcal may be set based on, for example, a necessary input amplitude and a time required for correction.

Here, although the random variable PN is set to “1” or “−1”, it is not limited to this, and is a value that is changed by a value in the plus direction and the minus direction with reference to 0. Thus, it is sufficient that the average value of the random variables is zero.
After analog-to-digital conversion through the pipeline type A / D converter 1, the digital signal Vout (ADC) corresponding to the analog signal Vin (ADC) output from the pipeline type A / D converter 1 is converted into an input signal Vin. When a digital signal corresponding to the added analog signal (PN × Vcal) is subtracted, the subtraction result, that is, the output Vout can be expressed by the following equation (14).
Vout = Vin−α × (Vin + PN × Vcal) (14)

Here, when the random variable PN used when calculating the analog signal (PN × Vcal) added to the input signal Vin is multiplied by the output Vout represented by the equation (14), as described above, the random variable PN Is “1” or “−1” and PN × PN = 1, and can be expressed by the following equation (15).
PN x Vout
= PN × Vin (1-α) −αVcal (15)
Since PN × Vin obtained by multiplying the input signal Vin by the random variable PN becomes zero when averaged over a long period of time, the equation (15) can be expressed as the equation (16) after all.
PN × Vout = −αVcal (16)

  Here, an accumulator 21, an up / down counter (up / dn counter) 22 for detecting a signal PN × Vout (= −α × Vcal = Verr) in the long term, a DAC (D / A converter) 23, , The gain of the Gain-AMP 12 of each MDAC 110 constituting the pipeline type A / D converter 1 is adjusted so that Verr (error signal) becomes zero.

  That is, the accumulator 21 accumulates the input error signal Verr, and the up / down counter 22 can consider that 1 / f ′ is greater than 1 / f from the equation (13) when the accumulated value is smaller than zero. A command signal for reducing the gain of the Gain-AMP 12 is output. On the contrary, when the integrated value in the accumulator 21 is larger than zero, it can be considered that 1 / f ′ is smaller than 1 / f from the equation (13), so that a command signal for increasing the gain of the Gain-AMP 12 is output.

  The DAC 23 adjusts the current values of the current sources I1 to I3 according to the command signal of the up / down counter 22. For example, when 1 / f ′ is decreased, the current amount of the current sources I1, I2 and I3 is decreased, and 1 / f ′ is decreased by decreasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2. Conversely, 1 / f ′ is increased by increasing the current amount of the current sources I1, I2, and I3 and increasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2.

When the gain of Gain-AMP 12 is adjusted as described above, α = 0.
Therefore, if α = 0 is substituted into the equation (14), the equation (14) becomes Vout = Vin. That is, this is equivalent to ideal analog-digital conversion of the input signal Vin.
In the calibration apparatus using the random signal addition method shown in FIG. 5, 31 is a computing unit that multiplies a random variable PN generated by a random signal generation circuit (not shown) and the like, and a preset voltage Vcal, 32 Is an adder that adds the input signal Vin to the pipeline type A / D converter 1 and the operation result PN × Vcal of the multiplier 31 and outputs the addition result Vin ′ to the pipeline type A / D converter 1. , 33 is a multiplier that multiplies the negative value (−PN) of the random variable PN generated by the random signal generation circuit and the like with a preset voltage Vcal, and 34 is an operation result of the multiplier 33 (−PN × Vcal) and an output Vout (ADC) of the pipelined A / D converter 1 are added and output as an output Vout, 35 is the random signal generation circuit Is a multiplier that multiplies the random variable PN generated by the above and the output Vout output from the adder 34.

In the calibration device of FIG. 5, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 of FIG. 2 may be adjusted. In this case, what is necessary is just to adjust the gain of MDAC-AMP11 in the procedure similar to the case where the gain adjustment of Gain-AMP12 is performed.
As described above, by using the calibration apparatus based on the random signal addition method shown in FIG. 5, the pipeline type A / D converter 1 performs accurate analog-digital conversion without adding a new capacity. Even if the DCgain “a0” of MDAC-AMP11 is low, accurate analog-to-digital conversion can be performed. Therefore, accurate analog-to-digital conversion can be realized while suppressing an increase in noise.

  Further, for example, as in the circuit of the multiplying DA converter that realizes the SPM of FIG. 23, the gain is adjusted by feeding back the output of the MDAC-AMP 11 to create the gain “1 / f ′” of the Gain-AMP 12. Compared to the method, the gain-AMP 12 in this embodiment has a simple circuit configuration as shown in FIG. Therefore, power consumption can be kept small.

  Further, even if the DCgain “a0” of the MDAC-AMP11 is relatively small, the analog-digital conversion can be performed accurately, so that the DCgain “a0” of the MDAC-AMP11 can be kept small. Therefore, the configuration of the MDAC-AMP 11 can be made simple, that is, the power supply voltage can be reduced, so that power consumption can be further suppressed.

  In the calibration apparatus of FIG. 5, the case of adjusting the Gain-AMP 12 of the MDAC 110 included in the Stage 1 of the pipeline A / D converter 1 has been described. When the Stage includes the MDAC 110 having the Gain-AMP 12, the gain of each Gain-AMP 12 may be adjusted in each Stage, and whether or not the Gain-AMP 12 is included is included in each Stage. You may make it adjust the gain of MDAC-AMP11 contained in.

<Threshold variation calibration device>
Next, another example of the calibration apparatus that performs gain adjustment of the pipeline type A / D converter 1 including the Gain-AMP 12 as a calibration apparatus will be described.
FIG. 6 is a schematic configuration diagram illustrating another example of a calibration apparatus that adjusts the gain 1 / f ′ of the Gain-AMP 12 in the pipelined A / D converter 1 including the Gain-AMP 12 illustrated in FIG. 3. It is.
The calibration apparatus shown in FIG. 6 performs calibration by changing the threshold value of the SADC circuit 102 included in the pipeline type A / D converter 1. A method of performing calibration by changing the threshold value of the SADC circuit 102 in this way is called a threshold value changing method.

As shown in FIG. 6, the calibration device using the threshold variation method does not require the multipliers 31 and 33 and the adders 32 and 34 that are included in the calibration device shown in FIG.
In the case of the calibration apparatus using the random signal addition method shown in FIG. 5, since a random signal irrelevant to the input signal is added and then AD conversion is performed, it is necessary to subtract a signal corresponding to the random signal added from the output signal. On the other hand, in the case of the calibration apparatus based on the threshold value variation method shown in FIG. 6, only the threshold value of the SADC circuit 102 is varied, and no random signal is added, so that a portion for subtracting the random signal is unnecessary. .

  That is, as shown in FIG. 6, the threshold value variation calibration apparatus multiplies the output Vout output from the pipeline A / D converter 1 by the random variable PN, and the output of the multiplier 35. , An up / down counter (up / dn counter) 22 for detecting a signal PN × Vout (= −α × Vcal = Verr) in the long term, a DAC (D / A converter) 23, The gain of each MDAC 110 constituting the pipeline A / D converter 1 is adjusted so that the error signal Verr (error signal) becomes zero using the output of the DAC 23.

In FIG. 3, the gain “1 / f ′” of the Gain-AMP 12 is different from the reciprocal “1 / f” of the feedback factor of the MDAC 11, and therefore the input / output characteristics of the pipeline type A / D converter 1 are nonlinear. Then, the input / output characteristics in this case can be assumed as shown in the following equation (17).
Vout = (1−α) × Vin (17)
Α in the equation (17) can be expressed as the following equation (18) using the gain “1 / f ′” of the Gain-AMP 12 and the reciprocal “1 / f” of the feedback factor of the MDAC 110.
α = Cf / Cs × (1 / a0) × (1 / f−1 / f ′) (18)

Here, a signal PN × Vcal obtained by multiplying a random voltage PN consisting of “1” or “−1” by a certain voltage Vcal is added to the output of the ADC in the SADC circuit 102. The voltage Vcal may be set based on, for example, a necessary input amplitude and a time required for correction.
A digital signal Vout corresponding to the analog signal Vin output from the pipeline A / D converter 1 after being converted from analog to digital through the pipeline A / D converter 1 can be expressed by the following equation (19).
Vout = Vin−α × (Vin + PN × Vcal)
= (1-α) Vin−α (PN × Vcal) (19)

Here, when the random variable PN is multiplied by the output Vout represented by the equation (19), as described above, the random variable PN is “1” or “−1” and PN × PN = 1. Can be represented by the following formula (20).
PN x Vout
= PN × Vin (1-α) −αVcal (20)
Since PN × Vin obtained by multiplying the input signal Vin by the random variable PN becomes zero when averaged over a long period of time, the equation (20) can be expressed as the equation (21).
PN × Vout = −αVcal (21)

  Here, using the accumulator 21, the up / down counter 22, and the DAC (D / A converter) 23, it is included in the pipeline type A / D converter 1 so that Verr (error signal) becomes zero. The gain of the Gain-AMP 12 of the MDAC 110 to be adjusted is adjusted.

  That is, the accumulator 21 integrates the input error signal Verr, and when the integrated value is smaller than zero, the up / down counter 22 can consider that 1 / f 'is larger than 1 / f, so that the gain of the Gain-AMP 12 is reduced. Command signal to be output. Conversely, when the integrated value in the accumulator 21 is larger than zero, it can be considered that 1 / f ′ is smaller than 1 / f, so that a command signal for increasing the gain of the Gain-AMP 12 is output. The DAC 23 adjusts the current values of the current sources I1 to I3 according to the command signal of the up / down counter 22. For example, when 1 / f ′ is decreased, the current amount of the current sources I1, I2 and I3 is decreased, and 1 / f ′ is decreased by decreasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2. Conversely, 1 / f ′ is increased by increasing the current amount of the current sources I1, I2, and I3 and increasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2.

When the gain of Gain-AMP 12 is adjusted as described above, α = 0.
Therefore, if α = 0 is substituted into the equation (19), the equation (19) becomes Vout = Vin. That is, this is equivalent to ideal analog-digital conversion of the input signal Vin.
In FIG. 6, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 in FIG. 2 may be adjusted by the same procedure as described above.

  Also in this case, when the pipeline type A / D converter 1 includes not only the Stage 1 but also other stages including the MDAC 110 having the Gain-AMP 12, the gain of each Gain-AMP 12 is adjusted in each Stage. The gain of the MDAC-AMP 11 included in each stage may be adjusted regardless of whether the Gain-AMP 12 is included or not.

<Detailed configuration diagram showing an example of a calibration apparatus using a threshold variation method>
Next, a detailed configuration of the calibration apparatus using the threshold variation method will be described.
FIG. 7 shows a detailed configuration of a calibration apparatus based on a threshold variation method that performs adjustment using the calibration method that varies the threshold of the SADC circuit 102 described in FIG. 6. In the case of performing background calibration, FIG. It is a block diagram which shows an example of a calibration apparatus.
As shown in FIG. 7, the pipeline A / D converter 1 includes a stage unit 41 including Stage 1 (unit block 100 (1)) and unit blocks 100 (2) to 100 (Stage 2 to Stage N). N)) including Backend ADC42.

The stage unit 41 includes an MDAC 110 and a SADC circuit 102.
The SADC circuit 102 includes an ADC 102a and a DAC 102b to which the input signal Vin is input, and further includes a multiplier 102c that multiplies the voltage Vcal and the random variable PN, an output of the ADC 102a, and an output of the multiplier 102c. And an arithmetic unit 102d for adding.

Then, as described above, the calibration apparatus shown in FIG. 7 performs calibration by changing the threshold of the SADC circuit 102 and changing the input / output function.
The MDAC 110 has the same configuration as the MDAC 110 shown in FIG.
Also, the output Vout output from the Backend ADC 42 and the random variable PN are multiplied by the multiplier 35, the calculation result in the calculation unit 43 is used as the error signal Verr, the error signal Verr is integrated in the accumulator 21, and the up / down counter 22 Then, a command signal is output to the DAC 23 according to whether the integrated value is smaller than zero, that is, 1 / f ′ can be regarded as larger than 1 / f. The DAC 23 outputs a command signal to the up / down counter 22. Accordingly, the current values of the current sources I1 to I3 of the Gain-AMP 12 are adjusted.

Here, the method of performing calibration by changing the threshold value of the SADC circuit 102 has an advantage that a high Feedback Gain can be obtained because a capacitor (CAP) for inserting a Dither signal is not added.
Also, in this method, an error generated by AD conversion is extracted on the assumption that a signal obtained by superimposing a Dither signal on an input signal is accumulated for a long period, and an optimum value is searched by feeding back this error.

  In FIG. 7, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 may be adjusted, and the capacitance value of sampling capacitor CsI may be adjusted. You can do it.

<Comparison with conventional calibration method>
Here, as in this embodiment, a method for adjusting the gain of the pipelined A / D converter 1 by adding a random signal to the input signal Vin or changing the threshold value of the SADC circuit 102. In order to clarify the difference from the conventional calibration method, a case where gain adjustment is performed without using a conventional random signal will be described.

FIG. 8 is a diagram schematically showing a part of the ADC 102a included in the SADC circuit 102 of Stage 1 when the MDAC 110 shown in FIG. 7 is a 2.5-bit MDAC, for example, and when a conventional calibration method is used. 2 shows a part of the ADC included in the SADC circuit 102.
A SADC circuit (hereinafter referred to as a conventional SADC circuit) in the case of using a conventional calibration method includes comparators 151 to 156 as shown in FIG.
The comparators 151 to 156 include the input signal Vin and the reference voltages (5/8) · Vr, (3/8) · Vr, (1/8) · Vr, (−1/8) · Vr, (−3/8). ) · Vr and (−5/8) · Vr. Vr is the maximum input range of the input signal Vin.

FIG. 9 is a diagram illustrating a transfer function (input / output characteristics) of a conventional SADC circuit that does not add a random signal. In FIG. 9, the horizontal axis is input, and the vertical axis is output. Further, a value indicated by “Δ” in FIG. 9 represents a threshold value of a conventional SADC circuit that does not add a random signal.
As shown in FIG. 9, in the case of a conventional SADC circuit that does not add a random signal, the value of the reference voltage to be compared does not change, so that an output signal with a transfer function adapted to the input signal is output.

Next, a case where random signals are added in the SADC circuit 102 as in this embodiment will be described.
FIG. 10 is a diagram schematically illustrating a part of the ADC included in the SADC circuit 102 of Stage 1 illustrated in FIG. 7 when the MDAC 110 is a 2.5-bit MDAC.
The SADC circuit 102 includes comparators 161 to 168.

  The comparators 161 to 168 exchange voltages to be compared with random signals. That is, when the random variable PN = 1, the input signal Vin and the reference voltages (15/16) · Vr, (11/16) · Vr, (7/16) · Vr, (3/16) · Vr, ( −1/16) · Vr, (−5/16) · Vr, (−9/16) · Vr, and (−13/16) · Vr. On the other hand, when the random variable PN = −1, the input signal Vin and the reference voltages (13/16) · Vr, (9/16) · Vr, (5/16) · Vr, (1/16) · Vr, (−3/16) · Vr, (−7/16) · Vr, (−11/16) · Vr, and (−15/16) · Vr are respectively compared. Vr is the maximum input range of the input signal Vin.

FIG. 11 is a diagram illustrating a transfer function (input / output characteristics) of the SADC circuit 102 in the present embodiment, in which the random variable PN is added. In FIG. 11, the horizontal axis represents the input to the SADC circuit 102, and the vertical axis represents the output. Further, the value indicated by “Δ” in FIG. 11 represents the threshold value of the SADC circuit 102 to which the random variable PN is added.
In FIG. 11, the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = 1, and the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = −1. Is also written.

When an input signal as in Example 1 enters from the input side, the output signal changes depending on the value of the random variable PN. For example, when PN = 1, the transfer function of the SADC circuit 102 when adding the random variable PN = 1 is applied, and the input signal of Example 1 becomes an output signal (PN = 1) according to Example 1. When PN = −1, the transfer function of the SADC circuit 102 when adding the random variable PN = −1 is applied, and the input signal of Example 1 becomes the output signal (PN = −1) according to Example 1. As a result, as shown in FIG. 11, the output result varies depending on the random variable PN.
In this case, since the output changes even with the same input depending on the random variable PN, if it is added over a long period, an error component remains as a result.

  On the other hand, when an input signal such as Example 2 is input from the input side, the output signal is not changed by the random variable PN. For example, when PN = 1, the transfer function of the SADC circuit 102 when adding the random variable PN = 1 is applied. When PN = −1, the transfer function of the SADC circuit 102 when adding the random variable PN = −1. Although the function is applied, since both transfer functions are the same, the input signal of Example 2 is an output signal (PN = 1 / −1) according to Example 2.

In this case, even if the random variable PN fluctuates, the output is always the same, so even if added for a long time, it is canceled out and no error remains.
By the way, whether or not errors are integrated, the accumulator 21 integrates all output signals.
Therefore, in order to shorten the calibration time, it is necessary to make the integration time of the accumulator 21 efficient, and as described above, the error signal in the multiplier 35 becomes zero by the input signal Vin. Since there are cases where the error signal does not become zero, a region that the input signal Vin can take when the error signal does not become zero is set as an error integration region, and it is determined whether or not the input signal Vin is a value within the error integration region. Perform efficient integration.

<Description of calibration method using threshold fluctuation method>
Next, a calibration method using a threshold variation method will be described.
In the present embodiment, for example, the back-end ADC 42 shown in FIG. 7 is used to distinguish the input signal Vin into a region (time) in which the error signal is integrated and a region (time) in which the error signal is not integrated, The error signal is integrated by the accumulator 21 only when the value of the area where the error signal is integrated, that is, the value within the error integration area.
The accumulator 21 may simply hold the previous integration result when the input signal Vin is a value in a region (time) in which the error signal is not integrated, or may add “0” to the previous integration result. Alternatively, both ends of the accumulator 21 may be bypassed.

FIG. 12A shows the transfer functions (input / output characteristics) of Stage 1 and Stage 2 in the ideal case where there is no offset in the comparators 161 to 168 of the SADC circuit 102 that adds the random variable PN shown in FIG. It is. In the diagram showing the transfer function of Stage 1 (the diagram on the left side of FIG. 12A), the horizontal axis represents the input to the SADC circuit 102, the vertical axis represents the output, and the value indicated by “Δ” on the horizontal axis is This represents the threshold value of the SADC circuit 102 of Stage1. The solid line represents the transfer characteristic when PN = 1, and the alternate long and short dash line represents the transfer characteristic when PN = -1.

In the diagram showing the transfer function of Stage 2 (the diagram on the right side of FIG. 12A), the horizontal axis represents the output of the SADC circuit 102 of Stage 2, the vertical axis represents the input of the SADC circuit 102 of Stage 2, and the vertical axis The value indicated by “Δ” indicates the threshold value of the SADC circuit 102 of Stage2.
In FIG. 12A, the region not affected by the random variable PN corresponds to (−1/4) · Vr to (1/4) · Vr of Stage 2 input (= Output of Stage 1). A determination circuit (not shown) determines that this area is an error integrated area (time), and distinguishes an error integrated area (time) from an unintegrated area (time). Only the accumulator 21 is integrated.

As described above, since only the areas where errors are integrated are integrated, it is not necessary to integrate as much as possible the input signals unnecessary for error integration, and the integration ratio of the error signals that are relatively necessary increases. That is, since the ratio of error components in the integrated signal increases, it is easy to extract error components even if the integration time is relatively short.
Here, the stage 2 input (= stage 1 output) is (−1/4) · Vr to (1/4) · Vr as shown in FIG. 12 (a) when the input signal inputted to Stage2 is In each segment divided into a plurality of segments, segment Seg. 3 and segment Seg. 2 when the output is 0 or more, the segment Seg. 4 when the output is 0 or less.

Whether the output is 0 or more or 0 or less can be determined from the AD conversion result of the back-end ADC 42, and the accumulator 21 does not perform integration if it corresponds to these. As described above, instead of adding a new determination circuit, the AD conversion result in the back-end ADC 42 can be used for the determination.
FIG. 12B is a diagram illustrating transfer functions (input / output characteristics) of Stage 1 and Stage 2 when the comparator of the SADC circuit 102 has Offset. In the diagram showing the transfer function of Stage 1 (the diagram on the left side of FIG. 12B), the horizontal axis represents the input to the SADC circuit 102, the vertical axis represents the output, and the value indicated by “Δ” on the horizontal axis is: This represents the threshold value of the SADC circuit 102 of Stage1. The solid line represents the transfer characteristic when PN = 1, and the alternate long and short dash line represents the transfer characteristic when PN = -1. In the diagram showing the transfer function of Stage 2 (the diagram on the right side of FIG. 12B), the horizontal axis represents the output of the SADC circuit 102 of Stage 2, and the vertical axis represents the input of the SADC circuit 102 of Stage 2. The value indicated by “Δ” on the vertical axis represents the threshold value of the SADC circuit 102 of Stage2.

  As shown in FIG. 12B, when the offsets are present in the comparators 161 to 168 of the SADC circuit 102, the area to be integrated is widened for the back-end ADC 42. Therefore, it is preferable to determine a region where error signals are not integrated in consideration of the offset of the comparator of the SADC circuit 102. For example, assuming that Offset is (1/32) · Vr, the area where the error signal is not integrated becomes 1/8 of the entire back-end ADC 42, and the time reduction effect is expected.

<Detailed configuration diagram showing an example of a calibration apparatus using a random signal addition method>
Next, a detailed configuration of the calibration apparatus using the random signal addition method will be described.
FIG. 13 is a detailed configuration diagram illustrating an example of a calibration apparatus using a random signal addition method that adds a random signal to the input signal described in FIG. 5.
Compared with the calibration apparatus based on the threshold value variation system shown in FIG. 7, the calibration apparatus based on the random signal addition system shown in FIG. 13 further includes multipliers 31 and 33, an adder 34, and addition for adding random signals. The place provided with the capacity as the container 32 is different. Components having the same functions as those of the calibration apparatus shown in FIG.

As shown in FIG. 13, the pipeline A / D converter 1 includes a stage unit 51 including Stage 1 (unit block 100 (1)) and unit blocks (100 (2) to 100 (N) from Stage 2 to Stage N. )) Including a Backend ADC 52.
The stage unit 51 includes an MDAC 110 and a SADC circuit 102 ′.

The SADC circuit 102 'includes an ADC 102a and a DAC 102b to which an input signal Vin is input, a multiplier 31 that multiplies the voltage Vcal and the random variable PN, and a multiplication result of the multiplier 31 is added to the input signal Vin. And a capacity as an adder 32.
The calibration apparatus shown in FIG. 13 adds a random signal to the input signal Vin, and performs calibration by changing the amplitude of the input signal Vin.

The MDAC 110 has the same configuration as the MDAC 110 shown in FIG.
Further, the output Vout (ADC) output from the Backend ADC 52 is added by the adder 34 to the operation result of the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN”, and the addition result and the random variable PN Is multiplied by a multiplier 35. The calculation result in the multiplier 35 is used as an error signal Verr, and the error signal Verr is integrated by the accumulator 21. In the up / down counter 22, the integrated value is smaller than zero, that is, 1 / f ′ is larger than 1 / f. A command signal is output to the DAC 23 according to whether it can be considered, and the DAC 23 adjusts the current values of the current sources I1 to I3 of the Gain-AMP 12 according to the command signal of the up / down counter 22.

In FIG. 13, the addition of the analog unit is realized by charging the capacitor as the adder 32 with a voltage of (Vcal × PN). However, the present invention is not limited to this. A vessel may be used.
Further, instead of the voltage Vcal, the reference voltage Vr used in the comparator of the ADC included in the SADC circuit 102 ′ can be used, and it can be realized in a ratio with the capacitance (CAP) CsI connected to the input terminal of the input signal Vin. For example, when Vcal = (1/4) · Vr, instead of setting the voltage Vcal in FIG. 13 to (1/4) · Vr, Vcal may be set to Vr and the CAP ratio may be set to 1: 4. .

In FIG. 13, the gain of Gain-AMP 12 is adjusted. However, the gain is not limited to this. For example, the gain of MDAC-AMP 11 may be adjusted.
FIG. 14 is a diagram showing an input signal and a transfer function (input / output characteristics) of the SADC circuit 102 ′ when the random variable PN is added to the input signal Vin in the random signal addition type calibration apparatus of FIG. is there. In FIG. 14, the horizontal axis represents the input signal to the SADC circuit 102 ', and the vertical axis represents the output.

In FIG. 14, the input signal when adding the random variable PN = 1 and the input signal when adding the random variable PN = −1 are shown together. Note that the position indicated by “Δ” in FIG. 14 represents the threshold value of the SADC circuit 102, and the transfer function and the threshold value are the same in the case of PN = 1 and PN = −1.
Even if the transfer function is the same, if the output varies depending on the random variable PN, an error component remains as a result if they are added over a long period of time.

On the other hand, even if the random variable PN fluctuates, if the output is the same, even if it is added over a long period, it is canceled out and no error remains.
In the calibration apparatus shown in FIG. 13, similarly to the calibration apparatus shown in FIG. 7, an area (time) in which error signals are integrated by using the back-end ADC 52 and an area in which error signals are not integrated. By distinguishing from (time) and accumulating only the area where error signals are accumulated by the accumulator 21, the calibration time can be shortened.

  As described above, according to the present invention, even when the circuit for extracting the voltage at the summing point Psum is realized by the gain-AMP 12 having a simple configuration, a high-accuracy gain is realized regardless of variations in the operating environment and the manufacturing process. it can.

<Configuration diagram showing another application example of calibration apparatus using random signal system>
Next, another application example of the calibration apparatus will be described.
FIG. 15 is a detailed configuration diagram illustrating another application example of the calibration apparatus using the random signal addition method.
The calibration apparatus shown in FIG. 15 performs gain adjustment in the sample hold circuit of the A / D converter, not in the pipeline type A / D converter. In FIG. 15, the input described in FIG. Calibration is performed by adding a random signal to the signal Vin.

  That is, the calibration apparatus shown in FIG. 15 uses an ADC (A / D converter 1) instead of the pipeline A / D converter 1 including the stage unit 51 including Stage 1 and the Backend ADC 52 including Stages thereafter. / D converter) 212 is for adjusting the gain of the sample hold circuit 211. This calibration apparatus is further provided with a level determination circuit 217 in the calibration apparatus shown in FIG.

Note that components having the same functions as those of the calibration apparatus shown in FIG. 13 are denoted by the same reference numerals and description thereof is omitted.
FIG. 15 is a block diagram illustrating an example of a calibration device for performing background calibration on the sample hold circuit 211.
As shown in FIG. 15, the sample hold circuit 211 includes an AMP 221, a gain-AMP 12, a capacitor 222 that connects the output terminal and the inverting input terminal of the AMP 221, one end connected to the input terminal of the input signal Vin, and the other end. Includes a sampling capacitor 223 connected to the inverting input terminal of the AMP 221 and the input terminal of the Gain-AMP 12, and further, a capacity as a multiplier 31 and an adder 32 that multiplies the voltage Vcal and the random variable PN. And comprising. A capacitor 213 for connecting the sample hold circuit 211 and the ADC 212 is connected between the output terminal of the AMP 221 and the output terminal of the Gain-AMP 12.

  The calibration apparatus shown in FIG. 15 includes a multiplier 33 that multiplies the voltage Vcal and the random variable “−PN” in the subsequent stage of the ADC 212 as the Backend ADC, an output Vout (ADC) of the ADC 212 as the Backend ADC, and a multiplier. And an adder 34 for adding the outputs of 33.

  Then, the output from the ADC 212 is added by the adder 34 to the calculation result of the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN”, and the addition result and the random variable PN are added by the multiplier 35. Multiply. The calculation result in the multiplier 35 is accumulated as an error signal Verr by the accumulator 21, and the up / down counter 22 can consider that the accumulated value is smaller than zero, that is, 1 / f 'is larger than 1 / f. Accordingly, a command signal is output to the DAC 23, and the DAC 23 adjusts the current values of the current sources I1 to I3 of the Gain-AMP 12 according to the command signal of the up / down counter 22.

In FIG. 15, the gain of Gain-AMP 12 is adjusted. However, the gain is not limited to this. For example, the gain of AMP 221 of sample hold circuit 211 may be adjusted, or a capacitor included in sample hold circuit 211 may be used. It is also possible to adjust.
Further, the level determination circuit 217 is configured by, for example, an ADC, and distinguishes between a region (time) in which error signals are integrated and a region (time) in which error signals are not integrated, similarly to the back-end ADC 52 in FIG.

If the input signal Vin corresponds to a region (time) in which the error signal is not integrated from the determination result of the level determination circuit 217, the accumulator 21 does not integrate.
In this way, the calibration apparatus shown in FIG. 15 also uses the level determination circuit 217 and the area (time) where error signals are integrated and the area (time) where integration is not performed, similarly to the calibration apparatus shown in FIG. And the accumulator 21 accumulates only the area where the error signal is accumulated, so that the calibration time can be shortened.
As described above, even when applied to the sample-and-hold circuit 211, a high-accuracy gain can be realized regardless of variations in operating environment and manufacturing process.

<Improvement of calibration method>
<Examination of improved error insertion method for all input ranges>
The present inventor further studied improvements on the above-described calibration method.
That is, in the calibration method by the calibration apparatus using the threshold fluctuation method shown in FIG. 7 described above, as shown in FIG. 12A, errors are integrated regardless of the voltage input at any voltage in the entire input range. It is constituted so that.
FIG. 16 shows an example of the transfer function (input / output characteristics) of the calibration device using the threshold variation method when there is a general error, and the characteristic line L1 in the figure is the actual transfer function when there is an error. (Input / output characteristics). The characteristic line L2 is a transfer function (input / output characteristics) when there is no error. The solid line represents the transfer function when PN = 1, and the broken line represents the transfer function when PN = -1.

In FIG. 16, for example, when the input signal is Example 3, the error signal to be extracted is a voltage corresponding to the error (Example 3) shown in the figure. When the input signal is Example 4, the error signal to be extracted is a voltage corresponding to the error (Example 4) shown in the figure. That is, it can be seen that the error amount is constant regardless of the input signal when the output signal has the same voltage. On the other hand, the signal accumulated by the accumulator 21 can be expressed by the following equation.
(Error amount to be integrated) = Σ [(Error signal) / (Input signal)]

  For this reason, when errors are accumulated over the entire input range, when the input signal is large, the signal that can be accumulated by the accumulator 21 is relative even though the magnitude of the error signal is the same as when the input signal is small. Will become smaller. If the signal accumulated by the accumulator 21 becomes smaller, the accumulated time must be lengthened accordingly.

<Circuit configuration / transfer function configuration diagram of calibration device for shortening calibration time>
<Improvement of calibration method by threshold fluctuation method>
In view of the above, a more efficient calibration method will be described below.
FIG. 17 is a diagram schematically illustrating a part of the ADC 102a included in the SADC circuit 102 of Stage 1 when the MDAC 110 illustrated in FIG. 7 is a 2.5-bit MDAC.
The ADC included in the SADC circuit 102 according to the present invention includes comparators 171 to 177 as shown in FIG.

  The comparator 174 switches the voltage to be compared with a random signal. That is, when the random variable PN = 1, the input signal Vin is compared with the reference voltage (1/16) · Vr. On the other hand, when the random variable PN = −1, the input signal Vin is compared with the reference voltage (−1/16) · Vr. Vr is the maximum input range of the input signal Vin. The other comparators 171 to 173 and 175 to 177 have a constant voltage to be compared with the input signal Vin regardless of the random signal. That is, the comparator 171 compares the input signal Vin with 3/4 · Vr. Similarly, the comparator 172 is (1/2) · Vr, the comparator 173 is (1/4) · Vr, the comparator 175 is (−1/4) · Vr, the comparator 176 is (−1/2) · Vr, the comparator 177 compares (−3/4) · Vr with the input signal Vin.

The ADC included in the SADC circuit 102 according to the present invention shown in FIG. 17 is such that, as shown in FIG. 10, in the ADC, the voltages to be compared are changed by random variables in all the comparators, but only one comparator at the center. There is a feature in replacing.
FIG. 18 is a diagram showing transfer functions (input / output characteristics) of Stage 1 and Stage 2 in an ideal case where there are no offsets in the comparators 171 to 177 included in the SADC circuit 102 that adds the random variable PN shown in FIG. is there.

In FIG. 18, the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = 1, and the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = −1. Is also written.
In the diagram showing the transfer function of Stage 1 (the diagram on the left side of FIG. 18A), the horizontal axis represents the input to the SADC circuit 102, the vertical axis represents the output, and the value indicated by “Δ” on the horizontal axis is: This represents the threshold value of the SADC circuit 102 of Stage1. The solid line represents the transfer function when PN = 1, and the broken line represents the transfer function when PN = -1. For each of the cases of PN = 1 and PN = −1, the input signal to the SADC circuit 102 and each segment seg. 0 to seg. 7 is represented.

In the diagram showing the transfer function of Stage 2 (the diagram on the right side of FIG. 18A), the horizontal axis represents the output of the SADC circuit 102 of Stage 2, the vertical axis represents the input of the SADC circuit 102 of Stage 2, and the vertical axis The value indicated by “Δ” indicates the threshold value of the SADC circuit 102 of Stage2.
It can be seen that FIG. 12A replaces the voltages to be compared by random variables in all the comparators, whereas FIG. 18A replaces only one central comparator.

  In FIG. 18 (a), regions not affected by the random variable PN are locations other than Stage-1 input (-1/4) · Vr to (1/4) · Vr and (-1/4) · Vr. Among the locations corresponding to .about. (1/4) .multidot.Vr, this corresponds to (-1/4) .multidot.Vr.about. (-1/4) .multidot. (1/4) .multidot.Vr of Stage 2 input (= stage 1 output). A determination circuit (not shown) determines a region (time) in which this region is error-integrated, and distinguishes a region (time) that has not been error-integrated (time), thereby distinguishing the region in which error is integrated. Only the accumulator 21 is integrated.

As described above, since the accumulator 21 accumulates only the region where the error is accumulated, it is not necessary to integrate the input signal unnecessary for the error accumulation as much as possible, and the accumulation ratio of the relatively necessary error signal is relatively high. That is, since the ratio of error components in the integrated signal increases, it is easy to extract error components even if the integration time is relatively short.
Here, the reason that the Stage1 input is other than (−1/4) · Vr to (1/4) · Vr is that the input signal input to Stage1 is divided into a plurality of parts as shown in FIG. In each segment, segment Seg. 0 to segment Seg. 2 and segment Seg. 5 to segment Seg. It's 7th. Further, among the places where the Stage 1 input corresponds to (−1/4) · Vr to (1/4) · Vr, the Stage 2 input (= Stage 1 output) is (−1/4) · Vr to (1/4). As shown in FIG. 12 (a), Vr becomes the segment Seg. In each Segment obtained by dividing the input signal input to Stage2 into a plurality of segments. 3 and segment Seg. 2 when the output is 0 or more, the segment Seg. 4 when the output is 0 or less.

  Whether the output is 0 or more or 0 or less can be determined from the AD conversion result of the back-end Back ADC 42 included in the threshold value fluctuation type calibration apparatus shown in FIG. Do not accumulate. Thus, instead of adding a new determination circuit, it is possible to use the AD conversion results in Stage 1 and the back-end ADC 42 in the subsequent stage.

Further, as shown in FIG. 18B, the above method can be performed in the same way even in the case of an actual comparator in which the comparators 171 to 177 included in the SADC circuit 102 have an offset.
Here, the number of integrations generally required for calibration can be expressed by the following equation.

n> [(input signal to be integrated) / (error amount to be integrated)] ²
For example, as shown in FIG. 12A, the voltage to be compared in all the comparators is changed according to the random variable PN, and as shown in FIG. 18A, the voltage to be compared with only one central comparator is used. When comparing with the replacement method, there is no difference in the error amount to be integrated, but the input signal to be integrated is smaller to 1/7 in the method of FIG. On the other hand, the area in which errors are not integrated is wider in the method of FIG. 18A, and the appearance probability of the area in which errors are integrated decreases. Assuming that the input signal is random, its appearance probability is 1/7.

Therefore, the necessary number of times of integration is n> (appearance probability ratio) × (input signal ratio to be integrated) ² = 7 × (1/7) ² = 1/7
Thus, the number of integrations may be 1/7 times less in the method of FIG.
In the above description, only the comparator 174 to be compared with the center value of the input signal is changed by the random signal PN. However, the present invention is not limited to this.

  For example, only the comparator 171 in FIG. 17 may be changed by the random signal PN. For example, when PN = −1, it is changed to (11/16) · Vr, and when PN = 1, it is changed to (13/16) · Vr. In this case, the input signal to be integrated becomes a large value of (11/16) · Vr to (13/16) / Vr. However, since the input signal to be integrated is known in advance, If the minutes are subtracted, the number of integrations is the same as when only the comparator to be compared with the center value of the input signal is changed by the random signal PN. For example, in the previous example, if (3/4) · Vr is subtracted when integrating in advance, the input signal to be integrated is (−1/16) · Vr to (1/16) · Vr. Become.

  This is because, for example, it is known that a certain signal is periodically input, such as a video signal, and if the signal input to Stage1 is known to have a high probability of appearing in a certain segment, integration is performed. More efficient integration is possible by increasing the appearance probability without increasing the input signal.

<Improvement of calibration method of random signal addition method>
<Detailed configuration diagram (improved) showing an example of a calibration apparatus using a random signal addition method>
FIG. 19 is a detailed configuration diagram illustrating an example of a calibration apparatus using a random signal addition method that adds a random signal to the input signal described with reference to FIG. 5. As in the above, more efficient calibration is performed. It is an example of the calibration apparatus for implement | achieving.

  19, the calibration device using the random signal addition method according to the present invention is a digital device that is the calculation result of the ADC 102 a of the SADC circuit 102 ′, compared with the calibration device using the general random signal addition method shown in FIG. 13. A comparator 61 that monitors the signal Digital1 and compares whether the digital signal Digital1 is equal to “0”, and a coefficient for multiplying the random signal by the multiplier 31 and the multiplier 33 according to the comparison result of the comparator 61. The difference is that the switches SW1 and SW2 are switched between “voltage Vcal” and “0”.

  When the comparison results of the comparator 61 are not equal, the change-over switches SW1 and SW2 set the voltage Vcal as a coefficient for multiplying the random signal (PN or −PN) by the multipliers 31 and 32, and the comparison result of the comparator 61 When equal, that is, when the digital signal Digital1 is “0”, “0” is set as a coefficient for multiplying the random signal (PN or −PN) by the multiplier 31 or 32.

In FIG. 19, components having the same functions as those of the calibration apparatus shown in FIG. 13 are denoted by the same reference numerals, and description thereof is omitted.
As shown in FIG. 19, the pipeline type A / D converter 1 includes a stage unit 51 including Stage 1 (unit block 100 (1)) and unit blocks (100 (2) to 100 (N) from Stage 2 to Stage N. )) Including a Backend ADC 52.

The stage unit 51 includes an MDAC 110 and a SADC circuit 102 ′.
The SADC circuit 102 'includes an ADC 102a and a DAC 102b to which an input signal Vin is input, a multiplier 31 that multiplies the voltage Vcal and the random variable PN, and a multiplication result of the multiplier 31 is added to the input signal Vin. And a capacity as an adder 32.

  The multipliers 31 and 33 for inputting random signals shown in FIG. 19 add a random signal (PN × Vcal) to the input signal Vin when the digital signal Digital1 as the calculation result of the ADC 102a is equal to “0”. When the digital signal Digital1 which is the calculation result of the ADC 102a is not equal to “0”, PN × 0, that is, “0” is added to the adder 32, and therefore no random signal is added to the input signal Vin. This makes it possible to add a random signal only in a segment where the input signal Vin is close to “0”.

  The calibration apparatus shown in FIG. 19 adds the random signal (PN × Vcal) to the input signal Vin only when the digital signal Digital1 that is the calculation result of the ADC 102a is equal to “0”, and the amplitude of the input signal Vin is increased. Change the calibration. When the digital signal Digital1 that is the calculation result of the ADC 102a is not equal to “0”, PN × 0, that is, “0” is added to the adder 32, so that the random signal is not added to the input signal Vin and is output as it is. Is done.

The MDAC 110 has the same configuration as the MDAC 110 shown in FIG.
Further, when the digital signal Digital1 that is the operation result of the ADC 102a is equal to “0”, the output Vout output from the Backend ADC 52 is added to the operation result in the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN”. (ADC) is added by the adder 34, and the addition result and the random variable PN are multiplied by the multiplier 35. The calculation result in the multiplier 35 is used as an error signal Verr, and the error signal Verr is integrated by the accumulator 21. In the up / down counter 22, the integrated value is smaller than zero, that is, 1 / f ′ is larger than 1 / f. A command signal is output to the DAC 23 according to whether it can be considered, and the DAC 23 adjusts the current values of the current sources I1 to I3 of the Gain-AMP 12 according to the command signal of the up / down counter 22. The accumulator 21 can perform more efficient integration by integrating only when the digital signal Digital1 that is the calculation result of the ADC 102a is equal to “0”.

In FIG. 19, addition in the analog unit is realized by charging the capacitor as the adder 32 with a voltage of Vcal × PN. However, the present invention is not limited to this, and the adder is replaced with a capacitor. It may be used.
Further, instead of the voltage Vcal, the reference voltage Vr used in the comparator of the ADC included in the SADC circuit 102 can be used, and it can be realized by a ratio with the capacitance (CAP) CsI connected to the input terminal of the input signal Vin. For example, when Vcal = (1/4) · Vr, instead of setting the voltage Vcal in FIG. 19 to (1/4) · Vr, Vcal may be set to Vr and the CAP ratio may be set to 1: 4. .

  In the above example, the random signal is added when the digital signal Digital1 that is the calculation result of the ADC 102a is equal to “0”. However, the present invention is not limited to this, and the probability that the input signal appears in a certain segment is high. When the input signal Vin enters the segment, the random signal is added to increase the appearance probability and more efficient integration is possible.

In FIG. 19, the gain of Gain-AMP 12 is adjusted. However, the present invention is not limited to this. For example, the gain of MDAC-AMP 11 may be adjusted.
FIG. 20 is a diagram illustrating an input signal and a transfer function (input / output characteristics) of the SADC circuit 102 ′ when the random variable PN is added to the input signal Vin. In FIG. 20, the horizontal axis represents the input signal to the SADC circuit 102 ', and the vertical axis represents the output.

In FIG. 20, the input signal when adding the random variable PN = 1 and the input signal when adding the random variable PN = −1 are shown together. Note that the position indicated by “Δ” in FIG. 20 represents the threshold value of the SADC circuit 102 ′, and the transfer function is the same and the threshold value is the same as in the case of PN = 1 and PN = −1.
Even if the transfer function is the same, if the output varies depending on the random variable PN, an error component remains as a result if they are added over a long period of time.

On the other hand, even if the random variable PN fluctuates, if the output is the same, even if it is added over a long period, it is canceled out and no error remains.
In the calibration apparatus using the random signal addition method shown in FIG. 19, the error signal is integrated by using the back-end ADC 52, as in the calibration apparatus using the threshold value fluctuation method shown in FIG. 7 having the configuration shown in FIG. It is possible to shorten the calibration time by distinguishing the area (time) in which the error signal is not accumulated and the area (time) in which the error signal is not accumulated, and accumulating only the area where the error signal is accumulated. it can.

As described above, according to the present invention, even when the circuit for extracting the voltage at the summing point Psum is realized by the gain-AMP 12 having a simple configuration, a high-accuracy gain is realized regardless of variations in the operating environment and the manufacturing process. it can.
In the above embodiment, the sample hold circuit calibration method according to the present invention is applied to a pipelined A / D converter or a sample hold circuit of an A / D converter. However, the present invention is not limited to this. For example, a ΔΣ A / D converter can be applied.
In addition, the scope of the present invention is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that provide the same effects as those intended by the present invention. Furthermore, the scope of the invention is not limited to the combinations of features of the invention defined by the claims, but can be defined by any desired combination of particular features among all the disclosed features.

1 Pipeline A / D Converter 11 MDAC-AMP
12 Gain-AMP
21 accumulator
22 Up / Down Counter (up / dn counter)
23 DAC (DA converter)
31, 33, 35 Multiplier 32, 34 Adder 61 Comparator 102, 102 'SADC (sub AD converter) circuit 102a ADC
110 MDAC (Multiplication type digital analog converter)
171 to 177 Comparator 211 Sample hold circuit 212 A / D converter SW1, SW2 changeover switch Mx1, Mx2, My1, My2 MOS transistors I1, I2, I3 Current source

Claims (19)

Only the analog signal of a predetermined amplitude among the analog signals to be converted is varied with a random variable, and the converted analog signal to be converted is converted into a digital signal by a sample and hold circuit,
Multiply the converted digital signal by the random variable and integrate the multiplied signal.
The sample-and-hold circuit calibration method, wherein the integration result is used as an error signal when the analog signal to be converted is converted into a digital signal.   2. The method of calibrating a sample-and-hold circuit according to claim 1, wherein the analog signal having the predetermined amplitude is an analog signal having an amplitude close to zero.   2. The method of calibrating a sample and hold circuit according to claim 1, wherein the analog signal having a predetermined amplitude is an analog signal having a constant amplitude that is periodically input. Determine whether the analog signal to be converted is a value within a preset error integration region,
When it is determined that the analog signal to be converted is not a value within the error integration region, the multiplication signal is not integrated, and only when it is determined that the analog signal to be converted is a value within the error integration region The sample-hold circuit calibration method according to any one of claims 1 to 3, wherein the multiplication signals are integrated. Whether the analog signal to be converted is a value within the error integration region,
5. The calibration method for a sample and hold circuit according to claim 4, wherein the determination is based on the analog signal to be converted or a digital signal obtained by converting the analog signal to be converted.   6. The calibration of the sample-and-hold circuit according to claim 4, wherein when it is determined that the analog signal to be converted is not a value within the error integration region, the previous integration result is held. Method. The sample and hold circuit has an amplifier,
7. The sample hold circuit calibration method according to claim 1, wherein the gain of the amplifier is adjusted based on the error signal.   8. The sample hold circuit calibration method according to claim 7, wherein the amplifier is a gain amplifier. The sample and hold circuit includes a multiplying digital-to-analog converter having an amplifier,
8. The method of calibrating a sample and hold circuit according to claim 7, wherein a gain of an amplifier included in the multiplying digital-analog converter is adjusted based on the error signal.   8. The sample hold circuit calibration method according to claim 7, wherein a gain of a main amplifier among amplifiers included in the sample hold circuit is adjusted based on the error signal. Random variation unit that varies the amplitude with a random variable only for analog signals of a predetermined amplitude among the analog signals to be converted,
A multiplying unit that multiplies the random variable by a conversion result obtained by converting the analog signal to be converted whose amplitude has been changed by the random changing unit into a digital signal by a sample and hold circuit;
An integration unit for integrating the multiplication results in the multiplication unit;
A calibration apparatus comprising:   12. The calibration apparatus according to claim 11, wherein the analog signal having the predetermined amplitude is an analog signal having an amplitude close to zero.   The calibration apparatus according to claim 11, wherein the analog signal having a predetermined amplitude is an analog signal having a constant amplitude that is periodically input. The integrating unit is
Determine whether the analog signal to be converted is a value within a preset error integration region,
When it is determined that the analog signal to be converted is not a value in the error region, the multiplication results in the multiplication unit are not integrated, and it is determined that the analog signal to be converted is a value in the error integration region 14. The calibration apparatus according to claim 11, wherein the multiplication results in the multiplication unit are integrated only when the multiplication is performed. The sample and hold circuit has an amplifier,
The adjustment part which adjusts the gain of the said amplifier based on the said integration result by using the integration result of the said integration part as an error signal in the said sample-and-hold circuit, The any one of Claim 11-14 characterized by the above-mentioned. The calibration device described in 1.   The calibration apparatus according to claim 15, wherein the amplifier is a gain amplifier. The sample and hold circuit includes a multiplying digital-to-analog converter having an amplifier,
The calibration device according to claim 15, wherein the adjustment unit adjusts a gain of an amplifier included in the multiplying digital-analog converter based on the error signal.   The calibration device according to claim 15, wherein the adjustment unit adjusts a gain of a main amplifier among amplifiers included in the sample hold circuit based on the error signal.   A sample-and-hold circuit comprising the calibration device according to claim 11.

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