JP2015097333A - Sample and hold circuit and a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve higher gain characteristics of a sample and hold circuit.SOLUTION: A multiplication-type DA converter (MDAC) 110 of a pipeline-type A/D converter 1 includes sampling capacitors CsI, an MDAC-AMP 11 in which the sampling capacitors CsI are connected to an input terminal, and a summing point monitoring (SPM) unit 12 connected to the MDAC-AMP 11. The SPM unit 12 includes an ADC 12a having an input terminal connected to a summing point and a DAC 12b connected to an output terminal of the ADC 12a. The SPM unit 12 monitors a voltage at the summing point in a hold phase, and supplies the monitoring result to sampling capacitors CsI+2 included in a sample and hold circuit at the stage after the next.

Description

  The present invention relates to a sample-and-hold circuit and an A / D converter, and more specifically, a circuit for converting an input signal to output using amplification by an operational amplifier, that is, for example, a pipeline type A / D converter, Further, the present invention relates to a ΔΣ A / D converter and the like, and a sample hold circuit and a multiple DAC (MDAC: multiplication type DA converter (digital analog converter)) included therein.

An example of the sample and hold circuit is a pipeline A / D converter. As this pipeline type A / D converter 10, for example, a circuit shown in FIG. 18 is known (see, for example, Patent Document 1).
FIG. 18 is a schematic configuration diagram illustrating an example of the pipeline type A / D converter 10.
As shown in FIG. 18, the pipeline type A / D converter 10 includes N-stage unit blocks 100 (1) to 100 (N) cascaded from Stage 1 to Stage N.

Since the unit blocks 100 (1) to 100 (N) have the same configuration, the configuration of StageI (unit block 100 (I)) will be described here.
As shown in FIG. 18, Stage I includes an SSH (subsample hold) circuit 101, a SADC (sub AD converter) circuit 102, a DAC (D / A converter) circuit 103, and an adder 104. Is done.

The Stage I SSH circuit 101 takes in the analog output signal Residue I-1 output from the previous unit block Stage I-1.
The SADC circuit 102 performs A / D conversion of the analog output signal ResidueI-1 captured by the SSH circuit 101 into a digital signal DigitalI. This digital signal DigitalI is output as an output signal (DigitalI) of StageI. The digital signal DigitalI output from the SADC circuit 102 is added together with the digital signals DigitalI output from the SADC circuits 102 of Stage1 to StageN according to a predetermined rule, and the result represents the result of A / D conversion. Output as a digital output signal.

The DAC circuit 103 generates an analog signal corresponding to the digital signal DigitalI from the SADC circuit 102 and outputs the analog signal to the adder 104.
The adder 104 subtracts the analog signal generated by the DAC circuit 103 from the analog signal captured by the SSH circuit 101, and outputs the analog signal as a subtraction result to the next unit block Stage I + 1 as Residue I as a residual signal. It has become. At this time, the analog signal (Residue I) as a residual signal obtained by subtracting by the adder 104 is amplified by a predetermined factor, so that the required accuracy of the next unit block Stage I + 1 is not increased and the same unit block (Stage I) is amplified. ) A / D conversion is possible depending on the configuration, and high-precision A / D conversion is realized.

Incidentally, the SSH circuit 101, the DAC circuit 103, and the adder 104 are generally configured by a combination of one operational amplifier and a capacitor CAP. A circuit configured by combining the operational amplifier and the capacitor CAP is referred to as a multiple DAC (multiplying DA converter (digital analog converter), hereinafter also referred to as MDAC) 105.
FIG. 19 is a schematic configuration diagram illustrating an example of the MDAC 105.

  In FIG. 19, (a) shows the circuit configuration in the sample phase (SamplingPhase), and (b) shows the circuit configuration in the hold phase (HoldingPhase). The MDAC 105 implements the circuit of FIG. 19A in the sample phase and the circuit of FIG. 19B in the hold phase by switching a switch or the like (not shown) according to the converted clock signal CLK. Note that the variable I of CsI in FIG. 19A means Cs included in StageI.

  As shown in FIG. 19, the MDAC 105 includes a sampling capacitor CsI in which unit capacitors of the same size are combined in parallel, and an MDAC-AMP11 formed of an operational amplifier and a parasitic capacitance Cp present at the input terminal of the MDAC-AMP11. . The MDAC 105 operates so as to alternately realize the sample phase (FIG. 19A) and the hold phase (FIG. 19B) in accordance with the input conversion clock signal CLK.

  In the sample phase (FIG. 19A), the analog output signal ResidueI-1 of the previous unit block StageI-1 is charged in the sampling capacitor CsI. That is, the analog output signal ResidueI-1 is input to one end of the sampling capacitor CsI, and the other end is connected to the inverting input terminal of the MDAC-AMP11. At this time, the input end and output end of the MDAC-AMP 11 are short-circuited to the ground level. The parasitic capacitance Cp is similarly shorted to the ground level.

  On the other hand, in the hold phase (FIG. 19B), the output terminal and the inverting input terminal of the MDAC-AMP 11 are connected via the capacitor Cf. In addition, the capacitor Cr is set to any one of “+ Vr”, “0”, and “−Vr” for each of a plurality of unit capacitors included in the capacitor Cr according to the digital signal DigitalI output from the SADC circuit 102 of FIG. Connect to. That is, one end of the capacitor Cr is connected to any one of “+ Vr”, “0”, and “−Vr”, and the other end is connected to the inverting input terminal of the MDAC-AMP 11. Each of the capacitor Cf and the capacitor Cr includes a part of a plurality of unit capacitors included in the sampling capacitor CsI. That is, in the hold phase, the sampling capacitor CsI uses a part of the unit capacitance included in the sampling capacitor CsI as the capacitance Cf that connects the output end and the inverting input end of the MDAC-AMP 11 and the remaining unit capacitance as the capacitance Cr. Used. Here, the case where a part of the plurality of unit capacitors included in the sampling capacitor CsI is used as the capacitor Cf and the capacitor Cr has been described, but the present invention is not limited to this. For example, a plurality of unit capacitors included in the sampling capacitor CsI may be used as they are as the capacitor Cr, and the capacitor Cf may be provided separately.

  The output of the MDAC-AMP 11 is connected to the sampling capacitor CsI + 1 of the MDAC 105 included in the unit block StageI + 1 of the next stage, and the output of the MDAC-AMP11 of StageI is output to the sampling capacitor CsI + 1 of the next stage as an analog output signal ResidueI. . Further, the non-inverting input terminal of the MDAC-AMP 11 is maintained at the ground level.

At this time, when the DC (direct current) gain of the MDAC-AMP 11 is “a0”, the voltage Va at the inverting input terminal of the MDAC-AMP 11 is expressed by the following equation (1) using the voltage Vout at the output terminal of the MDAC-AMP 11. Can be represented.
Va = − (1 / a0) × Vout (1)
For example, when the voltages connected to the unit capacitors included in the capacitor Cr are all zero, the following equation (2) is established from the charge conservation law stored in the capacitors in the sample phase and the hold phase.
CsI × Vin
= Cf (Vout-Va) + Cr (0-Va) + Cp (0-Va) (2)

From the expressions (1) and (2), the output Residue I of the MDAC-AMP 11 in the hold phase, that is, the output Vout of the MDAC 105 can be expressed by the following expression (3).
Vout
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))} × Vin
...... (3)

Here, “a0” in the expression (3) represents the DC (direct current) gain of the MDAC-AMP 11 as described above. “F” is called a feedback factor of the MDAC-AMP 11 and can be expressed by the following equation (4) using the respective capacitances Cr, Cf, and Cp.
f = Cf / (Cr + Cf + Cp) (4)
In the transfer function represented by Expression (3), when input / output characteristics are ideal, Expression (3) can be expressed as the following Expression (5).
Vout = (CsI / Cf) × Vin (5)
From formulas (3) and (5), it can be seen that DCGain “a0” of MDAC-AMP11 needs to be large to infinity in order to obtain ideal input / output characteristics.

In practice, DCGain “a0” is increased according to the required accuracy.
In general, in order to increase the DCGain of AMP, it is necessary to make it multistage or cascode. Therefore, it becomes a problem that it is difficult to maintain good stability or the output amplitude is limited.
In order to solve this problem, a method called Summing Point Monitoring (hereinafter referred to as SPM) has been devised as a method of obtaining MDAC-AMP 11 having high gain characteristics without increasing DCGain “a0”.

FIG. 20 is an example of a specific circuit of the multiplication type DA converter of FIG.
FIGS. 20A and 20B are examples of specific circuits for realizing the SPM. FIG. 20A shows a circuit configuration in the sample phase, and FIG. 20B shows a circuit configuration in the hold phase.
This circuit corrects an error occurring in the MDAC-AMP 11 by taking out the summing point (summing point) Psum of the MDAC-AMP 11 in FIG. 20B by the Gain-AMP 12.

FIG. 20C is another example of a specific circuit for realizing SPM (for example, see Non-Patent Document 1).
In this circuit, after sampling by the capacitor Ce1, it is transferred to the “Gain + ADC unit” by the capacitor Ce2, and the average value of the output voltage at the summing point is AD-converted by the low-speed AD converter 12, and then the AD converter 11 of the main path. This is a discrete SC (switched capacitor) circuit that corrects the result of the above.

JP 2012-60519 A

“A 16-bit 250-MS / s IF Sampling Pipelined ADC With Background Calibration”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010, p. 2602-p. 2612

However, when the average value is corrected in this way, the linear distortion component of the main path can be corrected. However, since high-order distortion cannot be corrected, high-accuracy conversion cannot be performed.
The present invention has been made in view of such problems, and in a sample-and-hold circuit in which a gain characteristic of a DA conversion amplifier generates high-order distortion, a sample capable of realizing higher gain characteristics. An object of the present invention is to provide a hold circuit and an A / D converter.

  One embodiment of the present invention includes a sampling capacitor (for example, the sampling capacitor CsI illustrated in FIG. 5) and an amplifier (for example, the MDAC-AMPI illustrated in FIG. 5) to which the sampling capacitor is connected to the input terminal. A sample-and-hold circuit that includes a computing unit (for example, SPM unit 12 shown in FIG. 5) and supplies the output of the amplifier to a sample-and-hold circuit in the next stage; The other sampling and holding circuit of one stage or a plurality of stages is connected, and the arithmetic unit monitors a voltage at a summing point that is a connection point of the sampling capacitor at an input terminal of the amplifier during the hold phase, and the summing The monitoring result of the voltage at the point is (Shown in FIG. 5, for example, the sampling capacitor CsI + 2) sampling capacitors included in one of the sample-and-hold circuit in the Chi sample phase is a sample-hold circuit, characterized in that the supply to the.

It may be a hold phase when the one sample and hold circuit is in the sample phase, and a sample phase when the one sample and hold circuit is in the hold phase.
The one sample-and-hold circuit may be a sample-and-hold circuit in the next stage of the next-stage sample-and-hold circuit.

The arithmetic unit may include an AD converter (for example, ADC 12a shown in FIG. 3) and a DA converter (for example, DAC 12b shown in FIG. 3) connected to the output terminal of the AD converter.
The AD converter may have an input terminal connected to the summing point, and the DA converter may have an output terminal connected to a sampling capacitor included in the one sample hold circuit.

The calculation unit may be configured to change a gain.
Another aspect of the present invention is an A / D converter characterized by using the sample and hold circuit according to any one of the above aspects.

  According to one embodiment of the present invention, analog-to-digital conversion can be performed with higher accuracy even when the DA conversion amplifier generates high-order distortion. Further, since it can be realized with a relatively simple configuration, power consumption can be reduced, and the gain characteristic of the DA conversion amplifier can be kept low, that is, the DA conversion amplifier has a simple configuration. Therefore, the power supply voltage can be reduced, and power consumption can be suppressed accordingly.

  Even when the circuit for extracting the summing point is realized with a simple configuration, a gain with high accuracy can be realized regardless of variations in the operating environment and the manufacturing process.

It is a schematic block diagram which shows an example of a pipeline type A / D converter. It is a block diagram which shows an example of the multiplication type DA converter using SPM. It is a conceptual diagram which shows an example of a SPM part. It is a conceptual diagram which shows the specific example of a SPM part. It is a block diagram which shows an example of the multiplication type DA converter using SPM in this invention. It is a block diagram which shows an example of the multiplication type DA converter using SPM in this invention. It is a schematic block diagram which shows an example of the calibration apparatus of a random signal addition system. It is a schematic block diagram which shows an example of the calibration apparatus of a threshold value fluctuation system. It is a conceptual diagram which shows an example of a more detailed structure of the calibration apparatus of a threshold value fluctuation system. It is a figure which shows typically a part of ADC contained in the SADC circuit of the calibration apparatus of a threshold value fluctuation system. It is a figure which shows an example of the transfer function (input / output characteristic) of a SADC circuit when not adding a random signal. It is a figure which shows typically a part of ADC contained in the SADC circuit of Stage1 at the time of using a 2.5-bit multiplication type DA converter. It is a figure which shows an example of the transfer function (input / output characteristic) of a SADC circuit in the case of adding a random signal. (A) is a figure which shows the transfer function (input / output characteristic) of Stage1 and Stage2 in the ideal case where there is no Offset in the comparator of the SADC circuit, and (b) is a case where there is Offset in the comparator of the SADC circuit It is a figure which shows the transfer function (input / output characteristic) of Stage1 and Stage2. It is a conceptual diagram which shows an example of a more detailed structure of the calibration apparatus of a random signal addition system. It is a figure which shows an example of the input signal and transfer function (input / output characteristic) of a SADC circuit when adding a random signal. It is a detailed block diagram which shows the modification of the calibration apparatus of a random signal addition system. It is a schematic block diagram which shows an example of a pipeline type A / D converter. It is a schematic block diagram which shows an example of a multiplication type DA converter. It is an example of the specific circuit of a multiplication type DA converter.

Embodiments of the present invention will be described below. In the following description, a pipeline type A / D converter in which each stage has a 2.5 bit configuration will be described as an example. However, the present invention is not limited to this, and may not be 2.5 bit. It does not have to be a / D converter.
<Configuration of pipeline type A / D converter>
FIG. 1 is a conceptual diagram showing an example of a pipeline type A / D converter 1 to which the present invention is applied.

  The pipeline type A / D converter 1 shown in FIG. 1 is different from the pipeline type A / D converter 10 shown in FIG. 18 in that an MDAC 110 is provided instead of the MDAC 105. In the pipeline type A / D converter 1 shown in FIG. 1, components having the same functions as those in the pipeline type A / D converter 10 shown in FIG. Omitted.

Next, the concept of SPM in the present invention will be described.
FIG. 2 is a schematic configuration diagram illustrating an example of the MDAC 110 using the SPM.
As shown in FIG. 2, the SPM is an SPM for monitoring the voltage Va at the input end of the MDAC-AMP 11 called a summing point (summing point) Psum with respect to a normal DAC and adjusting it to a desired gain. Part 12 is used.

  The input end of the SPM unit 12 is shorted to the ground level in the sample phase, and is connected to the summing point Psum in the hold phase. The output end of the SPM unit 12 is shorted to the ground level in the sample phase, and the next stage in the hold phase. It is characterized in that it is connected to the sampling capacitor CsI + 1 of the MDAC 110 included in the unit block StageI + 1. That is, by alternately repeating the sample phase (FIG. 2A) and the hold phase (FIG. 2B), the voltage Va at the summing point Psum is detected and amplified by the SPM unit 12, that is, (1 / f ′) × Va is stored in the sampling capacitor CsI + 1 at the next stage. “1 / f ′” is the gain of the SPM unit 12.

The output Vout (MDAC) of the MDAC-AMP 11 in the MDAC 110 using the SPM shown in FIG. 2 is the same as the output Vout of the MDAC-AMP 11 in the MDAC 105 shown in FIG. ) Expression can be expressed by the following expression (6).
Vout (MDAC)
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))} × Vin
...... (6)
On the other hand, the output Vout (SPM) of the SPM unit 12 can be expressed by the following equation (7) when the gain of the SPM unit 12 is “1 / f ′”.
Vout (SPM)
= (1 / f ') x Va
= -1 / (a0 * f ') * Vout (MDAC) (7)

  In the MDAC 110 using the SPM shown in FIG. 2, the difference between the output Vout (MDAC) of the MDAC-AMP 11 and the output Vout (SPM) of the SPM unit 12 is the total output of the unit block StageI. Can be expressed by the following equation (8).

Vout
= Vout (MDAC) -Vout (SPM)
= Vout (MDAC) + 1 / (a0 * f ') * Vout (MDAC)
= (CsI / Cf) × {1 / (1 + 1 / (a0 × f))}
× {1 + 1 / (a0 × f ′)} × Vin (8)
Here, when “f ′” is equal to “f”, the equation (8) can be expressed as the following equation (9).
Vout = (CsI / Cf) × Vin (9)
From Expression (9), it can be seen that the output Vout of the unit block StageI in the SPM does not depend on the DCGain “a0” of the MDAC-AMP11. That is, it is possible to maintain high gain characteristics even when DCGain “a0” has a high-order distortion component.

<Conceptual diagram of the SPM unit 12>
FIG. 3 is a conceptual diagram showing an example of the SPM unit 12 included in the pipeline type A / D converter 1 (FIG. 1) according to the present invention. The SPM unit 12 according to the present invention includes an ADC 12a that performs AD conversion and a DAC 12b that performs DA conversion on the output of the ADC 12a.
FIG. 4 is a conceptual diagram showing a more specific example of the ADC 12a and the DAC 12b included in the SPM unit 12 of FIG.
The pipeline type A / D converter 1 according to the present invention includes the MDAC 110 shown in FIG. 2 as the MDAC for the Stage 1 (100 (1)), and the ADC 12a and the DAC 12b shown in FIG. And are used. For Stage2 (100 (2)) to StageN (100 (N)), the MDAC 105 that does not have the SPM unit 12 shown in FIG. 19 is mounted.

  That is, in the pipeline type A / D converter 1, DCGain “a0” having the highest Stage1 (100 (1)) is required. Therefore, in the present embodiment, the MDAC 110 shown in FIG. 2 is mounted as the MDAC only for Stage 1 (100 (1)), and the ADC and DAC shown in FIG. The MDAC 110 shown in FIG. 2 is mounted as an MDAC for all the Stage 1 (100 (1)) to Stage N (100 (N)) or any of a plurality of Stages, and the SPM unit 12 is illustrated as the SPM unit 12. It is also possible to use the ADC and DAC shown in FIG.

  As shown in FIG. 4, the ADC 12a and the DAC 12b included in the SPM unit 12 according to the present invention are connected to the summing point Psum, and a plurality of comparators (Comp. Comp.) For comparing the voltage Va of the summing point Psum with different voltages. 1 to Comp.n), and one end is connected to one of + Vr / 0 / −Vr according to the comparison result of each comparator (Comp.1 to Comp.n) and charged to each voltage. The capacitors C1 to Cn are included. The comparators (Comp. 1 to Comp. N) correspond to the ADC 12a, and the capacitors C1 to Cn correspond to the DAC 12b.

These capacitors C1 to Cn store an error appearing at the summing point Psum in the hold phase, and transfer it to the next stage, like the sampling capacitor CsI + 1 of the next stage in FIG.
At this time, by adjusting the ratio of the capacitors C1 to Cn and the sampling capacitor CsI + 1, a gain of 1 / f ′ represented by the equation (7) is formed. When the gain of 1 / f ′ is equal to 1 / f expressed by the equation (4), the gain characteristic independent of the DCGain “a0” of the MDAC-AMP 11 can be shown as in the equation (9). As can be seen from 4), since 1 / f is calculated by the ratio of the capacitances, it is possible to easily form the capacitors C1 to Cn by forming a ratio similar to that of the main path.

  Here, the gain of 1 / f ′ is formed by the capacitance ratio. However, the present invention is not limited to this. For example, the stored voltage + Vr / 0 / −Vr may be adjusted. Further, the capacitors C1 to Cn may be variable by calibration described later without being fixed.

<Improvement of SPM 12>
The present inventor further studied improvement on a method of correcting an error (error) generated in the MDAC-AMP 11 using the above-described SPM unit 12.
Here, the multiplying DA converter using the SPM unit 12 shown in FIG. 2 has the output of the SPM unit 12 connected to the sampling capacitor CsI + 1 at the next stage, and an error is corrected at the time of sampling at the next stage. It is configured as follows.

  By the way, with this configuration, the SPM unit 12 samples the voltage Va at the summing point Psum in the hold phase in FIG. 2B and performs AD conversion immediately. It is necessary to provide an ADC 12a and a DAC 12b that can perform AD conversion and DA conversion at a high speed as shown in FIG.

In view of this point, the present inventor has devised a configuration that does not require high-speed AD conversion and DA conversion.
5 shows an example of an MDAC (multiplying DA converter) to which the present invention is applied, which is included in the pipeline type A / D converter 1 shown in FIG. 1 having a sample-and-hold circuit (SH circuit) connected in cascade. 2 is a schematic configuration diagram showing an example of Stage I including MDAC 110 using SPM unit 12 and Stage I + 1 including MDAC 105 not having SPM unit 12 that is the next stage. The MDAC shown in FIG. 5 is intended to alleviate the high speed of the SPM unit 12.

  In FIG. 5A, the portion including CrI, CpI, CfI, and MDAC-AMPI to which the identifier “I” is added is StageI, and the stage I MDAC 110 outputs ResidueI and transfers to the next stage. It shows that there is. The portion including CsI + 1, CpI + 1, and MDAC-AMPI + 1 with the identifier “I + 1” added is StageI + 1, which indicates that the MDAC 105 of StageI + 1 is in the sample phase state.

  Further, in FIG. 5B, the part including CsI, CpI, and MDAC-AMPI to which the identifier “I” is added is StageI, and the MDAC 110 is a sample phase having the output ResidueI-1 of the preceding Stage as an input signal. It shows that it is in a state. A portion including CrI + 1, CfI + 1, CpI + 1, and MDACCAMPI + 1 to which the identifier “I + 1” is added is StageI + 1, which indicates that the MDAC 105 is in the hold phase state.

Each of these capacitors and amplifiers performs the same operation as the corresponding part of the MDAC 105 that does not have the SPM unit 12 described in FIG. 19, and Stage I and Stage I + 1 are in the state of FIG. 5 (a) and the state of FIG. 5 (b). Is transferred alternately to the sampling capacitor (CsI + 2) of Stage I + 2, which is the next stage.
In the MDAC 110 in FIG. 5, the SPM monitors the voltage Va at the input end of the MDAC-AMP 11 called a summing point Psum with respect to a normal DAC and adjusts it to a desired gain as shown in FIG. 5A. The SPM unit 12 is used.

  As shown in FIG. 5A, the input terminal of the SPM unit 12 is connected to the Stage I summing point Psum in the Stage I hold phase, and is set to the ground level in the Stage I sample phase as shown in FIG. 5B. Shorted. Further, as shown in FIG. 5A, the output terminal of the SPM unit 12 is shorted to the ground level in the Stage I + 1 sample phase, and in the Stage I + 1 hold phase, as shown in FIG. It is characterized in that it is connected to the sampling capacitor CsI + 2 of the MDAC 110 included in the unit block StageI + 2.

That is, by alternately repeating the state of FIG. 5A and the state of FIG. 5B, the voltage VaI of the summing point Psum of Stage I is detected and amplified by the SPM unit 12, that is, (1 / f ′) X (Gain of StageI + 1) * Va is stored in the sampling capacitor CsI + 2 in the next stage.
Here, in the MDAC 110 having the configuration shown in FIG. 2, since the output terminal of the SPM unit 12 is connected to the sampling capacitor CsI + 1 of the next stage Stage I + 1, in the SPM part 12, the Stage I shown in FIG. It is necessary to simultaneously perform AD conversion and DA conversion when in the hold phase state.

  On the other hand, when the configuration of FIG. 5 is adopted, the output terminal of the SPM unit 12 is connected to the sampling capacitor CsI + 2 of the stage I + 2 in the next stage. Therefore, in Stage I, the signal is sampled in the hold phase of FIG. In addition, since the signal sampled during the sampling phase of FIG. 5B may be transferred, the SPM unit 12 compares the AD conversion and DA conversion periods with those of the configuration of FIG. Can be taken longer. As a result, the SPM unit 12 does not require high speed in AD conversion and DA conversion. As a result, it is possible to simplify the configuration of the ADC 12a and the DAC 12b that perform AD conversion and DA conversion, and to suppress power consumption.

In FIG. 5, the error is corrected by connecting the output terminal of the SPM unit 12 to the sampling capacitor CsI + 2 of the next stage (Stage I + 2). However, the error is not limited to this, and it can be returned to the subsequent stage such as Stage I + 3. is there.
FIG. 6 shows an example in which the output terminal of the SPM unit 12 is connected to the sampling capacitor CsI + 3 at the stage after 3 Stage. In FIG. 6A, Stage I indicates a hold phase state in which Residue I is output and transferred to the next stage. Similarly, Stage I + 2 indicates a hold phase state in which Residue I + 2 is output and transferred to the next stage. StageI + 1 indicates the state of the sample phase. In FIG. 6B, Stage I and Stage I + 2 indicate the sample phase state, and Stage I + 1 indicates the hold phase state. In this way, by returning an error in Stage I to a later stage, it is possible to further lengthen the period for performing AD conversion and DA conversion in the SPM unit 12. Therefore, for example, a low-speed and high-resolution ΔΣ ADC can be used as the ADC 12 a of the SPM unit 12.

Moreover, if this idea is scrutinized, it is also possible to correct the error by adding the error in Stage I to the final digital output value. With such a configuration, the DAC 12b included in the SPM 12 shown in FIG. 3 can be omitted, and the power consumption and the circuit area can be further suppressed.
Note that the output of the SPM unit 12 is the sample hold circuit in the subsequent stage when the sample hold circuit (for example, Stage I + 2 in FIG. 5 and Stage I + 3 in FIG. 6) to which the output of the SPM unit is supplied is in the sample phase. The stage I having the SPM unit 12 may be in the sample phase or in the hold phase when the subsequent sample hold circuit is in the sample phase.

  Therefore, to which sample hold circuit of the subsequent stage the output of the SPM unit 12 is supplied depends on the output timing of the processing result for the input signal Vin at a certain time in the SPM unit 12 and the SPM unit 12 for the input signal Vin at the same time. It may be determined based on the processing timing of the sample hold circuit of the output supply destination. That is, the processing result in the SPM unit 12 for the input signal Vin at the same time may be supplied to the subsequent sample and hold circuit at the timing when the latter sample and hold circuit executes processing for the input signal Vin at a certain time. . For example, the output timing may be adjusted on the SPM unit 12 side, and conversely, on the sample hold circuit side, processing for the input signal Vin may be executed after waiting for the signal input from the SPM unit 12. Good.

<Calibration device>
<An example of a random signal addition type calibration device>
7 shows a circuit for adjusting the gain 1 / f ′ of the SPM unit 12 in the pipeline type A / D converter 1 including the MDAC 110 having the SPM unit 12 shown in FIG. 1 is a schematic configuration diagram illustrating an example of a calibration device that performs gain adjustment of a D converter 1. FIG. The calibration apparatus shown in FIG. 7 performs calibration by adding a random signal to an input signal Vin. A method of performing calibration by adding a random signal to the input signal Vin in this way is called a random signal addition method.

  In the calibration apparatus using the random signal addition method shown in FIG. 7, the pipeline type A / D converter 1 is stage 1 in the MDAC 110 included in the pipeline type A / D converter 1 shown in FIG. 1 as described above. Then, the MDAC shown in FIG. 5 is mounted as the MDAC 110, and the gain-AMP having a simple configuration shown in FIG. 3 is used as the SPM unit 12.

  Here, a case where an error signal in Stage I is added to the sampling capacitor CsI + 2 of the next stage I + 2 will be described. However, the calibration device shown in FIG. 7 adds the sampling capacitor CsI + 1 of the next stage I + 1 shown in FIG. In addition, the present invention can be applied even when adding to the sampling capacitor CsI + 3 of Stage I + 3 after the third stage shown in FIG.

The gain (1 / f ′) of the SPM unit 12 shown in FIG. 3 is different from the reciprocal “1 / f” of the feedback factor f of the MDAC-AMP 11, so that the input / output characteristics of the pipeline type A / D converter 1 are different. Is nonlinear, the input / output characteristics in this case can be assumed as shown in the following equation (10).
Vout (ADC) = (1−α) × Vin (ADC) (10)
Α in the equation (10) can be expressed as follows using the gain (1 / f ′) of the SPM unit 12 and the reciprocal “1 / f” of the feedback factor f of the MDAC-AMP 11.
α = Cf / Cs × (1 / a0) × (1 / f−1 / f ′) (11)

Here, a random variable PN composed of “1” or “−1” is added to a signal (PN × Vcal) obtained by multiplying a certain voltage Vcal by the input signal Vin, and the added analog signal Vin (ADC) is a pipeline type. Input to the A / D converter 1. The voltage Vcal may be set based on, for example, a necessary input amplitude and a time required for correction.
Here, the random variable PN is set to “1” or “−1”, but is not limited to this, and is a value that is changed by a value in the positive direction and the negative direction with respect to 0. Any value can be used as long as the average value of the random variables becomes zero.

After analog-to-digital conversion through the pipeline type A / D converter 1, the digital signal Vout (ADC) corresponding to the analog signal Vin (ADC) output from the pipeline type A / D converter 1 is converted into an input signal Vin. When a digital signal corresponding to the added analog signal (PN × Vcal) is subtracted, the subtraction result, that is, the output Vout can be expressed by the following equation (12).
Vout = Vin−α × (Vin + PN × Vcal) (12)

Here, when the random variable PN used when calculating the analog signal PN × Vcal added to the input signal Vin is multiplied by the output Vout expressed by the equation (12), as described above, the random variable PN becomes “ Since “1” or “−1” and PN × PN = 1, it can be expressed by the following equation (13).
PN x Vout
= PN × Vin (1-α) −αVcal (13)

Since PN × Vin obtained by multiplying the input signal Vin by the random variable PN becomes zero when averaged over a long period of time, the equation (13) can be expressed as the following equation (14).
PN × Vout = −αVcal (14)
Here, an accumulator 21, an up / down counter (up / dn counter) 22 for detecting a signal PN × Vout (= −α × Vcal = Verr) in the long term, a DAC (D / A converter) 23, , The gain of the SPM unit 12 of each MDAC 110 included in the pipeline type A / D converter 1 is adjusted so that Verr (error signal) becomes zero.

That is, the accumulator 21 accumulates the input error signal Verr, and the up / down counter 22 can consider that 1 / f ′ is greater than 1 / f from the equation (11) when the accumulated value is smaller than zero. A command signal for reducing the gain of the SPM unit 12 is output. On the contrary, when the integrated value in the accumulator 21 is larger than zero, it can be considered that 1 / f ′ is smaller than 1 / f from the equation (11), so that a command signal for increasing the gain of the SPM unit 12 is output. The DAC 23 adjusts the current values of the current sources I1 to I3 according to the command signal of the up / down counter 22. For example, when 1 / f ′ is decreased, the current amount of the current sources I1, I2 and I3 is decreased, and 1 / f ′ is decreased by decreasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2. Conversely, 1 / f ′ is increased by increasing the current amount of the current sources I1, I2, and I3 and increasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2.
As described above, when the gain of the SPM unit 12 is adjusted, α = 0.

Therefore, if α = 0 is substituted into the equation (12), the equation (12) becomes Vout = Vin. That is, this is equivalent to ideal analog-digital conversion of the input signal Vin.
In the calibration apparatus using the random signal addition method shown in FIG. 7, reference numeral 31 denotes an arithmetic unit that multiplies a random variable PN generated by a random signal generation circuit (not shown) and the like, and a preset voltage Vcal, 32 Adds the input signal Vin to the pipeline type A / D converter 1 and the operation result (PN × Vcal) of the multiplier 31 and outputs the addition result Vin ′ to the pipeline type A / D converter 1. An adder 33 is a multiplier that multiplies a negative value (−PN) of a random variable PN generated by the random signal generation circuit and the like with a preset voltage Vcal, and 34 is an operation result (− PN × Vcal) and the output Vout (ADC) of the pipeline type A / D converter 1 are added and output as an output Vout, 35 is the random signal generator This is a multiplier that multiplies the random variable PN generated by a circuit or the like and the output Vout output from the adder 34.

  In the calibration device of FIG. 7, the gain of the SPM unit 12 is adjusted. However, the present invention is not limited to this. For example, the gain of the MDAC-AMP 11 of FIG. 2 may be adjusted. In this case, the gain of the MDAC-AMP 11 may be adjusted in the same procedure as when the gain of the SPM unit 12 is adjusted.

  As described above, the MDAC 110 of the pipeline type A / D converter 1 has the configuration shown in FIG. 5, the ADC 12a and ADC 12b shown in FIGS. 3 and 4 are provided in the SPM unit 12, and the random signal shown in FIG. By performing calibration using an addition type calibration apparatus, the pipeline A / D converter 1 can perform accurate analog-digital conversion without adding a new capacity. Since gain adjustment is performed for each stage, accurate analog-to-digital conversion can be performed even when the DCgain “a0” of the MDAC-AMP 11 has a high-order distortion component. Therefore, accurate analog-to-digital conversion can be realized while suppressing an increase in noise.

  Further, for example, like the circuit of the multiplication DA converter that realizes the conventional SPM shown in FIG. 20, the gain is adjusted by feeding back the output of the MDAC-AMP 11 and the gain “1 / f ′” of the SPM unit 12 is adjusted. Compared with the method of making “”, the SPM unit 12 in this embodiment has a simple circuit configuration as shown in FIG. Therefore, power consumption can be kept small.

  Further, even if the DCgain “a0” of the MDAC-AMP11 has a high-order distortion component, the analog-digital conversion can be performed accurately. Therefore, the DCgain “a0” of the MDAC-AMP11 has a high gain characteristic. Can keep. Therefore, the configuration of the MDAC-AMP 11 can be made simple, that is, the power supply voltage can be reduced, so that power consumption can be further suppressed.

  In the calibration apparatus of FIG. 7, the case where the SPM unit 12 of the MDAC 110 included in the Stage 1 of the pipeline type A / D converter 1 is adjusted has been described. When the Stage includes the MDAC 110 having the SPM unit 12, the gain of each SPM unit 12 may be adjusted in each Stage, and each Stage is included regardless of whether or not the SPM unit 12 is included. You may make it adjust the gain of MDAC-AMP11 contained in.

<One example of calibration apparatus of threshold fluctuation method>
FIG. 8 is a schematic configuration diagram illustrating another example of a calibration apparatus that adjusts the gain 1 / f ′ of the SPM unit 12 in the pipeline type A / D converter 1 including the SPM unit 12 illustrated in FIG. 3. It is.
The calibration apparatus shown in FIG. 8 performs calibration by changing the threshold value of the SADC circuit 102 included in the pipeline type A / D converter 1. A method of performing calibration by changing the threshold value of the SADC circuit 102 in this way is called a threshold value changing method.
As shown in FIG. 8, the calibration device using the threshold fluctuation method does not require the multipliers 31 and 33 and the adders 32 and 34 that are included in the calibration device using the random signal addition method shown in FIG.

  In the case of the calibration apparatus using the random signal addition method shown in FIG. 7, since the AD conversion is performed after adding the irrelevant random signal to the input signal, it is necessary to subtract the signal corresponding to the added random signal from the output signal. On the other hand, in the case of the calibration apparatus using the threshold value variation method shown in FIG. 8, only the threshold value of the SADC circuit 102 is varied, and the random signal is not added. .

  In other words, as shown in FIG. 8, the threshold value variation calibration apparatus multiplies the output Vout output from the pipeline A / D converter 1 by the random variable PN, and the output of the multiplier 35. , An up / down counter (up / dn counter) 22 for detecting a signal PN × Vout (= −α × Vcal = Verr) in the long term, a DAC (D / A converter) 23, , And the gain of the SPM unit 12 of each MDAC 110 included in the pipelined A / D converter 1 is adjusted using the output of the DAC 23 so that the error signal Verr (error signal) becomes zero.

In FIG. 3, the gain “1 / f ′” of the SPM unit 12 is different from the reciprocal “1 / f” of the feedback factor of the MDAC 11, and therefore the input / output characteristics of the pipelined A / D converter 1 are nonlinear. Then, the input / output characteristics in this case can be assumed as shown in the following equation (15).
Vout = (1−α) × Vin (15)
Α in the equation (15) can be expressed as the following equation (16) using the gain “1 / f ′” of the SPM unit 12 and the reciprocal “1 / f” of the feedback factor of the MDAC 110.
α = Cf / Cs × (1 / a0) × (1 / f−1 / f ′) (16)

Here, a signal (PN × Vcal) obtained by multiplying a random voltage PN consisting of “1” or “−1” by a certain voltage Vcal is added to the output of the ADC in the SADC circuit 102. The voltage Vcal may be set based on, for example, a necessary input amplitude and a time required for correction.
A digital signal Vout corresponding to the analog signal Vin output from the pipeline A / D converter 1 after being converted from analog to digital through the pipeline A / D converter 1 can be expressed by the following equation (17).
Vout = Vin−α × (Vin + PN × Vcal)
= (1-α) Vin−α (PN × Vcal) (17)

Here, when the random variable PN is multiplied by the output Vout represented by the equation (17), as described above, the random variable PN is “1” or “−1” and PN × PN = 1. And can be represented by the following formula (18).
PN x Vout
= PN × Vin (1-α) −αVcal (18)
Since PN × Vin obtained by multiplying the input signal Vin by the random variable PN becomes zero when averaged over a long period of time, the equation (18) can be expressed as the equation (19) after all.
PN × Vout = −αVcal (19)
Here, using the accumulator 21, the up / down counter 22, and the DAC (D / A converter) 23, it is included in the pipeline type A / D converter 1 so that Verr (error signal) becomes zero. The gain of the SPM unit 12 of the MDAC 110 to be adjusted is adjusted.

That is, the accumulator 21 accumulates the input error signal Verr, and the up / down counter 22 can consider that 1 / f ′ is greater than 1 / f when the integrated value is smaller than zero, so the gain of the SPM unit 12 is reduced. Command signal to be output. On the contrary, when the integrated value in the accumulator 21 is larger than zero, 1 / f ′ can be regarded as smaller than 1 / f, so that a command signal for increasing the gain of the SPM unit 12 is output. The DAC 23 adjusts the current values of the current sources I1 to I3 according to the command signal of the up / down counter 22. For example, when 1 / f ′ is decreased, the current amount of the current sources I1, I2 and I3 is decreased, and 1 / f ′ is decreased by decreasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2. Conversely, 1 / f ′ is increased by increasing the current amount of the current sources I1, I2, and I3 and increasing the mutual conductance gmx of the MOS transistors Mx1 and Mx2.
As described above, when the gain of the SPM unit 12 is adjusted, α = 0.

Therefore, if α = 0 is substituted into the equation (17), the equation (17) becomes Vout = Vin. That is, this is equivalent to ideal analog-digital conversion of the input signal Vin.
In FIG. 8, the gain of the SPM unit 12 is adjusted. However, the present invention is not limited to this. For example, the gain of the MDAC-AMP 11 of FIG. 2 may be adjusted by the same procedure as described above.

  Also in this case, when the pipeline A / D converter 1 includes not only the Stage 1 but also other stages including the MDAC 110 having the SPM unit 12, the gain of each SPM unit 12 is adjusted in each Stage. The gain of the MDAC-AMP 11 included in each stage may be adjusted regardless of whether or not the SPM unit 12 is included.

<Detailed configuration diagram showing an example of a calibration apparatus using a threshold variation method>
FIG. 9 shows an example of a more detailed configuration of a calibration apparatus based on a threshold variation method that performs adjustment using the calibration method that varies the threshold of the SADC circuit 102 described in FIG. 8, and shows the background calibration. It is a conceptual diagram of a calibration apparatus when performing.
As shown in FIG. 9, the pipeline type A / D converter 1 includes a stage unit 41 including Stage I (for example, Stage 1 (unit block 100 (1))), and units from Stage I + 1 to Stage N (for example, Stage 2 to Stage N). Backend ADC 42 including blocks 100 (2) to 100 (N).
The stage unit 41 includes an MDAC 110 and a SADC circuit 102.

The SADC circuit 102 includes an ADC 102a and a DAC 102b to which the input signal Vin is input, and further includes a multiplier 102c that multiplies the voltage Vcal and the random variable PN, an output of the ADC 102a, and an output of the multiplier 102c. And an arithmetic unit 102d for adding.
The calibration apparatus shown in FIG. 9 performs calibration by changing the threshold value of the SADC circuit 102 and changing the input / output function as described above.

Note that the Stage I MDAC 110 has the same configuration as the MDAC 110 shown in FIG. 5 described above, and the output terminal of the SPM unit 12 is connected to the sampling capacitor CsI + 2 included in the next stage Stage I + 2 included in the Backend ADC 42.
In addition, the output signal Vout obtained by digitally converting the input signal Vin through the stage unit 41 and the Backend ADC 42 is multiplied by the random variable PN by the multiplier 35, and the operation result in the multiplier 35 is used as the error signal Verr to generate the error signal Verr. The up / down counter 22 outputs a command signal to the DAC 23 according to whether the integrated value is smaller than zero, that is, 1 / f ′ can be regarded as larger than 1 / f. The DAC 23 adjusts the current values of the current sources I1 to I3 of the SPM unit 12 according to the command signal of the up / down counter 22.

Here, the method of performing calibration by changing the threshold value of the SADC circuit 102 has an advantage that a high Feedback Gain can be obtained because a capacitor (CAP) for inserting a Dither signal is not added.
Also, in this method, an error generated by AD conversion is extracted on the assumption that a signal obtained by superimposing a Dither signal on an input signal is accumulated for a long period, and an optimum value is searched by feeding back this error.

  In FIG. 9, the gain of the SPM unit 12 is adjusted. However, the present invention is not limited to this. For example, the gain of the MDAC-AMP 11 may be adjusted, and the capacitance value of the sampling capacitor CsI may be adjusted. You can do it.

<Comparison with conventional technology>
Next, as in the present embodiment, the gain of the pipeline A / D converter 1 is adjusted by adding a random signal to the input signal Vin or by using a threshold variation method that varies the threshold of the SADC circuit 102. In order to clarify the difference between the method and the prior art, a conventional case of performing gain adjustment without using a random signal will be described.

FIG. 10 is a diagram schematically illustrating a part of the ADC 102a included in the SADC circuit 102 of Stage 1 when the MDAC 110 is a 2.5-bit MDAC.
The conventional SADC includes comparators 151 to 156 as shown in FIG.
The comparators 151 to 156 include the input signal Vin and the reference voltages (5/8) · Vr, (3/8) · Vr, (1/8) · Vr, (−1/8) · Vr, (−3/8). ) · Vr and (−5/8) · Vr. Vr is the maximum input range of the input signal Vin.

FIG. 11 is a diagram showing a transfer function (input / output characteristics) of a conventional SADC that does not add a random signal. In FIG. 11, the horizontal axis is input, and the vertical axis is output. Further, the value indicated by “Δ” in FIG. 11 represents the threshold value of the SADC to which the random signal is not added.
As shown in FIG. 11, in the case of a SADC that does not add random signals, the value of the reference voltage to be compared does not change, so that an output signal with a transfer function adapted to the input signal is output.

Next, a case where random signals are added in the SADC circuit 102 as in this embodiment will be described.
FIG. 12 is a diagram schematically illustrating a part of the ADC included in the SADC circuit 102 of Stage 1 when the MDAC 110 is a 2.5-bit MDAC.
The SADC circuit 102 includes comparators 161 to 168.

  The comparators 161 to 168 exchange voltages to be compared with random signals. That is, when the random variable PN = 1, the input signal Vin and the reference voltages (15/16) · Vr, (11/16) · Vr, (7/16) · Vr, (3/16) · Vr, ( −1/16) · Vr, (−5/16) · Vr, (−9/16) · Vr, and (−13/16) · Vr. On the other hand, when the random variable PN = −1, the input signal Vin and the reference voltages (13/16) · Vr, (9/16) · Vr, (5/16) · Vr, (1/16) · Vr, (−3/16) · Vr, (−7/16) · Vr, (−11/16) · Vr, and (−15/16) · Vr are respectively compared. Vr is the maximum input range of the input signal Vin.

FIG. 13 is a diagram illustrating a transfer function (input / output characteristics) of the SADC circuit 102 in the present embodiment, in which the random variable PN is added. In FIG. 13, the horizontal axis represents the input to the SADC circuit 102, and the vertical axis represents the output. Further, the value indicated by “Δ” in FIG. 13 represents the threshold value of the SADC circuit 102 to which the random variable PN is added.
In FIG. 13, the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = 1, and the transfer function (input / output characteristics) of the SADC circuit 102 when adding the random variable PN = −1. Is also written.

  When an input signal as in Example 1 enters from the input side, the output signal changes depending on the value of the random variable PN. For example, when PN = 1, the transfer function of the SADC circuit 102 when adding the random variable PN = 1 is applied, and the input signal of Example 1 becomes an output signal (PN = 1) according to Example 1. When PN = −1, the transfer function of the SADC circuit 102 when adding the random variable PN = −1 is applied, and the input signal of Example 1 becomes the output signal (PN = −1) according to Example 1. As a result, as shown in FIG. 13, the output result varies depending on the random variable PN.

In this case, since the output changes even with the same input depending on the random variable PN, if it is added over a long period, an error component remains as a result.
On the other hand, when an input signal such as Example 2 is input from the input side, the output signal is not changed by the random variable PN. For example, when PN = 1, the transfer function of the SADC circuit 102 when adding the random variable PN = 1 is applied. When PN = −1, the transfer function of the SADC circuit 102 when adding the random variable PN = −1. Although the function is applied, since both transfer functions are the same, the input signal of Example 2 is an output signal (PN = 1 / −1) according to Example 2.

In this case, even if the random variable PN fluctuates, the output is always the same, so even if added for a long time, it is canceled out and no error remains.
By the way, whether or not errors are integrated, the accumulator 21 integrates all output signals.
In order to shorten the calibration time, the accumulation time of the accumulator 21 may be made efficient. Therefore, as described above, there are cases where the error signal in the multiplier 35 becomes zero or not depending on the input signal Vin. Therefore, the area that the input signal Vin can take when the error signal does not become zero. Is an error integration region, and it is determined whether the input signal Vin is a value within the error integration region, and efficient integration is performed.

That is, for example, by using the back-end ADC 42 shown in FIG. 9, the input signal Vin is classified into a region (time) in which the error signal is integrated and a region (time) in which the error signal is not integrated. The accumulator 21 accumulates the error signal only when the value in the accumulated area, that is, the value in the error accumulation area.
The accumulator 21 may simply hold the previous integration result when the input signal Vin is a value in a region (time) in which the error signal is not integrated, or may add “0” to the previous integration result. Alternatively, both ends of the accumulator 21 may be bypassed.

  FIG. 14A is a diagram showing transfer functions (input / output characteristics) of Stage 1 and Stage 2 in an ideal case where there is no offset in the comparators 161 to 168 of the SADC circuit 102 that adds the random variable PN shown in FIG. It is. In the diagram showing the transfer function of Stage 1 (the diagram on the left side of FIG. 14A), the horizontal axis represents the input to the SADC circuit 102, the vertical axis represents the output, and the value indicated by “Δ” on the horizontal axis is This represents the threshold value of the SADC circuit 102 of Stage1.

In the diagram showing the transfer function of Stage 2 (the diagram on the right side of FIG. 14A), the horizontal axis represents the output of the SADC circuit 102 of Stage 2, the vertical axis represents the input of the SADC circuit 102 of Stage 2, and the vertical axis The value indicated by “Δ” indicates the threshold value of the SADC circuit 102 of Stage2.
In FIG. 14A, a region not affected by the random variable PN corresponds to (−1/4) · Vr to (1/4) · Vr of Stage2 input (= Output of Stage1). A determination circuit (not shown) determines a region (time) in which this region is error-integrated, and distinguishes a region (time) that has not been error-integrated (time), thereby distinguishing the region in which error is integrated. Only the accumulator 21 is integrated.

As described above, since only the areas where errors are integrated are integrated, it is not necessary to integrate as much as possible the input signals unnecessary for error integration, and the integration ratio of the error signals that are relatively necessary increases. That is, since the ratio of error components in the integrated signal increases, it is easy to extract error components even if the integration time is relatively short.
Here, the Stage 2 input (= Stage 1 output) is (−1/4) · Vr to (1/4) · Vr as shown in FIG. 14 (a) because the input signal input to Stage2 is In each segment divided into a plurality of segments, segment Seg. 3 and segment Seg. 2 when the output is 0 or more, the segment Seg. 4 when the output is 0 or less.

Whether the output is 0 or more or 0 or less can be determined from the AD conversion result of the back-end ADC 42, and the accumulator 21 does not perform integration if it corresponds to these. As described above, instead of adding a new determination circuit, the AD conversion result in the back-end ADC 42 can be used for the determination.
FIG. 14B is a diagram illustrating transfer functions (input / output characteristics) of Stage 1 and Stage 2 when Offset is provided in the comparator of the SADC circuit 102. In the diagram showing the transfer function of Stage 1 (the diagram on the left side of FIG. 14B), the horizontal axis represents the input to the SADC circuit 102, the vertical axis represents the output, and the value indicated by “Δ” on the horizontal axis is This represents the threshold value of the SADC circuit 102 of Stage1. In the diagram showing the transfer function of Stage 2 (the diagram on the right side of FIG. 14B), the horizontal axis represents the output of the SADC circuit 102 of Stage 2, and the vertical axis represents the input of the SADC circuit 102 of Stage 2. The value indicated by “Δ” on the vertical axis represents the threshold value of the SADC circuit 102 of Stage2.

  As shown in FIG. 14B, when there is an offset in the comparators 161 to 168 of the SADC circuit 102, the area to be integrated is widened for the back-end Back ADC 42. Therefore, it is preferable to determine a region where error signals are not integrated in consideration of the offset of the comparator of the SADC circuit 102. For example, assuming that Offset is (1/32) · Vr, the area where the error signal is not integrated becomes 1/8 of the entire back-end ADC 42, and the time reduction effect is expected.

<Detailed configuration diagram showing an example of a calibration apparatus using a random signal addition method>
FIG. 15 is a conceptual diagram showing an example of a more detailed configuration of a calibration apparatus using a random signal addition method that adds a random signal to the input signal described in FIG.
The calibration apparatus using the random signal addition method shown in FIG. 15 is different from the calibration apparatus using the threshold fluctuation method shown in FIG. 9 in that the multipliers 31 and 33, the adder 34, and addition for adding random signals are added. The place provided with the capacity as the container 32 is different. Components having the same functions as those of the calibration apparatus shown in FIG.

As shown in FIG. 15, the pipeline type A / D converter 1 includes a stage unit 51 including Stage I (for example, Stage 1 (unit block 100 (1))) and a unit from Stage I + 1 to Stage N (for example, Stage 2 to Stage N). Backend ADC 52 including blocks 100 (2) to 100 (N).
The stage unit 51 includes an MDAC 110 and a SADC circuit 102 ′.

The SADC circuit 102 'includes an ADC 102a and a DAC 102b to which an input signal Vin is input, a multiplier 31 that multiplies the voltage Vcal and the random variable PN, and a multiplication result of the multiplier 31 is added to the input signal Vin. And a capacity as an adder 32.
The calibration apparatus shown in FIG. 15 adds a random signal to the input signal Vin and performs calibration by changing the amplitude of the input signal Vin.

The MDAC 110 has the same configuration as the MDAC 110 shown in FIG. 5 described above, and the output terminal of the SPM unit 12 is connected to the sampling capacitor Cs3 included in the subsequent stage 3 included in the Backend ADC 42.
Further, an adder 34 outputs an output Vout (ADC) obtained by digitally converting the input signal Vin through the stage unit 51 and the Backend ADC 52 to the calculation result in the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN”. Addition is performed to obtain an output signal Vout obtained by digitally converting the input signal Vin. The addition result of the adder 34, that is, the output signal Vout that is an A / D conversion value of the input signal Vin and the random variable PN are multiplied by the multiplier 35. The calculation result in the multiplier 35 is used as an error signal Verr, and the error signal Verr is integrated by the accumulator 21. In the up / down counter 22, the integrated value is smaller than zero, that is, 1 / f ′ is larger than 1 / f. A command signal is output to the DAC 23 according to whether it can be considered, and the DAC 23 adjusts the current values of the current sources I1 to I3 of the SPM unit 12 according to the command signal of the up / down counter 22.

In FIG. 15, the addition in the analog unit is realized by charging the capacitor as the adder 32 with a voltage of (Vcal × PN). However, the addition is not limited to this, and the addition is performed in place of the capacitor. A vessel may be used.
Alternatively, the reference voltage Vr used in the ADC comparator included in the SADC circuit 102 may be used instead of the voltage Vcal, and the ratio may be realized by a ratio with the sampling capacitor CsI connected to the input terminal of the input signal Vin. For example, when Vcal = (1/4) · Vr, instead of changing the voltage Vcal in FIG. 15 to (1/4) · Vr, Vcal is set to Vr, and the capacitance ratio of the capacitor is 1: 4. Also good.

In FIG. 15, the gain of the SPM unit 12 is adjusted. However, the present invention is not limited to this. For example, the gain of the MDAC-AMP 11 may be adjusted.
FIG. 16 is a diagram illustrating an input signal and a transfer function (input / output characteristics) of the SADC circuit 102 when the random variable PN is added to the input signal Vin. In FIG. 16, the horizontal axis represents the input signal to the SADC circuit 102, and the vertical axis represents the output.

In FIG. 16, the input signal when adding the random variable PN = 1 and the input signal when adding the random variable PN = −1 are shown together. Note that the position indicated by “Δ” in FIG. 16 represents the threshold value of the SADC circuit 102, and the transfer function is the same and the threshold value is the same as in the case of PN = 1 and PN = −1.
Even if the transfer function is the same, if the output varies depending on the random variable PN, an error component remains as a result if they are added over a long period of time.

On the other hand, even if the random variable PN fluctuates, if the output is the same, even if it is added over a long period, it is canceled out and no error remains.
In the random variable addition type calibration apparatus shown in FIG. 15, similarly to the threshold value fluctuation type calibration apparatus shown in FIG. 9, an area (time) in which error signals are integrated by using the back-end ADC 52. And the area where the error signal is not integrated (time), and only the area where the error signal is integrated is integrated by the accumulator 21, so that the calibration time can be shortened.
As described above, according to the present invention, even when a circuit for extracting the voltage at the summing point Psum is realized by the SPM unit 12 having a simple configuration, a high-accuracy gain is realized regardless of variations in the operating environment and the manufacturing process. it can.

<Configuration diagram showing another application example of calibration apparatus>
FIG. 17 is a conceptual diagram showing an example of a detailed configuration showing another application example of the calibration apparatus of the random variable addition method.
The calibration apparatus using the random signal addition method shown in FIG. 17 performs gain adjustment in the sample hold circuit of the A / D converter, not in the pipeline type A / D converter. Calibration is performed by a random variable addition method in which a random signal is added to the input signal Vin described in FIG.
That is, the calibration apparatus shown in FIG. 17 uses a post-stage ADC in place of the pipeline type A / D converter 1 including the stage 51 including Stage 1 and the Backend ADC 52 including Stage subsequent to that illustrated in FIG. (A / D converter) The gain of the sample hold circuit 211 of the 212 is adjusted, and this calibration apparatus performs calibration by the same method as the calibration apparatus shown in FIG.

In FIG. 17, components having the same functions as those of the calibration apparatus shown in FIG. 15 are denoted by the same reference numerals, and description thereof is omitted.
FIG. 17 is a block diagram illustrating an example of a calibration device for performing background calibration on the sample hold circuit 211.
As shown in FIG. 17, the sample hold circuit 211 includes an AMP 221, an SPM unit 12, a capacitor 222 that connects the output end and the inverting input end of the AMP 221, one end connected to the input end of the input signal Vin, and the other end. Includes a sampling capacitor 223 connected to the inverting input terminal of the AMP 221 and the input terminal of the SPM unit 12, and further, a capacity as a multiplier 31 and an adder 32 that multiplies the voltage Vcal and the random variable PN. And comprising. A sampling capacitor 213 for connecting the sample hold circuit 211 and the ADC 212 is connected to the output terminal of the AMP 221.

  As shown in FIG. 17, when the ADC 212 includes a plurality of sampling capacitors 213 connected in cascade, the analog input signal Vin transferred to the sampling capacitor 213 is converted into a digital signal by the method. Of these sampling capacitors 213, By connecting any one of the above and the output terminal of the SPM unit 12, an error signal generated in the sample and hold circuit can be transferred to the ADC 212.

In addition, since the SPM unit 12 only needs to be output when the sampling capacitor 213 connected to the output terminal of the SPM unit 12 enters the sampling phase, the processing of the SPM unit 12 does not need to be performed at high speed.
In FIG. 17, the error signal is transferred by connecting the output terminal of the SPM unit 12 to the sampling capacitor 213 of the ADC 212. However, the error signal is not limited to this and is connected to a resistor, Gain-AMP, or the like depending on the method of the ADC 212. Then, it may be transferred with an appropriate gain.

The calibration apparatus illustrated in FIG. 17 includes a multiplier 33 that multiplies the voltage Vcal and the random variable “−PN” in a subsequent stage of the ADC 212, and an addition that adds the output Vout (ADC) of the ADC 212 and the output of the multiplier 33. Instrument 34.
Then, the output Vout (ADC) output from the ADC 212 is added by the adder 34 to the operation result of the multiplier 33 that multiplies the voltage Vcal and the random variable “−PN”, and the addition result and the random variable PN are obtained. Multiply by the multiplier 35. The calculation result in the multiplier 35 is accumulated as an error signal Verr by the accumulator 21, and the up / down counter 22 can consider that the accumulated value is smaller than zero, that is, 1 / f 'is larger than 1 / f. Accordingly, a command signal is output to the DAC 23, and the DAC 23 adjusts the current values of the current sources I1 to I3 of the SPM unit 12 according to the command signal of the up / down counter 22.

In FIG. 17, the gain of the SPM unit 12 is adjusted. However, the present invention is not limited to this. For example, the gain of the AMP 221 of the sample hold circuit 211 may be adjusted, or a capacitor included in the sample hold circuit 211 may be used. It is also possible to adjust.
As described above, the configuration shown in FIG. 17 does not need to immediately transfer the error signal of the block (sample hold circuit 211 in the case of FIG. 17) in which an error is to be detected, similarly to the configuration shown in FIG. It is possible to further lengthen the period for performing AD conversion and DA conversion in FIG. 2, for example, a low-speed and high-resolution ΔΣ ADC can be used as the ADC 12a of the SPM unit 12.

Accordingly, also in this case, it is possible to realize a high-accuracy gain regardless of the operating environment and variations during the manufacturing process.
In the above embodiment, the case where the sample-and-hold circuit calibration method according to the present invention is applied to a pipelined A / D converter has been described. However, the present invention is not limited to this. For example, a successive approximation A / D Even a converter or a ΔΣ A / D converter can be applied. In these cases, if the error of the A / D converter is taken into account, the output terminal of the SPM unit is connected to an appropriate capacitor included in the subsequent stage, so that the accuracy is high regardless of variations in the operating environment and the manufacturing process. Gain can be realized.

  In addition, the scope of the present invention is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that provide the same effects as those intended by the present invention. Furthermore, the scope of the invention is not limited to the combinations of features of the invention defined by the claims, but can be defined by any desired combination of particular features among all the disclosed features.

1 Pipeline A / D Converter 11 MDAC-AMP
12 SPM part 12a ADC
12b DAC
21 accumulator
22 Up / Down Counter (up / dn counter)
23 DAC (DA converter)
31, 33, 35 Multiplier 32, 34 Adder 105, 110 MDAC (multiplication digital analog converter)
211 Sample hold circuit 212 A / D converter Mx1, Mx2, My1, My2 MOS transistors I1, I2, I3 Current source

Claims (7)

A sampling and holding circuit having a sampling capacitor and an amplifier connected to an input terminal of the sampling capacitor, and having an arithmetic unit connected to the amplifier, and supplying an output of the amplifier to a sample and hold circuit in the next stage,
After the sample and hold circuit of the next stage, another sample and hold circuit of one or more stages is connected,
The computing unit is
In the hold phase, the voltage at the summing point that is the connection point of the sampling capacitor at the input terminal of the amplifier is monitored,
A sample and hold circuit, wherein the summing point voltage monitoring result is supplied to a sampling capacitor included in one sample and hold circuit in a sample phase among the other sample and hold circuits.   2. The sample and hold circuit according to claim 1, wherein when the one sample and hold circuit is in a sample phase, a hold phase is set, and when the one sample and hold circuit is in a hold phase, a sample phase is set.   2. The sample and hold circuit according to claim 1, wherein the one sample and hold circuit is a sample and hold circuit in the next stage of the sample and hold circuit in the next stage. The computing unit is
The sample-and-hold circuit according to any one of claims 1 to 3, further comprising an AD converter and a DA converter connected to an output terminal of the AD converter. The AD converter has an input connected to the summing point,
The sample-and-hold circuit according to claim 4, wherein an output terminal of the DA converter is connected to a sampling capacitor included in the one sample-and-hold circuit.   The sample hold circuit according to any one of claims 1 to 5, wherein the arithmetic unit is configured to be able to change a gain.   An A / D converter comprising the sample-and-hold circuit according to any one of claims 1 to 6.

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