JP2015088560A - Electronic device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently obtain a high heat exhaust effect to be expected in a thermal conductive material to be arranged in an electronic component by demonstrating excellent thermal conductivity of the thermal conductive material as much as possible.SOLUTION: In a semiconductor device, it includes: an electronic component 10 on a rear surface of which a CNT 4 which is a thermal conductive material is arranged; and a heat spreader 30 which is a heat dissipation mechanism to be thermally connected with the electronic component, the heat spreader 30 has a hollow part 31 at which an opening 31a is formed, and an inside of which a hydraulic fluid 34 is encapsulated, and in the CNT 4, a tip part 4a which is a part of it is inserted into the hollow part 31 from the opening 31a, and immersed in the hydraulic fluid 34.

Description

  The present invention relates to an electronic device and a manufacturing method thereof.

  In an electronic device such as a semiconductor device, it is important to lower the operating temperature of a semiconductor chip in order to suppress leakage current and reduce power consumption. As a heat dissipation technique for a semiconductor chip, there is a technique for improving the connection between a semiconductor chip and a heat sink (see Patent Documents 1 and 2). In addition, a configuration has been devised in which a material having high thermal conductivity is directly connected to a heating element of a semiconductor chip to perform heat dissipation (see Patent Document 3).

JP 2010-50170 A JP 2010-114120 A JP 2005-109133 A

  Recently, it has been proposed to improve the exhaust heat characteristics by applying carbon nanotubes (CNT) having excellent thermal conductivity to thermal TSV and thermal interface material (TIM). The thermal conductivity of CNT has been experimentally obtained from several tens of W / mK to 1000 W / mK, which is several times smaller than that of conventional TIM material solder (50 W / mK) and Si substrate (168 W / mK). High thermal conductivity can be expected.

  When CNT is applied to the thermal TSV and TIM, the heat released from the heat generation part (hot spot) of the semiconductor chip is transmitted to the heat spreader by the TIM through the thermal TSV and is exhausted from the cooling unit.

  However, in this case, even if the thermal conductivity of the CNT itself is high, if the contact thermal resistance at the interface between the thermal TSV and the TIM or the interface between the TIM and the heat spreader is large, the expected heat exhaust effect cannot be obtained. There is a problem.

  The present invention has been made in view of the above problems, and is expected to be highly expected for the heat conductive material by demonstrating as much as possible the excellent heat conductivity of the heat conductive material disposed in the electronic component. It is an object of the present invention to provide an electronic device that can sufficiently obtain a heat exhaust effect and a manufacturing method thereof.

  The electronic device of the present invention includes an electronic component having a heat conductive material disposed on the back surface, and a heat dissipation mechanism thermally connected to the electronic component. The heat dissipation mechanism has an opening and is operated inside. It has a hollow portion in which a liquid is sealed, and a part of the heat conducting material enters the hollow portion from the opening and is immersed in the working fluid.

  An electronic device manufacturing method of the present invention includes a step of disposing a heat conductive material on a back surface of an electronic component, and a step of thermally connecting the electronic component and a heat dissipation mechanism, wherein the heat dissipation mechanism has an opening. A hollow portion formed, and a part of the heat conducting material is allowed to enter the hollow portion from the opening, and the heat conducting material is immersed in the working fluid injected into the hollow portion. The electronic component is connected to the heat dissipation mechanism and sealed.

  According to the present invention, it is possible to sufficiently obtain the high heat exhaustion effect expected of the heat conductive material by demonstrating as much as possible the excellent heat conductivity of the heat conductive material disposed in the electronic component. It becomes.

It is a schematic sectional drawing which shows the manufacturing method of the semiconductor device by this embodiment in order of a process. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1 showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view subsequent to FIG. 2, illustrating the method for manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 4 is a schematic cross-sectional view subsequent to FIG. 3 showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 5 is a schematic cross-sectional view subsequent to FIG. 4 showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 6 is a schematic cross-sectional view subsequent to FIG. 5 showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 7 is a schematic cross-sectional view subsequent to FIG. 6 showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view subsequent to FIG. 7 showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 9 is a schematic cross-sectional view subsequent to FIG. 8, illustrating the method for manufacturing the semiconductor device according to the present embodiment in the order of steps. FIG. 10 is a schematic cross-sectional view subsequent to FIG. 9 showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps. It is a schematic sectional drawing which shows the formation process of the element layer of the semiconductor device by this embodiment in order of a process. FIG. 12 is a schematic cross-sectional view subsequent to FIG. 11, illustrating the process of forming the element layer of the semiconductor device according to the present embodiment in order of processes. It is a schematic sectional drawing which shows the heat spreader of the semiconductor device by this embodiment. It is a schematic sectional drawing for demonstrating the heat dissipation mechanism in the semiconductor device by this embodiment.

Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the present embodiment, a semiconductor device in which a semiconductor chip is mounted on a package substrate as an electronic device will be described together with a manufacturing method thereof.
1 to 10 are schematic cross-sectional views illustrating the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.

First, as shown in FIG. 1, a plurality of holes 1 </ b> A are formed in the back surface 1 a of the silicon substrate 1.
For example, a silicon substrate 1 is prepared as a substrate. For example, the silicon substrate 1 has a thickness of about 775 μm.
The back surface of the silicon substrate 1 is processed to a predetermined depth by lithography and dry etching. As a result, a plurality of non-through holes 1A are formed on the back surface of the silicon substrate 1. The diameter of the hole 1A is, for example, about 20 μm to 100 μm, here about 50 μm, and the depth is equal to or less than the thickness of the substrate, for example, about 700 μm.

Subsequently, as shown in FIG. 2, a base material 2 and a catalyst material 3 are sequentially formed on the back surface 1a of the silicon substrate 1 and the bottom surface 1a _{1 of the} hole 1A.
Specifically, first, for example, Ta, TaN or the like is deposited to a thickness of about 15 nm by ALD, sputtering, or the like. Thus, the bottom surface 1a ₁ of the back surface 1a and the hole 1A of the silicon substrate 1, the base material 2 is formed as the barrier metal.
Next, the catalyst material is deposited to a thickness of several nm, for example, about 1 nm by a vacuum evaporation method or the like. As the catalyst material, a mixed material of one or more selected from Co, Ni, Fe and the like and one or more selected from Ti, TiN, TiO ₂ , V, Al and the like is used. . For example, Co / Ti or Fe / Al is selected. Thus, the back surface 1a and the hole 1A bottom 1a ₁ of the silicon substrate 1, the catalyst material 3 is formed on the base material 2.

Subsequently, as shown in FIG. 3, a CNT 4, which is a linear structure of carbon, is formed in the back surface 1 a of the silicon substrate 1 and the hole 1 </ b> A. For example, carbon nanofibers can be formed instead of CNTs.
In detail, the growth temperature is set to be equal to or lower than the melting point of the substrate material, for example, about 800 ° C. by the plasma CVD method or the thermal CVD method, and the application direction of the electric field is set to the direction perpendicular to the substrate surface. Execute the growth process. Thus, CNT4 is formed so as to stand from the catalyst material 2 existing on the bottom surface 1a ₁ of the back surface 1a and the hole 1A of the silicon substrate 1. The CNT 4 grows from the back surface 1a and the bottom surface 1a _{1 of} the hole 1A, and is formed to have a predetermined length that fills the hole 1A and protrudes from the hole 1A.

Subsequently, as shown in FIG. 4, the tip surface formed by the plurality of CNTs 4 is flattened.
More specifically, for example, chemical mechanical polishing (CMP) is performed on the tip portion of the CNT 4 in order to prepare the tip surface of the CNT 4. Thus, the CNT4 grown from the back 1a, in the CNT4 grown from the bottom surface 1a ₁ hole 1A, is the length from the back surface 1a of CNT4 is substantially the same, and a flat tip surface formed of a plurality of CNT4 Become.
Note that this planarization step may not be performed.

Subsequently, as shown in FIG. 5, the silicon substrate 1 is appropriately thinned.
Specifically, after the CNT 4 is formed, the surface 1b of the silicon substrate 1 is ground by grinding or the like as long as the base material 2 is not exposed. Thereby, the silicon substrate 1 is appropriately thinned. This substrate thinning process may be omitted.

Subsequently, as shown in FIG. 6, an element layer 5 including, for example, a MOS transistor element and a wiring structure thereof as a functional element is formed on the surface 1 b of the silicon substrate 1. 6 to 10, illustration of the internal structure of the element layer 5 is omitted for convenience of illustration.
The formation process of the element layer 5 is demonstrated using FIG.11 and FIG.12. 11 and 12, only the surface layer portion of the silicon substrate 1 is shown.

First, as shown in FIG. 11A, a transistor element 20a is formed.
Specifically, first, an element isolation structure 11 is formed on the surface layer of the silicon substrate 1 by, for example, an STI (Shallow Trench Isolation) method to determine an element active region.
Next, an impurity of a predetermined conductivity type is ion-implanted into the element active region to form the well 12.

  Next, a gate insulating film 13 is formed in the element active region by thermal oxidation or the like, a polycrystalline silicon film and a film thickness such as a silicon nitride film are deposited on the gate insulating film 13 by a CVD method, and a silicon nitride film or a polycrystalline silicon film is deposited. The gate electrode 14 is patterned on the gate insulating film 13 by processing the film and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching. At the same time, a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.

  Next, using the cap film 15 as a mask, an impurity having a conductivity type opposite to that of the well 12 is ion-implanted into the element active region to form a so-called extension region 16.

  Next, for example, a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.

  Next, using the cap film 15 and the sidewall insulating film 17 as a mask, an impurity having the same conductivity type as that of the extension region 16 is ion-implanted into the element active region to form a source / drain region 18 overlapping the extension region 16. Thus, the transistor element 20a is formed.

Subsequently, as shown in FIG. 11B, an interlayer insulating film 19 is formed.
Specifically, for example, silicon oxide is deposited so as to cover the transistor element 20a, and the interlayer insulating film 19 is formed. The surface of the interlayer insulating film 19 is polished by chemical mechanical polishing (CMP).

Subsequently, as illustrated in FIG. 11C, a contact hole 19 a is formed in the interlayer insulating film 19.
Specifically, the interlayer insulating film 19 is processed by lithography and dry etching. Thereby, a contact hole 19a exposing a part of the surface of the source / drain region 18 is formed.

Subsequently, as shown in FIG. 12A, a contact plug 21 is formed.
Specifically, a conductive material, for example, tungsten (W) is deposited on the interlayer insulating film 19 by a CVD method or the like in a thickness for embedding the contact hole 19a.
The surface of W is polished by CMP to leave W only in the contact hole 19a. Thus, the contact plug 21 formed by filling the contact hole 19a with W is formed.

Subsequently, as shown in FIG. 12B, a wiring structure 20b is formed.
Specifically, first, a wiring material, for example, an aluminum (Al) alloy is deposited on the interlayer insulating film 19 by a sputtering method or the like, and the Al alloy is processed by lithography and dry etching. As described above, the wiring 22 electrically connected to the contact plug 21 is formed on the interlayer insulating film 19.

Next, for example, silicon oxide is deposited on the interlayer insulating film 19 so as to cover the wiring 22, thereby forming the interlayer insulating film 23.
Next, the interlayer insulating film 23 is processed by lithography and dry etching to form a via hole 23 a that exposes a part of the surface of the wiring 22.
Next, a conductive material such as tungsten (W) is deposited on the interlayer insulating film 23 by a CVD method or the like so as to fill the via hole 23a. The surface of W is polished by CMP to leave W only in the via hole 23a. As a result, the via plug 24 formed by filling the via hole 23a with W is formed.

Next, a wiring material such as an Al alloy is deposited on the interlayer insulating film 23 by sputtering or the like, and the Al alloy is processed by lithography and dry etching. As a result, the wiring 25 electrically connected to the via plug 24 is formed on the interlayer insulating film 23.
Thereafter, an electrode pad 26 for external connection that is electrically connected to the wiring 25 is formed on the surface of the interlayer insulating film 23.

As described above, the element layer 5 having the transistor element 20a and the wiring structure 20b in the interlayer insulating films 19 and 23 and having the electrode pads 26 on the surface is formed.
In the above example, the wiring structure 20b of the element layer 5 is formed of two layers of wiring. However, the element layer may be formed by stacking wirings in multiple layers.

  Subsequently, as shown in FIG. 7, the silicon substrate 1 is processed by dicing, and each semiconductor chip 10 is cut out.

Subsequently, as shown in FIG. 8, the semiconductor chip 10 is mounted on the package substrate 20.
Specifically, a package substrate 20 in which a predetermined wiring layer is laminated is prepared. The surface 1 b of the semiconductor chip 10 is opposed to the surface of the package substrate 20, and the electrode pads 26 of the semiconductor chip 10 and predetermined portions of the package substrate 20 are electrically connected by solder bumps 32. A gap between the semiconductor chip 10 and the package substrate 20 is sealed with a predetermined insulating resin 33.

Subsequently, as shown in FIG. 9, a heat spreader 30 as a heat dissipation mechanism is disposed on the semiconductor chip 10.
As shown in FIG. 13, the heat spreader 30 is a housing-like member that does not have a bottom made of a highly heat conductive material such as Cu, and the upper surface portion is a hollow portion 31. The hollow portion 31 is formed with an opening 31a on the inner main surface thereof.

  When the heat spreader 30 is disposed on the semiconductor chip 10, the working fluid 34 is injected into the hollow portion 31 in a predetermined vacuum environment. As the hydraulic fluid 34, one selected from water, a fluorine-based solvent, and alcohols is used. Since CNT is hydrophobic, by using a fluorine-based solvent or alcohol as the operation 34, the CNT 4 comes into contact with the hydraulic fluid 34 with excellent affinity. Water has a large heat capacity and is suitable as the hydraulic fluid 34. However, when water is used as the hydraulic fluid 34, in order to make the surface of the CNT 4 hydrophilic in order to ensure affinity with the CNT 4, the CNT 4 is used. It is preferable to perform predetermined chemical modification (for example, chemical modification with a carboxyl group (—COOH)).

  Next, the tip portion of the CNT 4 of the semiconductor chip 10 having a predetermined length enters the hollow portion 31 from the opening 31a, and the CNT 4 is immersed in the working fluid 34. In this state, the semiconductor chip 10 is hermetically fixed to the hollow portion 31 using a predetermined adhesive 35. Then, the front end portion of the heat spreader 30 is bonded and fixed to the surface of the package substrate 20.

  Prior to the step of injecting the working fluid 34 into the hollow portion 31, first, the tip of the CNT 4 of the semiconductor chip 10 enters the hollow portion 31 from the opening 31 a in a predetermined vacuum environment, and the adhesive 35. The semiconductor chip 10 may be hermetically fixed to the hollow portion 31. In this case, after the semiconductor chip 10 is hermetically fixed to the hollow portion 31, the working liquid 34 is injected into the hollow portion 31 from a predetermined portion of the hollow portion 31, and the predetermined portion is closed.

Subsequently, as shown in FIG. 10, the upper surface of the hollow portion 31 of the heat spreader 30 is thermally connected to a predetermined cooling unit 37 such as an air-cooled type or a water-cooled type by a TIM 36 made of a metal material such as Cu or In. Is done.
As described above, the semiconductor device according to the present embodiment is formed. In this semiconductor device, solder bumps are disposed on the back surface of the package substrate 20 and mounted on, for example, a predetermined mother board.

  Hereinafter, the heat dissipation mechanism in the semiconductor device according to the present embodiment will be explained with reference to FIG. In FIG. 14, only the hollow part 31 of the semiconductor chip 10 and the heat spreader 30 is shown in the semiconductor device according to the present embodiment for convenience of explanation.

  In this semiconductor device, the tip portion of the CNT 4 of the semiconductor chip 10 enters the hollow portion 31 and is immersed in the working fluid 34. The hydraulic fluid 34 is excellent in affinity with the CNT 4 and penetrates along the CNT 4 to the tip portion of the CNT 4 in the hole 1A of the semiconductor chip 10.

In the semiconductor device, a predetermined portion of the element layer 5 of the semiconductor chip 10 becomes a heat generating portion (hot spot) 41 and is exhausted by the following series of phase change reduction (heat pipe principle).
The CNT 4 is heated by the heat radiation from the hot spot 41, and the working fluid 34 evaporates in the CNT 4 to absorb the latent heat of evaporation. The vapor passes through the hole 1A and moves into the hollow portion 31 of the heat spreader 30, the vapor condenses on the inner wall of the relatively low temperature hollow portion 31, and the latent heat of vaporization is released. The released latent heat of vaporization is exhausted to the cooling unit 37 via the TIM 36. On the other hand, the condensed hydraulic fluid 34 is circulated to the relatively high temperature CNT 4 by capillary action or gravity.

In the present embodiment, the heat conduction member existing between the hot spot 41 in the semiconductor chip 10 and the hollow portion 31 of the heat spreader 30 is only continuous CNT 4 having no interface between CNTs. A very small amount of the thin base material 2 and the catalyst material 3 exist at the bottom 1a ₁ of the hole 1A of the semiconductor chip 10, but there is almost no influence on the heat conduction and can be ignored. That is, in this case, the interface that substantially generates the thermal resistance is only one of the substrate portions of the CNT 4 and the semiconductor chip 10, and a highly efficient exhaust heat effect is obtained.

  As described above, according to the present embodiment, the excellent heat conductivity of the CNT 4 that is a heat conductive material disposed on the semiconductor chip 10 is exhibited as much as possible, thereby achieving high exhaust heat expected for the CNT 4. A sufficient effect can be obtained.

  The present invention can be applied not only to the semiconductor device described above, but also to a so-called 2.5D multilayer chip or the like in which a plurality of semiconductor chips are mounted on a plane, for example. In this case, a plurality of parallel semiconductor chips are arranged in the hollow portion of the heat spreader in the same manner as in this embodiment.

  Various aspects of the electronic device and the manufacturing method thereof are collectively described below as supplementary notes.

(Appendix 1) an electronic component having a heat conductive material disposed on the back surface;
A heat dissipation mechanism thermally connected to the electronic component,
The heat dissipation mechanism has a hollow portion in which an opening is formed and a working fluid is sealed inside,
A part of the heat conducting material enters the hollow portion from the opening and is immersed in the working fluid.

  (Supplementary note 2) The electronic device according to supplementary note 1, wherein the thermal conductive material is a linear structure of carbon.

(Appendix 3) The electronic component has a hole formed in the back surface,
The electronic device according to appendix 1 or 2, wherein the heat conductive material is embedded in the hole.

  (Additional remark 4) The said hydraulic fluid is 1 type chosen from water, a fluorine-type solvent, and alcohol, The electronic device of any one of Additional remarks 1-3 characterized by the above-mentioned.

(Additional remark 5) The process of arrange | positioning a heat conductive material in the back surface of an electronic component,
Thermally connecting the electronic component and the heat dissipation mechanism,
The heat dissipation mechanism has a hollow portion in which an opening is formed,
The electronic component is connected to a heat dissipation mechanism and sealed so that a part of the heat conductive material enters the hollow portion through the opening and the heat conductive material is immersed in the working fluid injected into the hollow portion. A method for manufacturing an electronic device.

  (Supplementary note 6) The method for manufacturing an electronic device according to supplementary note 5, wherein the thermal conductive material is a linear structure of carbon.

(Appendix 7) The electronic component has a hole formed in the back surface,
The method for manufacturing an electronic device according to appendix 5 or 6, wherein the thermally conductive material is embedded in the hole.

  (Additional remark 8) The said hydraulic fluid is 1 type chosen from water, a fluorine-type solvent, and alcohol, The manufacturing method of the electronic device any one of Additional remarks 5-7 characterized by the above-mentioned.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 1A Hole 1a Back surface 1a ₁ Bottom surface 1b Surface 2 Base material 3 Catalyst material 4 CNT
5 Element layer 10 Semiconductor chip 11 Element isolation structure 12 Well 13 Gate insulating film 14 Gate electrode 15 Cap film 16 Extension region 17 Side wall insulating film 18 Source / drain region 19, 23 Interlayer insulating film 19a Contact hole 20 Package substrate 20a Transistor element 20b Wiring structure 21 Contact plugs 22, 25 Wiring 23a Via hole 24 Via plug 26 Electrode pad 26
30 Heat spreader 31 Hollow portion 31a Opening 32 Solder bump 33 Resin 34 Hydraulic fluid 35 Adhesive 36 TIM
37 Cooling unit 41 Hot spot

Claims (8)

An electronic component having a heat conductive material disposed on the back surface;
A heat dissipation mechanism thermally connected to the electronic component,
The heat dissipation mechanism has a hollow portion in which an opening is formed and a working fluid is sealed inside,
A part of the heat conducting material enters the hollow portion from the opening and is immersed in the working fluid.   The electronic device according to claim 1, wherein the heat conductive material is a carbon linear structure. The electronic component has a hole formed in the back surface,
The electronic device according to claim 1, wherein the heat conductive material is embedded in the hole.   The electronic device according to any one of claims 1 to 3, wherein the hydraulic fluid is one selected from water, a fluorinated solvent, and alcohols. Arranging a heat conductive material on the back surface of the electronic component;
Thermally connecting the electronic component and the heat dissipation mechanism,
The heat dissipation mechanism has a hollow portion in which an opening is formed,
The electronic component is connected to a heat dissipation mechanism and sealed so that a part of the heat conductive material enters the hollow portion through the opening and the heat conductive material is immersed in the working fluid injected into the hollow portion. A method for manufacturing an electronic device.   The method for manufacturing an electronic device according to claim 5, wherein the heat conductive material is a linear structure of carbon. The electronic component has a hole formed in the back surface,
The method of manufacturing an electronic device according to claim 5, wherein the heat conductive material is embedded in the hole.   The method for manufacturing an electronic device according to claim 5, wherein the hydraulic fluid is one selected from water, a fluorine-based solvent, and alcohols.

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