JP2015079800A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device which forms a structure as represented by a gate electrode in a comparatively simple constitution and has high reliability.SOLUTION: A semiconductor device comprises a compound semiconductor layer 2, a gate electrode 8 formed on the compound semiconductor layer 2, a source electrode 4 and a drain electrode 5 which are formed on the compound semiconductor layer 2 and on both sides of the gate electrode 8, and a pair of projections 7a, 7b which are formed above the compound semiconductor layer 2 and on both sides of the gate electrode 8.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In a transistor, particularly a high electron mobility transistor (HEMT) of a compound semiconductor device, a so-called electron beam resist process is used when forming a gate electrode. In this case, an electron beam resist is applied to the surface of the compound semiconductor layer, and the electron beam resist is irradiated with an electron beam to form an opening. Etching is performed using the electron beam resist as a mask to form an opening in the underlying insulating film or the like, or a gate electrode is formed on the electron beam resist so as to fill the opening of the electron beam resist.

JP 2012-169539 A JP 2011-77123 A

  However, when a gate electrode is formed by an electron beam resist process, the electron beam resist has an adhesive property with the surface of the compound semiconductor layer or with a protective insulating film or a gate insulating film formed on the compound semiconductor layer. It is scarce. For this reason, when an opening is formed in the electron beam resist, the fracture is often caused by the stress applied to the electron beam resist, or the opening is often deformed. In this case, there is a problem that the gate electrode cannot be formed as designed.

  The present invention has been made in view of the above problems, and provides a highly reliable semiconductor device and a manufacturing method thereof by forming a structure represented by a gate electrode as designed with a relatively simple configuration. The purpose is to do.

  One embodiment of a compound semiconductor device includes a semiconductor layer, a first electrode formed above the semiconductor layer, and a pair of second electrodes formed on both sides of the first electrode above the semiconductor layer. And a pair of protrusions formed on both sides of the first electrode above the semiconductor layer.

  One embodiment of a method for manufacturing a compound semiconductor device includes a step of forming a semiconductor layer, a step of forming a pair of protrusions above the semiconductor layer, and covering the entire surface of the protrusions above the semiconductor layer. And a step of forming a resist mask having an opening at a portion spaced from the protrusions between the protrusions.

  According to the above aspects, a structure represented by a gate electrode is formed as designed with a relatively simple configuration, and a highly reliable semiconductor device is realized.

It is a schematic sectional drawing which shows the manufacturing method of the Schottky type AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1 illustrating a Schottky-type AlGaN / GaN.HEMT manufacturing method according to the first embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view showing the Schottky type AlGaN / GaN.HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 2. FIG. 4 is a schematic cross-sectional view illustrating the manufacturing method of the Schottky type AlGaN / GaN.HEMT according to the first embodiment in order of processes following FIG. 3. FIG. 5 is a schematic plan view showing a manufacturing process of the Schottky type AlGaN / GaN HEMT according to the first embodiment. It is a characteristic view which shows the various effects which AlGaN / GaN * HEMT by 1st Embodiment shows. FIG. 5 is a schematic cross-sectional view showing a method of manufacturing a Schottky AlGaN / GaN HEMT according to a second embodiment in the order of steps. FIG. 8 is a schematic cross-sectional view subsequent to FIG. 7 showing a manufacturing method of the Schottky type AlGaN / GaN.HEMT according to the second embodiment in the order of steps. FIG. 9 is a schematic cross-sectional view subsequent to FIG. 8 illustrating a Schottky type AlGaN / GaN.HEMT manufacturing method according to the second embodiment in the order of steps. FIG. 10 is a schematic cross-sectional view subsequent to FIG. 9 illustrating a Schottky-type AlGaN / GaN HEMT manufacturing method according to the second embodiment in the order of steps. It is a schematic sectional drawing which shows the manufacturing process of the AlGaN / GaN * HEMT of the comparative example of 2nd Embodiment. It is a schematic sectional drawing which shows the manufacturing process of the AlGaN / GaN * HEMT of the comparative example of 2nd Embodiment. It is a schematic sectional drawing which shows the manufacturing method of the Schottky type AlGaN / GaN * HEMT by 3rd Embodiment to process order. FIG. 14 is a schematic cross-sectional view subsequent to FIG. 13 showing a Schottky type AlGaN / GaN.HEMT manufacturing method according to the third embodiment in the order of steps. FIG. 15 is a schematic cross-sectional view showing the Schottky type AlGaN / GaN.HEMT manufacturing method according to the third embodiment in the order of steps, following FIG. 14. It is a schematic plan view showing a manufacturing process of a Schottky type AlGaN / GaN HEMT according to a third embodiment. It is a schematic sectional drawing which shows the manufacturing process of the Schottky type AlGaN / GaN * HEMT of 4th Embodiment. FIG. 18 is a schematic cross-sectional view illustrating a manufacturing process of the AlGaN / GaN HEMT according to the fourth embodiment of the Schottky type following FIG. 17. FIG. 19 is a schematic cross-sectional view illustrating a manufacturing process of the AlGaN / GaN HEMT according to the fourth embodiment of the Schottky type following FIG. 18. FIG. 20 is a schematic cross-sectional view illustrating the manufacturing process of the AlGaN / GaN HEMT according to the fourth embodiment of the Schottky type following FIG. 19. FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a MIS-type AlGaN / GaN HEMT according to a fifth embodiment in the order of steps. FIG. 22 is a schematic cross-sectional view showing the method of manufacturing the MIS type AlGaN / GaN.HEMT according to the fifth embodiment in order of steps, following FIG. 21. FIG. 23 is a schematic cross-sectional view showing the method of manufacturing the MIS type AlGaN / GaN HEMT according to the fifth embodiment in order of steps, following FIG. 22. It is a schematic sectional drawing which shows the manufacturing method of MIS type AlGaN / GaN * HEMT by 6th Embodiment in order of a process. FIG. 25 is a schematic cross-sectional view showing the manufacturing method of the MIS type AlGaN / GaN.HEMT according to the sixth embodiment in order of steps, following FIG. 24; FIG. 26 is a schematic cross-sectional view illustrating the manufacturing method of the MIS type AlGaN / GaN.HEMT according to the sixth embodiment in order of steps, following FIG. 25; It is a schematic sectional drawing which shows the manufacturing method of MIS type AlGaN / GaN * HEMT by 7th Embodiment in order of a process. FIG. 28 is a schematic cross-sectional view showing the manufacturing method of the MIS type AlGaN / GaN.HEMT according to the seventh embodiment in order of steps, following FIG. 27; It is a schematic sectional drawing which shows the manufacturing method of MIS type AlGaN / GaN * HEMT by 8th Embodiment in order of a process. FIG. 29 is a schematic cross-sectional view showing the manufacturing method of the MIS type AlGaN / GaN.HEMT according to the eighth embodiment in order of steps, following FIG. 29; FIG. 31 is a schematic cross-sectional view showing the manufacturing method of the MIS type AlGaN / GaN.HEMT according to the eighth embodiment in order of steps, following FIG. 30; It is a connection diagram which shows schematic structure of the power supply device by 9th Embodiment. It is a wiring diagram which shows schematic structure of the high frequency amplifier by 10th Embodiment.

Hereinafter, embodiments will be described in detail with reference to the drawings. In the following embodiments, the configuration of a semiconductor device will be described along with its manufacturing method.
In the following drawings, there are constituent members that are not shown in a relatively accurate size or thickness for convenience of illustration.

(First embodiment)
In the present embodiment, a Schottky AlGaN / GaN.HEMT is disclosed as a semiconductor device.
1 to 4 are schematic cross-sectional views showing a method of manufacturing a Schottky AlGaN / GaN HEMT according to the first embodiment in the order of steps.

First, as shown in FIG. 1A, a compound semiconductor layer 2 having a laminated structure of compound semiconductors is formed on, for example, a semi-insulating SiC substrate 1 as a growth substrate.
As the growth substrate, a Si substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the SiC substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.
The compound semiconductor layer 2 includes a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c, and a cap layer 2d. In the AlGaN / GaN.HEMT, a two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 2b and the electron supply layer 2c.

  More specifically, the following compound semiconductors are grown on the SiC substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.

  On the SiC substrate 1, AlN, i (Intensive Undoped) -GaN, n-AlGaN, and n-GaN are sequentially deposited, and a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c, and a cap layer 2d. Are stacked. A thin spacer layer such as AlGaN may be formed between the electron transit layer 2b and the electron supply layer 2c. As growth conditions for AlN, GaN, AlGaN, and GaN, a mixed gas of trimethylaluminum gas, trimethylgallium gas, and ammonia gas is used as a source gas. The presence / absence and flow rate of trimethylaluminum gas as an Al source and trimethylgallium gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material, is about 100 sccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing GaN and AlGaN as n-type, that is, when growing n-GaN in the cap layer 2d and n-AlGaN in the electron supply layer 2c, for example, SiH ₄ gas containing Si as an n-type impurity is predetermined. Add to source gas at flow rate. Thereby, Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 5 × 10 ¹⁸ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .
Here, the buffer layer 2a has a film thickness of about 0.1 μm, the electron transit layer 2b has a film thickness of about 3 μm, the electron supply layer 2c has a film thickness of about 20 nm, for example, an Al ratio of about 0.2 to 0.3, and the surface layer 2e has The film is formed to a thickness of about 10 nm.

Subsequently, as shown in FIG. 1B, an element isolation structure 3 is formed.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor layer 2. Thereby, the element isolation structure 3 is formed in the surface layers of the compound semiconductor layer 2 and the SiC substrate 1. An active region is defined on the compound semiconductor layer 2 by the element isolation structure 3.
The element isolation may be performed by using, for example, an STI (Shallow Trench Isolation) method instead of the above-described implantation method.

Subsequently, as shown in FIG. 1C, electrode grooves 2 </ b> A and 2 </ b> B are formed in the cap layer 2 d at the formation position of the source electrode and the drain electrode on the surface of the compound semiconductor layer 2.
More specifically, a resist mask 10 having openings 10a and 10b exposing the formation positions of the source and drain electrodes on the surface of the compound semiconductor layer 2 is formed. Using the resist mask 10, the cap layer 2d is removed by dry etching. Thereby, the electrode grooves 2A and 2B are formed. For dry etching, an inert gas such as Ar and a chlorine-based gas such as Cl ₂ are used as an etching gas. Here, the electrode groove may be formed by dry etching through the cap layer 2d to the surface layer portion of the electron supply layer 2c.

Subsequently, as shown in FIG. 2A, the source electrode 4 and the drain electrode 5 are formed.
Specifically, for example, Ti / Al (Ti is the lower layer and Al is the upper layer) is deposited as an electrode material in the electrode grooves 2A and 2B by the vapor deposition method using the resist mask 10. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. The resist mask 10 and Ti / Al deposited thereon are removed by a lift-off method. Thereafter, the SiC substrate 1 is heat-treated at, for example, about 550 ° C. in a nitrogen atmosphere, and the remaining Ti / Al is brought into ohmic contact with the electron supply layer 2c. In addition, when Ti / Al makes ohmic contact with the cap layer 2d without performing heat treatment, the heat treatment may not be performed. As a result, the source electrode 4 and the drain electrode 5 are formed in which the electrode grooves 2A and 2B are embedded under the Ti / Al.

Subsequently, as shown in FIG. 2B, a protective insulating film 6 is formed.
Specifically, an insulator such as silicon nitride (SiN) is deposited on the entire surface of the compound semiconductor layer 2 so as to cover the source electrode 4 and the drain electrode 5 to a thickness of, for example, about 50 nm using a plasma CVD method or the like. To do. Thereby, the protective insulating film 6 is formed. The protective insulating film 6 is formed using, for example, silane (SiH ₄ ) as an Si raw material and ammonia (NH ₃ ) as an N raw material, and the refractive index with respect to light having a wavelength of 633 nm is about 2.0 of stoichiometry.

Subsequently, as shown in FIG. 2C, a pair of protrusions 7 a and 7 b are formed on the protective insulating film 6.
Specifically, first, an insulating material, for example, HSQ (silicon oxide) is applied to the entire surface of the protective insulating film 6 by spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 7a and 7b made of silicon oxide are formed on the protective insulating film 6. FIG. 5A shows a state in which the protrusions 7a and 7b are viewed in plan. The protrusions 7 a and 7 b are formed in the active region defined by the element isolation structure 3 on the protective insulating film 6. The protrusions 7a and 7b are formed at a predetermined interval, here, for example, at an interval of about the width of the overgate portion of the gate electrode so that the gate electrode can be formed in the region between them.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed that opens a part where the pair of protrusions are formed, for example, aluminum (Al) is deposited on the resist mask as a metal material so as to fill the opening, and the resist mask and Al thereon are lifted off. Remove. Thus, a pair of protrusions made of Al are formed on the protective insulating film 6.

Subsequently, as shown in FIG. 3A, a resist mask 11 is formed.
Specifically, first, an electron beam resist is applied to the entire surface of the protective insulating film 6. As an electron beam resist, for example, the product name PMMA manufactured by US Microchem Co., Ltd. is applied by spin coating. After pre-baking the electron beam resist, the electron beam resist is irradiated with an electron beam, and, for example, 0.1 μm-long opening exposure is performed in the current direction of the gate electrode formation region. Develop the electron beam resist. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. Thus, a resist mask 11 having an opening 11a having a length of 0.1 μm is formed.

In the resist mask 11, protrusions 7a and 7b are embedded at portions spaced from the side surfaces of the opening 11a.
When the opening 11a of the resist mask 11 is formed, an internal stress (mainly tensile stress for expanding the opening diameter) is generated in the resist mask 11 to cause deformation of the opening 11a. In the present embodiment, the protrusions 7a and 7b are embedded in the resist mask 11 as described above. Therefore, even if encapsulated stress occurs, the protrusions 7a and 7b prevent the resist mask 11 from slipping on the surface of the protective insulating film 6, and the opening 11a is held in the desired opening state at the time of formation without deformation.

Subsequently, an opening 6 a is formed in the protective insulating film 6 as shown in FIG.
Specifically, the protective insulating film 6 is dry-etched using the resist mask 11 until the surface of the cap layer 2d is exposed at the bottom of the opening 11a. For example, SF ₆ is used as the etching gas. As a result, a strip-shaped opening 6a is formed in the protective insulating film 6 to expose the surface of the cap layer 2d with a length of about 0.1 μm.
The resist mask 11 is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 3C, a resist mask 12 for forming a gate is formed.
The resist mask 12 is composed of three layers of electron beam resist. Specifically, a lower layer resist 12A, an intermediate layer resist 12B, and an upper layer resist 12C are sequentially applied on the protective insulating film 6 so as to cover the protrusions 7a and 7b by a spin coating method. As the lower layer resist 12A, for example, trade name PMMA manufactured by Microchem Corporation of the United States is used. As the intermediate layer resist 12B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 12C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 12A is applied to a thickness in which the protrusions 7a and 7b are embedded.

  The applied lower layer resist 12A, intermediate layer resist 12B, and upper layer resist 12C are sequentially pre-baked. Thereafter, the upper layer resist 12C is irradiated with an electron beam, and exposure for opening of 0.8 μm length, for example, is performed in the current direction of the gate electrode formation region to develop the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Ca having a length of about 0.8 μm is formed in the upper resist 12C.

  Next, the intermediate layer resist 12B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 12B in a region set back by, for example, about 0.5 μm in the direction from the end of the opening 12Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 12B. An opening 12Ba is formed.

  Next, the lower resist 12A is irradiated with an electron beam so as to include the opening 6a of the protective insulating film 6 through the opening 12Ca and the opening 12Ba, and the exposure for opening having a length of, for example, 0.15 μm in the current direction of the gate electrode formation region. I do. The lower layer resist 12A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Aa having a length of about 0.15 μm is formed in the lower resist 12A.

In the lower layer resist 12A, protrusions 7a and 7b are embedded at portions spaced from the respective side surfaces of the opening 12Aa.
When the opening 12Aa is formed in the lower layer resist 12A, an internal stress (mainly tensile stress that expands the opening diameter) that causes deformation of the opening 12Aa occurs in the electric lower layer resist 12A. In the present embodiment, the protrusions 7a and 7b are embedded in the lower layer resist 12A as described above. Therefore, even if the internal stress occurs, the protrusions 7a and 7b suppress the slip of the lower resist 12A with respect to the surface of the protective insulating film 6, and the opening 12Aa is held in the desired opening state at the time of formation without being deformed.

  As described above, the resist mask 12 including the lower layer resist 12A having the opening 12Aa, the intermediate layer resist 12B having the opening 12Ba, and the upper layer resist 12C having the opening 12Ca is formed. In the resist mask 12, an opening through which the opening 12Aa, the opening 12Ba, and the opening 12Ca communicate is defined as 12a.

Subsequently, as shown in FIG. 4A, a gate electrode 8 is formed.
Specifically, using the resist mask 12, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 12a. The gate metal deposited on the resist mask 12 is not shown. As described above, the gate electrode 8 in which the fine gate portion 8a in which the opening 6a of the protective insulating film 6 and the opening 12Aa of the lower layer resist 12A are filled with the gate metal and the overgate portion 8b wider than the fine gate portion 8a is integrated. It is formed. The fine gate portion 8a is spaced from the protrusions 7a and 7b. The overgate portion 8b has protrusions 7a and 7b located below both ends thereof.

Subsequently, as shown in FIG. 4B, the resist mask 12 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 12 and unnecessary gate metal are removed by a lift-off method.

  The protrusions 7a and 7b extend along the longitudinal direction of the gate electrode 8 on both sides of the gate electrode 8, as shown in FIG. 5B (only the fine gate portion 8a of the gate electrode 8 is shown). Yes. The protrusion 7 a is formed between the gate electrode 8 and the source electrode 4 in the active region defined by the element isolation structure 3. The protrusion 7 b is formed between the gate electrode 8 and the drain electrode 5 in the active region defined by the element isolation structure 3.

Subsequently, as shown in FIG. 4C, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the protective insulating film 6 by a CVD method or the like so as to embed the gate electrode 8 and the protrusions 7a and 7b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 7a and 7b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, the protective insulating film of the interlayer insulating film 13 is formed by the protrusions 7a and 7b without applying an adhesive such as a silane coupling agent as a slip stopper between the protective insulating film 6 and the interlayer insulating film 13 as in the prior art. Slip with respect to 6 is suppressed. Thereby, the adhesion state of the interlayer insulating film 13 with the protective insulating film 6 is satisfactorily maintained.

After that, a Schottky type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 8.
The source electrode 4, the drain electrode 5, and the gate electrode 8 may be electrically connected without forming the interlayer insulating film 13.

  In this embodiment, by forming the protrusions 7a and 7b as described above, the opening 11a of the resist mask 11 and the opening 12Aa of the lower layer resist 12A are held in the intended opening state at the time of formation without deformation. . Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When the gate electrode manufactured according to the present embodiment was examined, the difference from the design value was suppressed within ± 5%, and no abnormal shape of the gate electrode was observed. These effects are summarized in FIG. (A) shows the formation rate of the side gate, and (b) shows the shift rate of the measured gate length.

  As described above, according to this embodiment, a structure such as the gate electrode 8 is formed as designed with a relatively simple configuration, and a highly reliable Schottky type that achieves high breakdown voltage and high output. AlGaN / GaN.HEMT can be obtained.

(Second Embodiment)
Hereinafter, the second embodiment will be described. In this embodiment, a Schottky-type AlGaN / GaN HEMT is manufactured as in the first embodiment, but the first is different in the order of the manufacturing process of the source and drain electrodes and the manufacturing process of the gate electrode. This is different from the embodiment. In addition, about the structural member etc. which respond | correspond to AlGaN / GaN * HEMT by 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
7 to 10 are schematic cross-sectional views illustrating a method for manufacturing a Schottky AlGaN / GaN HEMT according to the second embodiment in the order of steps.

First, similarly to the first embodiment, the steps of FIGS. 1A to 1C are sequentially performed. The state at this time is shown in FIG. The compound semiconductor layer 2 is formed on the SiC substrate 1, the element isolation structure 3 is formed, and the electrode grooves 2A and 2B are formed in the cap layer 2d on the surface of the compound semiconductor layer 2 where the source and drain electrodes are to be formed. The
In the present embodiment, after the formation of the electrode grooves 2A and 2B, the resist mask 10 is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 7B, a protective insulating film 6 is formed.
Specifically, an insulator such as silicon nitride (SiN) is deposited on the entire surface of the compound semiconductor layer 2 to a thickness of, for example, about 50 nm using a plasma CVD method or the like. Thereby, the protective insulating film 6 is formed. The protective insulating film 6 is formed using, for example, silane (SiH ₄ ) as an Si raw material and ammonia (NH ₃ ) as an N raw material, and the refractive index with respect to light having a wavelength of 633 nm is about 2.0 of stoichiometry.

Subsequently, as shown in FIG. 7C, a pair of protrusions 7 a and 7 b are formed on the protective insulating film 6.
Specifically, first, an insulator, for example, HSQ (silicon oxide), is applied to the entire surface of the protective insulating film 6.
Apply using spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 7a and 7b made of silicon oxide are formed on the protective insulating film 6. The protrusions 7 a and 7 b are formed in the active region defined by the element isolation structure 3 on the protective insulating film 6. The protrusions 7a and 7b are formed at a predetermined interval, here, for example, at an interval of about the width of the overgate portion of the gate electrode so that the gate electrode can be formed in the region between them.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed to open a portion where the pair of protrusions are formed, and Al, for example, is deposited as a metal material on the resist mask so as to fill the opening, and the resist mask and Al thereon are removed by lift-off. Thus, a pair of protrusions made of Al are formed on the protective insulating film 6.

Subsequently, as shown in FIG. 8A, a resist mask 11 is formed.
Specifically, first, an electron beam resist is applied to the entire surface of the protective insulating film 6. As an electron beam resist, for example, the product name PMMA manufactured by US Microchem Co., Ltd. is applied by spin coating. After pre-baking the electron beam resist, the electron beam resist is irradiated with an electron beam, and, for example, 0.1 μm-long opening exposure is performed in the current direction of the gate electrode formation region. Develop the electron beam resist. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. Thus, a resist mask 11 having an opening 11a having a length of 0.1 μm is formed.

In the resist mask 11, protrusions 7a and 7b are embedded at portions spaced from the side surfaces of the opening 11a.
When the opening 11a of the resist mask 11 is formed, an internal stress (mainly tensile stress for expanding the opening diameter) is generated in the resist mask 11 to cause deformation of the opening 11a. In the present embodiment, since the source electrode and the drain electrode are not yet formed in the state in which the resist mask 11 is formed, the occurrence of internal stress in the resist mask 11 becomes more significant than in the first embodiment.

  In the present embodiment, the protrusions 7a and 7b are embedded in the resist mask 11 as described above. Therefore, even if inclusion stress occurs (even if generation of inclusion stress becomes remarkable because the source electrode and the drain electrode are not formed), the protrusions 7a and 7b apply to the surface of the protective insulating film 6 of the resist mask 11. Slip is suppressed. As a result, the opening 11a is not deformed and is held in the desired opening state at the time of formation.

Subsequently, an opening 6 a is formed in the protective insulating film 6 as shown in FIG.
Specifically, the protective insulating film 6 is dry-etched using the resist mask 11 until the surface of the cap layer 2d is exposed at the bottom of the opening 11a. For example, SF ₆ is used as the etching gas. As a result, a strip-shaped opening 6a is formed in the protective insulating film 6 so as to expose the surface of the cap layer 2d with a length of about 0.1 μm.
The resist mask 11 is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 8C, a resist mask 12 for forming a gate is formed.
The resist mask 12 is composed of three layers of electron beam resist. Specifically, a lower layer resist 12A, an intermediate layer resist 12B, and an upper layer resist 12C are sequentially applied on the protective insulating film 6 so as to cover the protrusions 7a and 7b by a spin coating method. As the lower layer resist 12A, for example, trade name PMMA manufactured by Microchem Corporation of the United States is used. As the intermediate layer resist 12B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 12C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 12A is applied to a thickness in which the protrusions 7a and 7b are embedded.

  The applied lower layer resist 12A, intermediate layer resist 12B, and upper layer resist 12C are pre-baked. Thereafter, the upper layer resist 12C is irradiated with an electron beam, and exposure for opening of 0.8 μm length, for example, is performed in the current direction of the gate electrode formation region to develop the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Ca having a length of about 0.8 μm is formed in the upper resist 12C.

  Next, the intermediate layer resist 12B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 12B in a region set back by, for example, about 0.5 μm in the direction from the end of the opening 12Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 12B. An opening 12Ba is formed.

  Next, the lower resist 12A is irradiated with an electron beam so as to include the opening 6a of the protective insulating film 6 through the opening 12Ca and the opening 12Ba, and the exposure for opening having a length of, for example, 0.15 μm in the current direction of the gate electrode formation region. I do. The lower layer resist 12A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Aa having a length of about 0.15 μm is formed in the lower resist 12A.

In the lower layer resist 12A, protrusions 7a and 7b are embedded at portions spaced from the respective side surfaces of the opening 12Aa.
When the opening 12Aa is formed in the lower layer resist 12A, an internal stress (mainly tensile stress that expands the opening diameter) that causes deformation of the opening 12Aa occurs in the electric lower layer resist 12A. In the present embodiment, since the source electrode and the drain electrode are not yet formed in the state in which the lower layer resist 12A is formed, the occurrence of internal stress in the lower layer resist 12A becomes more significant than in the first embodiment.

  In the present embodiment, the protrusions 7a and 7b are embedded in the lower layer resist 12A as described above. Therefore, even if the internal stress occurs (even if the generation of the internal stress becomes significant because the source electrode and the drain electrode are not formed), the protrusions 7a and 7b cause the surface of the protective insulating film 6 of the lower resist 12A to be formed. Slip is suppressed. As a result, the opening 12Aa is held in the desired opening state at the time of formation without being deformed.

  As described above, the resist mask 12 including the lower layer resist 12A having the opening 12Aa, the intermediate layer resist 12B having the opening 12Ba, and the upper layer resist 12C having the opening 12Ca is formed. In the resist mask 12, an opening through which the opening 12Aa, the opening 12Ba, and the opening 12Ca communicate is defined as 12a.

Subsequently, as shown in FIG. 9A, a gate electrode 8 is formed.
Specifically, using the resist mask 12, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 12a. The gate metal deposited on the resist mask 12 is not shown. As described above, the gate electrode 8 in which the fine gate portion 8a in which the opening 6a of the protective insulating film 6 and the opening 12Aa of the lower layer resist 12A are filled with the gate metal and the overgate portion 8b wider than the fine gate portion 8a is integrated. It is formed. The fine gate portion 8a is spaced from the protrusions 7a and 7b. The overgate portion 8b has protrusions 7a and 7b located below both ends thereof.

Subsequently, as shown in FIG. 9B, the resist mask 12 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 12 and unnecessary gate metal are removed by a lift-off method.

Subsequently, as shown in FIG. 9C, the electrode grooves 2A and 2B of the cap layer 2d are exposed.
Specifically, the protective insulating film 6 is processed by lithography and dry etching to form openings 6b and 6c in the protective insulating film 6 that expose the electrode grooves 2A and 2B of the cap layer 2d.
The resist used for lithography is removed by ashing using oxygen plasma or wet processing using a chemical solution.

Subsequently, as shown in FIG. 10A, the source electrode 4 and the drain electrode 5 are formed.
For example, Ti / Al (the lower layer is Ti and the upper layer is Al) is used as the electrode material. For the electrode formation, for example, a saddle structure two-layer resist suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor layer 2 to form a resist mask that opens the electrode grooves 2A and 2B. Using this resist mask, Ti / Al is deposited, for example, by vapor deposition. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. By the lift-off method, the resist mask having a ridge structure and Ti / Al deposited thereon are removed. Thereafter, the SiC substrate 1 is heat-treated at, for example, 400 ° C. to 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere, and the remaining Ti / Al is brought into ohmic contact with the cap layer 2d. In addition, when Ti / Al makes ohmic contact with the cap layer 2d without performing heat treatment, the heat treatment may not be performed. As a result, the source electrode 4 and the drain electrode 5 are formed in which the electrode grooves 2A and 2B are embedded under the Ti / Al.

  The protrusions 7 a and 7 b extend along the longitudinal direction of the gate electrode 8 on both sides of the gate electrode 8. The protrusion 7 a is formed between the gate electrode 8 and the source electrode 4 in the active region defined by the element isolation structure 3. The protrusion 7 b is formed between the gate electrode 8 and the drain electrode 5 in the active region defined by the element isolation structure 3.

Subsequently, as shown in FIG. 10B, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the protective insulating film 6 by a CVD method or the like so as to embed the gate electrode 8 and the protrusions 7a and 7b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 7a and 7b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, the protective insulating film of the interlayer insulating film 13 is formed by the protrusions 7a and 7b without applying an adhesive such as a silane coupling agent as a slip stopper between the protective insulating film 6 and the interlayer insulating film 13 as in the prior art. Slip with respect to 6 is suppressed. Thereby, the adhesion state of the interlayer insulating film 13 with the protective insulating film 6 is satisfactorily maintained.

After that, a Schottky type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 8.
The source electrode 4, the drain electrode 5, and the gate electrode 8 may be electrically connected without forming the interlayer insulating film 13.

In the following, the operational effects of the AlGaN / GaN HEMT according to the present embodiment will be described based on a comparison with a comparative example.
FIG. 11 and FIG. 12 are schematic cross-sectional views showing a manufacturing process of an AlGaN / GaN.HEMT as a comparative example of the present embodiment. FIG. 11 corresponds to FIG. 8A, and FIG. 12 corresponds to FIG. 8C. The AlGaN / GaN HEMT of the comparative example is manufactured in the same manner as in this embodiment except that the protrusions 7a and 7b are not formed.

  In the AlGaN / GaN HEMT according to the comparative example, as shown in FIGS. 11A and 11B, when the opening 11a of the resist mask 11 is formed, the stress included in the resist mask 11 is deformed in the opening 11a. Occurs. As shown in the figure, the internal stress is mainly a tensile stress that tends to expand the opening 11a. Therefore, the opening diameter of the opening 11a is expanded as shown in FIG. 11A, or the resist mask 11 is broken as shown in FIG. 11B to form the side opening 11b.

  Similarly, in the AlGaN / GaN HEMT according to the comparative example, when the opening 12Aa is formed in the lower resist 12A of the resist mask 12 as shown in FIGS. 12A and 12B, the opening 12Aa is formed in the lower resist 12A. This causes internal stress that causes deformation. As shown in the figure, the internal stress is mainly a tensile stress that tends to expand the opening 12Aa. Therefore, the opening diameter of the opening 12Aa is expanded as shown in FIG. 12A, or the lower resist 12A is broken as shown in FIG. 12B to form the side opening 12Ab.

  In the comparative example, as a result of being as shown in FIGS. 11 and 12, there is a problem that the fine gate portion of the gate electrode is formed in a dimension different from the design value, or a side gate portion is formed in the gate electrode. When a predetermined number of AlGaN / GaN.HEMT was examined, the defect occurrence rate in the comparative example was 80% or more.

  On the other hand, in the present embodiment, the projections 7a and 7b are formed as described above, so that the opening 11a of the resist mask 11 and the opening 12Aa of the lower resist 12A are not deformed, and an intended opening state at the time of formation is formed. Retained. Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When a predetermined number of AlGaN / GaN HEMTs manufactured according to the present embodiment were examined, the defect occurrence rate was 2% or less. In the present embodiment, the difference from the design value of the gate electrode is suppressed within ± 5%, and no shape abnormality of the gate electrode was observed.

  As described above, according to this embodiment, a structure such as the gate electrode 8 is formed as designed with a relatively simple configuration, and a highly reliable Schottky type that achieves high breakdown voltage and high output. AlGaN / GaN.HEMT can be obtained.

(Third embodiment)
Hereinafter, a third embodiment will be described. In the present embodiment, a Schottky type AlGaN / GaN HEMT is fabricated as in the first embodiment, but differs from the first embodiment in that the formation positions of the pair of protrusions are different. In addition, about the structural member etc. which respond | correspond to AlGaN / GaN * HEMT by 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
FIG. 13 to FIG. 15 are schematic cross-sectional views showing the method of manufacturing the Schottky type AlGaN / GaN.HEMT according to the third embodiment in the order of steps.

  First, similarly to the first embodiment, the processes in FIGS. 1A to 2B are sequentially performed. The state at this time is shown in FIG. The compound semiconductor layer 2 is formed on the SiC substrate 1, the element isolation structure 3 is formed, and the electrode grooves 2A and 2B are formed in the cap layer 2d on the surface of the compound semiconductor layer 2 where the source and drain electrodes are to be formed. The Furthermore, a source electrode 4 and a drain electrode 5 filling the electrode grooves 2A and 2B are formed, and a protective insulating film 6 is formed on the entire surface of the compound semiconductor layer 2 so as to cover the source electrode 4 and the drain electrode 5.

Subsequently, as shown in FIG. 13B, a pair of protrusions 21 a and 21 b are formed on the protective insulating film 6.
Specifically, first, an insulating material, for example, HSQ (silicon oxide) is applied to the entire surface of the protective insulating film 6 by spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 21a and 21b made of silicon oxide are formed on the protective insulating film 6. FIG. 16A shows a state in which the protrusions 21a and 21b are viewed in plan. The protrusions 21 a and 21 b are formed on the protective insulating film 6 outside the active region defined by the element isolation structure 3, that is, above the element isolation structure 3.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed to open a portion where the pair of protrusions are formed, and Al, for example, is deposited as a metal material on the resist mask so as to fill the opening, and the resist mask and Al thereon are removed by lift-off. Thus, a pair of protrusions made of Al are formed on the protective insulating film 6.

Subsequently, as shown in FIG. 13C, a resist mask 11 is formed.
Specifically, first, an electron beam resist is applied to the entire surface of the protective insulating film 6. As an electron beam resist, for example, the product name PMMA manufactured by US Microchem Co., Ltd. is applied by spin coating. After pre-baking the electron beam resist, the electron beam resist is irradiated with an electron beam, and, for example, 0.1 μm-long opening exposure is performed in the current direction of the gate electrode formation region. Develop the electron beam resist. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. Thus, a resist mask 11 having an opening 11a having a length of 0.1 μm is formed.

In the resist mask 11, projections 21 a and 21 b are embedded at portions spaced from the side surfaces of the opening 11 a.
When the opening 11a of the resist mask 11 is formed, an internal stress (mainly tensile stress for expanding the opening diameter) is generated in the resist mask 11 to cause deformation of the opening 11a. In the present embodiment, the protrusions 21a and 21b are embedded in the resist mask 11 as described above. Therefore, even if the internal stress occurs, the protrusions 21a and 21b suppress the slip of the resist mask 11 with respect to the surface of the protective insulating film 6, and the opening 11a is held in an intended opening state at the time of formation without being deformed.

Subsequently, as shown in FIG. 14A, an opening 6 a is formed in the protective insulating film 6.
Specifically, the protective insulating film 6 is dry-etched using the resist mask 11 until the surface of the cap layer 2d is exposed at the bottom of the opening 11a. For example, SF ₆ is used as the etching gas. As a result, a strip-shaped opening 6a is formed in the protective insulating film 6 so as to expose the surface of the cap layer 2d with a length of about 0.1 μm.
The resist mask 11 is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 14B, a resist mask 12 for forming a gate is formed.
The resist mask 12 is composed of three layers of electron beam resist. Specifically, a lower layer resist 12A, an intermediate layer resist 12B, and an upper layer resist 12C are sequentially applied on the protective insulating film 6 so as to cover the protrusions 21a and 21b by a spin coating method. As the lower layer resist 12A, for example, trade name PMMA manufactured by Microchem Corporation of the United States is used. As the intermediate layer resist 12B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 12C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 12A is applied to a thickness in which the protrusions 21a and 21b are embedded.

  The applied lower layer resist 12A, intermediate layer resist 12B, and upper layer resist 12C are pre-baked. Thereafter, the upper layer resist 12C is irradiated with an electron beam, and exposure for opening of 0.8 μm length, for example, is performed in the current direction of the gate electrode formation region to develop the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Ca having a length of about 0.8 μm is formed in the upper resist 12C.

  Next, the intermediate layer resist 12B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 12B in a region set back by, for example, about 0.5 μm in the direction from the end of the opening 12Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 12B. An opening 12Ba is formed.

  Next, the lower resist 12A is irradiated with an electron beam so as to include the opening 6a of the protective insulating film 6 through the opening 12Ca and the opening 12Ba, and the exposure for opening having a length of, for example, 0.15 μm in the current direction of the gate electrode formation region. I do. The lower layer resist 12A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Aa having a length of about 0.15 μm is formed in the lower resist 12A.

In the lower layer resist 12A, protrusions 21a and 21b are embedded in portions spaced from the side surfaces of the opening 12Aa.
When the opening 12Aa is formed in the lower layer resist 12A, an internal stress (mainly tensile stress that expands the opening diameter) that causes deformation of the opening 12Aa occurs in the electric lower layer resist 12A. In the present embodiment, the protrusions 21a and 21b are embedded in the lower layer resist 12A as described above. Therefore, even if the internal stress occurs, the protrusions 21a and 21b suppress the slip of the lower resist 12A with respect to the surface of the protective insulating film 6, and the opening 12Aa is held in the desired opening state at the time of formation without being deformed.

  As described above, the resist mask 12 including the lower layer resist 12A having the opening 12Aa, the intermediate layer resist 12B having the opening 12Ba, and the upper layer resist 12C having the opening 12Ca is formed. In the resist mask 12, an opening through which the opening 12Aa, the opening 12Ba, and the opening 12Ca communicate is defined as 12a.

Subsequently, as shown in FIG. 14C, the gate electrode 8 is formed.
Specifically, using the resist mask 12, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 12a. The gate metal deposited on the resist mask 12 is not shown. As described above, the gate electrode 8 in which the fine gate portion 8a in which the opening 6a of the protective insulating film 6 and the opening 12Aa of the lower layer resist 12A are filled with the gate metal and the overgate portion 8b wider than the fine gate portion 8a is integrated. It is formed. The gate electrode 8 is spaced from the protrusions 21a and 21b.

Subsequently, as shown in FIG. 15A, the resist mask 12 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 12 and unnecessary gate metal are removed by a lift-off method.

  The protrusions 21a and 21b extend along the longitudinal direction of the gate electrode 8 on both sides of the gate electrode 8, as shown in FIG. 16B (only the fine gate portion 8a of the gate electrode 8 is shown). Yes. The protrusion 21 a is formed outside the source electrode 4 above the element isolation structure 3. The protrusion 21 b is formed outside the drain electrode 5 above the element isolation structure 3.

Subsequently, as shown in FIG. 15B, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the protective insulating film 6 by a CVD method or the like so as to embed the gate electrode 8 and the protrusions 21a and 21b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 21a and 21b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, the protrusions 21a and 21b cause the interlayer insulating film 13 to slip with respect to the protective insulating film 6 without applying an adhesive such as a silane coupling agent as a slip stopper between the protective insulating film 6 and the interlayer insulating film 13. Deterred. Thereby, the adhesion state of the interlayer insulating film 13 with the protective insulating film 6 is satisfactorily maintained.

After that, a Schottky type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 8.
The source electrode 4, the drain electrode 5, and the gate electrode 8 may be electrically connected without forming the interlayer insulating film 13.

  In this embodiment, by forming the protrusions 21a and 21b as described above, the opening 11a of the resist mask 11 and the opening 12Aa of the lower layer resist 12A are held in the intended opening state at the time of formation without deformation. . Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When the gate electrode manufactured according to the present embodiment was examined, the difference from the design value was suppressed within ± 5%, and no abnormal shape of the gate electrode was observed.

  As described above, according to this embodiment, a structure such as the gate electrode 8 is formed as designed with a relatively simple configuration, and a highly reliable Schottky type that achieves high breakdown voltage and high output. AlGaN / GaN.HEMT can be obtained.

(Fourth embodiment)
Hereinafter, a fourth embodiment will be described. In this embodiment, a Schottky type AlGaN / GaN HEMT is manufactured as in the second embodiment, but is different from the second embodiment in that the formation positions of the pair of protrusions are different. In addition, about the structural member etc. corresponding to AlGaN / GaN * HEMT by 2nd Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
FIG. 17 to FIG. 20 are schematic cross-sectional views showing the method of manufacturing the Schottky AlGaN / GaN.HEMT according to the fourth embodiment in the order of steps.

  First, similarly to the second embodiment, after sequentially performing the processes of FIGS. 1A to 1C, the process of FIG. 7B is performed. The state at this time is shown in FIG. The compound semiconductor layer 2 is formed on the SiC substrate 1, the element isolation structure 3 is formed, and the electrode grooves 2A and 2B are formed in the cap layer 2d on the surface of the compound semiconductor layer 2 where the source and drain electrodes are to be formed. The Further, a protective insulating film 6 is formed on the entire surface of the compound semiconductor layer 2.

Subsequently, as shown in FIG. 17B, a pair of protrusions 21 a and 21 b is formed on the protective insulating film 6.
Specifically, first, an insulating material, for example, HSQ (silicon oxide) is applied to the entire surface of the protective insulating film 6 by spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 21a and 21b made of silicon oxide are formed on the protective insulating film 6. The protrusions 21 a and 21 b are formed on the protective insulating film 6 outside the active region defined by the element isolation structure 3, that is, above the element isolation structure 3.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed to open a portion where the pair of protrusions are formed, and Al, for example, is deposited as a metal material on the resist mask so as to fill the opening, and the resist mask and Al thereon are removed by lift-off. Thus, a pair of protrusions made of Al are formed on the protective insulating film 6.

Subsequently, as shown in FIG. 17C, a resist mask 11 is formed.
Specifically, first, an electron beam resist is applied to the entire surface of the protective insulating film 6. As an electron beam resist, for example, the product name PMMA manufactured by US Microchem Co., Ltd. is applied by spin coating. After pre-baking the electron beam resist, the electron beam resist is irradiated with an electron beam, and, for example, 0.1 μm-long opening exposure is performed in the current direction of the gate electrode formation region. Develop the electron beam resist. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. Thus, a resist mask 11 having an opening 11a having a length of 0.1 μm is formed.

In the resist mask 11, projections 21 a and 21 b are embedded at portions spaced from the side surfaces of the opening 11 a.
When the opening 11a of the resist mask 11 is formed, an internal stress (mainly tensile stress for expanding the opening diameter) is generated in the resist mask 11 to cause deformation of the opening 11a. In the present embodiment, since the source electrode and the drain electrode are not yet formed in the state in which the resist mask 11 is formed, the occurrence of internal stress in the resist mask 11 becomes more significant than in the third embodiment.

  In the present embodiment, the protrusions 21a and 21b are embedded in the resist mask 11 as described above. Therefore, even if inclusion stress occurs (even if generation of inclusion stress becomes significant because the source electrode and the drain electrode are not formed), the protrusions 21a and 21b apply to the surface of the protective insulating film 6 of the resist mask 11 with the protrusions 21a and 21b. Slip is suppressed. As a result, the opening 11a is not deformed and is held in the desired opening state at the time of formation.

Subsequently, as illustrated in FIG. 18A, an opening 6 a is formed in the protective insulating film 6.
Specifically, the protective insulating film 6 is dry-etched using the resist mask 11 until the surface of the cap layer 2d is exposed at the bottom of the opening 11a. For example, SF ₆ is used as the etching gas. As a result, a strip-shaped opening 6a is formed in the protective insulating film 6 so as to expose the surface of the cap layer 2d with a length of about 0.1 μm.
The resist mask 11 is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 18B, a resist mask 12 for forming a gate is formed.
The resist mask 12 is composed of three layers of electron beam resist. Specifically, a lower layer resist 12A, an intermediate layer resist 12B, and an upper layer resist 12C are sequentially applied on the protective insulating film 6 so as to cover the protrusions 21a and 21b by a spin coating method. As the lower layer resist 12A, for example, trade name PMMA manufactured by Microchem Corporation of the United States is used. As the intermediate layer resist 12B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 12C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 12A is applied to a thickness in which the protrusions 21a and 21b are embedded.

  The applied lower layer resist 12A, intermediate layer resist 12B, and upper layer resist 12C are pre-baked. Thereafter, the upper layer resist 12C is irradiated with an electron beam, and exposure for opening of 0.8 μm length, for example, is performed in the current direction of the gate electrode formation region to develop the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Ca having a length of about 0.8 μm is formed in the upper resist 12C.

  Next, the intermediate layer resist 12B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 12B in a region set back by, for example, about 0.5 μm in the direction from the end of the opening 12Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 12B. An opening 12Ba is formed.

  Next, the lower resist 12A is irradiated with an electron beam so as to include the opening 6a of the protective insulating film 6 through the opening 12Ca and the opening 12Ba, and the exposure for opening having a length of, for example, 0.15 μm in the current direction of the gate electrode formation region. I do. The lower layer resist 12A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 12Aa having a length of about 0.15 μm is formed in the lower resist 12A.

In the lower layer resist 12A, protrusions 21a and 21b are embedded in portions spaced from the side surfaces of the opening 12Aa.
When the opening 12Aa is formed in the lower layer resist 12A, an internal stress (mainly tensile stress that expands the opening diameter) that causes deformation of the opening 12Aa occurs in the electric lower layer resist 12A. In the present embodiment, since the source electrode and the drain electrode are not yet formed in the state in which the lower layer resist 12A is formed, the generation of the internal stress in the lower layer resist 12A becomes more significant than in the third embodiment.

  In the present embodiment, the protrusions 21a and 21b are embedded in the lower layer resist 12A as described above. Therefore, even if inclusion stress occurs (even if generation of inclusion stress becomes significant because the source electrode and the drain electrode are not formed), the protrusions 21a and 21b cause the surface of the protective insulating film 6 of the lower resist 12A to be affected. Slip is suppressed. As a result, the opening 12Aa is held in the desired opening state at the time of formation without being deformed.

  As described above, the resist mask 12 including the lower layer resist 12A having the opening 12Aa, the intermediate layer resist 12B having the opening 12Ba, and the upper layer resist 12C having the opening 12Ca is formed. In the resist mask 12, an opening through which the opening 12Aa, the opening 12Ba, and the opening 12Ca communicate is defined as 12a.

Subsequently, as shown in FIG. 18C, the gate electrode 8 is formed.
Specifically, using the resist mask 12, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 12a. The gate metal deposited on the resist mask 12 is not shown. As described above, the gate electrode 8 in which the fine gate portion 8a in which the opening 6a of the protective insulating film 6 and the opening 12Aa of the lower layer resist 12A are filled with the gate metal and the overgate portion 8b wider than the fine gate portion 8a is integrated. It is formed. The gate electrode 8 is spaced from the protrusions 21a and 21b.

Subsequently, as shown in FIG. 19A, the resist mask 12 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 12 and unnecessary gate metal are removed by a lift-off method.

Subsequently, as shown in FIG. 19B, the electrode grooves 2A and 2B of the cap layer 2d are exposed.
Specifically, the protective insulating film 6 is processed by lithography and dry etching to form openings 6b and 6c in the protective insulating film 6 that expose the electrode grooves 2A and 2B of the cap layer 2d.
The resist used for lithography is removed by ashing using oxygen plasma or wet processing using a chemical solution.

Subsequently, as shown in FIG. 20A, the source electrode 4 and the drain electrode 5 are formed.
For example, Ti / Al (the lower layer is Ti and the upper layer is Al) is used as the electrode material. For the electrode formation, for example, a saddle structure two-layer resist suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor layer 2 to form a resist mask that opens the electrode grooves 2A and 2B. Using this resist mask, Ti / Al is deposited, for example, by vapor deposition. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. By the lift-off method, the resist mask having a ridge structure and Ti / Al deposited thereon are removed. Thereafter, the SiC substrate 1 is heat-treated at, for example, 400 ° C. to 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere, and the remaining Ti / Al is brought into ohmic contact with the cap layer 2d. In addition, when Ti / Al makes ohmic contact with the cap layer 2d without performing heat treatment, the heat treatment may not be performed. As a result, the source electrode 4 and the drain electrode 5 are formed in which the electrode grooves 2A and 2B are embedded under the Ti / Al.

  The protrusions 21 a and 21 b extend along the longitudinal direction of the gate electrode 8 on both sides of the gate electrode 8. The protrusion 21 a is formed outside the source electrode 4 above the element isolation structure 3. The protrusion 21 b is formed outside the drain electrode 5 above the element isolation structure 3.

Subsequently, as shown in FIG. 20B, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the protective insulating film 6 by a CVD method or the like so as to embed the gate electrode 8 and the protrusions 21a and 21b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 21a and 21b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, the protrusions 21a and 21b cause the interlayer insulating film 13 to slip with respect to the protective insulating film 6 without applying an adhesive such as a silane coupling agent as a slip stopper between the protective insulating film 6 and the interlayer insulating film 13. Deterred. Thereby, the adhesion state of the interlayer insulating film 13 with the protective insulating film 6 is satisfactorily maintained.

After that, a Schottky type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 8.
The source electrode 4, the drain electrode 5, and the gate electrode 8 may be electrically connected without forming the interlayer insulating film 13.

  In this embodiment, by forming the protrusions 21a and 21b as described above, the opening 11a of the resist mask 11 and the opening 12Aa of the lower layer resist 12A are held in the intended opening state at the time of formation without deformation. . Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When the gate electrode manufactured according to the present embodiment was examined, the difference from the design value was suppressed within ± 5%, and no abnormal shape of the gate electrode was observed.

  As described above, according to this embodiment, a structure such as the gate electrode 8 is formed as designed with a relatively simple configuration, and a highly reliable Schottky type that achieves high breakdown voltage and high output. AlGaN / GaN.HEMT can be obtained.

(Fifth embodiment)
Hereinafter, the second embodiment will be described. In the present embodiment, an AlGaN / GaN.HEMT is manufactured as in the first embodiment, but is different from the first embodiment in that it is a MIS type AlGaN / GaN.HEMT. In addition, about the structural member etc. which respond | correspond to AlGaN / GaN * HEMT by 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
FIG. 21 to FIG. 23 are schematic cross-sectional views showing the method of manufacturing the MIS type AlGaN / GaN.HEMT according to the fifth embodiment in the order of steps.

  First, similarly to the first embodiment, the steps in FIGS. 1A to 2A are sequentially performed. The situation at this time is shown in FIG. The compound semiconductor layer 2 is formed on the SiC substrate 1, the element isolation structure 3 is formed, and the electrode grooves 2A and 2B are formed in the cap layer 2d on the surface of the compound semiconductor layer 2 where the source and drain electrodes are to be formed. The Furthermore, the source electrode 4 and the drain electrode 5 which fill the electrode grooves 2A and 2B are formed.

Subsequently, as shown in FIG. 21B, a gate insulating film 22 is formed.
Specifically, for example, Al ₂ O ₃ is deposited on the compound semiconductor layer 2 as an insulating material. Al ₂ O ₃ alternately supplies TMA gas and O ₃ by, for example, atomic layer deposition (ALD method). In the present embodiment, Al ₂ O ₃ is deposited so that the thickness is about ₂ nm to 200 nm, for example, about 20 nm. Thereby, the gate insulating film 22 is formed.

Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

Subsequently, as shown in FIG. 21C, a pair of protrusions 7 a and 7 b are formed on the gate insulating film 22.
Specifically, first, an insulator, for example, HSQ (silicon oxide) is applied to the entire surface of the gate insulating film 22 by using spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 7a and 7b made of silicon oxide are formed on the gate insulating film 22. The protrusions 7 a and 7 b are formed in the active region defined by the element isolation structure 3 on the gate insulating film 22. The protrusions 7a and 7b are formed at a predetermined interval, here, for example, at an interval of about the width of the overgate portion of the gate electrode so that the gate electrode can be formed in the region between them.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed to open a portion where the pair of protrusions are formed, and Al, for example, is deposited as a metal material on the resist mask so as to fill the opening, and the resist mask and Al thereon are removed by lift-off. Thus, a pair of protrusions made of Al are formed on the gate insulating film 22.

Subsequently, as shown in FIG. 22A, a resist mask 23 for forming a gate is formed.
The resist mask 23 is composed of three layers of electron beam resist. Specifically, a lower layer resist 23A, an intermediate layer resist 23B, and an upper layer resist 23C are sequentially applied on the gate insulating film 22 so as to cover the protrusions 7a and 7b by spin coating. As the lower layer resist 23A, for example, trade name PMMA manufactured by Microchem Inc. in the United States is used. As the intermediate layer resist 23B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 23C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 23A is applied to a thickness in which the protrusions 7a and 7b are embedded.

  The applied lower layer resist 23A, intermediate layer resist 23B, and upper layer resist 23C are pre-baked. Thereafter, the upper layer resist 23C is irradiated with an electron beam to perform exposure for opening having a length of, for example, 0.8 μm in the current direction of the gate electrode formation region, thereby developing the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 23Ca having a length of about 0.8 μm is formed in the upper resist 23C.

  Next, the intermediate layer resist 23B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 23B in a region set back by, for example, about 0.5 μm in the direction from the end of the opening 23Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 23B. An opening 23Ba is formed.

  Next, the lower resist 23A is irradiated with an electron beam through the opening 23Ca and the opening 23Ba to perform, for example, 0.1 μm-long opening exposure in the current direction of the gate electrode formation region. The lower layer resist 23A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. Thus, a strip-shaped opening 23Aa having a length of about 0.1 μm is formed in the lower layer resist 23A to expose a part of the surface of the gate insulating film 22.

In the lower layer resist 23A, protrusions 7a and 7b are embedded at portions spaced from the respective side surfaces of the opening 23Aa.
When the opening 23Aa is formed in the lower layer resist 23A, an internal stress (mainly tensile stress that expands the opening diameter) is generated in the electric lower layer resist 23A. In the present embodiment, the protrusions 7a and 7b are embedded in the lower layer resist 23A as described above. Therefore, even if the internal stress occurs, the protrusions 7a and 7b suppress the slip of the lower resist 23A with respect to the surface of the gate insulating film 22, and the opening 23Aa is held in the intended opening state at the time of formation without being deformed.

  As described above, the resist mask 23 including the lower layer resist 12A having the opening 23Aa, the intermediate layer resist 23B having the opening 23Ba, and the upper layer resist 23C having the opening 23Ca is formed. In the resist mask 23, an opening through which the opening 23Aa, the opening 23Ba, and the opening 23Ca communicate is referred to as 23a.

Subsequently, as shown in FIG. 22B, a gate electrode 24 is formed.
Specifically, using the resist mask 23, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 23a. The gate metal deposited on the resist mask 23 is not shown. As described above, the gate electrode 24 is formed in which the fine gate portion 24a for embedding the opening 23Aa of the lower layer resist 23A with the gate metal and the overgate portion 24b wider than the fine gate portion 24a are integrated. The fine gate portion 24a is spaced from the protrusions 7a and 7b. The over gate portion 24b has protrusions 7a and 7b located below both end portions thereof.

Subsequently, as shown in FIG. 23A, the resist mask 23 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 23 and unnecessary gate metal are removed by a lift-off method.

  The protrusions 7 a and 7 b extend along the longitudinal direction of the gate electrode 24 on both sides of the gate electrode 24. The protrusion 7 a is formed between the gate electrode 24 and the source electrode 4 in the active region defined by the element isolation structure 3. The protrusion 7 b is formed between the gate electrode 24 and the drain electrode 5 in the active region defined by the element isolation structure 3.

Subsequently, as shown in FIG. 23B, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the gate insulating film 22 by a CVD method or the like so as to embed the gate electrode 24 and the protrusions 7a and 7b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 7a and 7b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, the gate insulating film of the interlayer insulating film 13 is formed by the protrusions 7a and 7b without applying an adhesive such as a silane coupling agent as a slip stopper between the gate insulating film 22 and the interlayer insulating film 13 as in the prior art. Slip with respect to 22 is suppressed. Thereby, the adhesion state between the interlayer insulating film 13 and the gate insulating film 22 is satisfactorily maintained.

Thereafter, MIS type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 24.
Note that the source electrode 4, the drain electrode 5, and the gate electrode 24 may be electrically connected without forming the interlayer insulating film 13.

  In the present embodiment, by forming the protrusions 7a and 7b as described above, the opening 23Aa of the lower layer resist 23A is held in the desired opening state at the time of formation without being deformed. Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When the gate electrode manufactured according to the present embodiment was examined, the difference from the design value was suppressed within ± 5%, and no abnormal shape of the gate electrode was observed.

  As described above, according to the present embodiment, a structure such as the gate electrode 24 is formed as designed with a relatively simple structure, and a highly reliable MIS type AlGaN that achieves high breakdown voltage and high output. /GaN.HEMT can be obtained.

(Sixth embodiment)
The sixth embodiment will be described below. In the present embodiment, a MIS type AlGaN / GaN HEMT is fabricated as in the fifth embodiment. However, the fifth and fifth embodiments are different in the order of the source electrode and drain electrode manufacturing process and the gate electrode manufacturing process. It is different from the embodiment. In addition, about the structural member etc. corresponding to AlGaN / GaN * HEMT by 5th Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
24 to 26 are schematic cross-sectional views showing a method of manufacturing the MIS type AlGaN / GaN.HEMT according to the sixth embodiment in the order of steps.

First, similarly to the first embodiment, the steps of FIGS. 1A to 1C are sequentially performed. The state at this time is shown in FIG. The compound semiconductor layer 2 is formed on the SiC substrate 1, the element isolation structure 3 is formed, and the electrode grooves 2A and 2B are formed in the cap layer 2d on the surface of the compound semiconductor layer 2 where the source and drain electrodes are to be formed. The
In the present embodiment, after the formation of the electrode grooves 2A and 2B, the resist mask 10 is removed by an ashing process using oxygen plasma or a wet process using a chemical solution.

Subsequently, as shown in FIG. 24B, a gate insulating film 22 is formed.
Specifically, for example, Al ₂ O ₃ is deposited on the compound semiconductor layer 2 as an insulating material. Al ₂ O ₃ alternately supplies TMA gas and O ₃ by, for example, atomic layer deposition (ALD method). In the present embodiment, Al ₂ O ₃ is deposited so that the thickness is about ₂ nm to 200 nm, for example, about 20 nm. Thereby, the gate insulating film 22 is formed.

Al ₂ O ₃ may be deposited by, for example, a plasma CVD method or a sputtering method instead of the ALD method. Further, instead of depositing Al ₂ O ₃ , Al nitride or oxynitride may be used. In addition, an oxide, nitride, oxynitride of Si, Hf, Zr, Ti, Ta, and W, or an appropriate selection thereof may be deposited in multiple layers to form a gate insulating film. .

Subsequently, as shown in FIG. 24C, a pair of protrusions 7 a and 7 b are formed on the gate insulating film 22.
Specifically, first, an insulator, for example, HSQ (silicon oxide) is applied to the entire surface of the gate insulating film 22 by using spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 7a and 7b made of silicon oxide are formed on the gate insulating film 22. The protrusions 7 a and 7 b are formed in the active region defined by the element isolation structure 3 on the gate insulating film 22. The protrusions 7a and 7b are formed at a predetermined interval, here, for example, at an interval of about the width of the overgate portion of the gate electrode so that the gate electrode can be formed in the region between them.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed to open a portion where the pair of protrusions are formed, and Al, for example, is deposited as a metal material on the resist mask so as to fill the opening, and the resist mask and Al thereon are removed by lift-off. Thus, a pair of protrusions made of Al are formed on the gate insulating film 22.

Subsequently, as shown in FIG. 25A, a resist mask 23 for forming a gate is formed.
The resist mask 23 is composed of three layers of electron beam resist. Specifically, a lower layer resist 23A, an intermediate layer resist 23B, and an upper layer resist 23C are sequentially applied on the gate insulating film 22 so as to cover the protrusions 7a and 7b by spin coating. As the lower layer resist 23A, for example, trade name PMMA manufactured by Microchem Inc. in the United States is used. As the intermediate layer resist 23B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 23C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 23A is applied to a thickness in which the protrusions 7a and 7b are embedded.

  The applied lower layer resist 23A, intermediate layer resist 23B, and upper layer resist 23C are pre-baked. Thereafter, the upper layer resist 23C is irradiated with an electron beam to perform exposure for opening having a length of, for example, 0.8 μm in the current direction of the gate electrode formation region, thereby developing the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 23Ca having a length of about 0.8 μm is formed in the upper resist 23C.

  Next, the intermediate layer resist 23B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 23B in a region set back by, for example, about 0.5 μm in the direction from the end of the opening 23Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 23B. An opening 23Ba is formed.

  Next, the lower resist 23A is irradiated with an electron beam through the opening 23Ca and the opening 23Ba to perform, for example, 0.1 μm-long opening exposure in the current direction of the gate electrode formation region. The lower layer resist 23A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. Thus, a strip-shaped opening 23Aa having a length of about 0.1 μm is formed in the lower layer resist 23A to expose a part of the surface of the gate insulating film 22.

In the lower layer resist 23A, protrusions 7a and 7b are embedded at portions spaced from the respective side surfaces of the opening 23Aa.
When the opening 23Aa is formed in the lower layer resist 23A, an internal stress (mainly tensile stress that expands the opening diameter) is generated in the electric lower layer resist 23A. In the present embodiment, since the source electrode and the drain electrode are not yet formed in the state in which the lower layer resist 23A is formed, the occurrence of the internal stress in the lower layer resist 23A becomes remarkable as compared with the case of the fifth embodiment.

  In the present embodiment, the protrusions 7a and 7b are embedded in the lower layer resist 23A as described above. Therefore, even if inclusion stress occurs (even if the generation of inclusion stress becomes significant because the source electrode and the drain electrode are not formed), the protrusions 7a and 7b cause the surface of the gate insulating film 22 of the lower layer resist 23A to be affected. Slip is suppressed. As a result, the opening 23Aa is held in the desired opening state at the time of formation without being deformed.

  As described above, the resist mask 23 including the lower layer resist 23A having the opening 34Aa, the intermediate layer resist 23B having the opening 23Ba, and the upper layer resist 23C having the opening 23Ca is formed. In the resist mask 23, an opening through which the opening 23Aa, the opening 23Ba, and the opening 23Ca communicate is referred to as 23a.

Subsequently, as shown in FIG. 25B, a gate electrode 24 is formed.
Specifically, using the resist mask 12, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 23a. The gate metal deposited on the resist mask 23 is not shown. As described above, the gate electrode 24 is formed in which the fine gate portion 24a for embedding the opening 23Aa of the lower layer resist 23A with the gate metal and the overgate portion 24b wider than the fine gate portion 24a are integrated. The fine gate portion 24a is spaced from the protrusions 7a and 7b. The over gate portion 24b has protrusions 7a and 7b located below both end portions thereof.

Subsequently, as shown in FIG. 25C, the resist mask 23 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 23 and unnecessary gate metal are removed by a lift-off method.

Subsequently, as shown in FIG. 26A, the electrode grooves 2A and 2B of the cap layer 2d are exposed.
Specifically, the gate insulating film 22 is processed by lithography and dry etching to form openings 22a and 22b in the gate insulating film 22 that expose the electrode grooves 2A and 2B of the cap layer 2d.
The resist used for lithography is removed by ashing using oxygen plasma or wet processing using a chemical solution.

Subsequently, as shown in FIG. 26B, the source electrode 4 and the drain electrode 5 are formed.
For example, Ti / Al (the lower layer is Ti and the upper layer is Al) is used as the electrode material. For the electrode formation, for example, a saddle structure two-layer resist suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor layer 2 to form a resist mask that opens the electrode grooves 2A and 2B. Using this resist mask, Ti / Al is deposited, for example, by vapor deposition. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. By the lift-off method, the resist mask having a ridge structure and Ti / Al deposited thereon are removed. Thereafter, the SiC substrate 1 is heat-treated at, for example, 400 ° C. to 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere, and the remaining Ti / Al is brought into ohmic contact with the cap layer 2d. In addition, when Ti / Al makes ohmic contact with the cap layer 2d without performing heat treatment, the heat treatment may not be performed. As a result, the source electrode 4 and the drain electrode 5 are formed in which the electrode grooves 2A and 2B are embedded under the Ti / Al.

  The protrusions 7 a and 7 b extend along the longitudinal direction of the gate electrode 24 on both sides of the gate electrode 24. The protrusion 7 a is formed between the gate electrode 24 and the source electrode 4 in the active region defined by the element isolation structure 3. The protrusion 7 b is formed between the gate electrode 24 and the drain electrode 5 in the active region defined by the element isolation structure 3.

Subsequently, as shown in FIG. 26C, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the gate insulating film 22 by a CVD method or the like so as to embed the gate electrode 24 and the protrusions 7a and 7b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 7a and 7b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, the gate insulating film of the interlayer insulating film 13 is formed by the protrusions 7a and 7b without applying an adhesive such as a silane coupling agent as a slip stopper between the gate insulating film 22 and the interlayer insulating film 13 as in the prior art. Slip with respect to 22 is suppressed. Thereby, the adhesion state between the interlayer insulating film 13 and the gate insulating film 22 is satisfactorily maintained.

Thereafter, MIS type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 24.
Note that the source electrode 4, the drain electrode 5, and the gate electrode 24 may be electrically connected without forming the interlayer insulating film 13.

  In the present embodiment, by forming the protrusions 7a and 7b as described above, the opening 23Aa of the lower layer resist 23A is held in the desired opening state at the time of formation without being deformed. Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When the gate electrode manufactured according to the present embodiment was examined, the difference from the design value was suppressed within ± 5%, and no abnormal shape of the gate electrode was observed.

  As described above, according to the present embodiment, a structure such as the gate electrode 24 is formed as designed with a relatively simple structure, and a highly reliable MIS type AlGaN that achieves high breakdown voltage and high output. /GaN.HEMT can be obtained.

(Seventh embodiment)
The seventh embodiment will be described below. In the present embodiment, an MIS type AlGaN / GaN HEMT is fabricated as in the fifth embodiment, but is different from the fifth embodiment in that the formation positions of the pair of protrusions are different. In addition, about the structural member etc. corresponding to AlGaN / GaN * HEMT by 5th Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
27 to 28 are schematic cross-sectional views showing a method of manufacturing a MIS type AlGaN / GaN.HEMT according to the seventh embodiment in the order of steps.

  First, similarly to the fifth embodiment, the steps shown in FIGS. 1A to 2B and 21B are sequentially performed. The situation at this time is shown in FIG. The compound semiconductor layer 2 is formed on the SiC substrate 1, the element isolation structure 3 is formed, and the electrode grooves 2A and 2B are formed in the cap layer 2d on the surface of the compound semiconductor layer 2 where the source and drain electrodes are to be formed. The Further, a source electrode 4 and a drain electrode 5 that fill the electrode grooves 2A and 2B are formed, and a gate insulating film 22 is formed on the entire surface of the compound semiconductor layer 2 so as to cover the source electrode 4 and the drain electrode 5.

Subsequently, as shown in FIG. 27B, a pair of protrusions 21 a and 21 b is formed on the gate insulating film 22.
Specifically, first, an insulator, for example, HSQ (silicon oxide) is applied to the entire surface of the gate insulating film 22 by using spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 21a and 21b made of silicon oxide are formed on the gate insulating film 22. The protrusions 21 a and 21 b are formed on the gate insulating film 22 outside the active region defined by the element isolation structure 3, that is, above the element isolation structure 3.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed to open a portion where the pair of protrusions are formed, and Al, for example, is deposited as a metal material on the resist mask so as to fill the opening, and the resist mask and Al thereon are removed by lift-off. Thus, a pair of protrusions made of Al are formed on the gate insulating film 22.

Subsequently, as shown in FIG. 27C, a resist mask 23 for forming a gate is formed.
The resist mask 23 is composed of three layers of electron beam resist. Specifically, a lower layer resist 23A, an intermediate layer resist 23B, and an upper layer resist 23C are sequentially applied on the gate insulating film 22 by a spin coating method so as to cover the protrusions 21a and 21b. As the lower layer resist 23A, for example, trade name PMMA manufactured by Microchem Inc. in the United States is used. As the intermediate layer resist 23B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 23C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 23A is applied to a thickness for embedding the protrusions 21a and 21b.

  The applied lower layer resist 23A, intermediate layer resist 23B, and upper layer resist 23C are pre-baked. Thereafter, the upper layer resist 23C is irradiated with an electron beam to perform exposure for opening having a length of, for example, 0.8 μm in the current direction of the gate electrode formation region, thereby developing the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 23Ca having a length of about 0.8 μm is formed in the upper resist 23C.

  Next, the intermediate layer resist 23B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 12B in the region set back by, for example, about 0.5 μm in the direction from the end of the opening 23Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 12B. An opening 23Ba is formed.

  Next, the lower resist 12A is irradiated with an electron beam through the opening 23Ca and the opening 23Ba to perform, for example, 0.1 μm-long opening exposure in the current direction of the gate electrode formation region. The lower layer resist 23A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 23Aa having a length of about 0.1 μm is formed in the lower layer resist 23A.

In the lower layer resist 23A, protrusions 21a and 21b are embedded in portions spaced from the side surfaces of the opening 23Aa.
When the opening 23Aa is formed in the lower layer resist 23A, an internal stress (mainly tensile stress that expands the opening diameter) is generated in the electric lower layer resist 23A. In the present embodiment, the protrusions 21a and 21b are embedded in the lower layer resist 23A as described above. Therefore, even if encapsulated stress occurs, the protrusions 21a and 21b prevent the lower resist 23A from slipping on the surface of the gate insulating film 22, and the opening 23Aa is held in the desired opening state at the time of formation without being deformed.

  As described above, the resist mask 23 including the lower layer resist 23A having the opening 23Aa, the intermediate layer resist 23B having the opening 23Ba, and the upper layer resist 23C having the opening 23Ca is formed. In the resist mask 23, an opening through which the opening 23Aa, the opening 23Ba, and the opening 23Ca communicate is referred to as 23a.

Subsequently, as shown in FIG. 28A, a gate electrode 24 is formed.
Specifically, using the resist mask 23, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 23a. The gate metal deposited on the resist mask 23 is not shown. As described above, the gate electrode 24 is formed in which the fine gate portion 24a for embedding the opening 23Aa of the lower layer resist 23A with the gate metal and the overgate portion 24b wider than the fine gate portion 24a are integrated. The gate electrode 24 is spaced from the protrusions 21a and 21b.

Subsequently, as shown in FIG. 28B, the resist mask 23 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 23 and unnecessary gate metal are removed by a lift-off method.

  The protrusions 21 a and 21 b extend along the longitudinal direction of the gate electrode 24 on both sides of the gate electrode 24. The protrusion 21 a is formed outside the source electrode 4 above the element isolation structure 3. The protrusion 21 b is formed outside the drain electrode 5 above the element isolation structure 3.

Subsequently, as shown in FIG. 28C, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the gate insulating film 22 by a CVD method or the like so as to embed the gate electrode 24 and the protrusions 21a and 21b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 21a and 21b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, without providing an adhesive such as a silane coupling agent as a slip stopper between the gate insulating film 22 and the interlayer insulating film 13, the protrusions 21a and 21b cause the interlayer insulating film 13 to slip with respect to the gate insulating film 22. Deterred. Thereby, the adhesion state between the interlayer insulating film 13 and the gate insulating film 22 is satisfactorily maintained.

Thereafter, MIS type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 24.
Note that the source electrode 4, the drain electrode 5, and the gate electrode 24 may be electrically connected without forming the interlayer insulating film 13.

  In the present embodiment, by forming the protrusions 21a and 21b as described above, the opening 23Aa of the lower layer resist 23A is held in the desired opening state at the time of formation without being deformed. Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When the gate electrode manufactured according to the present embodiment was examined, the difference from the design value was suppressed within ± 5%, and no abnormal shape of the gate electrode was observed.

  As described above, according to the present embodiment, a structure such as the gate electrode 24 is formed as designed with a relatively simple structure, and a highly reliable MIS type AlGaN that achieves high breakdown voltage and high output. /GaN.HEMT can be obtained.

(Eighth embodiment)
The eighth embodiment will be described below. In the present embodiment, an MIS type AlGaN / GaN HEMT is manufactured as in the sixth embodiment, but is different from the sixth embodiment in that the formation positions of the pair of protrusions are different. In addition, about the structural member etc. corresponding to AlGaN / GaN * HEMT by 6th Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
FIG. 29 to FIG. 31 are schematic cross-sectional views showing the method of manufacturing the MIS type AlGaN / GaN.HEMT according to the eighth embodiment in the order of steps.

  First, similarly to the sixth embodiment, the steps of FIGS. 1A to 2B and FIG. 24B are sequentially performed. The situation at this time is shown in FIG. The compound semiconductor layer 2 is formed on the SiC substrate 1, the element isolation structure 3 is formed, and the electrode grooves 2A and 2B are formed in the cap layer 2d on the surface of the compound semiconductor layer 2 where the source and drain electrodes are to be formed. The Further, a gate insulating film 22 is formed on the entire surface of the compound semiconductor layer 2.

Subsequently, as illustrated in FIG. 29B, a pair of protrusions 21 a and 21 b is formed on the gate insulating film 22.
Specifically, first, an insulator, for example, HSQ (silicon oxide) is applied to the entire surface of the gate insulating film 22 by using spin coating or the like. The silicon oxide is formed in a thickness (lower than the fine gate portion of the gate electrode), for example, about 200 nm, which is thinner than the lower layer resist of the three-layer electron beam resist for forming the gate electrode, which will be described later. The If the silicon oxide is too thin, it will not be possible to sufficiently exhibit the anti-slip effect of the lower layer resist described later, so that it is necessary to secure a thickness of about 1/3 or more of the thickness of the lower layer resist, for example.

  HSQ (silicon oxide) is processed by electron beam drawing and development / curing to leave silicon oxide in a pair of strips (stripe shapes). Thus, a pair of protrusions 21a and 21b made of silicon oxide are formed on the gate insulating film 22. The protrusions 21 a and 21 b are formed on the gate insulating film 22 outside the active region defined by the element isolation structure 3, that is, above the element isolation structure 3.

  The pair of protrusions may be formed of, for example, a metal material instead of the insulator. In this case, a resist mask is formed to open a portion where the pair of protrusions are formed, and Al, for example, is deposited as a metal material on the resist mask so as to fill the opening, and the resist mask and Al thereon are removed by lift-off. Thus, a pair of protrusions made of Al are formed on the gate insulating film 22.

Subsequently, as shown in FIG. 29C, a resist mask 23 for forming a gate is formed.
The resist mask 23 is composed of three layers of electron beam resist. Specifically, a lower layer resist 23A, an intermediate layer resist 23B, and an upper layer resist 23C are sequentially applied on the gate insulating film 22 by a spin coating method so as to cover the protrusions 21a and 21b. As the lower layer resist 23A, for example, trade name PMMA manufactured by Microchem Inc. in the United States is used. As the intermediate layer resist 23B, for example, trade name PMGI manufactured by US Microchem Corporation is used. As the upper layer resist 23C, for example, trade name ZEP-520 manufactured by Nippon Zeon Co., Ltd. is used. The lower layer resist 23A is applied to a thickness for embedding the protrusions 21a and 21b.

  The applied lower layer resist 23A, intermediate layer resist 23B, and upper layer resist 23C are pre-baked. Thereafter, the upper layer resist 23C is irradiated with an electron beam to perform exposure for opening having a length of, for example, 0.8 μm in the current direction of the gate electrode formation region, thereby developing the resist. As the developer, for example, trade name ZEP-SD manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 23Ca having a length of about 0.8 μm is formed in the upper resist 23C.

  Next, the intermediate layer resist 23B is wet-etched using, for example, a trade name NMD-W manufactured by Tokyo Ohka Co., Ltd. as a developer. By wet etching, the intermediate layer resist 23B in a region set back by, for example, about 0.5 μm in the direction from the end of the opening 23Ca toward the source electrode 4 and the direction toward the drain electrode 5 is removed, and a band-like pattern is formed on the intermediate layer resist 23B. An opening 23Ba is formed.

  Next, the lower resist 12A is irradiated with an electron beam through the opening 23Ca and the opening 23Ba to perform, for example, 0.1 μm-long opening exposure in the current direction of the gate electrode formation region. The lower layer resist 23A is developed. As the developer, for example, trade name ZMD-B manufactured by Nippon Zeon Co., Ltd. is used. As a result, a strip-shaped opening 23Aa having a length of about 0.1 μm is formed in the lower layer resist 23A.

In the lower layer resist 23A, protrusions 21a and 21b are embedded in portions spaced from the side surfaces of the opening 23Aa.
When the opening 23Aa is formed in the lower layer resist 23A, an internal stress (mainly tensile stress that expands the opening diameter) is generated in the electric lower layer resist 23A. In the present embodiment, since the source electrode and the drain electrode are not yet formed in the state in which the lower layer resist 23A is formed, the occurrence of the internal stress in the lower layer resist 23A becomes more significant than in the seventh embodiment.

  In the present embodiment, the protrusions 21a and 21b are embedded in the lower layer resist 23A as described above. Therefore, even if inclusion stress occurs (even if generation of inclusion stress becomes significant because the source electrode and the drain electrode are not formed), the protrusions 21a and 21b cause the surface of the gate insulating film 22 of the lower layer resist 23A to be affected. Slip is suppressed. As a result, the opening 23Aa is held in the desired opening state at the time of formation without being deformed.

  As described above, the resist mask 23 including the lower layer resist 23A having the opening 23Aa, the intermediate layer resist 23B having the opening 23Ba, and the upper layer resist 23C having the opening 23Ca is formed. In the resist mask 23, an opening through which the opening 23Aa, the opening 23Ba, and the opening 23Ca communicate is referred to as 23a.

Subsequently, as shown in FIG. 30A, a gate electrode 24 is formed.
Specifically, using the resist mask 23, Ni is deposited to a thickness of about 10 nm and Au is subsequently deposited to a thickness of about 300 nm as a gate metal over the entire surface including the inside of the opening 23a. The gate metal deposited on the resist mask 12 is not shown. As described above, the gate electrode 24 is formed in which the fine gate portion 24a for embedding the opening 23Aa of the lower layer resist 23A with the gate metal and the overgate portion 24b wider than the fine gate portion 24a are integrated. The gate electrode 24 is spaced from the protrusions 21a and 21b.

Subsequently, as shown in FIG. 30B, the resist mask 23 is removed.
Specifically, the SiC substrate 1 is infiltrated into N-methyl-pyrrolidinone heated to 80 ° C., and the resist mask 23 and unnecessary gate metal are removed by a lift-off method.

Subsequently, as shown in FIG. 30C, the electrode grooves 2A and 2B of the cap layer 2d are exposed.
Specifically, the protective insulating film 6 is processed by lithography and dry etching to form openings 22a and 22b in the gate insulating film 22 that expose the electrode grooves 2A and 2B of the cap layer 2d.
The resist used for lithography is removed by ashing using oxygen plasma or wet processing using a chemical solution.

Subsequently, as shown in FIG. 31A, the source electrode 4 and the drain electrode 5 are formed.
For example, Ti / Al (the lower layer is Ti and the upper layer is Al) is used as the electrode material. For the electrode formation, for example, a saddle structure two-layer resist suitable for the vapor deposition method and the lift-off method is used. This resist is applied onto the compound semiconductor layer 2 to form a resist mask that opens the electrode grooves 2A and 2B. Using this resist mask, Ti / Al is deposited, for example, by vapor deposition. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. By the lift-off method, the resist mask having a ridge structure and Ti / Al deposited thereon are removed. Thereafter, the SiC substrate 1 is heat-treated at, for example, 400 ° C. to 1000 ° C., for example, about 550 ° C. in a nitrogen atmosphere, and the remaining Ti / Al is brought into ohmic contact with the cap layer 2d. In addition, when Ti / Al makes ohmic contact with the cap layer 2d without performing heat treatment, the heat treatment may not be performed. As a result, the source electrode 4 and the drain electrode 5 are formed in which the electrode grooves 2A and 2B are embedded under the Ti / Al.

  The protrusions 21 a and 21 b extend along the longitudinal direction of the gate electrode 24 on both sides of the gate electrode 24. The protrusion 21 a is formed outside the source electrode 4 above the element isolation structure 3. The protrusion 21 b is formed outside the drain electrode 5 above the element isolation structure 3.

Subsequently, as shown in FIG. 31B, an interlayer insulating film 13 is formed.
Specifically, an insulator, for example, silicon oxide is deposited on the gate insulating film 22 by a CVD method or the like so as to embed the gate electrode 24 and the protrusions 21a and 21b. Thereby, the interlayer insulating film 13 is formed.

  In the present embodiment, the protrusions 21a and 21b are embedded in the interlayer insulating film 13 at portions separated from each other by a predetermined distance. Therefore, the gate insulating film of the interlayer insulating film 13 is formed by the protrusions 21a and 21b without applying an adhesive such as a silane coupling agent as a slip stopper between the gate insulating film 22 and the interlayer insulating film 13 as in the prior art. Slip with respect to 22 is suppressed. Thereby, the adhesion state between the interlayer insulating film 13 and the gate insulating film 22 is satisfactorily maintained.

Thereafter, MIS type AlGaN / GaN HEMT is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 24.
Note that the source electrode 4, the drain electrode 5, and the gate electrode 24 may be electrically connected without forming the interlayer insulating film 13.

  In the present embodiment, by forming the protrusions 21a and 21b as described above, the opening 23Aa of the lower layer resist 23A is held in the desired opening state at the time of formation without being deformed. Therefore, the gate electrode is formed almost according to the intended design value without forming the side gate portion. When the gate electrode manufactured according to the present embodiment was examined, the difference from the design value was suppressed within ± 5%, and no abnormal shape of the gate electrode was observed.

  As described above, according to the present embodiment, a structure such as the gate electrode 24 is formed as designed with a relatively simple structure, and a highly reliable MIS type AlGaN that achieves high breakdown voltage and high output. /GaN.HEMT can be obtained.

  In the first to eighth embodiments, the case where one protrusion is provided on each side of the gate electrode 8 or the gate electrode 24 as the protrusion is illustrated, but the present invention is not limited to this aspect. For example, it is possible to provide both the protrusions 7a and 7b and the protrusions 21a and 21b. It is also conceivable to provide a plurality of protrusions in parallel on both sides of the gate electrode 8 or the gate electrode 24. In these embodiments, the resist mask 11 and the lower resists 12A and 23A can be more reliably prevented from slipping, and the interlayer insulating film 13 can be more stably formed.

(Ninth embodiment)
In the present embodiment, a power supply device including one type of AlGaN / GaN.HEMT selected from the first to eighth embodiments is disclosed.
FIG. 32 is a connection diagram illustrating a schematic configuration of the power supply device according to the ninth embodiment.

The power supply device according to this embodiment includes a high-voltage primary circuit 31 and a low-voltage secondary circuit 32, and a transformer 33 disposed between the primary circuit 31 and the secondary circuit 32. The
The primary circuit 31 includes an AC power supply 34, a so-called bridge rectifier circuit 35, and a plurality (four in this case) of switching elements 36a, 36b, 36c, and 36d. The bridge rectifier circuit 35 includes a switching element 36e.
The secondary side circuit 32 includes a plurality (three in this case) of switching elements 37a, 37b, and 37c.

  In the present embodiment, the switching elements 36a, 36b, 36c, 36d, and 36e of the primary side circuit 31 are one type of AlGaN / GaN HEMT selected from the first to third embodiments. On the other hand, the switching elements 37a, 37b, and 37c of the secondary circuit 32 are normal MIS • FETs using silicon.

  According to the present embodiment, a structure such as a gate electrode is formed as designed with a relatively simple configuration, and a highly reliable AlGaN / GaN HEMT that realizes high breakdown voltage and high output is applied to a power supply device. . As a result, a highly reliable high-power power supply device is realized.

(Tenth embodiment)
In the present embodiment, a high-frequency amplifier including one kind of AlGaN / GaN.HEMT selected from the first to eighth embodiments is disclosed.
FIG. 33 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the tenth embodiment.

The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 41, mixers 42a and 42b, and a power amplifier 43.
The digital predistortion circuit 41 compensates for nonlinear distortion of the input signal. The mixer 42a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 43 amplifies the input signal mixed with the AC signal, and has one type of AlGaN / GaN HEMT selected from the first to third embodiments. In FIG. 33, for example, by switching the switch, the output-side signal is mixed with the AC signal by the mixer 42b and sent to the digital predistortion circuit 41.

  In this embodiment, a structure such as a gate electrode is formed as designed with a relatively simple configuration, and highly reliable AlGaN / GaN HEMT that realizes high breakdown voltage and high output is applied to a high-frequency amplifier. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first to tenth embodiments, AlGaN / GaN.HEMT is exemplified as the compound semiconductor device. As a compound semiconductor device, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

・ Other HEMT examples 1
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors that can have a lattice constant close to the composition. In this case, in the first to tenth embodiments described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of AlN, the electron supply layer is formed of n-InAlN, and the cap layer is formed of n-GaN. If necessary, n-GaN in the cap layer can be omitted. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by the spontaneous polarization of InAlN.

  According to this example, similarly to the AlGaN / GaN.HEMT described above, a highly reliable InAlN / GaN.HEMT that achieves high breakdown voltage and high output is realized by forming a structure such as a gate electrode as designed. .

・ Other HEMT examples 2
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter has a smaller lattice constant than the former. In this case, in the first to tenth embodiments described above, the electron transit layer is formed of i-GaN, the intermediate layer is formed of i-InAlGaN, the electron supply layer is formed of n-InAlGaN, and the cap layer is formed of n ⁺ -GaN. If necessary, n-GaN in the cap layer can be omitted.

  According to this example, similarly to the AlGaN / GaN.HEMT described above, a highly reliable InAlGaN / GaN.HEMT that achieves high breakdown voltage and high output is realized by forming a structure such as a gate electrode as designed. .

  Hereinafter, various aspects of the semiconductor device and its manufacturing method will be collectively described as additional notes.

(Appendix 1) a semiconductor layer;
A first electrode formed above the semiconductor layer;
A pair of second electrodes formed on both sides of the first electrode above the semiconductor layer;
A pair of protrusions formed on both sides of the first electrode above the semiconductor layer.

  (Additional remark 2) The said protrusion is formed in the strip | belt shape along the longitudinal direction of the said 1st electrode, The semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Additional remark 3) The semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned. The interlayer insulation film which covers the said protrusion is formed on the said semiconductor layer.

  (Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the protrusion is made of an insulating material or a metal material.

(Appendix 5) An active region is defined above the semiconductor layer,
The first electrode and the second electrode are formed in the active region,
5. The semiconductor device according to claim 1, wherein the protrusion is formed between the first electrode and the second electrode in the active region.

(Appendix 6) An active region is defined above the semiconductor layer,
The first electrode and the second electrode are formed in the active region,
The semiconductor device according to any one of appendices 1 to 4, wherein the protrusion is formed outside the active region.

  (Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein the first electrode is in direct contact with the surface of the semiconductor layer.

  (Supplementary note 8) The semiconductor device according to any one of supplementary notes 1 to 6, wherein the first electrode is formed on the semiconductor layer via an insulating film.

(Appendix 9) forming a semiconductor layer;
Forming a pair of protrusions above the semiconductor layer;
Forming a resist mask having an opening in a portion spaced from the protrusions between the protrusions so as to cover the entire surface of the protrusions above the semiconductor layer. Method.

  (Additional remark 10) The said protrusion is formed in the strip | belt shape along the longitudinal direction of the said 1st electrode, The manufacturing method of the semiconductor device of Additional remark 9 characterized by the above-mentioned.

(Appendix 11) After forming the resist mask, forming a first electrode on the resist mask so as to fill the opening of the resist mask;
The method for manufacturing a semiconductor device according to appendix 9 or 10, further comprising:

(Supplementary note 12) An active region is defined above the semiconductor layer,
The method of manufacturing a semiconductor device according to any one of appendices 9 to 11, wherein the protrusion is formed in the active region together with the first electrode.

(Supplementary note 13) An active region is defined above the semiconductor layer,
The first electrode is formed in the active region;
13. The method of manufacturing a semiconductor device according to any one of appendices 9 to 12, wherein the protrusion is formed outside the active region.

  (Supplementary note 14) The method for manufacturing a semiconductor device according to any one of supplementary notes 9 to 13, further comprising a step of forming a pair of second electrodes above the semiconductor layer.

  (Supplementary note 15) The semiconductor according to supplementary note 14, wherein the second electrode is formed on both sides of the first electrode after forming the first electrode and removing the resist mask. Device manufacturing method.

(Supplementary Note 16) A power supply circuit including a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A semiconductor layer;
A first electrode formed above the semiconductor layer;
A pair of second electrodes formed on both sides of the first electrode above the semiconductor layer;
A power supply circuit comprising: a pair of protrusions formed on both sides of the first electrode above the semiconductor layer.

(Supplementary Note 17) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A semiconductor layer;
A first electrode formed above the semiconductor layer;
A pair of second electrodes formed on both sides of the first electrode above the semiconductor layer;
A high frequency amplifier comprising: a pair of protrusions formed on both sides of the first electrode above the semiconductor layer.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 Compound semiconductor layer 2a Buffer layer 2b Electron travel layer 2c Electron supply layer 2d Cap layer 3 Element isolation structure 2A, 2B Electrode groove 4 Source electrode 5 Drain electrode 6 Protective insulating films 6a, 6b, 6c, 10a, 10b, 11a, 12Aa, 12Ba, 12Ca, 23Aa, 23Ba, 23Ca, 22a, 22b Openings 7a, 7b, 21a, 21b Protrusions 8, 24 Gate electrodes 8a, 24a Fine gates 8b, 24b Over gates 10, 11, 12, 23 Resist Mask 11, 12, 13 Resist mask 12A, 23A Lower layer resist 12B, 23B Middle layer resist 12C, 23C Upper layer resist 11b, 12Ab Side opening 13 Interlayer insulating film 22 Gate insulating film 31 Primary side circuit 32 Secondary side circuit 33 Transformer 34 AC Power supply 35 Bridge rectifier 36a, 36b, 36c, 36d, 36e, 37a, 37b, 37c switching element 41 digital predistortion circuit 42a, 42b mixer 43 Power amplifier

Claims (10)

A semiconductor layer;
A first electrode formed above the semiconductor layer;
A pair of second electrodes formed on both sides of the first electrode above the semiconductor layer;
A pair of protrusions formed on both sides of the first electrode above the semiconductor layer.   The semiconductor device according to claim 1, wherein the protrusion is formed in a band shape along a longitudinal direction of the first electrode.   The semiconductor device according to claim 1, wherein an interlayer insulating film that covers the protrusion is formed on the semiconductor layer. An active region is defined above the semiconductor layer;
The first electrode and the second electrode are formed in the active region,
The semiconductor device according to claim 1, wherein the protrusion is formed between the first electrode and the second electrode in the active region. An active region is defined above the semiconductor layer;
The first electrode and the second electrode are formed in the active region,
The semiconductor device according to claim 1, wherein the protrusion is formed outside the active region. Forming a semiconductor layer;
Forming a pair of protrusions above the semiconductor layer;
Forming a resist mask having an opening in a portion spaced from the protrusions between the protrusions so as to cover the entire surface of the protrusions above the semiconductor layer. Method.   The method of manufacturing a semiconductor device according to claim 6, wherein the protrusion is formed in a band shape along a longitudinal direction of the first electrode. Forming a first electrode on the resist mask so as to fill the opening of the resist mask after forming the resist mask;
The method of manufacturing a semiconductor device according to claim 6, further comprising:   The method for manufacturing a semiconductor device according to claim 6, further comprising a step of forming a pair of second electrodes above the semiconductor layer.   The semiconductor device according to claim 9, wherein the second electrode is formed on both sides of the first electrode after forming the first electrode and removing the resist mask. Method.

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