JP2012104760A - Compound semiconductor device, and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device with high reliability, which prevents the fluctuation and degradation of device characteristics due to electric field concentration around a gate electrode, even if adopting a fine gate structure for miniaturizing the gate electrode.SOLUTION: In a gate electrode 8, a trunk-shaped lower part 8a of a fine gate structure, and an upper part 8b expanding in an umbrella-shape (an overhang shape) from an upper end of the lower part 8a so as to be wider than an upper end are integrally formed. The lower part 8a has a first part 8aa including a lower end, and a second part 8ab on the first part 8aa. A protection wall 7 is formed so as to cover only both side surfaces of the first part 8aa.

Description

  The present invention relates to a compound semiconductor device and a method for manufacturing the same, and particularly to a high electron mobility transistor (HEMT).

  Among HEMTs, particularly those with high output and high frequency use, it is required to make the gate electrode finer in order to improve high frequency characteristics. Therefore, a HEMT having a so-called overhang-shaped cross-sectional T-shaped gate electrode has been devised. This HEMT has a so-called fine gate structure in which the lower part of the gate electrode has a narrow width, which contributes to the miniaturization of the gate electrode.

JP 2000-124228 A Japanese Patent Laid-Open No. 6-168962 Japanese Patent Laid-Open No. 11-233527 JP 2001-85448 A

  However, the miniaturization of the gate electrode increases the electric field strength around the gate electrode and causes a problem of deteriorating device characteristics. When electric field concentration occurs around the gate electrode, chemical and physical changes in the gate electrode and the compound semiconductor layer are promoted, and device characteristics fluctuate and deteriorate. Therefore, it is essential to establish a technique for preventing deterioration of device characteristics in order to increase the speed of HEMT operation using a fine gate structure.

  The present invention has been made in view of the above-mentioned problems, and adopts a fine gate structure to reduce the size of the gate electrode, but prevents fluctuation and deterioration of device characteristics due to electric field concentration around the gate electrode. An object of the present invention is to provide a highly reliable compound semiconductor device and a manufacturing method thereof.

  One aspect of the compound semiconductor device includes a compound semiconductor layer and a gate electrode formed above the compound semiconductor layer. The gate electrode is formed from a trunk-like lower portion and an upper end of the lower portion from the upper end. And an upper portion that widens in an umbrella shape, and the lower portion includes a first portion including a lower end and a second portion on the first portion, and the first portion The protective wall which covers only the side surface of this part is formed.

  One aspect of a method for manufacturing a compound semiconductor device includes a step of forming a protective wall above the compound semiconductor layer, and a step of forming a gate electrode so as to fill a gap between the protective walls, A trunk-like lower part and an upper part that spreads in an umbrella shape wider than the upper end from the upper end of the lower part are integrally formed, and the lower part includes a first part including a lower end, and the first part A second portion on the first portion, and the protective wall covers only the side surface of the first portion.

  According to each of the above embodiments, the fine gate structure is adopted to miniaturize the gate electrode, but the device characteristics change and deterioration due to electric field concentration around the gate electrode are prevented, and the compound semiconductor device has high reliability. Is realized.

It is a schematic sectional drawing which shows the manufacturing method of the Schottky type AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1 illustrating a Schottky-type AlGaN / GaN.HEMT manufacturing method according to the first embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view showing the Schottky type AlGaN / GaN.HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 2. It is a schematic sectional drawing which shows the Schottky type AlGaN / GaN * HEMT by a comparative example. 1 is a schematic cross-sectional view showing a Schottky type AlGaN / GaN HEMT according to a first embodiment. It is a characteristic view which shows the result of having performed the high temperature electricity supply experiment about AlGaN / GaN * HEMT by a comparative example and 1st Embodiment. 6 is a schematic cross-sectional view showing the main steps of a method for manufacturing a Schottky AlGaN / GaN.HEMT according to Modification 1 of the first embodiment. FIG. FIG. 6 is a schematic cross-sectional view showing a Schottky AlGaN / GaN.HEMT according to Modification 1 of the first embodiment. FIG. 10 is a schematic cross-sectional view showing the main steps of a method for manufacturing a Schottky AlGaN / GaN HEMT according to Modification 2 of the first embodiment. FIG. 6 is a schematic cross-sectional view showing a Schottky AlGaN / GaN.HEMT according to a second modification of the first embodiment. FIG. 11 is a schematic cross-sectional view showing the main steps of a method for manufacturing a Schottky AlGaN / GaN HEMT according to Modification 3 of the first embodiment. FIG. 10 is a schematic cross-sectional view showing a Schottky AlGaN / GaN.HEMT according to Modification 3 of the first embodiment. FIG. 10 is a schematic cross-sectional view showing the main steps of a method for manufacturing a Schottky AlGaN / GaN.HEMT according to Modification 4 of the first embodiment. FIG. 10 is a schematic cross-sectional view showing a Schottky AlGaN / GaN.HEMT according to Modification 4 of the first embodiment. FIG. 6 is a schematic cross-sectional view showing a Schottky AlGaN / GaN HEMT in which the third modification of the first embodiment is combined with the first modification. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the MIS type AlGaN / GaN * HEMT by 2nd Embodiment. FIG. 6 is a schematic cross-sectional view showing a MIS type AlGaN / GaN HEMT according to a second embodiment. FIG. 6 is a schematic cross-sectional view showing an MIS type AlGaN / GaN HEMT according to various modifications of the second embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 3rd Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In the following embodiments, a so-called AlGaN / GaN HEMT using GaN as an electron transit layer and AlGaN as an electron supply layer is disclosed as a compound semiconductor device, and the configuration thereof will be described together with a manufacturing method. In the following drawings, there are constituent members that are not shown in a relatively accurate size and thickness for convenience of illustration.

(First embodiment)
In the present embodiment, a Schottky type AlGaN / GaN HEMT is disclosed.
1 to 3 are schematic cross-sectional views showing a method of manufacturing a Schottky AlGaN / GaN HEMT according to the first embodiment in the order of steps.

  First, as shown in FIG. 1A, a compound semiconductor layer 2 is formed on, for example, a semi-insulating SiC substrate 1 as a growth substrate. The compound semiconductor layer 2 includes a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c, and a surface layer 2d. In the AlGaN / GaN.HEMT, a two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 2b and the electron supply layer 2c.

  More specifically, the following compound semiconductors are grown on the SiC substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.

  On the SiC substrate 1, AlN, GaN, AlGaN, and GaN are sequentially deposited to form a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c, and a surface layer 2d. As growth conditions for AlN, GaN, AlGaN, and GaN, a mixed gas of trimethylaluminum gas, trimethylgallium gas, and ammonia gas is used as a source gas. The presence / absence and flow rate of trimethylaluminum gas as an Al source and trimethylgallium gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing GaN and AlGaN as n-type, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, and Si is doped into GaN and AlGaN. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .
Here, the buffer layer 2a has a film thickness of about 0.1 μm, the electron transit layer 2b has a film thickness of about 2 μm, the electron supply layer 2b has a film thickness of about 30 nm, for example, an Al ratio of about 0.2 to 0.3, and the surface layer 5 has The film is formed to a thickness of about 10 nm.

Subsequently, as shown in FIG. 1B, an element isolation structure 3 is formed.
Specifically, for example, argon (Ar) is implanted into the element isolation region of the compound semiconductor layer 2. Thereby, the element isolation structure 3 is formed in the surface layers of the compound semiconductor layer 2 and the SiC substrate 1. An active region is defined on the compound semiconductor layer 2 by the element isolation structure 3.

Subsequently, a resist mask is formed, and the surface layer 2d at the position where the source and drain electrodes are to be formed on the surface of the surface layer 2d is removed.
The surface layer 2d is dry-etched using a resist mask to remove the surface layer 2d. Regarding the amount of removal, the surface layer 2d may be completely removed or even a part of the electron supply layer 2c may be removed. For dry etching, an inert gas such as Ar and a chlorine-based gas such as Cl ₂ are used as an etching gas. The etching depth of the surface layer 2d does not necessarily match the film thickness of the surface layer 2d.

Subsequently, as shown in FIG. 1C, the source electrode 4 and the drain electrode 5 are formed.
Specifically, for example, Ti / Al is used as the electrode material. For electrode formation, a two-layer resist opening having a saddle structure suitable for vapor deposition / lift-off method is used. Ti / Al is deposited using this resist opening as a mask. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. By the lift-off method, the resist mask having a ridge structure and Ti / Al deposited thereon are removed. Thereafter, the SiC substrate 1 is heat-treated at, for example, about 550 ° C. in a nitrogen atmosphere, and the remaining Ti / Al is brought into ohmic contact with the electron supply layer 2c (or on the surface layer 2d). Thus, the source electrode 4 and the drain electrode 5 are formed on the electron supply layer 2c (or on the surface layer 2d).

Subsequently, as shown in FIG. 2A, an insulating film 6 is formed.
Specifically, for example, a SiN film is deposited to a thickness of about 50 nm so as to cover the entire surface of the SiC substrate 1 including the source electrode 4 and the drain electrode 5 by PECVD, for example. Thereby, the insulating film 6 is formed.

Subsequently, as shown in FIG. 2B, an opening 6 a is formed in the insulating film 6.
Specifically, a resist is applied on the insulating film 6. As the resist, an electron beam resist such as a polymethyl methacrylate (PMMA) resist manufactured by Microchem Corporation of the United States is used. For example, 80 nm-long opening drawing is performed on the resist by the electron beam drawing method, and development is performed using, for example, a MIBK / IPA mixed solution. Thereby, an opening is formed in the resist. Using this resist as a mask, the insulating film 6 is dry etched. For this dry etching, SF ₆ is used as an etching gas. Thereby, an opening 6a having a width of, for example, 100 nm is formed in the insulating film 6 to expose a part of the surface of the surface layer 2d.

Subsequently, a protective wall 7 is formed as shown in FIG.
More specifically, an electron beam photosensitive SOD (Spin On Dielectric) film, which is an HSQ (Hydrogen Silsequioxane) compound, for example, is formed on the insulating film 6 to a thickness of, for example, 100 nm by a spin coating method. With respect to the SOD film, an electron beam is dosed to each rectangular region having a width of 100 nm, for example, with each of the positions retracted about 10 nm from the opening end of the opening 6a toward the source electrode 4 side and the drain electrode 5 side, respectively. Develop and cure the SOD film. Thus, the protective wall 7 made of the SOD film is formed. The protective wall 7 is an insulating structure having a width of 100 nm, with one end at a position recessed, for example, by about 10 nm from the opening end of the opening 6a toward the source electrode 4 side and the drain electrode 5 side. Between the protective walls 7, a gap 7 a having a width of 120 nm communicating with the opening 6 a of the insulating film 6 is formed.

  Although the case where the protective wall 7 is formed with a width of 100 nm has been illustrated, the width of the protective wall 7 is preferably equal to or smaller than the width of the umbrella-shaped upper portion of the gate electrode described later. If the width of the protective wall 7 is larger than the width of the umbrella-shaped upper portion of the gate electrode, there is a problem that parasitic capacitance increases. Therefore, by making the width of the protective wall 7 equal to or less than the width of the umbrella-shaped upper portion of the gate electrode, it is possible to sufficiently suppress the deterioration of the device characteristics without increasing the parasitic capacitance.

Subsequently, as shown in FIG. 3A, a three-layer resist mask 12 for forming a gate electrode is formed.
A lower layer resist 21, an intermediate resist 22, and an upper layer resist 23 are sequentially applied on the entire surface of the SiC substrate 1. As the lower layer resist 21, for example, a PMMA resist (manufactured by Microchem Inc., USA) is used. As the intermediate resist 22, for example, a polymethylglutarimide (PMGI) resist (manufactured by Microchem Inc., USA) is used. As the upper resist 23, for example, trade name ZEP520-A (manufactured by Nippon Zeon Co., Ltd.) is used.

  Openings 23 a are formed in the upper layer resist 23. Specifically, for example, 0.8 μm length is drawn on the upper resist 23 by the electron beam drawing method, and the upper resist 23 is developed with the MEK / MIBK mixed solution. As a result, an opening 23 a is formed in the upper layer resist 23.

  Next, an opening 22 a is formed in the intermediate resist 22. Specifically, using the upper layer resist 23 in which the opening 23a is formed as a mask, the intermediate resist 22 is wet-etched using TMAH to a position retracted about 0.2 μm on one side from the opening end of the opening 23a. As a result, an opening 22 a wider than the opening 23 a is formed in the intermediate resist 22. Due to the presence of the opening 22a of the intermediate resist 22, the opening 23a of the upper resist 23 has a bowl shape in which the opening end protrudes inward from the opening end of the opening 22a.

Next, an opening 21 a is formed in the lower resist 21. Specifically, the lower layer resist 21 is drawn by an electron beam drawing method. This drawing is performed so as to have substantially the same width as the gap 7 a formed between the protective walls 7, here, 120 nm long. The lower resist 21 is developed with the MEK / MIBK mixed solution. As a result, an opening 21 a having substantially the same width as the gap 7 a is formed in the lower resist 21. The side surface of the protective wall 7 is exposed on the inner wall surface of the opening 21a.
As described above, the lower layer resist 21, the intermediate resist 22, and the upper layer resist 23 are laminated, and the three-layer resist mask 12 having the openings 21a, 22a, and 23a communicating with each other is formed.

Subsequently, as shown in FIG. 3B, a gate electrode 8 is formed.
Specifically, for example, Ni / Au is used as the electrode material, and the electrode material is embedded so that the opening 6a and the opening 21a of the insulating film 6 are filled with the electrode material by vapor deposition or the like, and the electrode material exists in the opening 22a. accumulate. The electrode material is also deposited on the upper resist 23. As the electrode material, Pt / Au may be deposited instead of Ni / Au.

  The lift-off method using a heated organic solvent removes the three-layer resist mask 12 and unnecessary electrode material, here the electrode material deposited on the upper-layer resist 23. As described above, the overhanging gate electrode 8 is formed on the surface layer 2d so as to fill the gap 7a as well as the opening 6a with the electrode material and protrude above the protective wall 7.

  Thereafter, various processes such as formation of wirings that are electrically connected to the source electrode 4, the drain electrode 5, and the gate electrode 8 are performed. When used in a high frequency device, an interlayer insulating film covering the gate electrode 8 is not formed. As described above, the Schottky AlGaN / GaN HEMT according to the present embodiment is formed.

The superiority of the AlGaN / GaN HEMT according to the present embodiment will be described below based on a comparison with a comparative example.
FIG. 4 is a schematic sectional view showing a Schottky type AlGaN / GaN.HEMT according to a comparative example. FIG. 5 is a schematic cross-sectional view showing the Schottky type AlGaN / GaN.HEMT according to the present embodiment. In FIG. 4, the same code | symbol is attached | subjected about the structural member corresponding to this embodiment. 4 and 5, for convenience of illustration, only the portion on the compound semiconductor layer 2 is shown, and the illustration of the SiC substrate and the element isolation structure 3 is omitted.

  As shown in FIG. 4, the Schottky AlGaN / GaN HEMT according to the comparative example has a gate electrode 101 having a conventional fine gate structure, and no protective wall 7 is provided. In this case, the junction part of the gate electrode 101 which is the lower end of the gate electrode 101 and the insulating film 6 is in contact with the atmosphere, and when electric field concentration occurs at the junction part, it easily reacts with atmospheric constituent elements and moisture. There is a problem that device characteristics deteriorate.

  On the other hand, in the AlGaN / GaN HEMT according to the present embodiment, the protective wall 7 is disposed on the side surface of the gate electrode 8 as shown in FIG. The gate electrode 8 is integrally formed with a trunk-like lower portion 8a having a fine gate structure and an upper portion 8b extending in an umbrella shape (overhang shape) wider than the upper end of the lower portion 8a. The lower portion 8a has a first portion 8aa including a lower end and a second portion 8ab on the first portion 8aa. The protective wall 7 is formed so as to cover only both side surfaces of the first portion 8aa.

  The protective wall 7 covers a joint portion between the gate electrode 8 which is the lower end of the gate electrode 8 and the insulating film 6, and the joint portion is not exposed to the outside. As a result, the junction portion does not come into contact with atmospheric constituent elements and moisture, and deterioration of device characteristics due to electric field concentration is prevented as much as possible.

  The protective wall 7 is provided so as to cover only the side surface of the first portion 8aa of the lower portion 8a. From the viewpoint of maintaining good high-frequency characteristics, it is necessary to suppress the parasitic capacitance by minimizing the amount of the dielectric material existing around the gate electrode 8. In the present embodiment, the protective wall 7 is disposed only on the key portion, that is, the side surface of the first portion 8aa, in order to prevent deterioration of device characteristics and maintain reliability. The protective wall 7 is not disposed in the second portion 8ab and the upper portion 8b, and a gap (an interlayer insulating film is formed between the protective wall 7 where the second portion 8ab exists and the upper portion 8b. In that case, the insulator) is formed. The air in the air gap or the insulator of the interlayer insulating film has a dielectric constant lower than that of a normal dielectric material. Therefore, the parasitic capacitance is minimized and good high frequency characteristics can be obtained.

  A high-temperature energization experiment was performed on the above-described comparative example and the AlGaN / GaN HEMT according to the present embodiment. In this experiment, AlGaN / GaN HEMT was pinch-off energized at 160 ° C., and the relationship between the gate leak current (Ig) and the ratio (%) of the pinch-off current (Id) to the energization time (min) was examined. The experimental results are shown in FIG.

  In the AlGaN / GaN HEMT according to the comparative example, as shown in FIG. 6B, the gate leakage current started to increase in about 40 minutes after the start of energization, and thereafter the gate leakage current as a whole increased and decreased repeatedly. Maintained. From this result, it is clearly shown that the gate leakage current is high in the comparative example, but the device characteristics are deteriorated.

  On the other hand, in the AlGaN / GaN HEMT according to the present embodiment, as shown in FIG. 6A, the gate leakage current decreases substantially monotonously with the energization time, and the increase tendency of the gate leakage current is not observed. I couldn't. From this result, it is clearly shown that the gate leakage current is low in this embodiment, and it can be seen that high reliability can be obtained without deterioration of device characteristics.

  As described above, according to the present embodiment, the fine gate structure is adopted to reduce the size of the gate electrode 8, but the fluctuation and deterioration of device characteristics due to electric field concentration around the gate electrode 8 can be prevented, A highly reliable Schottky type AlGaN / GaN HEMT is realized.

[Modification]
Hereinafter, various modifications of the present embodiment will be described. In these modified examples, a Schottky type AlGaN / GaN HEMT is disclosed as in the first embodiment. In each modified example, the same components as those of the AlGaN / GaN HEMT according to the first embodiment are denoted by the same reference numerals.

(Modification 1)
This example is different from the first embodiment in that the shape of the gate electrode is different.
FIG. 7 is a schematic cross-sectional view showing the main steps of a method for manufacturing a Schottky AlGaN / GaN.HEMT according to Modification 1 of the first embodiment.

  First, similarly to the first embodiment, each step of FIG. 1A to FIG. 2B is executed.

Subsequently, as shown in FIG. 7A, a protective wall 31 is formed. In this example, the protective wall 31 is formed so that the distance from the opening end of the opening 6a of the insulating film 6 is larger on the drain electrode 5 side than on the source electrode 4 side.
Specifically, an electron beam photosensitive SOD film, which is an HSQ compound, for example, is formed as an insulating film on the insulating film 6 by a spin coating method to a thickness of, for example, 100 nm. An electron beam is dosed to the SOD film. This dose is one end at a position retracted by about 10 nm from one opening end of the opening 6a on the source electrode 4 side, and one end by a position retracted by about 100 nm from the other opening end of the opening 6a on the drain electrode 5 side. For example, it is performed on each rectangular region having a width of 100 nm. Thereafter, the SOD film is developed and cured.

  Thus, the protective wall 31 that is an insulating structure made of the SOD film is formed. On the source electrode 4 side, the protective wall 31 is formed to have a width of 100 nm with a position retreated about 10 nm from the opening end of the opening 6a as one end. On the drain electrode 5 side, the opening 6a is formed to have a width of 100 nm with a position retreated about 100 nm from the opening end as one end. A gap 31a having a width of 210 nm including the opening 6a of the insulating film 6 is formed between the protective walls 31.

  Subsequently, similarly to FIG. 3A of the first embodiment, a three-layer resist mask 12 for forming a gate electrode is formed.

Subsequently, as shown in FIG. 7B, a gate electrode 32 is formed.
Specifically, Ni / Au, for example, is used as the electrode material, and the electrode material is deposited so that the opening 6a and the opening 21a of the insulating film are filled with the electrode material by vapor deposition or the like, and the electrode material exists in the opening 22a. To do. The electrode material is also deposited on the upper resist 23. As the electrode material, Pt / Au may be deposited instead of Ni / Au.

  The lift-off method using a heated organic solvent removes the three-layer resist mask 12 and unnecessary electrode material, here the electrode material deposited on the upper-layer resist 23. As described above, the overhanging gate electrode 32 is formed on the surface layer 2d so as to fill the gap 31a as well as the opening 6a with the electrode material and protrude above the protective wall 31.

  Thereafter, various processes such as formation of wirings that are electrically connected to the source electrode 4, the drain electrode 5, and the gate electrode 32 are performed. When used in a high frequency device, an interlayer insulating film covering the gate electrode 32 is not formed. As described above, the Schottky AlGaN / GaN HEMT according to this example is formed.

  FIG. 8 shows a Schottky AlGaN / GaN HEMT according to this example. In FIG. 8, for convenience of illustration, only the portion on the compound semiconductor layer 2 is shown, and the illustration of the SiC substrate and the element isolation structure 3 is omitted.

  In this AlGaN / GaN HEMT, a protective wall 31 is disposed on the side surface of the gate electrode 32. The gate electrode 32 is integrally formed with a trunk-like lower portion 32a having a fine gate structure and an upper portion 32b extending from the upper end of the lower portion 32a to an umbrella shape (overhang shape) wider than the upper end. The lower portion 32a has a first portion 32aa including a lower end, and a second portion 32ab on the first portion 32aa. The first portion 32aa is formed so as to run over the opening 6a on the buried insulating film 6, and the running width W1 on the drain electrode 5 side is larger than the running width W2 on the source electrode 4 side. In this example, the riding width W1 is about 100 nm and the riding width W2 is about 10 nm. The protective wall 31 is formed so as to cover only both side surfaces of the first portion 32aa.

  The protective wall 31 in this example covers a joint portion between the gate electrode 32 which is the lower end of the gate electrode 32 and the insulating film 6, and the joint portion is not exposed to the outside. The protection wall 31 is formed such that the run width W1 on the drain electrode 5 side is larger than the run width W2 on the source electrode 4 side. Electric field concentration in the vicinity of the HEMT gate electrode occurs particularly at the drain electrode. In this example, the running width W1 of the gate electrode 32 on the drain electrode 5 side is large, and therefore the distance from the junction between the gate electrode 32 and the insulating film 6 to the exposed surface of the protective wall 31 is also large. Thereby, the contact with the atmospheric constituent elements and moisture at the bonding portion is more reliably suppressed, and deterioration of device characteristics due to electric field concentration is prevented as much as possible.

  The protective wall 31 is provided so as to cover only the side surface of the first portion 32aa of the lower portion 32a. From the viewpoint of maintaining good high frequency characteristics, it is necessary to suppress the parasitic capacitance by minimizing the amount of the dielectric material existing around the gate electrode 32. In the present embodiment, the protective wall 31 is disposed only on the key portion, that is, the side surface of the first portion 32aa, in order to prevent deterioration of device characteristics and maintain reliability. The protective wall 31 is not disposed in the second portion 32ab and the upper portion 32b, and a gap (interlayer insulating film is formed between the protective wall 31 and the upper portion 32b, which are portions where the second portion 32ab exists. In that case, the insulator) is formed. The air in the air gap or the insulator of the interlayer insulating film has a dielectric constant lower than that of a normal dielectric material. Therefore, the parasitic capacitance is minimized and good high frequency characteristics can be obtained.

  As described above, according to the present example, the fine gate structure is employed to reduce the size of the gate electrode 32, but the device characteristics are prevented from changing and deteriorating due to the electric field concentration around the gate electrode 32, and thus reliable. A highly Schottky AlGaN / GaN HEMT is realized.

(Modification 2)
This example is different from the first embodiment in that the shape of the protective wall is different.
FIG. 9 is a schematic cross-sectional view showing the main steps of a method for manufacturing a Schottky AlGaN / GaN.HEMT according to the second modification of the first embodiment.

  First, similarly to the first embodiment, each step of FIG. 1A to FIG. 2B is executed.

Subsequently, as shown in FIG. 9A, a protective wall 33 is formed. In this example, the protective wall 33 is formed so that the drain electrode 5 side is wider than the source electrode 4 side.
Specifically, an electron beam photosensitive SOD film, which is an HSQ compound, for example, is formed as an insulating film on the insulating film 6 by a spin coating method to a thickness of, for example, 100 nm. With respect to the SOD film, an electron beam is dosed to each rectangular region, with each of the positions retracted, for example, by about 10 nm from the opening end of the opening 6a toward the source electrode 4 side and the drain electrode 5 side. The rectangular region on the source electrode 4 side is, for example, 100 nm wide, and the rectangular region on the drain electrode 5 side is, for example, 200 nm wider than the source electrode 4 side. Develop and cure the SOD film. Thus, the protective wall 33 that is an insulating structure made of the SOD film is formed. The protective wall 33 has one end at a position retreated, for example, by about 10 nm from the opening end of the opening 6a to the source electrode 4 side and the drain electrode 5 side, and is formed to have a width of 100 nm on the source electrode 4 side and a width of 200 nm on the drain electrode 5 side. The Between the protective walls 33, a gap 33a having a width of 120 nm including the opening 6a of the insulating film 6 is formed.

  Subsequently, similarly to FIG. 3A of the first embodiment, a three-layer resist mask 12 for forming a gate electrode is formed.

Subsequently, as shown in FIG. 9B, a gate electrode 34 is formed.
Specifically, Ni / Au, for example, is used as the electrode material, and the electrode material is deposited so that the opening 6a and the opening 21a of the insulating film are filled with the electrode material by vapor deposition or the like, and the electrode material exists in the opening 22a. To do. The electrode material is also deposited on the upper resist 23. As the electrode material, Pt / Au may be deposited instead of Ni / Au.

  The lift-off method using a heated organic solvent removes the three-layer resist mask 12 and unnecessary electrode material, here the electrode material deposited on the upper-layer resist 23. As described above, the overhanging gate electrode 34 is formed on the surface layer 2d so that the gap 33a as well as the opening 6a is filled with the electrode material and protrudes above the protective wall 33.

  Thereafter, various processes such as formation of wirings that are electrically connected to the source electrode 4, the drain electrode 5, and the gate electrode 34 are performed. When used in a high frequency device, an interlayer insulating film covering the gate electrode 34 is not formed. As described above, the Schottky AlGaN / GaN HEMT according to this example is formed.

  FIG. 10 shows a Schottky AlGaN / GaN HEMT according to this example. In FIG. 10, for convenience of illustration, only the portion on the compound semiconductor layer 2 is shown, and the illustration of the SiC substrate and the element isolation structure 3 is omitted.

  In this AlGaN / GaN HEMT, a protective wall 31 is disposed on the side surface of the gate electrode 34. The gate electrode 34 is integrally formed with a trunk-like lower part 34a having a fine gate structure and an upper part 34b extending from the upper end of the lower part 34a to an umbrella shape (overhang shape) wider than the upper end. The lower portion 34a has a first portion 34aa including a lower end, and a second portion 34ab on the first portion 34aa. The first portion 34aa is formed so as to run over the opening 6a on the insulating film 6. The protective wall 33 is formed so as to cover only both side surfaces of the first portion 34aa.

  The protective wall 33 covers a joint portion between the gate electrode 34, which is the lower end of the gate electrode 34, and the insulating film 6, and the joint portion is not exposed to the outside. The protective wall 33 in this example is formed wider on the drain electrode 5 side than on the source electrode 4 side. Here, the former has a width of about 200 nm, and the latter has a width of about 100 nm. Electric field concentration in the vicinity of the HEMT gate electrode occurs particularly at the drain electrode. In this example, the width of the protective wall 33 on the drain electrode 5 side is large, and thus the distance from the junction between the gate electrode 34 and the insulating film 6 to the exposed surface of the protective wall 33 is also large. Thereby, the contact with the atmospheric constituent elements and moisture at the bonding portion is more reliably suppressed, and deterioration of device characteristics due to electric field concentration is prevented as much as possible.

  The protective wall 33 is provided so as to cover only the side surface of the first portion 34aa of the lower portion 34a. From the viewpoint of maintaining good high-frequency characteristics, it is necessary to suppress the parasitic capacitance by minimizing the amount of dielectric material existing around the gate electrode 34. In the present embodiment, the protective wall 33 is disposed only on the key portion, that is, the side surface of the first portion 34aa, in order to prevent deterioration of device characteristics and maintain reliability. The protective wall 33 is not disposed in the second portion 34ab and the upper portion 34b, and a gap (an interlayer insulating film is formed between the protective wall 33 and the upper portion 34b where the second portion 34ab exists. In that case, the insulator) is formed. The air in the air gap or the insulator of the interlayer insulating film has a dielectric constant lower than that of a normal dielectric material. Therefore, the parasitic capacitance is minimized and good high frequency characteristics can be obtained.

  As described above, according to this example, the fine gate structure is employed to reduce the size of the gate electrode 34, but the device characteristics can be prevented from changing and deteriorating due to electric field concentration around the gate electrode 34, and thus reliable. A highly Schottky AlGaN / GaN HEMT is realized.

(Modification 3)
This example is different from the first embodiment in that the shape of the gate electrode is different.
FIG. 11 is a schematic cross-sectional view showing the main steps of a Schottky AlGaN / GaN.HEMT manufacturing method according to Modification 3 of the first embodiment.

  First, similarly to the first embodiment, each step of FIGS. 1A to 2C is executed. A protective wall 7 is formed on the insulating film 6.

Subsequently, as shown in FIG. 11A, a three-layer resist mask 35 for forming a gate electrode is formed.
Similar to the first embodiment, a lower layer resist 21, an intermediate resist 22, and an upper layer resist 23 are sequentially applied to the entire surface of the compound semiconductor substrate 2. An opening 23 a is formed in the upper resist 23 and an opening 22 a is formed in the intermediate resist 22 sequentially. Due to the presence of the opening 22a of the intermediate resist 22, the opening 23a of the upper resist 23 has a bowl shape in which the opening end protrudes inward from the opening end of the opening 22a.

Next, an opening 21 b is formed in the lower layer resist 21. Specifically, the lower layer resist 21 is drawn by an electron beam drawing method. This drawing is performed so as to be wider than the gap 7a (120 nm width) formed between the protective walls 7 and 220 nm in this case. The lower resist 21 is developed with the MEK / MIBK mixed solution. As a result, an opening 21b wider than the gap 7a is formed in the lower resist 21. The inner wall surface of the opening 21b is located at a location retreated by about 50 nm from the opposing side surfaces of the protective wall 7 on the source electrode 4 side and the drain electrode 5 side. Therefore, on the inner wall surface of the opening 21a, the side surface of the protective wall 7 protrudes inward by about 50 nm and is exposed.
As described above, the lower layer resist 21, the intermediate resist 22, and the upper layer resist 23 are laminated to form a three-layer resist mask 35 having openings 21b, 22a, and 23a that communicate with each other.

Subsequently, as shown in FIG. 11B, a gate electrode 36 is formed.
Specifically, for example, Ni / Au is used as the electrode material, and the electrode material is deposited so that the electrode material is embedded in the opening 22b by filling the opening 6a and the opening 21b of the insulating film by an evaporation method or the like. To do. The electrode material is also deposited on the upper resist 23. As the electrode material, Pt / Au may be deposited instead of Ni / Au.

  By the lift-off method using a heated organic solvent, the three-layer resist mask 35 and unnecessary electrode material, here, the electrode material deposited on the upper-layer resist 23 are removed. As described above, the overhanging gate electrode 36 is formed on the surface layer 2d so that the gap 7a as well as the opening 6a is filled with the electrode material and protrudes above the protective wall 7.

  Thereafter, various processes such as formation of wirings that are electrically connected to the source electrode 4, the drain electrode 5, and the gate electrode 36 are performed. When used in a high frequency device, an interlayer insulating film covering the gate electrode 36 is not formed. As described above, the Schottky AlGaN / GaN HEMT according to this example is formed.

  FIG. 12 shows a Schottky type AlGaN / GaN.HEMT according to this example. In FIG. 12, for convenience of illustration, only the portion on the compound semiconductor layer 2 is shown, and the illustration of the SiC substrate and the element isolation structure 3 is omitted.

  In this AlGaN / GaN HEMT, the protective wall 7 is disposed on the side surface of the gate electrode 36. The gate electrode 36 is integrally formed with a trunk-like lower part 36a having a fine gate structure and an upper part 36b extending from the upper end of the lower part 36a to an umbrella shape (overhang shape) wider than the upper end. The lower portion 36a has a first portion 36aa including a lower end, and a second portion 36ab on the first portion 36aa. At the boundary between the first portion 36aa and the second portion 36ab, the second portion 36ab is wider than the first portion 36aa, and here, a step having a width of about 50 nm is formed on each of the left and right sides. That is, the second portion 36ab is formed on the protective wall 7 so as to run on the riding width of about 50 nm. The protective wall 7 is formed so as to cover only both side surfaces of the first portion 36aa.

  The protective wall 31 covers a joint portion between the gate electrode 36, which is the lower end of the gate electrode 36, and the insulating film 6, and the joint portion is not exposed to the outside. In this example, a step is formed at the boundary between the first portion 36aa and the second portion 36ab, so to speak, the shape inflection point is increased. As a result, chemical and physical changes in the multilayer metal structure of the gate electrode 36 and the semiconductor crystal due to the penetration of atmospheric constituent elements and moisture into the junction are more reliably suppressed, and device characteristics are deteriorated due to electric field concentration. Is prevented as much as possible.

  The protective wall 7 is provided so as to cover only the side surface of the first portion 36aa of the lower portion 36a. From the viewpoint of maintaining good high-frequency characteristics, it is necessary to suppress the parasitic capacitance by minimizing the amount of dielectric material existing around the gate electrode 36. In the present embodiment, the protective wall 7 is disposed only on the key portion, that is, the side surface of the first portion 36aa, in order to prevent deterioration of device characteristics and maintain reliability. The protective wall 7 is not disposed in the second portion 36ab and the upper portion 36b, and a gap (an interlayer insulating film is formed between the protective wall 7 where the second portion 36ab exists and the upper portion 36b. In that case, the insulator) is formed. The air in the air gap or the insulator of the interlayer insulating film has a dielectric constant lower than that of a normal dielectric material. Therefore, the parasitic capacitance is minimized and good high frequency characteristics can be obtained.

  As described above, according to the present example, the fine gate structure is adopted to reduce the size of the gate electrode 36, but the device characteristics are prevented from changing and deteriorating due to the electric field concentration around the gate electrode 36, and thus reliable. A highly Schottky AlGaN / GaN HEMT is realized.

(Modification 4)
This example is different from the first embodiment in that the shape of the insulating film covering the surface of the compound semiconductor layer is different.
FIG. 13 is a schematic cross-sectional view showing the main steps of a method for manufacturing a Schottky AlGaN / GaN.HEMT according to Modification 4 of the first embodiment.

  First, similarly to the first embodiment, each step of FIG. 1A to FIG. 1C is executed.

Subsequently, as shown in FIG. 13A, an insulating film 37 is formed.
Specifically, for example, a SiN film is deposited to a thickness of about 50 nm so as to cover the entire surface of the SiC substrate 1 including the source electrode 4 and the drain electrode 5 by PECVD, for example. Thereby, the insulating film 37 is formed.

Subsequently, as shown in FIG. 13B, the insulating film 37 is patterned.
Specifically, a resist is applied on the insulating film 37. A resist is processed by lithography to form a resist mask that exposes the surface of the insulating film 37 on the source electrode 4 and the drain electrode 5 and covers the surface of the insulating film 37 with a width of about 1 μm including a portion where the gate electrode is to be formed. Using this resist mask, the insulating film 37 is dry etched. As a result, the insulating film 37 is left in a width of about 1 μm including the portion where the gate electrode is to be formed on the surface of the surface layer 2 d of the compound semiconductor layer 2.

Subsequently, as illustrated in FIG. 13C, an opening 37 a is formed in the insulating film 37.
Specifically, a resist is applied on the insulating film 37. As the resist, an electron beam resist such as a polymethyl methacrylate (PMMA) resist manufactured by Microchem Corporation of the United States is used. For example, 80 nm-long opening drawing is performed on the resist by the electron beam drawing method, and development is performed using, for example, a MIBK / IPA mixed solution. Thereby, an opening is formed in the resist. Using this resist as a mask, the insulating film 37 is dry etched. For this dry etching, SF ₆ is used as an etching gas. Thereby, an opening 37a having a width of, for example, 100 nm is formed in the insulating film 37 to expose a part of the surface of the surface layer 2d.

  Thereafter, as in the first embodiment, each step of FIG. 2D to FIG. 3B is executed to form wirings that are electrically connected to the source electrode 4, the drain electrode 5, and the gate electrode 8. Perform various steps. When used in a high frequency device, an interlayer insulating film covering the gate electrode 8 is not formed. As described above, the Schottky AlGaN / GaN HEMT according to this example is formed.

  FIG. 14 shows a Schottky AlGaN / GaN HEMT according to this example. In FIG. 14, for convenience of illustration, only the portion on the compound semiconductor layer 2 is shown, and the illustration of the SiC substrate and the element isolation structure 3 is omitted.

  In this AlGaN / GaN.HEMT, the protective wall 7 covers the junction between the gate electrode 8 which is the lower end of the gate electrode 8 and the insulating film 37, and the junction is not exposed to the outside. As a result, the junction portion does not come into contact with atmospheric constituent elements and moisture, and deterioration of device characteristics due to electric field concentration is prevented as much as possible.

  The protective wall 7 is provided so as to cover only the side surface of the first portion 8aa of the lower portion 8a. From the viewpoint of maintaining good high-frequency characteristics, it is necessary to suppress the parasitic capacitance by minimizing the amount of the dielectric material existing around the gate electrode 8. In this example, the protective wall 7 is disposed only at a key portion, that is, the side surface of the first portion 8aa, in order to prevent deterioration of device characteristics and maintain reliability. The protective wall 7 is not disposed in the second portion 8ab and the upper portion 8b, and a gap (an interlayer insulating film is formed between the protective wall 7 where the second portion 8ab exists and the upper portion 8b. In that case, the insulator) is formed. The air in the air gap or the insulator of the interlayer insulating film has a dielectric constant lower than that of a normal dielectric material. Therefore, the parasitic capacitance is minimized and good high frequency characteristics can be obtained.

  Further, in the AlGaN / GaN HEMT according to this example, the insulating film 37 exposes the source electrode 4 and the drain electrode 5, covers the lower end of the gate electrode 8 and the lower surface of the protective wall 7 on the compound semiconductor layer 2, and It exists only in the region included below 8b. In the HEMT, it is necessary to minimize the amount of dielectric on the compound semiconductor layer from the viewpoint of improving high-frequency characteristics. In addition, depending on the method of forming the insulating film, the portion of the insulating film other than the immediate vicinity of the gate electrode may cause the sheet resistance (source resistance) to increase. In this example, the insulating film 37 that defines the gate length is disposed only in the immediate vicinity of the gate electrode 8. Thereby, the high frequency characteristic and output characteristic of AlGaN / GaN.HEMT can be greatly improved.

  As described above, according to this example, the fine gate structure is adopted to reduce the size of the gate electrode 8, but the device characteristics are prevented from changing and deteriorating due to the electric field concentration around the gate electrode 8, thereby being reliable. A highly Schottky AlGaN / GaN HEMT is realized.

  In addition, in the above-described modified examples 1 to 4, any two, any three, or all four examples are combined, and an AlGaN / GaN HEMT having the characteristics of the combined modified examples is realized. Anyway.

As an example, the case where the modification 3 is combined with the modification 1 will be described.
As shown in FIG. 15, in the gate electrode 36, the second portion 36 ab is wider than the first portion 36 aa at the boundary between the first portion 36 aa and the second portion 36 ab of the lower portion 36 a. Is formed. That is, the second portion 36ab is formed on the protective wall 31 so as to run on the protection wall 31 with a width of about 50 nm, for example. Further, in the gate electrode 36, the rising width W1 on the drain electrode 5 side of the first portion 36aa of the lower part 36a is larger than the rising width W2 on the source electrode 4 side. With this configuration, deterioration of device characteristics due to electric field concentration is more reliably prevented.

(Second Embodiment)
In the present embodiment, an MIS type AlGaN / GaN HEMT is disclosed.
FIG. 16 is a schematic cross-sectional view showing the main steps of a method for manufacturing an MIS type AlGaN / GaN HEMT according to the second embodiment.

  First, similarly to the first embodiment, each step of FIG. 1A to FIG. 1C is executed.

Subsequently, as shown in FIG. 16A, an insulating film 6 is formed.
Specifically, for example, an Al ₂ O ₃ film is deposited by sputtering, for example, so as to cover the entire surface of the SiC substrate 1 including the source electrode 4 and the drain electrode 5. Thereby, the insulating film 41 is formed.

Subsequently, as shown in FIG. 16B, a protective wall 7 is formed.
Specifically, an electron beam sensitive SOD film, which is an HSQ compound, for example, is formed as an insulating film on the insulating film 41 to a thickness of, for example, 100 nm by a spin coating method. With respect to the SOD film, an electron beam is dosed to each rectangular region having a width of, for example, 100 nm on the source electrode 4 side and the drain electrode 5 side so that the distance between the opposing sides is, for example, about 100 nm. Develop and cure the SOD film. Thus, the protective wall 7 made of the SOD film is formed. The protective wall 7 is an insulating structure having a width of 100 nm in which a portion on the source electrode 4 side and a portion on the drain electrode 5 side are separated by about 100 nm. Between the protective walls 7, a gap 7 b having a width of 100 nm is formed on the insulating film 41.

  Subsequently, similarly to FIG. 3A of the first embodiment, a three-layer resist mask 12 for forming a gate electrode is formed.

Subsequently, as shown in FIG. 16C, a gate electrode 42 is formed.
Specifically, for example, Ni / Au is used as the electrode material, and the inside of the opening 21a is filled with the electrode material by vapor deposition or the like, and the electrode material is deposited so that the electrode material exists in the opening 22a. The electrode material is also deposited on the upper resist 23. As the electrode material, Pt / Au may be deposited instead of Ni / Au.

  The lift-off method using a heated organic solvent removes the three-layer resist mask 12 and unnecessary electrode material, here the electrode material deposited on the upper-layer resist 23. As described above, the overhanging gate electrode 42 is formed on the insulating film 41 functioning as the gate insulating film so as to fill the gap 7b with the electrode material and protrude above the protective wall 7.

  Thereafter, various processes such as formation of wirings that are electrically connected to the source electrode 4, the drain electrode 5, and the gate electrode 42 are performed. When used in a high frequency device, an interlayer insulating film that covers the gate electrode 42 is not formed. Thus, the MIS type AlGaN / GaN HEMT according to the present embodiment is formed.

  FIG. 17 shows a MIS type AlGaN / GaN.HEMT according to the present embodiment. In FIG. 17, for convenience of illustration, only the portion on the compound semiconductor layer 2 is shown, and the illustration of the SiC substrate and the element isolation structure 3 is omitted.

  In this AlGaN / GaN HEMT, the protective wall 7 is disposed on the side surface of the gate electrode 42. The gate electrode 42 is integrally formed with a trunk-like lower portion 42a having a fine gate structure and an upper portion 42b that extends from the upper end of the lower portion 42a to an umbrella shape (overhang shape) wider than the upper end. The lower portion 42a has a first portion 42aa including a lower end, and a second portion 42ab on the first portion 42aa. The protective wall 7 is formed so as to cover only both side surfaces of the first portion 42aa.

  The protective wall 7 covers the junction between the gate electrode 42, which is the lower end of the gate electrode 42, and the insulating film 41, and the junction is not exposed to the outside. When the insulating film 41 is thin and electric field concentration occurs at the junction site when the protective wall 7 is not present, it cannot be said that the resistance against the electric field concentration is sufficient. In the present embodiment, by disposing the protective wall 7 as described above, deterioration of device characteristics due to electric field concentration is prevented as much as possible without the junction portion contacting with atmospheric constituent elements and moisture. .

  The protective wall 7 is provided so as to cover only the side surface of the first portion 42aa of the lower portion 42a. From the viewpoint of maintaining good high frequency characteristics, it is necessary to suppress the parasitic capacitance by minimizing the amount of the dielectric material existing around the gate electrode 42. In the present embodiment, the protective wall 7 is disposed only on the key portion, that is, the side surface of the first portion 42aa, in order to prevent deterioration of device characteristics and maintain reliability. The protective wall 7 is not disposed in the second portion 42ab and the upper portion 42b, and a gap (an interlayer insulating film is formed between the protective wall 7 where the second portion 42ab exists and the upper portion 42b. In that case, the insulator) is formed. The air in the air gap or the insulator of the interlayer insulating film has a dielectric constant lower than that of a normal dielectric material. Therefore, the parasitic capacitance is minimized and good high frequency characteristics can be obtained.

  As described above, according to the present embodiment, the fine gate structure is adopted and the gate electrode 42 is miniaturized, but the device characteristics are prevented from being changed / deteriorated due to electric field concentration around the gate electrode 42, A highly reliable MIS AlGaN / GaN HEMT is realized.

  As illustrated in FIG. 18, various modifications of the first embodiment may be applied to this embodiment. Further, any two of the following three examples, or all three examples can be combined, and an AlGaN / GaN HEMT having the characteristics of the combined examples can be realized.

FIG. 18A shows an MIS type AlGaN / GaN HEMT having a protective wall 33 and a gate electrode 34 to which the second modification of the first embodiment is applied.
FIG. 18B shows an MIS type AlGaN / GaN HEMT having the protective wall 7 and the gate electrode 36 to which the third modification of the first embodiment is applied.
FIG. 18C shows a MIS-type AlGaN / GaN HEMT to which the fourth modification of the first embodiment is applied. In this AlGaN / GaN.HEMT, the insulating film 41 covers the lower surface of the gate electrode 42 and the lower surface of the protective wall 7 and exists only in the region included below the upper portion 8b.

(Third embodiment)
In the present embodiment, a high-frequency amplifier including one type of AlGaN / GaN HEMT selected from the first embodiment and its modifications, and the second embodiment and its modifications is disclosed.
FIG. 19 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the third embodiment.

The high-frequency amplifier includes a digital predistortion circuit 51, mixers 52a and 52b, and a power amplifier 53.
The digital predistortion circuit 51 compensates for nonlinear distortion of the input signal. The mixer 52a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 53 amplifies the input signal mixed with the AC signal, and is one type of AlGaN selected from the first embodiment and its modifications, and the second embodiment and its modifications. /GaN.HEMT. In FIG. 19, for example, by switching the switch, the output side signal can be mixed with the AC signal by the mixer 52b and sent to the digital predistortion circuit 51.

  In this embodiment, the gate electrode is miniaturized by adopting a fine gate structure, but a highly reliable Schottky-type AlGaN / GaN that prevents fluctuation and deterioration of device characteristics due to electric field concentration around the gate electrode. -Apply HEMT to high frequency amplifiers. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

[Other Embodiments]
In the first embodiment and its modifications, the second embodiment and its modifications, and the third embodiment, an AlGaN / GaN HEMT is exemplified as the compound semiconductor device. As the compound semiconductor device, besides the AlGaN / GaN.HEMT, for example, the following HEMT can be applied.

(Other HEMT example 1)
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors whose lattice constants can be close by composition. In this case, in the above embodiments and modifications, the electron transit layer is formed of GaN, the electron supply layer is formed of InAlN, and the surface layer is formed of GaN. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by the spontaneous polarization of InAlN.

  According to this example, as in the AlGaN / GaN HEMT described above, the fine gate structure is adopted to make the gate electrode finer, but the device characteristics are prevented from fluctuating / deteriorating due to electric field concentration around the gate electrode. Thus, highly reliable InAlN / GaN is realized.

(Other HEMT example 2)
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter has a smaller lattice constant than the former. In this case, in the above embodiments and modifications, the electron transit layer is formed of GaN, the electron supply layer is formed of InAlGaN, and the surface layer is formed of GaN.

  According to this example, as in the AlGaN / GaN HEMT described above, the fine gate structure is adopted to make the gate electrode finer, but the device characteristics are prevented from fluctuating / deteriorating due to electric field concentration around the gate electrode. Thus, a highly reliable InAlGaN / GaN.HEMT is realized.

  Hereinafter, various aspects of the method of manufacturing a compound semiconductor device, the compound semiconductor device, and the like will be collectively described as appendices.

(Appendix 1) a compound semiconductor layer;
A gate electrode formed above the compound semiconductor layer,
The gate electrode is integrally formed with a trunk-like lower portion and an upper portion that spreads in an umbrella shape wider than the upper end from the upper end of the lower portion,
The lower portion has a first portion including a lower end and a second portion on the first portion;
A compound semiconductor device, wherein a protective wall that covers only a side surface of the first portion is formed.

(Appendix 2) In the lower part, a step is formed in which the second part is wider than the first part at the boundary between the first part and the second part,
The compound semiconductor device according to appendix 1, wherein the second portion is formed so as to run on the protective wall.

(Additional remark 3) It further contains the source electrode and drain electrode which were formed in the side part of the said gate electrode on the said compound semiconductor layer,
The compound semiconductor device according to appendix 1 or 2, wherein the protective wall is thicker in a portion on the drain electrode side than on a portion on the source electrode side.

(Appendix 4) An insulating film is formed between the compound semiconductor layer and the gate electrode,
4. The compound semiconductor device according to any one of appendices 1 to 3, wherein the gate electrode is directly connected to the compound semiconductor layer through an opening formed in the insulating film.

  (Supplementary Note 5) The first portion of the lower portion is formed so as to fill the opening and ride on the insulating film, and the run width is larger on the drain electrode side than on the source electrode side. Item 5. The compound semiconductor device according to appendix 4.

(Appendix 6) An insulating film is formed between the compound semiconductor layer and the gate electrode,
4. The compound semiconductor device according to any one of appendices 1 to 3, wherein the gate electrode is formed above the compound semiconductor layer via the insulating film.

  (Additional remark 7) The said insulating film covers the lower surface of the said protective wall, and is formed only in the area | region included under the said upper part, The additional description 4-6 characterized by the above-mentioned Compound semiconductor device.

(Appendix 8) A step of forming a protective wall above the compound semiconductor layer;
Forming a gate electrode so as to embed a gap between the protective walls,
The gate electrode is integrally formed with a trunk-like lower portion and an upper portion that spreads in an umbrella shape wider than the upper end from the upper end of the lower portion,
The lower portion has a first portion including a lower end and a second portion on the first portion;
The method for manufacturing a compound semiconductor device, wherein the protective wall covers only a side surface of the first portion.

(Appendix 9) In the lower portion, a step is formed in which the second portion is wider than the first portion at the boundary between the first portion and the second portion,
9. The method of manufacturing a compound semiconductor device according to appendix 8, wherein the second portion is formed so as to run on the protective wall.

(Additional remark 10) Before the process of forming the said protective wall, it further includes the process of forming a source electrode and a drain electrode in the side part of the said gate electrode on the said compound semiconductor layer,
10. The method of manufacturing a compound semiconductor device according to appendix 8 or 9, wherein the protective wall is thicker on a portion on the drain electrode side than on a portion on the source electrode side.

(Appendix 11) Before the step of forming the protective wall, a step of forming an insulating film on the compound semiconductor layer;
After the step of forming the protective wall, further comprising forming an opening exposing a part of the surface of the compound semiconductor layer in a portion between the protective walls of the insulating film,
11. The method of manufacturing a compound semiconductor device according to any one of appendices 8 to 10, wherein the gate electrode is directly connected to the compound semiconductor layer through an opening formed in the insulating film.

  (Supplementary Note 12) The first portion of the lower portion is formed so as to fill the opening and run over the insulating film, and the running width is larger on the drain electrode side than on the source electrode side. Item 14. The method for manufacturing a compound semiconductor device according to appendix 11, wherein:

(Additional remark 13) Before the process of forming the said protective wall, the process of forming an insulating film on the said compound semiconductor layer is further included,
11. The method of manufacturing a compound semiconductor device according to any one of appendices 8 to 10, wherein the gate electrode is formed above the compound semiconductor layer via the insulating film.

  (Additional remark 14) The said insulating film covers the bottom face of the said protective wall, and is formed only in the area | region included under the said upper part, The additional description 8-13 characterized by the above-mentioned A method for manufacturing a compound semiconductor device.

(Supplementary Note 15) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A compound semiconductor layer;
A gate electrode formed above the compound semiconductor layer,
The gate electrode is integrally formed with a trunk-like lower portion and an upper portion that spreads in an umbrella shape wider than the upper end from the upper end of the lower portion,
The lower portion has a first portion including a lower end and a second portion on the first portion;
A high-frequency amplifier, wherein a protective wall that covers only a side surface of the first portion is formed.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 Compound semiconductor layer 2a Buffer layer 2b Electron travel layer 2c Electron supply layer 2d Surface layer 3 Element isolation structure 4 Source electrode 5 Drain electrodes 6, 37, 41 Insulating films 6a, 11a, 11b, 21a, 21b, 22a, 23a, 37a Opening 7, 31, 33 Protective walls 7a, 31a, 33a Air gaps 8, 32, 34, 36, 42, 101 Gate electrodes 8a, 32a, 34a, 36a, 42a Lower portions 8b, 32b, 34b, 36b, 42b Upper portion 8aa, 32aa, 34aa, 36aa, 42aa First portion 8ab, 32ab, 34ab, 36ab, 42ab Second portion 11 Resist mask 12, 35 Three layer resist mask 21 Lower layer resist 22 Middle resist 23 Upper layer resist 51 Digital Predistortion circuit 52a, 52b Mixer 5 3 Power amplifier

Claims (6)

A compound semiconductor layer;
A gate electrode formed above the compound semiconductor layer,
The gate electrode is integrally formed with a trunk-like lower portion and an upper portion that spreads in an umbrella shape wider than the upper end from the upper end of the lower portion,
The lower portion has a first portion including a lower end and a second portion on the first portion;
A compound semiconductor device, wherein a protective wall that covers only a side surface of the first portion is formed. In the lower portion, a step is formed at the boundary between the first portion and the second portion, the second portion being wider than the first portion,
The compound semiconductor device according to claim 1, wherein the second portion is formed so as to run on the protective wall. A source electrode and a drain electrode formed on a side of the gate electrode on the compound semiconductor layer;
The compound semiconductor device according to claim 1, wherein the protective wall is thicker in a portion on the drain electrode side than on a portion on the source electrode side. An insulating film is formed between the compound semiconductor layer and the gate electrode,
The gate electrode is directly connected to the compound semiconductor layer through an opening formed in the insulating film;
The first portion of the lower portion is formed so as to fill the opening and run over the insulating film, and the running width is larger on the drain electrode side than on the source electrode side. The compound semiconductor device according to claim 1. Forming a protective wall above the compound semiconductor layer;
Forming a gate electrode so as to embed a gap between the protective walls,
The gate electrode is integrally formed with a trunk-like lower portion and an upper portion that spreads in an umbrella shape wider than the upper end from the upper end of the lower portion,
The lower portion has a first portion including a lower end and a second portion on the first portion;
The method for manufacturing a compound semiconductor device, wherein the protective wall covers only a side surface of the first portion. In the lower portion, a step is formed in which the second portion is wider than the first portion at the boundary between the first portion and the second portion,
6. The method of manufacturing a compound semiconductor device according to claim 5, wherein the second portion is formed so as to run on the protective wall.

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